JP2002171035A - Large-scaled circuit board - Google Patents

Large-scaled circuit board

Info

Publication number
JP2002171035A
JP2002171035A JP2000364702A JP2000364702A JP2002171035A JP 2002171035 A JP2002171035 A JP 2002171035A JP 2000364702 A JP2000364702 A JP 2000364702A JP 2000364702 A JP2000364702 A JP 2000364702A JP 2002171035 A JP2002171035 A JP 2002171035A
Authority
JP
Japan
Prior art keywords
circuit board
region
area
sized
blank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000364702A
Other languages
Japanese (ja)
Other versions
JP4428853B2 (en
Inventor
Ryokichi Ogata
良吉 緒方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000364702A priority Critical patent/JP4428853B2/en
Publication of JP2002171035A publication Critical patent/JP2002171035A/en
Application granted granted Critical
Publication of JP4428853B2 publication Critical patent/JP4428853B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a large-scaled circuit board, which enables inspection of each circuit board region for high-frequency characteristics on the large-sized circuit board to be carried out, and which can prevent the generation of cracks due to a sharp shrinkage of itself, when it is baked. SOLUTION: The large-sized circuit board 10 is formed with separate division recesses 2 and 3 for extracting the respective circuit board regions 9, at least on each side of each circuit board region 9. By dividing the large-sized circuit board 10 along the division recesses 2 and 3, a plurality of substrates are obtained. Blank regions 5 are formed between the circuit board regions 9, which are adjacent at least in either X or Y direction. In part of a region wherein the division recesses 2 and 3 cross the blank region 5, a part 4 through which ceramic sections holding the division recesses 2 and 3 in between are connected is formed. In a boundary between each circuit board region 9 and the blank regions 5, terminal electrodes 6 and 7 are formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、回路基板となる回
路基板領域が縦横に配置され、分割溝に沿って分割処理
することにより、複数の回路基板が抽出できる大型回路
基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-sized circuit board from which a plurality of circuit boards can be extracted by arranging circuit board regions to be circuit boards vertically and horizontally and performing division processing along division grooves.

【0002】[0002]

【従来の技術】回路基板は、基板のサイズの小型化、実
装回路の高周波化などが求められており、回路基板材料
には、耐熱性、耐久性、熱伝導性等に優れるアルミナセ
ラミック材料などが多用されている。そして、回路基板
には、ICチップ、LSIチップ等の半導体素子をはじ
め、各種電子部品素子が表面に実装されたり、また、表
面に形成したキャビティーに収容されたりしている。し
かも、回路基板に形成した所定回路網とマザーボードの
回路との接続は、回路基板の端面に形成した半円形状の
スルーホール電極が用いられる。このような回路基板を
効率的に製造するために、各回路基板となる回路基板領
域が縦横に配置された大型回路基板が使用され、回路基
板の製造の最終工程で、回路基板領域を縦横に仕切る分
割溝でもって分割処理していた。
2. Description of the Related Art A circuit board is required to have a smaller board size and a higher frequency of a mounted circuit. For example, an alumina ceramic material having excellent heat resistance, durability, heat conductivity, etc. is required. Is often used. On the circuit board, various electronic component elements such as semiconductor elements such as IC chips and LSI chips are mounted on the surface, or are housed in cavities formed on the surface. In addition, a semicircular through-hole electrode formed on the end face of the circuit board is used to connect the predetermined circuit network formed on the circuit board to the circuit on the motherboard. In order to efficiently manufacture such a circuit board, a large-sized circuit board is used in which circuit board areas to be each circuit board are arranged vertically and horizontally, and the circuit board area is vertically and horizontally arranged in the final process of manufacturing the circuit board. The dividing process was performed by the dividing groove.

【0003】この分割溝(以下、スナップラインとい
う)は、セラミックから成る大型回路基板を焼成処理す
る前に、基板の厚みの30〜70%の深さの溝となるよ
うに、金型のプレスにより形成していた。そして、焼成
後、各種部品を基板に実装し、最終段階でスナップライ
ンにそって複数の回路基板を抽出していた。
[0003] The divided grooves (hereinafter referred to as snap lines) are formed by pressing a mold so that the grooves have a depth of 30 to 70% of the thickness of the substrate before firing the large circuit board made of ceramic. Was formed. After firing, various components were mounted on the board, and a plurality of circuit boards were extracted along the snap line in the final stage.

【0004】図3は、従来の一実施例のスナップライン
を形成した複数の回路基板が抽出できる大型回路基板を
示す平面図である。また、図4は、一般的な基板の製造
方法を示す平面図である。図において、30は大型回路
基板、31は回路基板、32はY方向のスナップライ
ン、33はX方向のスナップライン、35は大型回路基
板の外周部の余白領域、39は分割後回路基板31とな
る各回路基板領域である。
FIG. 3 is a plan view showing a conventional large-sized circuit board from which a plurality of circuit boards on which snap lines are formed can be extracted. FIG. 4 is a plan view showing a general substrate manufacturing method. In the figure, 30 is a large circuit board, 31 is a circuit board, 32 is a snap line in the Y direction, 33 is a snap line in the X direction, 35 is a blank area on the outer peripheral portion of the large circuit board, and 39 is the divided circuit board 31 Circuit board regions.

【0005】同図によれば、大型回路基板30の焼成前
に、スナップライン32、33を形成し、必要に応じて
内部配線や表面配線を基板と同時に焼結し、または焼結
した後の回路基板領域39の表面に表面配線を形成し、
各種電子部品を搭載した後、スナップライン32、33
で分割することにより、各回路基板31を得ていた。図
4では、大型回路基板30を2段階で分割処理して、回
路基板31を得る分割工程を示している。即ち、図4
(a)に示す大型回路基板30を、スナップライン32
に沿って1次分割処理を行い(図4(b))、次いで、
短冊状の回路基板30‘に残存するスナップライン33
にそって、2次分割処理を行い、個々の回路基板31を
得ていた。
According to FIG. 1, before firing the large circuit board 30, snap lines 32 and 33 are formed, and if necessary, internal wiring and surface wiring are sintered together with the substrate, or after sintering. Forming surface wiring on the surface of the circuit board region 39;
After mounting various electronic components, snap lines 32, 33
Thus, each circuit board 31 was obtained. FIG. 4 shows a dividing step in which the large circuit board 30 is divided into two stages to obtain the circuit board 31. That is, FIG.
The large circuit board 30 shown in FIG.
A primary division process is performed along (FIG. 4B).
Snap line 33 remaining on strip-shaped circuit board 30 '
According to the above, a secondary division process is performed to obtain individual circuit boards 31.

【0006】[0006]

【発明が解決しようとする課題】一般に、回路基板領域
に各種電子部品を実装して、所定回路網を構成した後に
は、その所定回路網の正常に動作するかのついて検査工
程が必要となる。上述の大型回路基板を用いて製造する
場合、各回路基板領域39を分割処理して回路基板31
した後に測定するのではなく、分割前の大型回路基板3
0の状態で測定することが望ましい。
Generally, after various electronic components are mounted on a circuit board area to form a predetermined circuit network, an inspection process is required to check whether the predetermined circuit network operates normally. . In the case of manufacturing using the above-mentioned large circuit board, each circuit board area 39 is divided and the circuit board 31 is processed.
The large circuit board 3 before splitting is not measured after
It is desirable to measure in the state of 0.

【0007】また、各回路基板31の所定回路網が高周
波で動作する場合には、その回路網の動作とともに特性
インピーダンスを測定する。この時、入出力端子電極と
グランド端子電極に測定用プローブをあてて特性インピ
ーダンスなどを測定する。そして、この入力端子電極や
グランド端子電極は、回路基板31の端面に形成される
ことから、大型回路基板30では、隣接しあう回路基板
領域39を仕切る分割溝(実際には、分割溝の延長線)
に形成する必要がある。即ち、分割溝に、分割処理後、
凹部となる貫通孔を形成し、この貫通孔の内壁面に各端
子電極となる導体膜を形成する必要がある。図5では、
例えば分割溝32状に貫通孔を形成して、その内壁面に
端子電極36、37となる導体膜を形成している。
When a predetermined network of each circuit board 31 operates at a high frequency, the characteristic impedance is measured together with the operation of the network. At this time, a measurement probe is applied to the input / output terminal electrode and the ground terminal electrode to measure characteristic impedance and the like. Since the input terminal electrode and the ground terminal electrode are formed on the end surface of the circuit board 31, the large circuit board 30 has a dividing groove (actually, an extension of the dividing groove) for partitioning the adjacent circuit board regions 39. line)
Must be formed. That is, after the dividing process,
It is necessary to form a through hole serving as a concave portion and to form a conductor film serving as each terminal electrode on the inner wall surface of the through hole. In FIG.
For example, a through-hole is formed in the shape of the dividing groove 32, and a conductor film to be the terminal electrodes 36 and 37 is formed on the inner wall surface.

【0008】ここで、図5に示すように、大型回路基板
30において、隣接した回路基板領域39は回路網が繰
り返しパターンとなるため、また、隣接しあう回路基板
領域39を仕切る分割溝を跨いで貫通孔が形成されるた
め、隣接しあう回路基板39どおしの端子電極36、3
7が接することになる。 即ち、隣接する各回路基板領
域39の入出力端子電極36どおし、グランド端子電極
37どうし、または入出端子電極力36とグランド端子
電極37が接合される。このため、1つの回路基板領域
に形成された回路網の諸特性を検査しようとしても、互
いに接合しあう端子電極36、37が存在しているた
め、単独の回路基板領域39の特性を測ることができな
かった。
Here, as shown in FIG. 5, in the large circuit board 30, the adjacent circuit board area 39 has a repetitive pattern of a circuit network, and also straddles a dividing groove which partitions the adjacent circuit board area 39. Is formed, the terminal electrodes 36, 3 between the adjacent circuit boards 39 are formed.
7 will be in contact. That is, the input / output terminal electrodes 36 of the adjacent circuit board regions 39 and the ground terminal electrodes 37 or the input / output terminal electrode force 36 and the ground terminal electrodes 37 are joined. Therefore, even if an attempt is made to inspect various characteristics of a circuit network formed in one circuit board region, since the terminal electrodes 36 and 37 that are bonded to each other are present, it is necessary to measure the characteristics of the single circuit board region 39. Could not.

【0009】このため、高周波特性の検査を、大型回路
基板30に、半導体素子、厚膜抵抗素子、各種電子部品
等を実装した後、分割処理を余儀なくされてしまってい
た。このため、不良品の発見が遅れによるむだな工程が
増えるという問題点があった。
For this reason, it has been necessary to inspect the high frequency characteristics after mounting a semiconductor element, a thick-film resistance element, various electronic components, and the like on the large-sized circuit board 30, and then perform a dividing process. For this reason, there is a problem that useless processes increase due to delay in finding defective products.

【0010】一方、各回路基板31の表面に、特性測定
用電極を形成することも考えられるが、基板の占有面積
が制約され、小型化の要求に応えられないという問題点
があった。
On the other hand, it is conceivable to form a characteristic measuring electrode on the surface of each circuit board 31, but there is a problem that the area occupied by the board is restricted, and it is not possible to meet the demand for miniaturization.

【0011】また、上記大型回路基板30の製造時に、
図6の太線で示すように、基板30にヒビ38が入る問
題点があった。これは、特に、焼成処理時の焼成炉内の
位置により、焼成温度に分布が生じるためと考えられて
いる。このヒビ38の発生は、大型回路基板30の中央
に近付くほど発生しやすく、また、大型回路基板30の
セラミック材料の収縮率が大きいほど発生しやすかっ
た。そして、大型回路基板30にヒビ38が入ると、大
型回路基板30上に各種電子部品を実装する際に、大型
回路基板30が完全に割れてしまったり、実装時に位置
ずれが発生するという問題点があった。このような問題
を解決するにあたり、焼成プロファイルを調整して、急
激な基板収縮を抑えたり、スナップライン32、33を
浅くしてヒビ38を抑制する方法が考えられる。しか
し、焼成プロファイルを調整する方法では、ヒビ38の
発生は抑制できるものの、大型回路基板30にそりが発
生したりする。またスナップライン32、33を部分的
に浅くする方法では、大型回路基板30を各回路基板3
1に分割する際に、応力がかかりやすくなるため、端部
にばりが発生し、寸法ばらつきの原因となる。
Further, when manufacturing the large circuit board 30,
As shown by the thick line in FIG. 6, there is a problem that the cracks 38 enter the substrate 30. This is considered to be due to distribution of the firing temperature depending on the position in the firing furnace during the firing process. The generation of the cracks 38 was more likely to occur closer to the center of the large circuit board 30, and was more likely to occur as the shrinkage of the ceramic material of the large circuit board 30 was larger. When the cracks 38 enter the large-sized circuit board 30, when mounting various electronic components on the large-sized circuit board 30, the large-sized circuit board 30 is completely broken or a positional shift occurs during mounting. was there. In order to solve such a problem, it is conceivable to adjust the firing profile to suppress rapid substrate shrinkage, or to reduce the snap lines 32 and 33 to suppress the cracks 38. However, in the method of adjusting the firing profile, although the generation of the crack 38 can be suppressed, the large circuit board 30 may be warped. In the method of making the snap lines 32 and 33 partially shallow, the large circuit board 30 is
At the time of division into ones, stress is likely to be applied, so that burrs are generated at the ends, which causes dimensional variations.

【0012】本発明は、上述の問題に鑑みて案出された
ものであり、その目的は、分割前の大型回路基板の状態
で、回路動作の特性検査を簡単に行うことができ、且つ
大型回路基板を焼成する際の急激な基板収縮による、ヒ
ビの発生を防止できる大型回路基板を提供するものであ
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to easily perform a characteristic test of circuit operation in a state of a large circuit board before division, and An object of the present invention is to provide a large-sized circuit board capable of preventing generation of cracks due to rapid contraction of the board when firing the circuit board.

【0013】[0013]

【課題を解決するための手段】本発明は、基板の端面に
厚み方向に延びる凹部を設け、且つ該凹部の内壁面に端
子電極を形成した矩形状の回路基板となる回路基板領域
を、その周囲に余白領域を設けて縦横に配置して成る大
型回路基板であって、前記回路基板領域と前記余白領域
とは、縦横で交差しあう余白領域で非連続となる断続し
た分割溝によって仕切られるとともに、前記回路基板領
域と前記余白領域との間の分割溝に、前記凹部となる貫
通孔を形成し、該貫通孔の内壁面に隣接する他の回路基
板領域と非導通の端子電極を形成したことを特徴した大
型回路基板である。
According to the present invention, there is provided a circuit board region which becomes a rectangular circuit board in which a concave portion extending in the thickness direction is provided on an end face of the substrate, and a terminal electrode is formed on an inner wall surface of the concave portion. A large-sized circuit board having a margin area provided in the periphery and arranged vertically and horizontally, wherein the circuit board area and the margin area are separated by intermittent divided grooves that are discontinuous in margin areas intersecting vertically and horizontally. In addition, a through hole serving as the concave portion is formed in a division groove between the circuit board region and the blank region, and a terminal electrode that is not conductive with another circuit board region adjacent to an inner wall surface of the through hole is formed. This is a large-sized circuit board characterized by the following.

【0014】[0014]

【発明の実施の形態】以下、本発明の大型回路基板を図
面に基づいて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A large circuit board according to the present invention will be described below with reference to the drawings.

【0015】図1(a)は、本発明の大型回路基板の平
面図であり、図1(b)は、図1(a)中、丸印部分の
拡大図であり、図2は、図1の隣り合う6つの回路基板
領域のみに着目した部分拡大図である。
FIG. 1A is a plan view of a large circuit board according to the present invention, FIG. 1B is an enlarged view of a circle in FIG. 1A, and FIG. FIG. 3 is a partially enlarged view focusing on only six adjacent circuit board regions.

【0016】図において、10は大型回路基板、9は回
路基板領域であり、5は各回路基板の領域に連続して形
成された余白領域であり、2、3は回路基板領域9と余
白領域5とを仕切る断続したスナップラインである。
尚、2はY方向の断続したスナップラインであり、3は
X方向のスナップラインである。また、4はスナップラ
イン2、3が他方側に延びる余白領域内で途切れて形成
された余白連結部であり、6は入出力端子、7はグラン
ド端子である。なお、図において、焼成の前後で番号は
区別しないこととする。
In the figure, 10 is a large circuit board, 9 is a circuit board area, 5 is a blank area formed continuously with each circuit board area, and 2 and 3 are a circuit board area 9 and a blank area. This is an intermittent snap line that separates 5 and 5.
Note that reference numeral 2 denotes an intermittent snap line in the Y direction, and reference numeral 3 denotes a snap line in the X direction. Reference numeral 4 denotes a margin connecting portion formed by interrupting the snap lines 2 and 3 in a margin area extending to the other side, 6 denotes an input / output terminal, and 7 denotes a ground terminal. In the drawings, numbers are not distinguished before and after firing.

【0017】大型回路基板10は、単板または多層構造
であり、例えばセラミック基板から成る。例えば、85
0〜1050℃前後の比較的低い温度で焼成可能にする
ガラスーセラミック材料からなり、セラミック材料とし
ては、クリストバライト、石英、コランダム(αアルミ
ナ)、ムライト、コージェライトなどの絶縁セラミック
材料、BaTiO3 、Pb4Fe2Nb212、TiO2
どの誘電体セラミック材料、Ni−Znフェライト、M
n−Znフェライト(広義の意味でセラミックという)
などの磁性体セラミック材料などが挙げられる。なお、
その平均粒径1.0〜6.0μm、好ましくは1.5〜
4.0μmに粉砕したものを用いる。また、セラミック
材料は2種以上混合して用いられてもよい。特に、コラ
ンダムを用いた場合、コスト的に有利となる。ガラス材
料は、焼成処理することによってコージェライト、ムラ
イト、アノーサイト、セルジアン、スピネル、ガーナイ
ト、ウイレマイト、ドロマイト、ペタライトやその置換
誘導体の結晶やスピネル構造の結晶相を析出するもので
あればよく、例えば、B23、SiO2、Al23、Z
nO、アルカリ土類酸化物を含むガラスフリットが挙げ
られる。この様なガラスフリットは、ガラス化範囲が広
くまた屈伏点が600〜800℃付近となっている。
The large circuit board 10 has a single-plate or multi-layer structure, and is made of, for example, a ceramic substrate. For example, 85
It is made of a glass-ceramic material that can be fired at a relatively low temperature of about 0 to 1050 ° C. As the ceramic material, insulating ceramic materials such as cristobalite, quartz, corundum (α-alumina), mullite, cordierite, BaTiO 3 , Dielectric ceramic materials such as Pb 4 Fe 2 Nb 2 O 12 and TiO 2 , Ni—Zn ferrite, M
n-Zn ferrite (ceramic in a broad sense)
And other magnetic ceramic materials. In addition,
Its average particle size is 1.0 to 6.0 μm, preferably 1.5 to 6.0 μm.
Use the one crushed to 4.0 μm. Further, two or more ceramic materials may be used in combination. In particular, the use of corundum is advantageous in terms of cost. The glass material may be any one that precipitates a crystal phase of a cordierite, mullite, anorthite, serdian, spinel, garnite, willemite, dolomite, a crystal of petalite or a substituted derivative thereof or a spinel structure by firing, and for example, , B 2 O 3 , SiO 2 , Al 2 O 3 , Z
Glass frit containing nO and alkaline earth oxides is exemplified. Such a glass frit has a wide vitrification range and a yield point around 600 to 800 ° C.

【0018】各回路基板領域9の表面には、図示してい
ないが、表面配線が形成され、必要に応じてICチッ
プ、SAW素子、抵抗、コンデンサ、インダクタンス素
子などの各種部品が実装される。また、回路基板の端
面、即ち、各回路基板領域の端面には、基板の厚みを貫
通する貫通孔11内の内壁面に、表面配線と接続する入
出力端子電極6、グランド端子電極7が形成されてい
る。これら表面配線や入出力端子電極6、グランド端子
電極7は、Ag系(Ag単体、Ag−Pd、Ag−Pt
などのAg合金)を主成分とする導体膜(導体)からな
る。この入出力端子電極6、グランド端子電極7は、各
回路基板領域9に形成された回路網の特性を測定する際
にチェック用端子として利用される。
Although not shown, surface wiring is formed on the surface of each circuit board region 9, and various components such as IC chips, SAW elements, resistors, capacitors, and inductance elements are mounted as necessary. Further, on the end surface of the circuit board, that is, on the end surface of each circuit board area, an input / output terminal electrode 6 and a ground terminal electrode 7 connected to the surface wiring are formed on the inner wall surface in the through hole 11 penetrating the thickness of the board. Have been. These surface wiring, input / output terminal electrode 6 and ground terminal electrode 7 are made of Ag (Ag alone, Ag-Pd, Ag-Pt).
(Ag alloy, etc.). The input / output terminal electrode 6 and the ground terminal electrode 7 are used as check terminals when measuring the characteristics of the circuit network formed in each circuit board region 9.

【0019】図1、2において、互いに直交するスナッ
プライン2、3は、大型回路基板10の一方の面または
両主面に形成されている。このスナップライン2、3
は、縦横に配置された矩形状の回路基板となる回路基板
領域9の各辺となる部位に形成されている。また、各回
路基板領域9の周囲には、余白領域5が形成されてい
る。
In FIGS. 1 and 2, snap lines 2 and 3 orthogonal to each other are formed on one surface or both main surfaces of a large circuit board 10. This snap line 2,3
Are formed on the respective sides of the circuit board region 9 which is a rectangular circuit board arranged vertically and horizontally. A margin region 5 is formed around each circuit board region 9.

【0020】従って、一方方向から見ると、大型回路基
板10は、余白領域5、回路基板領域9、余白領域5、
回路基板領域9・・余白領域5の順に配置されているこ
とになる。また、他方方向も同様である。即ち、スナッ
プライン2、3は、従来は回路基板領域と回路基板領域
を仕切るために形成されているが、本発明では、回路基
板領域9と余白領域5とを仕切るために形成されてい
る。
Accordingly, when viewed from one direction, the large-sized circuit board 10 includes the blank area 5, the circuit board area 9, the blank area 5,
The circuit board areas 9 are arranged in the order of the blank area 5. The same applies to the other direction. That is, the snap lines 2 and 3 are conventionally formed to separate the circuit board area from the circuit board area. However, in the present invention, the snap lines 2 and 3 are formed to separate the circuit board area 9 from the blank area 5.

【0021】また、スナップライン2、3は、個々の回
路基板領域9に応じて、断続して形成されており、従来
のように複数の回路基板領域39に沿って連続して形成
されているものと相違している。即ち、スナップライン
2、3は、交差する余白領域5で途切れるように形成さ
れている。この途切れる部位は、余白領域5の余白連結
部4となり、余白領域5は、スナップライン2、3によ
って分断されることがなく、各回路基板領域9の周囲で
連続している。言い換えれば、ストリップライン2、3
は、直交わる余白領域5の中央部付近で、非連続となる
ような断続した溝である。
The snap lines 2 and 3 are formed intermittently in accordance with the individual circuit board areas 9 and are formed continuously along a plurality of circuit board areas 39 as in the prior art. It is different from the one. That is, the snap lines 2 and 3 are formed so as to be interrupted at the intersecting blank area 5. The part where this breaks is the margin connecting part 4 of the margin area 5, and the margin area 5 is continuous around each circuit board area 9 without being divided by the snap lines 2 and 3. In other words, strip lines 2, 3
Is an intermittent groove that is discontinuous near the center of the orthogonal blank area 5.

【0022】従って、回路基板の端面に形成された凹部
内に被着される端子電極6、7は、各回路基板領域9と
余白領域5とを仕切るスナップライン2、3に形成され
るため、隣り合う回路基板領域9の向かい合う端子電極
6、7と非導通の状態となっている。
Therefore, the terminal electrodes 6 and 7 attached in the concave portions formed on the end face of the circuit board are formed on the snap lines 2 and 3 that separate the circuit board area 9 and the blank area 5 from each other. It is in a non-conductive state with the terminal electrodes 6 and 7 facing the adjacent circuit board region 9.

【0023】上述の製造方法に適用した一実施例につい
て説明する。まず、CaO−Al23−SiO2−B2
3系のガラス粉末60wt%とアルミナ粉末40wt%
とを混合した粉体に、例えばDOP等の可塑剤と、例え
ばアクリル樹脂あるいはブチラール樹脂等のバインダー
と、例えばトルエン、キシレン、アルコール類等の溶剤
とを加え、十分に混練して粘度2000〜40000c
psのスラリーを作製し、ドクターブレード法によって
例えば0.2mm厚の複数枚の低温焼成用のグリーンシ
ートを形成する。
An embodiment applied to the above-described manufacturing method will be described. First, CaO-Al 2 O 3 -SiO 2 -B 2 O
3 series glass powder 60wt% and alumina powder 40wt%
, A plasticizer such as DOP, a binder such as an acrylic resin or a butyral resin, and a solvent such as toluene, xylene, and alcohols, and sufficiently kneaded to obtain a viscosity of 2,000 to 40,000 c.
A ps slurry is prepared, and a plurality of low-temperature firing green sheets having a thickness of, for example, 0.2 mm are formed by a doctor blade method.

【0024】次に、打ち抜き型やパンチングマシーン等
を用いて、各グリーンシートの複数の所定位置に、例え
ば0.2mmφの端面スルーホール導体、ビアホール導
体となる孔を打ち抜き形成し、各孔にAg、Ag−P
d、Au、Cu等の導体ペーストを充填する。各グリー
ンシートには配線用の導体パターンをスクリーン印刷す
る。
Next, using a punching die, a punching machine, or the like, a hole serving as a through-hole conductor and a via-hole conductor having an end face of, for example, 0.2 mmφ is punched out at a plurality of predetermined positions of each green sheet. , Ag-P
A conductive paste such as d, Au, or Cu is filled. A conductor pattern for wiring is screen-printed on each green sheet.

【0025】次に導体パターンをスクリーン印刷した複
数のグリーンシートを積層し、この大型回路基板10を
例えば80〜150℃、50〜250kg/cm2の条
件で熱圧着して一体化する。
Next, a plurality of green sheets on which conductor patterns are screen-printed are laminated, and the large-sized circuit board 10 is integrated by thermocompression bonding at, for example, 80 to 150 ° C. and 50 to 250 kg / cm 2 .

【0026】次に、熱圧着された大型回路基板10の表
裏両面に、スナップライン2をプレスにより形成する。
次に、矢印Xで示す方向のスナップライン3を大型回路
基板10の表裏両面に形成し、図1に示すように、Y方
向のスナップライン2とX方向のスナップライン3が形
成された大型回路基板10を得る。
Next, snap lines 2 are formed on both the front and back surfaces of the large-sized circuit board 10 which is thermocompression-bonded by pressing.
Next, a snap line 3 in a direction indicated by an arrow X is formed on both front and back surfaces of the large-sized circuit board 10, and as shown in FIG. 1, a large-sized circuit in which a snap line 2 in the Y direction and a snap line 3 in the X direction are formed. A substrate 10 is obtained.

【0027】次に大型回路基板10を電気式連続ベルト
炉を使用して、空気中で900℃、20分の保持条件で
焼成する。なお、導体ペーストがNi、Cuの場合は還
元または中性雰囲気で焼成する。ここで、大型回路基板
10上に半導体素子、厚膜抵抗素子、各種電子部品等を
半田などで接合・実装を行う。
Next, the large-sized circuit board 10 is fired in an air at 900 ° C. for 20 minutes using an electric continuous belt furnace. When the conductive paste is Ni or Cu, the paste is reduced or fired in a neutral atmosphere. Here, semiconductor elements, thick-film resistance elements, various electronic components, and the like are joined and mounted on the large circuit board 10 by soldering or the like.

【0028】次に、Y方向のスナップライン2に沿っ
て、手またはブレイクローラ等の機械等で焼成後の大型
回路基板10を分割する。次に、X方向のスナップライ
ン3に沿って、大型回路基板10を分割する。
Next, the fired large circuit board 10 is divided along the snap line 2 in the Y direction by hand or a machine such as a break roller. Next, the large circuit board 10 is divided along the snap line 3 in the X direction.

【0029】このようにして、最終製品としての回路基
板が得られる。
In this manner, a circuit board as a final product is obtained.

【0030】かくして本発明の大型回路基板10によれ
ば、少なくともX、Y方向のいずれかに隣接する回路基
板領域9間に余白領域5が設けられ、図2に示すよう
に、回路基板領域9と余白領域5に跨がる貫通孔(回路
基板では、端面の凹部となる部分)の内壁に特性測定用
端子となる入出力端子電極6、グランド端子電極7を形
成ししており、隣接配置しあう回路基板領域9の入出力
端子電極6、グランド端子電極7とが導通することが一
切ないため、大型回路基板10の状態で各回路基板領域
9自体の特性を測定しても、隣接配置しあう回路基板領
域9の回路網の影響を一切受けないことになる。すなわ
ち、大型回路基板10の状態で、特性の測定が可能であ
り、しかも、製造工程の早い段階で不良品を除去でき、
むだ工程が減少でとする。
Thus, according to the large-sized circuit board 10 of the present invention, the blank area 5 is provided at least between the circuit board areas 9 adjacent in any of the X and Y directions, and as shown in FIG. An input / output terminal electrode 6 serving as a characteristic measuring terminal and a ground terminal electrode 7 are formed on the inner wall of a through hole (a portion of the circuit board that becomes a concave portion of an end face) extending over the margin region 5 and are disposed adjacent to each other. Since the input / output terminal electrode 6 and the ground terminal electrode 7 in the circuit board area 9 are not electrically connected to each other, even if the characteristics of each circuit board area 9 itself are measured in the state of the large circuit board 10, the circuit board area 9 is located adjacently. The circuit network of the circuit board region 9 is not affected at all. In other words, the characteristics can be measured in the state of the large circuit board 10, and the defective product can be removed at an early stage of the manufacturing process.
The waste process is reduced.

【0031】また、スナップライン2、3が直交する余
白領域5を横切る部位に、余白連結部4を設けたため、
焼成時に各回路基板領域9のスナップライン2、3に沿
って大型回路基板10にヒビが入ることを抑制できる。
なお、余白連結部4の幅が200μm未満である場合、
ヒビの抑制効果が不十分になるため、余白連結部4の幅
の下限は200μm以上であることが望ましい。
Further, since the margin connecting portion 4 is provided at a portion where the snap lines 2 and 3 cross the margin region 5 orthogonal to each other,
Cracking of the large circuit board 10 along the snap lines 2 and 3 of each circuit board area 9 during firing can be suppressed.
When the width of the margin connection part 4 is less than 200 μm,
Since the effect of suppressing cracks becomes insufficient, the lower limit of the width of the margin connection portion 4 is preferably 200 μm or more.

【0032】また、一方方向の余白連結部4の幅が、一
方方向の回路基板領域9の長さの1/3を越えると、大
型回路基板10の分割処理時、安定して分割することが
できず、その結果、分割時にばりが発生してしまう。こ
のため、余白連結部4の幅の上限は、同一方向に延びる
回路基板領域9の長さの1/3以下であることが望まし
い。
If the width of the one-way margin connecting portion 4 exceeds one-third of the length of the circuit board region 9 in one direction, the large circuit board 10 can be stably divided during the dividing process. As a result, burrs are generated at the time of division. For this reason, it is desirable that the upper limit of the width of the margin connection portion 4 be equal to or less than 1 / of the length of the circuit board region 9 extending in the same direction.

【0033】さらに、ヒビの発生を抑制するために、焼
成プロファイルを調整したり、スナップライン2、3を
浅くする必要がないため、基板のそりが大きくなった
り、端部にばりが発生することはない。
Further, since it is not necessary to adjust the firing profile or to make the snap lines 2 and 3 shallow in order to suppress the generation of cracks, the warpage of the substrate becomes large and burrs are generated at the end. There is no.

【0034】本発明者は、複数の回路基板が抽出できる
大型回路基板10について、ヒビの発生頻度を求めた。
大型回路基板10は、焼成後の寸法が75〜80mm
角、厚みが0.75〜1.0mmで、分割により基板が
35〜45個得られるものを用いた。
The inventor has determined the frequency of occurrence of cracks in the large circuit board 10 from which a plurality of circuit boards can be extracted.
The size of the large circuit board 10 after firing is 75 to 80 mm
The corner and thickness used were 0.75 to 1.0 mm, and 35 to 45 substrates were obtained by division.

【0035】また、X、Y方向のスナップライン3、2
の幅は25〜80μm、深さは大型回路基板10厚みに
対して1/5となるようにした。
The snap lines 3 and 2 in the X and Y directions
Has a width of 25 to 80 μm and a depth of 1/5 with respect to the thickness of the large circuit board 10.

【0036】良否の判定基準は、100個の焼成後の大
型回路基板10を目視し、ヒビが発生する割合を求め
た。
As a criterion of pass / fail, 100 large fired large-sized circuit boards 10 were visually observed, and the rate of occurrence of cracks was determined.

【0037】実験の結果、図3に示すような従来の大型
回路基板30はヒビの発生率が5%だったが、図1に示
すような本実施例の大型回路基板10は、ヒビの発生率
が0%となった。
As a result of the experiment, the conventional large-sized circuit board 30 shown in FIG. 3 had a crack generation rate of 5%, but the large-sized circuit board 10 of this embodiment shown in FIG. The rate was 0%.

【0038】なお、本発明は上記の実施の形態例に限定
されるものではなく、本発明の要旨を逸脱しない範囲内
での種々の変更や改良等は何ら差し支えない。
It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention.

【0039】例えば、基板用セラミックスの材料とし
て、低温焼成基板に限らず、アルミナ基板、窒化アルミ
ニウム基板、ムライト基板等どのような大型回路基板に
適用しても良いし、生の大型回路基板は積層基板に限ら
ず、プレス成形体あるいは押し出し成形体あっても良
い。
For example, the ceramic material for the substrate is not limited to a low-temperature fired substrate, but may be applied to any large-sized circuit substrate such as an alumina substrate, an aluminum nitride substrate, and a mullite substrate. Not only the substrate but also a press-formed body or an extruded body may be used.

【0040】また、本実施の形態では、X、Y方向のス
ナップライン2、3を大型回路基板10の表裏両面に形
成したが、片面のみに形成しても良い。
In the present embodiment, the snap lines 2 and 3 in the X and Y directions are formed on both the front and back surfaces of the large-sized circuit board 10, but may be formed on only one surface.

【0041】また、第1及び第2のスナップライン2、
3が交差する部分を、スナップライン2、3の他の部分
に比べて深くしてもよい。このことにより、分割時にか
かる応力を軽減することができ、ばりの発生を低減で
き、寸法ばらつきを防止することができる。
Also, the first and second snap lines 2,
A portion where 3 intersects may be deeper than other portions of the snap lines 2 and 3. As a result, the stress applied at the time of division can be reduced, the occurrence of burrs can be reduced, and dimensional variations can be prevented.

【0042】[0042]

【発明の効果】以上のように、本発明によれば、少なく
ともX、Y方向のいずれかに隣接する回路基板領域間に
余白領域が設けられ、該回路基板領域と余白領域との間
に、隣接する回路基板領域と非導通状態の端子電極が形
成されている。このため、大型回路基板の状態で各回路
基板領域自体の特性を安定して測定することができる。
As described above, according to the present invention, a blank area is provided at least between circuit board areas adjacent to one of the X and Y directions, and between the circuit board area and the blank area, A terminal electrode is formed in a non-conductive state with an adjacent circuit board region. Therefore, the characteristics of each circuit board area itself can be stably measured in the state of the large circuit board.

【0043】また、スナップラインが直交する余白領域
を横切る部位に余白連結部が形成されているため、焼成
時に各回路基板領域のスナップラインに沿って大型回路
基板にヒビが入ることを抑制でき、大型回路基板の製造
時の取り扱いが容易となる。
Further, since the margin connecting portion is formed at a portion where the snap line crosses a margin region orthogonal to the orthogonal direction, it is possible to suppress cracking of the large circuit board along the snap line of each circuit board region during firing. Handling at the time of manufacturing a large circuit board becomes easy.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の大型回路基板を示し、(a)はその平
面図であり、(b)は余白領域の交差部分の拡大平面図
である。
1A and 1B show a large-sized circuit board according to the present invention, wherein FIG. 1A is a plan view thereof, and FIG. 1B is an enlarged plan view of an intersection of a blank area.

【図2】大型回路基板の端子電極の形状状態を示す部分
平面図である。
FIG. 2 is a partial plan view showing a shape of a terminal electrode of a large circuit board.

【図3】従来の大型回路基板を示す平面図である。FIG. 3 is a plan view showing a conventional large circuit board.

【図4】一般的な大型回路基板の製造方法を示す平面図
である。
FIG. 4 is a plan view illustrating a method for manufacturing a general large-sized circuit board.

【図5】従来の大型回路基板の端子電極部分の拡大平面
図である。
FIG. 5 is an enlarged plan view of a terminal electrode portion of a conventional large circuit board.

【図6】従来の大型回路基板に発生していたヒビを説明
する平面図である。
FIG. 6 is a plan view illustrating a crack that has occurred on a conventional large circuit board.

【符号の説明】[Explanation of symbols]

10、30 大型回路基板 31 基板 2、32 Y方向のスナップライン 3、33 X方向のスナップライン 4 余白連結部 5、35 余白部 6、36 入出力端子 7、37 グランド端子 38 基板のヒビ 9、39 回路基板領域 10, 30 Large circuit board 31 Board 2, 32 Snap line in Y direction 3, 33 Snap line in X direction 4 Margin connection part 5, 35 Margin part 6, 36 Input / output terminal 7, 37 Ground terminal 38 Board crack 9, 39 Circuit board area

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板の端面に厚み方向に延びる凹部を設
け、且つ該凹部の内壁面に端子電極を形成した矩形状の
回路基板となる回路基板領域を、その周囲に余白領域を
設けて縦横に配置して成る大型回路基板であって、 前記回路基板領域と前記余白領域とは、縦横で交差しあ
う余白領域で非連続となる断続した分割溝によって仕切
られるとともに、 前記回路基板領域と前記余白領域との間の分割溝に、前
記凹部となる貫通孔を形成し、該貫通孔の内壁面に隣接
する他の回路基板領域と非導通状態の端子電極を形成し
たことを特徴した大型回路基板。
1. A circuit board region, which is a rectangular circuit board having a concave portion extending in the thickness direction at an end surface of the substrate and having terminal electrodes formed on the inner wall surface of the concave portion, and a blank region provided around the circuit board region. A large circuit board arranged in the circuit board area, and the circuit board area and the blank area are separated by intermittent divided grooves that are discontinuous in a blank area crossing vertically and horizontally, and the circuit board area and the A large-sized circuit, wherein a through-hole serving as the concave portion is formed in a dividing groove between a blank region and a terminal electrode in a non-conductive state with another circuit board region adjacent to an inner wall surface of the through-hole. substrate.
JP2000364702A 2000-11-30 2000-11-30 Large circuit board Expired - Fee Related JP4428853B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000364702A JP4428853B2 (en) 2000-11-30 2000-11-30 Large circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000364702A JP4428853B2 (en) 2000-11-30 2000-11-30 Large circuit board

Publications (2)

Publication Number Publication Date
JP2002171035A true JP2002171035A (en) 2002-06-14
JP4428853B2 JP4428853B2 (en) 2010-03-10

Family

ID=18835594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000364702A Expired - Fee Related JP4428853B2 (en) 2000-11-30 2000-11-30 Large circuit board

Country Status (1)

Country Link
JP (1) JP4428853B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165516A (en) * 2005-12-13 2007-06-28 Matsushita Electric Ind Co Ltd Method of manufacturing chip type network electronic component
JP2007173867A (en) * 2007-03-20 2007-07-05 Koa Corp Substrate for electronic component, and method for manufacturing electronic component
JP2007201274A (en) * 2006-01-27 2007-08-09 Kyocera Corp Multiple patterning wiring board
JP2008160055A (en) * 2006-11-29 2008-07-10 Kyocera Corp Package for housing electronic components, package for multiple housing of electronic components and electronic device, and method of discriminating these
CN117412501A (en) * 2023-11-16 2024-01-16 上海巨传电子有限公司 FPC (Flexible printed Circuit) whole board and FPC circuit board manufacturing process

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165516A (en) * 2005-12-13 2007-06-28 Matsushita Electric Ind Co Ltd Method of manufacturing chip type network electronic component
JP2007201274A (en) * 2006-01-27 2007-08-09 Kyocera Corp Multiple patterning wiring board
JP2008160055A (en) * 2006-11-29 2008-07-10 Kyocera Corp Package for housing electronic components, package for multiple housing of electronic components and electronic device, and method of discriminating these
JP2007173867A (en) * 2007-03-20 2007-07-05 Koa Corp Substrate for electronic component, and method for manufacturing electronic component
CN117412501A (en) * 2023-11-16 2024-01-16 上海巨传电子有限公司 FPC (Flexible printed Circuit) whole board and FPC circuit board manufacturing process

Also Published As

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