JP2002169788A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a plurality of subsystems from mutually resetting due to the dispersion of the timing of monitoring and resetting and the instability of a signal at the time of resetting and to prevent a whole system from stopping. SOLUTION: At least one subsystem in a plurality of subsystems invalidates the reset signal transmitted to the microprocessor of the self-subsystem by the other subsystem while the self-subsystem transmits the reset signal to the microprocessor of the other subsystem. Thus, the careless stop of the system is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a plurality of microprocessors, capable of monitoring runaway from each other and resetting the runaway microprocessor.

[0002]

2. Description of the Related Art A technique relating to a multiprocessor system having a plurality of microprocessors and capable of monitoring runaway from each other and resetting the runaway microprocessor is disclosed in, for example, JP-A-2-206866 and JP-A-3-206866. 38737 and the like. The technique described in Japanese Patent Application Laid-Open No. Hei 2-206866 discloses a technique in which data written by any one of microprocessors to a shared memory shared by a plurality of microprocessors (whether or not data is normal)
Is monitored by another microprocessor to determine whether or not the microprocessor has runaway, and resets the microprocessor that has runaway. Also,
In the technique described in Japanese Patent Application Laid-Open No. 3-38737, each of a plurality of microprocessors of an electric circuit system communicating with each other monitors whether or not communication with a partner is performed within a predetermined time interval. If it is detected that communication with the other party has not been performed for a certain period of time and communication with the other party has been interrupted, the system is stopped in a safe state,
The system is restarted.

[0003]

As described in the above-mentioned publication, when a plurality of microprocessors are provided, and the runaway microprocessors can be monitored, and the runaway microprocessors can be reset, they can be reset to each other. With the configuration, reset timings overlap due to variations and instability of monitoring and reset timings, and the system may be inadvertently stopped. The present invention has been made in view of such problems in the conventional technology, and at least one of a plurality of subsystems transmits a reset signal to a microprocessor of another subsystem. It is an object of the present invention to provide a multiprocessor system in which a reset signal sent from another subsystem to a microprocessor of the own subsystem during the operation is invalidated.

[0004]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a system in which a plurality of subsystems each having a microprocessor are provided with a reset signal for restarting the microprocessor of another subsystem that has runaway. A multiprocessor system having reset signal transmitting means for transmitting, wherein at least one subsystem transmits the reset signal to a microprocessor of another subsystem while the reset signal transmitting means of its own subsystem transmits the reset signal. The reset signal sending means of the other subsystem includes reset signal gate means for invalidating the reset signal sent to the microprocessor of the own subsystem. In the multiprocessor system according to the present invention, at least one of a plurality of subsystems including a microprocessor transmits a reset signal to a microprocessor of another subsystem while another subsystem transmits a reset signal to a microprocessor of another subsystem. Since the subsystem has reset signal gating means to invalidate the reset signal sent to the microprocessor of its own subsystem, multiple subsystems may be monitored due to variations in monitoring and reset timing and instability of the signal at reset. Can be prevented from resetting each other and stopping the entire system. Further, even if the reset signal gating means invalidates the reset signal and the reset signal sending means of the own subsystem stops sending the reset signal to the microprocessor of another subsystem, By maintaining the invalid state of the reset signal for the microprocessor of the own subsystem until all the reset signals for the microprocessor disappear, the influence of the variation in the time during which the reset signal is active can also be prevented. Further, in the multiprocessor system, the reset signal gate means is provided, for example, in a master subsystem that controls the entire system among a plurality of subsystems. Thereby, stop due to mutual reset can be effectively prevented.

[0005]

Embodiments of the present invention will be described below with reference to the accompanying drawings to provide an understanding of the present invention.
The following embodiments are specific examples of the present invention and do not limit the technical scope of the present invention. FIG. 1 shows a schematic configuration of a multiprocessor system according to an embodiment of the present invention. As shown in FIG. 1, a multiprocessor system according to an embodiment of the present invention includes a master board (master subsystem (one of subsystems)) 1
And one peripheral board (subsystem) 2. The master board 1 includes a microprocessor 11, a reset signal sending unit 12, a forced reset unit 13, a reset signal gate unit 14, and the like, and controls the entire multiprocessor system. Signal transmission means 22 and the like are provided. The two microprocessors 11 and 21 periodically monitor each other to determine whether or not the other microprocessors 21 and 11 run away.
When 11 runs out of control, the reset signal sending means 12 and 22 are operated. Reset signal sending means 1
Numerals 1 and 22 are for transmitting reset signals for resetting the microprocessors 21 and 11. The output of the reset signal sending means 12 on the master board 1 side is connected to the reset input 23 of the microprocessor 22 on the peripheral board 2 side. When a negative logic pulse sent by the reset signal sending means 12 is input to the reset input 23, the microprocessor 2 on the peripheral substrate 2 side
1 is reset. On the other hand, the output of the reset signal sending means 22 on the peripheral board 2 side is connected to the input of the reset signal gate means 14 instead of the reset input 15 of the microprocessor 11 on the master board 1 side. The reset input 15 of the microprocessor 11 on the master substrate 1 side is connected to the output of an AND element which receives the output of the reset signal gate means 14 and the output of the forced reset means 13 as inputs.

The reset signal gate means 14 keeps the reset signal transmission means 12 on the master substrate 1 side transmitting the reset signal to the microprocessor 21 on the peripheral substrate 2 side while the reset signal transmitting means 12 on the peripheral substrate 2 side transmits the reset signal. The reset signal sending means 22 invalidates the reset signal sent to the microprocessor 11 on the master substrate 1 side. FIG. 2 shows a specific configuration of the reset signal gate means 14. The reset signal gate means 14
Are, for example, as shown in FIG.
Delay element 142, and element 143, or element 14
4 The output of the reset signal sending means 22 on the side of the peripheral substrate 2 is connected to one input of the or element 144 and one input of the and element 143. The other input of the or element 144 is
The Q output of the flip-flop 141 is connected. The D input of the flip-flop 141 is grounded, the clock pulse input of the flip-flop 141 is the output of the AND element 143, and the preset input of the flip-flop 141 is the reset signal transmitting means on the master substrate 1 side. Twelve outputs are connected. The other input of the AND element 143 is connected to the output of the delay element 142, and the input of the delay element 142 is connected to the output of the reset signal sending means 12 on the master substrate 1 side. And
The output of the or element 144 and the forced reset means 13
Is connected to the input of the AND element 145.
The forcible resetting means 13 is for forcibly resetting the microprocessor 11 on the master substrate 1 at the time of initial operation or the like. The forced reset means 13
Alternatively, when a negative logic pulse is output from the or element 145, the microprocessor 1 on the master substrate 1 side
1 is reset. The reset signal gate means 14
The reset signal transmitting means 22 on the peripheral substrate 1 side
To invalidate the reset signal sent to the microprocessor 11 on the master substrate 1 side in this example, in this example, the input of the and element 143 and the or element 144 (the input of the reset signal gate means 14) is Even if the reset signal sent from the reset signal sending means 22 on the peripheral substrate 2 side is input, no negative logic pulse is output to the output of the or element 144 (the output of the reset signal gate means 14). Means that.

FIGS. 3 and 4 show timing charts corresponding to the reset signal gate means of FIG. As shown in FIG. 3, while a pulse of a negative logic (reset signal) is being output from the forced reset means 13, the reset signal is directly input to the reset input 15 of the microprocessor 11 on the master substrate 1 side. When the microprocessor 11 of the master board 1 is reset, the reset signal sending means 11 of the master board 1 automatically sends the reset signal to the microprocessor 21 of the peripheral board 2 ( (Refer to the master → peripheral reset signal in FIG. 3). At this time, since the reset signal is input to the preset input of the flip-flop 141, the value of the Q output of the flip-flop 141 is set to a value obtained by inverting the reset signal (in this case, H (high)). . On the other hand, as shown by the peripheral → master reset signal in FIG. 3, there is no reset signal from the reset signal sending means 22 on the peripheral board 2 side to the microprocessor 11 on the master board 1 side (H continues. When the reset signal is sent from the reset signal sending means 11 on the master board 1 side to the microprocessor 21 on the peripheral board 2 side, the reset signal is delayed by the delay element 143. A signal (pulse of negative logic) delayed by an amount is input to the clock pulse input of the flip-flop 141. When the signal to the clock pulse input falls, the value of the Q output of the flip-flop 141 is maintained. However, when the signal to the clock pulse input rises after the reset signal is sent, the flip-flop 141 receives the signal. Since the value of the D input of the flip-flop 141 is always L (low), the value of the Q output of the flip-flop 141 changes from H to L. In this way, the Q output of the flip-flop changes as shown in FIG. 3, but in this example, the master board 1 sent from the reset signal sending means 22 on the peripheral board 2 side
Since the state where the reset signal to the microprocessor 11 on the side is not present continues, the forced reset means 1
Only the reset signal from No. 3 is input to the reset input of the microprocessor 11 on the master substrate 1 side.

For example, after the master board 1 and the peripheral board 2 are reset during the initial operation as described above, normal processing is performed, and the two microprocessors 1
1 and 21 are in a state of monitoring each other's runaway. During normal processing, for example, as shown in FIG. 4, when the reset signal is not sent from the reset signal sending means 12 on the master board 1 side to the microprocessor 21 on the peripheral board 2 side, the peripheral board 2 When the reset signal is transmitted from the reset signal transmitting means 21 on the side to the microprocessor 11 on the master substrate 1 side (refer to peripheral → master reset signal), the reset signal is output from the or element 144 as it is, That is, the reset signal is output from the reset signal gate means 14, and the reset signal is input to the reset input 15 of the microprocessor 11 on the master substrate 1 through the AND element 145, and the microprocessor 11 on the master substrate 1 is reset. You. In the meantime, if the reset signal is sent from the reset signal sending means 12 on the master board 1 side to the microprocessor 21 on the peripheral board 2 side (see the master → peripheral reset signal in FIG. 4), the reset signal is sent to the flip-flop. Input to the preset input of the flip-flop 141,
The value of the Q output changes to H, and the output of the or element 144, ie, the output 145 of
Also changes to H. As a result, the reset signal transmitting means 12 on the master substrate 1 side sends the flip-flop 1
While the reset signal is being supplied to the preset input 41, the reset signal sent from the reset signal sending means 22 on the peripheral board 2 to the microprocessor 11 on the master board 1 is invalidated.
When the invalid state of the reset signal is released (when the Q output of the flip-flop 141 becomes L), the reset signal from the reset signal transmitting means 11 on the master substrate 1 side disappears. This is when the time has elapsed since the delay by the delay element 143 (see CLK (corresponding to clock pulse input) and Q (corresponding to Q output) in FIG. 4).

Furthermore, the width of the reset signal temporarily sent by the reset signal sending means 22 on the peripheral board 2 side to the microprocessor 11 on the master board 1 side is as shown in FIG. If the reset signal sent from the reset signal sending means 12 on the master board 1 side to the microprocessor 21 on the peripheral board 2 ceases as shown in FIG. As described above, the state in which the Q output of the flip-flop is H, and thus the invalid state, is caused by the reset signal transmitted by the reset signal transmitting means 22 on the peripheral substrate 2 side to the microprocessor 11 on the master substrate 1 side. Is maintained until disappears. As described above, in the multiprocessor system according to the embodiment of the present invention, the master board that controls the entire system operates while the reset signal sending unit of the own board sends the reset signal to the microprocessor on the peripheral board. And reset signal gate means for invalidating the reset signal sent to the microprocessor by the reset signal sending means of the peripheral board to the master board.
It is possible to prevent the plurality of boards from resetting each other and stopping the entire system due to variations in monitoring and reset timings and instability of signals at the time of reset. Moreover, even if the reset signal gate means invalidates the reset signal and the reset signal sending means on the master board no longer sends the reset signal to the microprocessor on the peripheral board, the reset signal gate means does not send the reset signal to the microprocessor on the master board. Until the reset signal disappears, the reset signal is kept invalid with respect to the microprocessor on the master substrate, so that the influence of the variation in the time during which the reset signal is active can be prevented. Further, since the reset signal gate means is provided in the master subsystem, the stop due to the mutual reset can be effectively prevented.

Although the multiprocessor system according to the embodiment of the present invention is composed of two subsystems, the present invention is not limited to this, and a multiprocessor system having three or more subsystems may be used. It is possible to apply the present invention. For example, FIG. 5 shows three subsystems (master board 1, peripheral board 2,
This is a multiprocessor system including a peripheral board 3), and the reset signal gate means 14 is provided on the master board 1 as in the above embodiment. The configuration shown in FIG. 5 and the case of the embodiment (configuration shown in FIG. 1)
The difference between the two is that the two outputs of the reset signal generating means 12 of the master board 1 are
Reset input 2 of microprocessors 21 and 31 of 3
3 and 33 and the reset signal gate means 14
And not only the output of the reset signal generating means 22 of the peripheral substrate 2 but also the peripheral substrate 3
The output of the reset signal generating means 32 on the side is also connected to the reset signal gate means 14. The specific configuration of the reset signal gate means 14 in this case is as shown in FIG. 6, for example. The difference between the example of FIG. 6 and the example of FIG. 2 is that two and elements 146 and 147 are added to the example of FIG. The and element 146 includes the reset signal sent from the reset signal sending means 12 of the master board 1 to the microprocessor 21 of the peripheral board 2 and the reset signal sent to the microprocessor 31 of the peripheral board 3. The reset signal to be sent is input, and the output of the AND element 146 is used as the preset input of the flip-flop 141 and the delay element 14.
2 inputs. The two inputs of the AND element 147 are connected to the output of the reset signal transmitting means 22 of the peripheral board 2 and the output of the reset signal transmitting means 32 of the peripheral board 3, respectively.
The output of the element 147 is output from the and element 143 and the o element.
Connected to the input of r element 144. That is, in the examples of FIGS. 5 and 6, the reset signal is transmitted from the reset signal transmitting means 12 of the master substrate 1 to at least one of the microprocessors 21 and 31 of the two peripheral substrates 2 and 3. During this period, any of the reset signals to the microprocessor 11 of the master board 1 sent by the reset signal sending means 23, 33 of the peripheral boards 2, 3 are invalidated.

In this case, the initial operation of the master substrate 1
The initial operation of the peripheral substrates 2 and 3 is, for example, as shown in FIG.
(A), as shown in the flowchart of FIG. 7 (b). First, in the master substrate 1, the forced reset means 1
3, the microprocessor 11 is reset (in this case, the same as the initialization) (S101), and then automatically transmitted from the reset signal sending means 12 of the master substrate 1.
The microprocessor 2 of the two peripheral boards 2 and 3
1 and 31 are output (S1
02), the microprocessors 21, 31 of the peripheral boards 2, 3 are reset (S201). Next, the peripheral boards 2 and 3 shift to normal processing (S202), and the master board 1 resets the microprocessor 1 again (S103) and shifts to normal processing (S104). The monitoring operation of the master substrate 1 and the monitoring operation of the peripheral substrates 2 and 3 after shifting to the normal processing are as shown in the flowcharts of FIGS. 7C and 7D, respectively. The master board 1 first checks the response of the peripheral board 2 (of the microprocessor 21) (S105), and determines whether or not the response is normal (S106). If the response is not normal, the reset signal transmitting means 12 of the master substrate 1
Then, the reset signal is sent to the microprocessor 21 of the peripheral board 2 (S107). On the other hand, when the response is normal, or after the reset signal is sent from the reset signal sending means 12 of the master board 1 to the microprocessor 21 of the peripheral board 2, the reset signal of the peripheral board 3 (the microprocessor 31
Is checked (S108), and it is determined whether or not the response is normal (S109). If the response is not normal, the reset signal is sent from the reset signal sending means 12 of the master board 1 to the microprocessor 31 of the peripheral board 3 (S1).
10). On the other hand, when the response is normal, or after the reset signal is sent from the reset signal sending means 12 of the master board 1 to the microprocessor 31 of the peripheral board 3, the steps S105 to S110 are performed.
Is repeated (periodically). In the peripheral boards 2 and 3, a response check (of the microprocessor 11) of the master board 1 is performed in parallel with this (S203), and it is determined whether or not the response is normal. (S204). If the response is not normal, the reset signal sending means 22, 3 of the peripheral boards 2, 3
2 to the microprocessor 11 of the master board 1
, The reset signal is transmitted (S205).
On the other hand, when the response is normal or after the reset signal is sent from the reset signal sending means 22 and 32 of the peripheral boards 2 and 3 to the microprocessor 11 of the master board 1, the steps S203 to S203 are executed. S20
5 is repeated (periodically).

[0012]

As described above, in the multiprocessor system according to the present invention, at least one of a plurality of subsystems including a microprocessor has its own subsystem reset to the microprocessor of another subsystem. Since the reset signal gate means disables the reset signal sent from other subsystems to the microprocessor of the own subsystem while the signal is being sent, fluctuations in monitoring and reset timing and reset signals are provided. , The plurality of subsystems can be prevented from resetting each other and stopping the entire system. Further, even if the reset signal gate means invalidates the reset signal and the own subsystem stops sending the reset signal to the microprocessors of the other subsystems, all the resets for the microprocessors of the own subsystem are performed. By keeping the reset signal invalid for the microprocessor of the own subsystem until the signal disappears, it is possible to prevent the influence of variations in the time during which the reset signal is active. Further, in the multiprocessor system, if the reset signal gating means is provided in a master subsystem that controls the entire system among a plurality of subsystems, stop due to mutual reset can be effectively prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration example of reset signal gate means provided in the multiprocessor system according to the embodiment of the present invention.

FIG. 3 is a timing chart for explaining an operation example of the reset signal gate unit shown in FIG. 2;

FIG. 4 is a timing chart illustrating another operation example of the reset signal gate unit shown in FIG. 2;

FIG. 5 is a diagram showing a schematic configuration of a multiprocessor system according to an embodiment of the present invention.

FIG. 6 is a diagram showing a specific configuration example of reset signal gate means provided in the multiprocessor system according to the embodiment of the present invention.

FIG. 7 is a flowchart illustrating an example of an initial operation and a monitoring operation of each subsystem in the multiprocessor system according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Master board 2, 3 ... Peripheral board 11, 21, 31 ... Microprocessor 12, 22, 32 ... Reset signal sending means 14 ... Reset signal gate means

Claims (3)

[Claims] 1. A multiprocessor system comprising reset signal transmitting means for transmitting a reset signal for restarting a microprocessor of another subsystem which has runaway, wherein each of the plurality of subsystems having a microprocessor is at least one of: In one subsystem, while the reset signal sending means of the own subsystem sends the reset signal to the microprocessor of another subsystem, the reset signal sending means of the other subsystem sends the reset signal to the microprocessor of the own subsystem. A multiprocessor system comprising reset signal gate means for invalidating the reset signal sent to a processor. 2. The method according to claim 1, wherein said reset signal gating means invalidates said reset signal and said reset signal sending means of the own subsystem stops sending said reset signal to a microprocessor of another subsystem. 2. The multiprocessor system according to claim 1, wherein the reset signal for the microprocessor of the own subsystem is kept invalid until all the reset signals for the microprocessor of the subsystem disappear. 3. The multiprocessor system according to claim 1, wherein said reset signal gate means is provided in a master subsystem which controls the entire system among a plurality of subsystems.