JP2002169769A - Bus master and bus mediating system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus master mediating circuit where a bus master can be added and extendibility is easy and to provide the bus master for the same. SOLUTION: A bus master (203) can be connected between a high-order bus mediating circuit (202) or a bus mediating circuit in a high-order bus master and plural low-order bus masters (204) and it includes a bus mediating circuit in a bus master (213). When the bus mediating circuit in the bus master (213) receives a plurality of bus request signals from a plurality of low-order bus masters (204 and 207), they mediate them and can transfer the received bus request signals to the high-order bus mediating circuit (202). The bus mediating circuit in the bus master (213) can transmit a bus permission signal to one of the low-order bus masters based on the bus permission signal from the high- order bus mediating circuit (202) and the result of mediation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus master and a bus arbitration system, and more particularly to a bus master having a bus arbitration circuit therein.

[0002]

2. Description of the Related Art A system bus is used for transmitting and receiving information such as data signals and address signals between devices in a computer system. The system bus is
Because multiple devices are shared, only one sending device at a time sends information on the bus and one or more receiving devices selectively receive that information to avoid collision with other information. Need to be controlled. Therefore, a management mechanism (a bus arbiter or a bus arbitration circuit) for arbitrating the right to use the bus, that is, the right to send information, is required.

FIG. 1 shows such a conventional bus arbitration circuit 1.
2 illustrates a bus arbitration system including the H.02. On the bus 101,
Bus arbitration circuit 102 and bus masters 103 and 10
4, 105 are connected. Three-system bus arbitration circuit 10
Reference numeral 2 denotes a bus master 1 which is fully connected to three bus masters 103 to 105 and is an arbitration slave desiring to use the bus.
It is an arbitration master that manages which of 03 to 105 is given the right to use the bus. The bus arbitration circuit is sometimes incorporated in the CPU. As in the conventional example, a single bus arbitration circuit can be formed by combining general-purpose logics. Hereinafter, a protocol for the bus master to obtain the right to use the bus will be described.

For example, when the bus master 103 receives a bus request signal BR
To the bus arbitration circuit 102. Upon receiving the bus request signal BR, the bus arbitration circuit 102
When it is determined that the bus use right may be permitted to the bus master 103, a bus permission signal is asserted to the bus master 103 to notify that the bus becomes available at the end of the current bus cycle. Bus master 1 that has received the bus permission signal
03 may be configured to assert the bus permission acknowledge signal, indicating that the user has obtained the right to use the bus,
Data is transmitted using a bus. Since the bus acknowledge signal is not essential to the present invention, it will not be specifically described herein. Each bus master sends a bus request signal at any time during or between bus cycles.
BR can be issued.

[0005]

In a conventional bus arbitration system, a three-system bus arbitration circuit 1 as shown in FIG.
02 cannot be added even if it is desired to add a fourth bus master, and the bus arbitration system cannot be expanded. In order to expand the bus arbitration system, it is necessary to add an additional input / output terminal and an additional internal circuit to the bus arbitration circuit 102, which is practically impossible.

If the expansion of the bus master can be expected from the beginning, it is sufficient to prepare a sufficient amount of input / output terminals and internal circuits for the bus arbitration circuit. However, in this case, for example, if expansion of ten bus masters is enabled, an extra 2 × 10 pins are required, which leads to an increase in the number of pins, an increase in cost, and an increase in area, which is not practical.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bus master arbitration circuit to which a bus master can be added and which is easily expandable, and a bus master therefor.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a bus arbitration system according to an embodiment of the present invention.
2 are connected. The bus system may be a synchronous bus that transfers data or the like in synchronization with the system clock, an asynchronous bus that transfers data while the transmitting side and the receiving side each receive confirmation by handshaking, and an address bus. A pipelined bus that requires arbitration for both data buses may be used, and a bus system of any transfer system may be used. The bus arbitration circuit 202 may be a single arbitration circuit or an arbitration circuit built in the CPU, and may be any number of systems. However, the bus arbitration circuit 202 is illustrated as two arbitration circuits for simplicity of description. An arbitration circuit 202 and bus masters 203, 204, 20
5, 206, 207 and 208 are connected. A bus master is a device that controls the system bus by outputting address control and control commands, such as a CPU, a numerical coprocessor, and a DMA controller, but may transmit data and the like to the system bus. Anything is fine. Normally, each bus master is provided with a bus driver which is a drive circuit for sending a signal to the bus, but is not essential for the description of the present invention, and thus the description is omitted here.

Two-system bus arbitration circuit 20 serving as arbitration master
2 is an arbitration slave that is connected to the two bus masters 203, 206,
206 is used to manage the right to use the bus. Normally, the bus arbitration circuit 202 monitors the bus 201, and grants the bus master a use right based on the result. There is also a system in which bus arbitration is performed by giving priority to the usage right of the bus master, but the description is omitted here for simplicity.

The bus master 203 has a lower bus master 2
04, 207 are connected, and the lower bus masters 204, 2
07 further have lower bus masters 205 and 2 respectively.
08 are cascaded. Inside each bus master, bus arbitration circuits 213, 214, 215, 216, 207, and 20 within the bus master similar to the bus arbitration circuit 202 are provided.
8 are provided. These arbitration circuits are three-system bus arbitration circuits that arbitrate bus requests from three bus masters, that is, their own bus master and two lower-order bus masters.
Instead of spontaneously issuing a bus permission signal, the bus permission signal from the bus arbitration circuit 202 is simply transferred. Hereinafter, a protocol for the bus master to obtain the right to use the bus will be described.

For example, the bus master 204 and the bus master 207 each transmit a bus request signal BR to the bus master 203.
Assert for The bus master 203 receives the bus request signal BR from the bus master 204 and the bus master 207.
From the bus request signal BR to the bus arbitration circuit 202,
The bus arbitration circuit 213 in the bus master arbitrates for these bus request signals. The bus permission signal issued as a result of the arbitration is not directly transmitted to the lower bus master, but is used for controlling the bus permission signal from the bus arbitration circuit 202 as described later. The bus arbitration circuit 202 that has received the bus request signal BR does not know that those bus request signals have been issued from the lower bus masters of the bus master 203, and recognizes them as if they were issued by the bus master 203. I do. Bus arbitration circuit 2
02, when it is determined that the bus master 203 may be granted the right to use the bus, a bus grant signal is sent to the bus master 20.
Assert 3 to signal that the bus will be available at the end of the current bus cycle. The bus master 203 that has received the bus permission signal transfers the bus permission signal from the bus arbitration circuit 202 to a lower-order bus master that has determined that the use right can be permitted as a result of arbitration by the internal bus arbitration circuit 213 in the bus master. . Upon receiving the bus permission signal, the bus master 204 knows that it has obtained the right to use the bus, and transmits data and the like using the bus. Each bus master can issue the bus request signal BR at any time during a bus cycle or between cycles.

FIG. 3 is a block diagram for explaining the operation of the bus arbitration circuit 202. The arbitration circuit 212 receives the bus request signal BR0 from the bus master 203 and the bus master 206
Arbitrates by receiving the bus request signal BR1 from the
1 is monitored, and when it is determined that a bus permission signal may be issued, a bus permission signal is issued. Here, it is assumed that a bus permission signal BG0 is issued to the bus master 203.

FIG. 4 is a block diagram for explaining the operation of the bus arbitration circuit 213 in the bus master inside the bus master 203. The bus arbitration circuit 213 is connected to the bus master 20.
4 and a bus request signal BR1 from the bus master 207 to receive and arbitrate. Bus arbitration circuit 2
23 is shown as two systems for the sake of simplicity, but may be three or more systems. Bus request signal BR0,
BR1 also has an OR circuit or wired OR connection,
The data is transferred to a higher-order bus master, or to the bus arbitration circuit 202 in the example of FIG. The bus permission signal BG0 of FIG.
Is the bus enable signal switching circuit 2 as the reception signal BGin in FIG.
33 is input. Assuming that the bus arbitration circuit 223 outputs the bus permission signal C0 as a result of the arbitration, the signal C0 becomes high and the signal C1 becomes low, and the reception signal BGin becomes the bus permission signal BG0 by the two AND circuits and becomes the bus master. 204
Only forwarded to. Bus arbitration circuits 202 and 213
Are circuits having exactly the same function, so that while BGin is active, C0 and BGin of the arbitration circuit 223 have the same signal waveform. As a result, the bus permission signal given to the arbitration circuit 204 is
The signal waveform becomes the same as that of BGin, and the bus master 204 operates exactly the same as when a bus permission signal is directly obtained from the arbitration circuit 202. The bus permission signal is active high here, but may be active low or another type of signal. Although the bus permission signal switching circuit is shown as two AND circuits, any circuit may be used depending on the format of the bus permission signal.

The bus master 204 that has received the bus permission signal
Knows that he has obtained the right to use the bus, and transmits data and the like using the bus. All the bus masters may have a bus arbitration circuit inside, or only the bus master following the lower-order bus master may have the bus arbitration circuit. By cascading bus masters having a bus arbitration circuit, the upper arbitration circuit need only arbitrate bus requests from a predetermined number of lower bus masters.

[0015]

According to the above embodiment, when designing a system requiring bus arbitration, it is easy to add a bus arbitration slave, and there is no need to change the bus arbitration master. When the signal delay time does not matter, the number of bus arbitration slaves to be connected is not limited, and cascade connection can be performed one after another due to self-expandability. When incorporated into a semiconductor IC, the number of terminals for bus arbitration signals can be reduced.

[Brief description of the drawings]

FIG. 1 shows a bus arbitration system including a conventional bus arbitration circuit.

FIG. 2 illustrates a bus arbitration system with an arbitration circuit in a bus master according to one embodiment of the present invention.

FIG. 3 is a block diagram illustrating an operation of the bus arbitration circuit 202 of FIG. 2;

FIG. 4 is a block diagram for explaining an operation of the bus arbitration circuit 213 in the bus master of FIG. 2;

[Explanation of symbols]

 201 Bus 202 Bus arbitration circuit 203-208 Bus master 213-218 Bus master arbitration circuit 233 Bus permission signal switching circuit

Claims (6)

[Claims] 1. A bus master connectable between an upper bus arbitration circuit or a bus arbitration circuit in an upper bus master and a plurality of lower bus masters in a bus arbitration system, including a bus arbitration circuit in the bus master; When the bus arbitration circuit in the bus master receives a plurality of bus request signals from a plurality of lower bus masters, the bus arbitration circuit can arbitrate them and transfer the received bus request signals to an upper bus arbitration circuit; And the bus arbitration circuit in the bus master,
A bus master, which can transmit a bus permission signal to one of the plurality of lower-level bus masters based on a bus permission signal from a higher-level bus arbitration circuit and a result of the arbitration. 2. The bus master according to claim 1, wherein transmission of a bus permission signal to a lower-level bus master based on a bus permission signal from the higher-level bus arbitration circuit and a result of the arbitration is performed, A bus master, which is achieved by a bus enable signal switching circuit. 3. The bus master according to claim 1, wherein the transfer of the received bus request signal to an upper bus arbitration circuit is achieved by an OR circuit. 4. A bus arbitration system including a bus, a bus arbitration circuit connected to the bus, an upper bus master connected to the bus and the bus arbitration circuit, and a lower bus master connected to the bus and the upper bus master, wherein the upper bus master is a bus master. An internal bus arbitration circuit; the bus master internal bus arbitration circuit arbitrates a plurality of bus request signals from a plurality of lower bus masters when the bus request signals are received, and transfers the received bus request signals to an upper bus arbitration circuit. And the bus arbitration circuit in the bus master transmits a bus permission signal to one of the plurality of lower-level bus masters based on a bus permission signal from a higher-level bus arbitration circuit and a result of the arbitration. A bus arbitration system. 5. The bus arbitration system according to claim 4, wherein the bus arbitration circuit transmits a bus permission signal to a lower-level bus master based on a bus permission signal from the higher-level bus arbitration circuit and a result of the arbitration. Is achieved by a bus enable signal switching circuit in an upper bus master; 6. The bus arbitration system according to claim 4, wherein the transfer of the received bus request signal to an upper bus arbitration circuit is achieved by an OR circuit in an upper bus master. Features a bus arbitration system.