JP2002165134A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption and prevent deterioration of image quality. SOLUTION: A vertical transfer register 106 fetches electric charges, which a photoelectric conversion device 104 in each array generates through light reception, through synchronizing with a vertical synchronous signal 118, and transfers the electric charges in order to a horizontal transfer register 110 through synchronizing with vertical transfer clocks from ϕV1 to ϕV4. The horizontal transfer register 110 introduces the electric charges fetched from the vertical transfer register 106 synchronized with a horizontal synchronizing signal 120, and transfers the electric charges in the direction of a FD region 114 through synchronizing with horizontal transfer clocks ϕH1 and ϕH2. The electric charges fetched from the horizontal transfer register 110 become image signals, by being converted into a voltage in the FD region 114, and are outputted to outsides through an output circuit 116. Then a switching control part 6 outputs control signals 10, in order to cut off the switching part 4 during vertical and horizontal blanking periods, and as a result, power will not be supplied to the output circuit 116 during the blanking periods, and the output circuit 116 stops its operation and will not consume power.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state imaging device.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional solid-state imaging device. Conventional solid-state imaging device 1 shown in FIG.
Reference numeral 02 denotes an interline transfer type solid-state imaging device as an example, which includes a large number of photoelectric conversion elements 104, a vertical transfer register 106, a vertical transfer register driving circuit 108, a horizontal transfer register 110, and a horizontal transfer register driven in a matrix. The circuit 112 includes a floating diffusion (FD) region 114 and an output circuit 116.

The vertical transfer register 106 and the horizontal transfer register 110 are both CCD (Charge C).
The vertical transfer register 106 is provided for each column of the photoelectric conversion elements 104, and simultaneously captures, in synchronization with the vertical synchronization signal 118, electric charges generated by receiving the light by the photoelectric conversion elements 104 in each column. At the same time, the four-phase vertical transfer clocks φV1, φV2, φV3,
The data is sequentially transferred in the direction of the horizontal transfer register 110 in synchronization with φV4.

On the other hand, the horizontal transfer register 110 transfers the electric charges transferred by the plurality of vertical transfer registers 106 to each other.
The two-phase horizontal transfer clock φH generated by the horizontal transfer register drive circuit 112 is simultaneously input from the vertical transfer registers 106 in synchronization with the horizontal synchronization signal 120.
1. The acquired charges are sequentially transferred in the direction of the FD region 114 in synchronization with φH2. Then, the charges transferred by the horizontal transfer register 110 are converted into a voltage in the FD region 114 to become a video signal 115, which is output to the outside of the solid-state imaging device 102 through the output circuit 116 with low impedance.

[0005]

By the way, in recent years, with the increase in definition of a photographed image, this type of solid-state imaging device 102
(Therefore, the number of photoelectric conversion elements 104) tends to increase more and more. Further, the solid-state imaging device 102
In order to reduce the size and weight of the device incorporating the, it is required that the size of the solid-state imaging device 102 be smaller. However, when the number of pixels increases, the frame cycle is constant, so that the charge transfer speed in the vertical transfer register 106 and the horizontal transfer register 110 must be increased, and the driving frequency of the vertical transfer register 106 and the horizontal transfer register 110 increases. As a result, the power consumption of the solid-state imaging device 102 increases.

In order to reduce the size of the solid-state imaging device 102, the size of each photoelectric conversion element 104 must be reduced.
4 reduces the amount of charge generated. Therefore,
The output circuit 116 must be designed so that the power supply voltage and the current flowing through the circuit have sufficiently large values in order to secure a required SN ratio. As a result, the output circuit 116
In this case, the power consumption also increases.

When the power consumption of the solid-state imaging device 102 increases, the temperature of the solid-state imaging device 102 increases,
As characteristics of a solid-state imaging device using a semiconductor photoelectric conversion element and a CCD, fixed pattern noise and dark current shot noise increase, and image quality deteriorates. Further, if the temperature rise is severe, the absolute maximum rating of the solid-state imaging device will be exceeded, resulting in thermal damage and a shortened life.

The present invention has been made to solve these problems, and its object is to reduce power consumption and
An object of the present invention is to provide a solid-state imaging device that prevents deterioration of image quality due to a rise in temperature.

[0009]

According to the present invention, in order to achieve the above object, a plurality of photoelectric conversion elements arranged in a row and electric charges generated by receiving light by each photoelectric conversion element are taken in synchronization with a synchronization signal. A charge transfer register that sequentially transfers the captured charges in synchronization with a transfer clock, and an output circuit that outputs a video signal generated from the charges transferred by the charge transfer register to the outside with low impedance,
A solid-state imaging device in which the charge transfer register sequentially outputs charges for one row of the photoelectric conversion elements in a period outside a blanking period in each cycle of a synchronization signal, wherein power supply to the output circuit is turned on / off. A switching unit that is turned off, and a switching unit that supplies a control signal to the switching unit to control the switching unit, and that turns off power supply to the output circuit during the blanking period or a period substantially matching the blanking period. And a control unit.

Further, according to the present invention, there are provided a plurality of photoelectric conversion elements arranged in a matrix, and a vertical synchronization signal which is provided for each column of the photoelectric conversion elements and generated by the photoelectric conversion elements in each column. A plurality of vertical transfer registers for sequentially transferring the received charges in synchronization with a vertical transfer clock, and simultaneously capturing the charges transferred by the plurality of vertical transfer registers in synchronization with a horizontal synchronization signal, A horizontal transfer register for sequentially transferring the received charges in synchronization with a horizontal transfer clock; and an output circuit for outputting a video signal generated from the charges transferred by the horizontal transfer register to the outside with low impedance, wherein the vertical transfer From the register, the charges of all photoelectric conversion elements are sequentially stored in a period outside the vertical blanking period in each cycle of the vertical synchronization signal. A solid-state imaging device in which the horizontal transfer register sequentially outputs charges taken in at one time from the vertical transfer registers into the horizontal transfer register during a period outside the horizontal blanking period in each cycle of the horizontal synchronization signal. A switching unit for turning on / off a power supply to the output circuit; and supplying a control signal to the switching unit to control the switching unit;
A switching control unit that turns off power supply to the output circuit during the vertical blanking period and the horizontal blanking period, or during a period substantially corresponding to these blanking periods.

In the solid-state imaging device according to the present invention, the switching control unit controls the switching unit by supplying a control signal to the switching unit, and supplies a power supply to the output circuit during a blanking period or a period substantially coincident with the blanking period. Turn off the supply. Therefore, the output circuit stops operating during the blanking period when there is no need to output the video signal,
Since no power is consumed, power consumption of the solid-state imaging device can be reduced.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of the solid-state imaging device according to the present invention. 2A and 2B are timing charts showing driving pulses of the solid-state imaging device of FIG. 1, wherein FIG. 2A shows a vertical transfer clock, FIG. 2B shows a vertical transfer clock when the time axis is elongated, and FIG. The horizontal transfer clocks near the signals are shown. 3A is a timing chart illustrating a control signal generated by a switching control unit included in the solid-state imaging device illustrated in FIG. 1, and FIG. 3B is a timing chart illustrating the control signal in detail by extending a time axis. is there. In FIG. 1, the same elements as those in FIG. 5 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

The solid-state imaging device 2 shown in FIG. 1 differs from the conventional solid-state imaging device shown in FIG. 5 in that a switching unit 4 and a switching control unit 6 are newly provided.
The switching unit 4 is inserted in series with the power supply line 8 to turn on / off the power supply to the output circuit 116. Then, the switching control unit 6 controls the switching unit 4
To control the switching unit 4 by supplying a control signal 10 to the
The power supply to the output circuit 116 is turned off during a blanking period of the vertical synchronizing signal 118 and the horizontal synchronizing signal 120 or a period substantially matching the blanking period.

Next, the operation of the solid-state imaging device 2 configured as described above will be described. First, driving of the vertical transfer register 106 and the horizontal transfer register 110 will be described with reference to a timing chart. As shown in FIG. 2A, the vertical transfer register drive circuit 108, based on the vertical synchronizing signal 118 and the horizontal synchronizing signal 120, controls the four-phase vertical transfer clocks φV1, φV2, φV3 and φV4 are generated and supplied to each vertical transfer register 106. FIG. 2A shows an example of a period of an even field. In practice, the even field is followed by an odd field, and each frame is constituted by the even field and the odd field.

FIG. 2B shows the vicinity of the period ta in FIG. 2A in detail, and shows the vertical transfer clocks φV 1 and φV 1.
V3 is a period during which the horizontal synchronization signal 120 is at a low level,
That is, in the horizontal blanking period 12, they become low level and middle level at predetermined timings, respectively.
At other points, the level is the middle level and the low level, respectively. However, the vertical transfer clocks φV1, φV3
Are at the high level at the timing when the vertical synchronization signal 118 changes from the low level to the high level, that is, at the timing when the vertical blanking period 14 ((A) in FIG. 2) ends. The vertical transfer clock φV3 is at the middle level near the timing of the high level.

The vertical transfer clocks .phi.V2 and .phi.V4 are at the low level and the middle level respectively during the horizontal blanking period 12, and at the other levels respectively. However, the vertical transfer clock φV2 goes low near the timing when the vertical transfer clock φV1 goes high as described above.

On the other hand, the horizontal transfer register drive circuit 112
The horizontal synchronizing signal 12 is based on the horizontal synchronizing signal 120 as shown in FIG.
0 horizontal transfer clocks φH1 and φ
H2 is generated and supplied to the horizontal transfer register 110.
The horizontal transfer clocks φH1 and φH2 are constant at a high level and a low level, respectively, during the horizontal blanking period 12, and during periods other than the horizontal blanking period 12,
The clocks have the same frequency and the opposite phase and the same duty ratio.

As described above, the vertical transfer clocks φV1, φV1
When V3 goes high at the end of the vertical blanking period 14, each photoelectric conversion element 104 stores the corresponding photoelectric conversion element 1 in the corresponding vertical transfer register 106.
The signal charges generated by receiving light at 04 are taken in at once. At this time, as described above, the vertical transfer clock φV2 is at the low level and φV4 is at the middle level for a certain period of time, so that the backflow of the charges taken into the vertical transfer register 106 is prevented.

Thereafter, the vertical transfer clocks φV1 to φV4
As described above, each time the signal level goes low and high in each horizontal blanking period 12, the signal charge taken into the vertical transfer register 106 is transferred horizontally by two cells (charge storage units) of the vertical transfer register 106. The data is transferred in the direction of the register 110. Here, 1
The transfer of electric charge for two cells during one horizontal blanking period is due to the interlace operation.

At this time, the signal charges output from the respective vertical transfer registers 106 are simultaneously taken into the horizontal transfer register 110 in synchronization with the horizontal synchronizing signal. After that, when the horizontal blanking period 12 ends, (C) in FIG. )
Are sequentially transferred to the FD area 114 in synchronization with the horizontal transfer clocks φH1 and φH2 shown in FIG. The transferred signal charge is converted into a voltage in the FD area 114, and the video signal 11
5 is supplied to the output circuit 116. Output circuit 116
Converts this video signal into a low-impedance solid-state
Output to the outside of.

By repeating such an operation, the signal charges taken into each vertical transfer register 106 are converted into a video signal and output from the output circuit 116, and the operation for one field is completed. In the subsequent field, a video signal is generated by the same operation except that the signal charge supplied from the vertical transfer register 106 to the horizontal transfer register 110 is shifted by one cell due to the interlace operation.

In the solid-state imaging device 2 of the present embodiment, at the same time as this operation, the switching control unit 6 performs the vertical blanking period based on the vertical synchronizing signal 118 and the horizontal synchronizing signal 120 as shown in FIG. During the period 14 and the horizontal blanking period 12, the control signal 10 having a low level is generated and output to the switching unit 4. The switching unit 4 is turned on when the control signal 10 is at a high level, and turned off when the control signal 10 is at a low level. Therefore, only when the control signal 10 is at the high level, the output circuit 11
6, the output circuit 116 operates, and when the control signal 10 is at a low level, no power is supplied to the output circuit 116, and the output circuit 116 stops operating.

Even if the operation of the output circuit 116 is stopped during the horizontal blanking period 12, no signal charge is output from the horizontal transfer register 110 and no video signal is output from the FD region 114 during this period. No problem. Also, vertical blanking period 1
Even if the operation of the output circuit 116 is stopped in step 4, the transfer of the signal charges taken from the photoelectric conversion element 104 into the vertical transfer register 106 is completed in a period outside the vertical blanking period 14, and the image for one field Since the signal is output from the FD area 114, no problem occurs.

By stopping the operation of the output circuit 116 during the vertical blanking period 14 and the horizontal blanking period 12 as described above, no power is consumed by the output circuit 116 during these periods. 2 can reduce power consumption. As a result, problems such as deterioration of image quality due to an increase in fixed pattern noise and dark current shot noise due to an increase in temperature of the solid-state imaging device 2 and thermal damage and shortening of the life of the solid-state imaging device 2 due to a large temperature increase are caused. It is possible to solve the problem of inviting.

The switching control unit 6 may be formed on the same semiconductor chip as the photoelectric conversion element 104 and each charge transfer register. Alternatively, the switching control unit 6 may be provided outside the semiconductor chip and externally supply the control signal 10 to the switching unit. 4 may be provided. Here, the case where the present invention is applied to the solid-state imaging device 2 of the interline transfer system has been described as an example. However, the present invention is of course effective for the solid-state imaging device of the frame transfer system and the frame interline transfer system. is there. In the present embodiment, the low-level periods of the vertical synchronizing signal 118 and the horizontal synchronizing signal 120 correspond to the vertical blanking period 14 respectively.
And the horizontal blanking period 12. However, the period in which the synchronization signal is at a specific logic level and the blanking period need not necessarily match, and the period in which the synchronization signal is at a low level, for example, is longer than the blanking period. It can be short or long.

The solid-state imaging device 2 in which the photoelectric conversion elements 104 are arranged in a matrix form captures a plurality of photoelectric conversion elements arranged in a line and charges generated by receiving light by each photoelectric conversion element and synchronizes with the transfer clock. Therefore, it is easy for those skilled in the art to implement the present invention in a linear sensor based on the present embodiment since the configuration includes a linear sensor including a charge transfer register for sequentially transferring the data.

[0027]

FIG. 4 is a circuit diagram showing a specific example of the output circuit 116 and the switching section 4 shown in FIG. In this example, the output circuit 116 is a three-stage source follower circuit 16
It consists of. Each source follower circuit 16 is composed of field effect transistors 18 and 20, the drain of the field effect transistor 18 is connected to the power supply line 8, the source is connected to the drain of the field effect transistor 20, and the source of the field effect transistor 20 is connected to the ground 22. Have been.

The FD region 114 is connected to the gate of the field effect transistor 18 forming the leading source follower circuit 16.
, While a bias voltage Vgg is applied to the gate of the field-effect transistor 20 at each stage. The gates of the second-stage and third-stage field-effect transistors 18 are connected to the source of the previous-stage field-effect transistor 18, and a video signal is taken out as an output signal from the source of the final-stage field-effect transistor 18, and the solid-state imaging is performed. It is output to the outside of the device 2. Also,
The switching unit 4 is a field effect transistor 2 in this embodiment.
The drain of the field-effect transistor 24 is connected to the power supply Vdd, the source is connected to the power supply line 8, and the control signal 10 is supplied to the gate from the switching control unit 6.

When the high-level control signal 10 is supplied from the switching control unit 6, the field effect transistor 24 is turned on, power is supplied to each source follower circuit 16, and the output circuit 116 operates. When the low-level control signal 10 is supplied from the control unit 6, the field-effect transistor 24 is turned off, and power is not supplied to each source follower circuit 16, and the output circuit 11
6 stops the operation.

It should be noted that, as shown in FIG.
May be supplied to the gate of the field effect transistor 24 via a resistor for adjusting the signal level of the control signal 10, and the gate may be supplied to remove noise mixed in the control signal 10. It is also effective to adopt a configuration in which a capacitor is connected to the periphery.

When the waveform of the control signal 10 is dull, there is a slight delay before the switching section 4 is turned on and power is supplied to the output circuit 116.
Therefore, in anticipation of this delay, it is effective to generate the control signal 10 so that it becomes high level slightly before the end of each blanking period. Control signal 1
In a case where switching noise is mixed in the video signal when the level is switched to 0, it is effective to generate the control signal 10 so that the control signal 10 becomes low level slightly after the start of each blanking period.

[0032]

As described above, in the solid-state imaging device according to the present invention, the switching control section supplies a control signal to the switching section to control the switching section, and the switching period substantially coincides with the blanking period. The power supply to the output circuit is turned off during the period. Therefore, during a blanking period in which there is no need to output a video signal, the output circuit stops operating and consumes no power, so that power consumption of the solid-state imaging device can be suppressed. In addition, as a result, there is a problem that image quality is degraded due to an increase in fixed pattern noise and dark current shot noise due to a rise in the temperature of the solid-state imaging device, and thermal damage and a reduction in the life of the solid-state imaging device due to a large temperature rise. The problem can be solved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a solid-state imaging device according to the present invention.

FIG. 2A is a timing chart showing a vertical transfer clock of the solid-state imaging device, FIG. 2B is a timing chart showing a vertical transfer clock when a time axis is extended,
(C) is a timing chart showing a horizontal transfer clock near the horizontal synchronization signal.

3A is a timing chart illustrating a control signal generated by a switching control unit included in the solid-state imaging device in FIG. 1; FIG. 3B is a timing chart illustrating the control signal in detail by extending a time axis; .

FIG. 4 is a circuit diagram showing a specific example of an output circuit and a switching unit shown in FIG.

FIG. 5 is a block diagram illustrating an example of a conventional solid-state imaging device.

[Explanation of symbols]

2 ... solid-state imaging device, 4 ... switching unit, 6 ... switching control unit, 8 ... power supply line, 10 ... control signal,
12 horizontal blanking period, 14 vertical blanking period, 16 source follower circuit, 18 field effect transistor, 20 field effect transistor, 22 ground, 24 field effect transistor, 102 ... Solid-state imaging device, 104 photoelectric conversion element, 106 vertical transfer register, 108 vertical transfer register drive circuit, 110 horizontal transfer register, 112 horizontal transfer register drive circuit, 114
... FD area, 116 ... output circuit, 118 ... vertical synchronization signal, 120 ... horizontal synchronization signal.

Claims (6)

[Claims] 1. A plurality of photoelectric conversion elements arranged in a row, and charges generated by receiving light by each of the photoelectric conversion elements are captured in synchronization with a synchronization signal, and the captured charges are sequentially transferred in synchronization with a transfer clock. A charge transfer register, and an output circuit for outputting a video signal generated from the charges transferred by the charge transfer register to the outside at a low impedance, wherein the charge transfer register outputs a video signal outside a blanking period in each cycle of the synchronization signal. A solid-state imaging device in which charges of one row of the photoelectric conversion elements are sequentially output during the period of: a switching unit that turns on / off power supply to the output circuit; and a control signal that supplies a control signal to the switching unit. Controlling a switching unit to supply power to the output circuit during the blanking period or during a period substantially matching the blanking period; A solid-state imaging apparatus characterized by comprising a switching control unit to turn off the supply. 2. A large number of photoelectric conversion elements arranged in a matrix, and a charge provided by each of the photoelectric conversion elements provided for each column of the photoelectric conversion elements and received and generated in synchronization with a vertical synchronization signal. At the same time, a plurality of vertical transfer registers for sequentially transferring the fetched charges in synchronization with a vertical transfer clock, and the charges transferred by the plurality of vertical transfer registers are simultaneously fetched in synchronization with a horizontal synchronization signal, and the fetched charges are A horizontal transfer register for sequentially transferring in synchronization with a horizontal transfer clock, and an output circuit for outputting a video signal generated from the charges transferred by the horizontal transfer register to the outside with low impedance, from the vertical transfer register, The charges of all the photoelectric conversion elements are sequentially output in a period outside the vertical blanking period in each cycle of the vertical synchronization signal, and From the flat transfer register, in a period outside the horizontal blanking period in each cycle of the horizontal synchronization signal, a solid-state imaging device in which the charges taken in at once from each vertical transfer register into the horizontal transfer register are sequentially output, A switching unit for turning on / off a power supply to the output circuit; a control signal supplied to the switching unit to control the switching unit; the vertical blanking period and the horizontal blanking period; A solid-state imaging device comprising: a switching control unit that turns off power supply to the output circuit during a period substantially coincident with the period. 3. The switching control section supplies the control signal for turning off the power supply to the output circuit a little after the start of the blanking period, and supplies the power supply slightly before the end of the blanking period. The solid-state imaging device according to claim 1, wherein the control signal that turns on is supplied to the output circuit. 4. The switching unit includes a field effect transistor, and a channel of the field effect transistor is inserted in series with a power supply line of the output circuit.
The solid-state imaging device according to claim 1, wherein the switching control unit supplies the control signal to a gate of the field-effect transistor. 5. The solid-state imaging device according to claim 1, wherein said output circuit is constituted by a multi-stage source follower circuit. 6. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is an interline transfer system, a frame transfer system, or a frame interline transfer system.