JP2002163242A - Data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer the transferred data at high speed and with good efficiency to a shared memory in processing the data by a plurality of processors. SOLUTION: A transfer end detecting circuit 5 provided in this data processing system 1 outputs an interrupt request signal IRQ2 to a slave processor 3 when a master processor 2 gains a write access to a specified address a1 of the shared memory 6, and outputs an interrupt request signal IRQ1 to the master processor 2 when the slave processor 3 gains a write access to a specified address a2 of the shared memory 6, and storage of transferred data in the shared memory 6 is recognized by the master processor 2 or the slave processor 3 to which do not gain a right access. The master processor 2 or the slave processor 3 to which the interrupt request signals IRQ1, IRQ2 are input performs the operation of reading the data stored in the shared memory 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer processing technique, and more particularly to a technique which is effective when applied to a data transfer end notification in processing while transferring data between a plurality of microprocessors.

[0002]

2. Description of the Related Art According to studies made by the present inventor, G
In a data processing system used for mobile phones for Europe such as SM (Group Special Mobile), microcomputer processing and DSP (Digita Digital Mobile) are used.
l Signal Processor) In order to perform a well-balanced process, there is a type provided with two or more microprocessors. In the case of such a data processing system, a storage device such as a semiconductor memory is commonly shared between microprocessors.

When tasks are shared among these microprocessors, for example, when a certain microprocessor completes data transfer, an interrupt request is issued to the other party to notify it, or other microprocessors not performing data transfer are notified. The microprocessor periodically performs data ready status detection, so-called polling, checks whether necessary data is available or not, and if so, performs a process of retrieving the data.

As an example describing this type of data processing technology in detail, see Koji Yada (author), published by Ohm Co., Ltd. on January 30, 1987, "Software Knowledge (Second Edition)". P199, and this document describes polling and the like in data transmission.

[0005]

However, the present inventor has found that the data transfer technique in the above-described data processing system has the following problems.

In other words, when the microprocessor on the data transfer side notifies the end of the data transfer, these must be processed by software. Similarly, if other microprocessors that are not transferring data detect the status of data ready, the processing must be performed in a software manner, and when frequent data is exchanged, the overhead is outweighed by the benefit of task sharing. And the processing capability is reduced, thereby deteriorating the performance.

It is an object of the present invention to provide a data processing system capable of transferring data at high speed and efficiently when performing data processing using a plurality of processors.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the data processing system of the present invention comprises two or more microprocessors, a semiconductor memory accessible by the two or more microprocessors, and one of the two or more microprocessors. A transfer that detects that notification data has been written to a preset notification address when a write access is made to the semiconductor memory, and outputs a data transfer end detection signal to other microprocessors that have not made a write access to the semiconductor memory. And an end detecting means.

Further, the data processing system of the present invention comprises a first microprocessor, a second microprocessor, a semiconductor memory accessible by the first and second microprocessors, and a first and second microprocessor. When one of the processors performs write access to the semiconductor memory, it detects that the notification data has been written to a preset notification address, and sends the data to the microprocessor that has not write-accessed the semiconductor memory. Transfer end detecting means for outputting a transfer end detection signal.

Further, the data processing system of the present invention comprises:
A first microprocessor connected to the common bus, having a control right for the common bus, and having a function of transferring the control right for the common bus based on an input bus right request signal; and a first microprocessor connected to the common bus. A second microprocessor for outputting a bus right request signal for requesting control of the common bus at the time of data transfer, a semiconductor memory connected to the common bus and accessible by the first and second microprocessors, When one of the microprocessors makes a write access to the semiconductor memory, it detects that the notification data has been written to a preset first notification address and sends the data to a second microprocessor that has not made a write access to the semiconductor memory. A transfer end detection signal is output, and when the second microprocessor makes a write access to the semiconductor memory, a preset second notification address is set. Detects that the notification data is written to the scan is obtained by a transfer completion detecting means for outputting a first data transfer completion detection signal to the microprocessor that is not write access to the semiconductor memory.

Further, the data processing system of the present invention comprises a first microprocessor connected to the first bus,
A second microprocessor connected to the bus, a first selector connected to the first bus and switching a connection destination based on a control signal, and a first selector connected to the second bus and switching a connection destination based on a control signal A second selector, a semiconductor memory connected to the first and second selectors and accessible by the first and second microprocessors, and a second memory when the first microprocessor requests access to the semiconductor memory. A control signal is output to the first selector so that the first microprocessor is connected to the semiconductor memory,
When the microprocessor requests access to the semiconductor memory, the microprocessor outputs a control signal to the second selector so that the second microprocessor and the semiconductor memory are connected. When there is a request for access at the same time, a memory access arbitration means for outputting a wait signal to a preset low-priority processor to access the high-priority microprocessor, When write access is made to the memory, the first
When detecting that the notification data has been written to the notification address and outputting a data transfer end detection signal to the second microprocessor that has not made a write access to the semiconductor memory, the second microprocessor has made a write access to the semiconductor memory. Transfer end detecting means for detecting that the notification data has been written to a preset second notification address and outputting a data transfer end detection signal to a first microprocessor which has not made write access to the semiconductor memory; It is provided with.

Further, the data processing system of the present invention comprises:
A first microprocessor connected to the first bus, a second microprocessor connected to the second bus, and connected to the first and second buses, so that the first and second microprocessors can access at the same time. When the semiconductor memory having the dual-port function and the first microprocessor perform write access to the semiconductor memory, the writing of the notification data to the preset first notification address is detected and the writing to the semiconductor memory is performed. A data transfer end detection signal is output to the second microprocessor that has not accessed,
When the second microprocessor makes a write access to the semiconductor memory, the second microprocessor detects that the notification data has been written to the second notification address set in advance and sends the notification to the first microprocessor that has not made a write access to the semiconductor memory. A data transfer end detection signal is output, and when there is an access request to the same address of the semiconductor memory simultaneously from the first and second microprocessors, an access error signal for notifying an access error to a preset microprocessor is output. And a transfer end detecting means for outputting.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is an explanatory diagram showing a circuit configuration of a data transfer processing system according to Embodiment 1 of the present invention. FIG. 2 is a diagram showing a data transfer processing system according to Embodiment 1 of the present invention. FIG. 3 is a circuit diagram of a transfer end detection circuit provided, FIG. 3 is an explanatory diagram of control logic in the transfer end detection circuit provided in the data transfer processing system according to the first embodiment of the present invention, and FIG. 6 is a signal timing chart of the data transfer processing system according to the first embodiment.

In the first embodiment, the data processing system 1 is used, for example, for data processing in a GMS mobile phone. The data processing system 1 is shown in FIG.
As shown in FIG. 1, a master processor (first microprocessor) 2, a slave processor (second microprocessor) 3, a memory access arbitration circuit 4, a transfer end detecting circuit (transfer end detecting means) 5, and a shared memory (semiconductor) (Memory 6).

Address terminals A1, A provided for master processor 2 and slave processor 3, respectively.
2. A common address bus (common bus) B1 and a common data bus (common bus) B2 are connected to the data terminals D1 and D2, respectively. Address terminals A1 and A2 output an address signal, and data are input / output to data terminals D1 and D2.

The master processor 2 has a preferential right to use the common address bus B1 and the common data bus B2, and can always access the shared memory 6. The common memory 6 is connected to a common address bus B1 and a common data bus B2. Data and address signals are transmitted from the master processor 2 and the slave processor 3 via the common address bus B1 and the common data bus B2. Input and output.

The shared memory 6 has, for example, an SRA
M (Static Random Access Mem)
and the interface may be either a clock synchronous type or a clock asynchronous type. The transfer end detection circuit 5 has a common address bus B
1 is connected.

Further, the master processor 2 outputs a write enable signal WE1, a chip select signal CS1, and a bus permission signal BACK. The write enable signal WE1 is a write enable signal output when the master processor 2 performs a write access, and is connected so as to be output to the memory access arbitration circuit 4 and the transfer end detection circuit 5.

The chip select signal CS1 is a signal output when the master processor 2 accesses the shared memory 6, and is similarly connected so as to be output to the memory access arbitration circuit 4 and the transfer end detection circuit 5. Have been.

The bus permission signal BACK is a signal output when the master processor 2 permits the slave processor 3 to use the common address bus B1 and the common data bus B2, and is output to the slave processor 3. It is connected to the.

Further, the slave processor 3 outputs a write enable signal WE2, a chip select signal CS2, and a bus right request signal BREQ. The write enable signal WE2 is a write enable signal output when the master processor 2 performs write access, and is connected so as to be output to the memory access arbitration circuit 4 and the transfer end detection circuit 5.

The chip select signal CS2 is a signal output when the slave processor 3 accesses the shared memory 6, and is connected so as to be output to the memory access arbitration circuit 4 and the transfer end detection circuit 5. .

The bus right request signal BREQ is a signal for the slave processor 3 to output a request to use the common address bus B1 and the common data bus B2 to the master processor 2, and is connected so as to be output to the master processor 2. ing.

The memory access arbitration circuit 4 converts the input write enable signals WE1 and WE2 and the chip select signals CS1 and CS2 into a write enable signal W.
Em and a chip select signal CSm are output to the shared memory 6 to control the write / read operation of the shared memory 6.

When a write access is made to certain addresses a1 and a2 in the shared memory 6, the transfer end detecting circuit 5 sends an interrupt request signal to either the master processor 2 or the slave processor 3 which has not made write access. It outputs IRQ1 and IRQ2, respectively.

The interrupt request signal IRQ1 is connected so as to be output to the master processor 2, and the interrupt request signal IRQ2 is connected so as to be output to the slave processor 3.

The circuit configuration of the transfer end detecting circuit 5 will be described.

As shown in FIG. 2, the transfer end detection circuit 5 includes an address decode circuit 7, a 3-input AND circuit 8,
9, delay circuits 10, 11, inverters 12, 13,
And two-input AND circuits 14 and 15.

The input section of the address decode circuit 7 is connected to a common address bus B1. The address decode circuit 7 outputs an address decode signal ADR1 when a specific address (first notification address) a1 is input from the common address bus B1, and outputs the address decode signal ADR1.
When a specific address (second notification address) a2 is input from the controller, the address decoder 2 outputs an address decode signal ADR2.

The address decode signal ADR1 output from the address decode circuit 7 is connected so as to be input to the input section of the AND circuit 8, and the address decode signal ADR2 is input to the input section of the AND circuit 9. Connected.

The input sections of the AND circuits 8 and 9 are connected so as to receive the write enable signals WE1 and WE2 and the chip select signals CS1 and CS2, respectively.

The output of the AND circuit 8 is connected to the input of the delay circuit 10 and one input of the AND circuit 14, and the output of the AND circuit 9 is connected to the output of the delay circuit 11. The input unit and one input unit of the AND circuit 15 are connected.

The output of the delay circuit 10 is connected to the input of the inverter 12, and the output of the inverter 12 is connected to the other input of the AND circuit 14. The output of the delay circuit 11 includes an inverter 13
Are connected. The other input of the AND circuit 15 is connected to the output of the inverter 13.

The signal output from the AND circuit 14 becomes the interrupt request signal IRQ2, and the AND circuit 15
Is an interrupt request signal IRQ1.

Next, the operation of the present embodiment will be described with reference to the control logic in the transfer end detection circuit 5 of FIGS. 1, 2 and 3 and the timing chart of FIG.

FIG. 4 shows an address signal Ad, a write enable signal WE1 output from the master processor 2, a write enable signal WE2 output from the slave processor 3, and a chip output from the master processor 2 from top to bottom. Select signal CS1, chip select signal C output from slave processor 3
S2, the signal timing of the interrupt request signal IRQ1 input to the master processor 2 and the signal timing of the interrupt request signal IRQ2 input to the slave processor 3 are shown.

First, a cycle T1 in FIG. 4 shows a case where the master processor 2 transmits certain data to the slave processor 3, and the master processor 2 sends a chip select signal CS1 and a write enable signal W
E1 is output. At this time, since the master processor 2 has the bus right, the chip select signal CS2 and the write enable signal W
E1 is never asserted.

After writing the data to be transmitted to the slave processor 3 to the shared memory 6, the master processor 2 sends information notifying that the data transfer has been completed to the shared memory 6, as shown in cycle T1 of FIG. Write to a specific address a1.

When the transfer end detecting circuit 5 detects the write-accessed address a1, the transfer request detecting circuit 5
Q2 is output to the slave processor 3 to make the slave processor 3 recognize that certain data has been stored in the shared memory 6.

In a cycle T2 in FIG. 4, a write enable signal WE1 of a high level ('1') and a chip select signal CS1 are input to the transfer end detection circuit 5,
Further, since the address signal Ad is other than the address a1, the address decode signal ADR1 becomes low level ('
0 '). Therefore, as shown in FIG. 3, the transfer end detection circuit 5 outputs a low level ('0') interrupt request signal I.
RQ1 and IRQ2 are output. Note that the interrupt request signal IRQ1 is a chip select signal CS2,
Since the write enable signal WE1 is not asserted, it goes low ('0') regardless of the state of the address signal Ad.

Further, in cycle T1 of FIG.
The write enable signal WE1 and the chip select signal CS1 are “1”, and the address signal Ad is the address a2. When this address a2 is detected by the address decode circuit 7, the address decode signal ADR1 becomes "1", and "1" is input to all the input sections of the AND circuit 8, and as shown in FIG. '
1 '. As the interrupt request signal IRQ2, "1" is output for a certain time delayed by the delay circuit 10.

The slave processor 3 to which the interrupt request signal IRQ2 output from the transfer end detection circuit 5 is input,
The bus request signal BREQ is output to request the master processor 2 for the bus right. The master processor 2 to which the bus right request signal BREQ has been input receives the bus permission signal BAC
K is output to the slave processor 3, and the slave processor 3 acquires the bus right. After acquiring the bus right, the slave processor 3 receives the information from the address a1, and subsequently reads out the data stored in the shared memory 6.

A case will be described in which data is transmitted from slave processor 3 to master processor 2.

First, the slave processor 3 issues a bus right request signal BRE for requesting the master processor 2 for a bus right.
And outputs a bus enable signal BAC of the master processor 2.
By receiving K, the bus right is acquired.

After the slave processor 3 acquires the bus right, the chip select signal CS2 and the write enable signal WE2 are output from the slave processor 3, as shown in cycle T3 in FIG.
Is written to the shared memory 6. Thereafter, as shown in a cycle T3 of FIG. 4, information notifying that the data transfer has been completed is written to a specific address a2 of the shared memory 6.

When the transfer end detecting circuit 5 detects the write accessed address a2, the interrupt request signal IR
Q1 is output to the master processor 2 to make the master processor 2 recognize that certain data is stored in the shared memory 6.

In cycle T4 of FIG. 4, write enable signal WE2 is set to "0" and chip select signal CS is set to "0".
2 is “1”, the address decode signal A
DR2 becomes '1'. Therefore, as shown in FIG. 3, the transfer end detection circuit 5 outputs low level ('0') interrupt request signals IRQ1 and IRQ2.

Further, in cycle T3 of FIG.
Since the write enable signal WE2 and the chip select signal CS2 are "1", the address signal Ad is the address a2, the address decode signal ADR1 is "0", and the address decode signal ADR2 is "1", as shown in FIG. Then, the interrupt request signal IRQ1 becomes '1'.

The master processor 3 receiving the interrupt request signal IRQ1 receives the information from the address a2, and subsequently reads the data stored in the shared memory 6.

Thus, in the first embodiment, when either the master processor 2 or the slave processor 3 writes data, the transfer end detecting circuit 5 detects the writing, and the other end where the data is not written. Since the interrupt request signal is output to the processor, the software processing such as polling is not required, and data can be exchanged at high speed and efficiently.

Further, since data can be exchanged efficiently, the processing load of the master processor 2 and the slave processor 3 can be equalized even when there is a complicated processing task, and the power consumption of the data processing system 1 can be reduced. It can be significantly reduced.

Furthermore, in the first embodiment, the interrupt request signal IRQ generated by the transfer end detecting circuit 5
1, IRQ2 is a pulse signal, but a level signal is generated, and a signal notifying that the processor has accepted the interrupt is transmitted to the transfer end detecting circuit 5, and then the interrupt request signal is negated. Good.

According to the first embodiment, the specific addresses a1 and a2 are the addresses physically existing in the address space of the shared memory 6;
1, a2 may be another hardware configuration such as a memory-mapped register.

Further, in the first embodiment, the data processing system 1 has a configuration having one slave processor 3, but the slave processor may have a configuration having two or more slave processors as required.

(Embodiment 2) FIG. 5 is an explanatory diagram showing a circuit configuration of a data transfer processing system according to Embodiment 2 of the present invention. FIG. 6 is a diagram showing a data transfer processing system according to Embodiment 2 of the present invention. FIG. 7 is a circuit diagram of the provided transfer end detection circuit, FIG. 7 is an explanatory diagram of control logic in the transfer end detection circuit provided in the data transfer processing system according to the second embodiment of the present invention, and FIG. 10 is a signal timing chart of the data transfer processing system according to the second embodiment.

In the second embodiment, as shown in FIG. 5, the data processing system 1a includes processors 2a and 3
a, memory access arbitration circuit (memory access arbitration means) 4a, transfer end detection circuit (transfer end detection means) 5
a, shared memory 6, and selectors 16 and 17.

Processor (first microprocessor)
An address bus (first bus) AB1 and a data bus (first bus) DB1 are connected to the address terminal A1 and the data terminal D1 provided in 2a, respectively.

Processor (second microprocessor)
An address bus (second bus) AB2 and a data bus (second bus) DB2 are connected to the address terminal A2 and the data terminal D2 provided in 3a, respectively. Address terminals A1 and A2 output an address signal, and data are input / output to data terminals D1 and D2.

The processors 2a and 3a receive the write enable signals WE1 and WE2 and the chip select signal CS
1 and CS2, respectively. The write enable signals WE1 and WE2 are permission signals output when the processors 2a and 3a perform write access, respectively, and are connected so as to be output to the memory access arbitration circuit 4a.

The chip select signals CS1 and CS2 are output when the processors 2a and 3a access the shared memory 6, and are also connected so as to be output to the memory access arbitration circuit 4a.

Address buses AB 1 and AB 2 are connected to the input section of the selector (first selector) 16.
The output of the selector 16 is connected to the shared memory 6 and the transfer end detection circuit 5a, and outputs an address signal Am.

Data buses DB1 and DB2 are connected to the input section of the selector (second selector) 17. The shared memory 6 is connected to an output section of the selector 17, and data Dm is input / output. These selectors 1
6, 17 include, for example, multiplexers,
A signal is selected and output based on the control signal SEL.

The memory access arbitration circuit 4a outputs the input write enable signals WE1 and WE2 and the chip select signals CS1 and CS2 to the transfer end detection circuit 5a and the shared memory 6 as the write enable signal WEm and the chip select signal CSm, respectively. I do.

The memory access arbitration circuit 4a controls the control signals SEL and SEL based on the write enable signals WE1 and WE2 and the chip select signals CS1 and CS2.
And wait signals WAIT1 and WAIT2.

The control signal SEL controls the selectors 16 and 17, and the wait signals WAIT1 and WAIT2 put the processors 2a and 3a in the wait state, respectively. Control signal SEL is output to selectors 16 and 17 and transfer end detection circuit 5a, respectively, and wait signal WAIT
1, WAIT2 are output to the processors 2a, 3a, respectively.

When there is a write access to certain specific addresses a1 and a2, the transfer end detection circuit 5a sends an interrupt request signal I to a processor that has not made write access.
RQ1 and IRQ2 are output, respectively. The interrupt request signal IRQ1 is output to the processor 2a, and the interrupt request signal IRQ2 is output to the processor 3a.

The circuit configuration of the transfer end detecting circuit 5a will be described.

As shown in FIG. 6, the transfer end detecting circuit 5a comprises an address decode circuit 7a and a 4-input AND circuit 8
a, 9a, delay circuits 10a, 11a, inverter 1
2a, 13a, 18 and a 2-input AND circuit 14
a and 15a.

The input section of the address decode circuit 7a has
The address signal Am is input. The address decode circuit 7a outputs an address decode signal ADR1 when a specific address a1 is input, and outputs an address decode signal ADR2 when a specific address a2 is input.
Is output.

Address decode signal ADR1 output from address decode circuit 7a is connected so as to be input to the input section of AND circuit 8a, and address decode signal ADR2 is input to the input section of AND circuit 9a. It is connected.

The input sections of the AND circuits 8a and 9a are connected to receive the write enable signal WEm and the chip select signal CSm, respectively. The input of the AND circuit 8a and the input of the inverter 18 are connected so that the control signal SEL is input. The output of the inverter 18 is connected to the input of the AND circuit 9a.

The outputs of the AND circuits 8a and 9a are connected to the inputs of the delay circuits 10a and 11a and one of the inputs of the AND circuits 14a and 15a, respectively. The outputs of the delay circuits 10a and 11a are connected to the inputs of the inverters 12a and 13a.

The outputs of the inverters 12a and 13a
The other input units of the AND circuits 14a and 15a are connected. The signal output from the AND circuit 14a becomes the interrupt request signal IRQ2, and the signal output from the AND circuit 15a becomes the interrupt request signal IRQ1.

Next, the operation of the present embodiment will be described with reference to the control logic in the transfer end detection circuit 5a of FIGS. 5, 6, and 7, and the timing chart of FIG.

Here, FIG. 8 shows that
Address signals Ad1, Ad2, a write enable signal WE1 output from the processor 2a, a write enable signal WE2 output from the processor 3a, a chip select signal CS1 output from the processor 2a, a chip select signal CS2 output from the processor 3a, Control signal SE output from memory access arbitration circuit 4a
L, an address signal Am, a write enable signal WEm,
Chip select signal CSm, interrupt request signal IRQ1 input to processor 2a, interrupt request signal IRQ2 input to processor 3a, wait signal WAIT1 input to processor 2a, and processor 3
The signal timing of the wait signal WAIT2 input to “a” is shown.

First, when accessing the shared memory 6, the processors 2a and 3a receive the chip select signals CS1 and CS1.
CS2 is output, and a write enable signal W is output for recognizing whether the access is a read or a write.
E1 and WE2 are output.

The chip select signals CS1 and CS2 and the write enable signals WE1 and WE2 output from the processors 2a and 3a correspond to the memory access arbitration circuit 4a.
Is input to

The memory access arbitration circuit 4a generates a control signal SEL from the input chip select signals CS1 and CS2 and the write enable signals WE1 and WE2, and performs control so that the processor that has requested access can access the shared memory 6. Do.

The selectors 16 and 17 input and output the address signal and the data signal of the processor 2a when the control signal SEL is at the high level ('1'), and when the control signal SEL is at the low level ('0'). Inputs and outputs an address signal and a data signal of the processor 3a.

For example, as shown in cycle T1 of FIG. 8, when the transfer end detecting circuit 5a detects the address a2 when the processor 3a makes a write access, an interrupt request signal IRQ1 is output to the processor 2a and certain data is output. The fact that the data is stored in the shared memory 6 is indicated by the
To be recognized.

At this time, the high-level ('1') write enable signal WEm, the chip select signal CSm, and the low-level ('0') are supplied to the transfer end detection circuit 5a.
Is input, and the address signal Ad2
Is the address a2, as shown in FIG. 7, the address decode signal ADR1 goes low ('0'), the address decode signal ADR2 goes high ('1'),
A high-level ('0') interrupt request signal IRQ1 is output from the transfer end detection circuit 5a.

As shown in a cycle T5 of FIG.
When there is a request to access the shared memory 6 from the two processors 2a and 3a at the same time, the memory access arbitration circuit 4a causes the processor having a higher priority to access the shared memory 6 in accordance with a preset priority.

For example, assuming that the priority of the processor 2a is high, a wait signal WAIT2 is output to the processor 3a having a low priority, and the processor 3a is put into a wait state.

When the access of the processor 2a is completed, the memory access arbitration circuit 4a changes the control signal SEL from "1" to "1" as shown in a cycle T6 of FIG.
It is controlled to invert to 0 'so that the processor 3a accesses the shared memory 6.

Thus, also in the second embodiment,
When either the processor 2a or the processor 3a writes data, the transfer end detecting circuit 5a
Detects this and outputs an interrupt request signal to the other processor to which data has not been written, so that software processing such as polling becomes unnecessary, and data can be exchanged at high speed and efficiently.

(Embodiment 3) FIG. 9 is an explanatory diagram showing a circuit configuration of a data transfer processing system according to Embodiment 3 of the present invention. FIG. 10 is a diagram showing a data transfer processing system according to Embodiment 3 of the present invention. FIG. 11A is a circuit diagram of a provided transfer end detection circuit, FIG. 11A is a diagram for explaining control logic in one address decoding circuit provided in the transfer end detection circuit according to the third embodiment of the present invention, and FIG. FIG. 12C is an explanatory diagram of control logic in the other address decode circuit provided in the transfer end detecting circuit. FIG. 12C is an explanatory diagram of control logic in the address match detecting circuit provided in the transfer end detecting circuit.
9 is a signal timing chart of the data transfer processing system according to the third embodiment of the present invention.

In the third embodiment, as shown in FIG. 9, the data processing system 1b includes processors 2b and 3
b, a transfer end detecting circuit (transfer end detecting means) 5b, and a shared memory (semiconductor memory) 6a.

Processor (first microprocessor)
An address bus AB1 and a data bus DB1 are connected to an address terminal A1 and a data terminal D1 provided in the processor 2b, respectively, and an address terminal A2 and a data terminal D provided in a processor (second microprocessor) 3b are provided.
2 is connected to an address bus AB2 and a data bus DB2. Address terminals A1 and A2 output an address signal, and data are input / output to data terminals D1 and D2.

The processors 2b and 3b provide the write enable signals WE1 and WE2 and the chip select signal CS
1 and CS2, respectively. Write enable signals WE1, WE2, chip select signals CS1, CS2
Are connected so as to be output to the transfer end detection circuit 5b.

The write enable signals WE1 and WE2 are
This is a permission signal output when each of the processors 2b and 3b performs write access, and includes a chip select signal CS.
1 and CS2, the processors 2b and 3b are shared memory 6a
Is a signal that is output when accessing. Further, address buses AB1 and AB2 are connected to the transfer end detection circuit 5b.

The transfer end detecting circuit 5b outputs interrupt request signals IRQ1 and IRQ2 and an access error signal ERR2. Interrupt request signal IRQ
When there is a write access to certain addresses a1 and a2, IRQ2 and IRQ2 are output to the processors that have not made write access.

The interrupt request signal IRQ1 is output to the processor 2b, and the interrupt request signal IRQ2 is output to the processor 3b. Access error signal ERR2
Causes the processor 3b to recognize that the access has been illegal.

The shared memory 6a has an address bus AB
1 and AB2, and data buses DB1 and DB2, respectively. Further, the shared memory 6a is constituted by a so-called dual port memory having hardware that can be accessed by the two processors 2b and 3b.

Thus, two processors 2
b, 3b, even if a memory access request is issued,
The access operation can be performed in parallel as long as the same address is not accessed.

The circuit configuration of the transfer end detecting circuit 5b will be described.

As shown in FIG. 10, the transfer end detecting circuit 5b comprises address decode circuits 7b and 7c, three-input AND circuits 8b and 9b, delay circuits 10b and 11b, inverters 12b and 13b, and two-input logical products. Circuit 14b, 1
5b and an address coincidence detection circuit 19.

Address signals Ad1 and Ad of address buses AB1 and AB2 are supplied to address decode circuits 7b and 7c.
2 are connected so as to be input respectively. The address decode circuits 7b and 7c are provided with a certain address a
1 and a2, the address decode signal ADR
1 and ADR2 are output.

The address decode signal ADR1 output from the address decode circuit 7b is connected so as to be input to the input section of the AND circuit 8b, and the address decode signal ADR2 is input to the input section of the AND circuit 9b. It is connected.

The input sections of the AND circuits 8b and 9b are connected to receive the write enable signals WE1 and WE2 and the chip select signals CS1 and CS2, respectively.

The address match detection circuit 19 has the address signals Ad1 and Ad of the address buses AB1 and AB2.
2 and the chip select signals CS1 and CS2.

The outputs of the AND circuits 8b and 9b are connected to the inputs of the delay circuits 10b and 11b and one of the inputs of the AND circuits 14b and 15b, respectively. The input sections of the inverters 12b and 13b are connected to the section.

The output sections of the inverters 12b and 13b have
The other input units of the AND circuits 14b and 15b are connected. The signal output from the AND circuit 14b becomes the interrupt request signal IRQ2, and the signal output from the AND circuit 15b becomes the interrupt request signal IRQ1.

Next, the operation of the present embodiment will be described with reference to the control logic in the transfer end detecting circuit 5b of FIGS. 9, 10, and 11, and the timing chart of FIG.

Here, FIG. 12 shows the address signals Ad1 and Ad2, the write enable signal WE1 output from the processor 2b, the processor 3
b, a write enable signal WE2, a chip select signal CS1 output from the processor 2b, a chip select signal CS output from the processor 3b
2. Interrupt request signal IR input to processor 2b
Q1, an interrupt request signal I input to the processor 3b
RQ2 and the signal timing of the access error signal ERR2 input to the processor 3b are shown.

First, when accessing the shared memory 6a, the processors 2b and 3b receive the chip select signal CS
1, CS2 is output and whether the access is a read
The write enable signals WE1 and WE2 are output in order to recognize whether the data is a write.

The chip select signals CS1 and CS2 and the write enable signals WE1 and WE2 output from the processors 2b and 3b are input to the shared memory 6a and the transfer end detection circuit 5b.

For example, as shown in cycle T1 of FIG. 12, when the transfer end detecting circuit 5b detects the address a2 when the processor 3b makes a write access, an interrupt request signal IRQ1 is output to the processor 2a, and a certain data is output. Is stored in the shared memory 6a to the processor 2a.

When the address a2 is detected, the address decode circuit 7c of the transfer end detection circuit 5b sends the address a2 as shown in FIG.
As shown in FIG. 1B, the address decode signal ADR2 of “1” is output, and the interrupt request signal IRQ1 of “1” is output from the AND circuit 14b.

As shown in cycle T5 of FIG. 12, when two processors 2a and 3a simultaneously access to the same address of shared memory 6a, the processing is terminated.
As shown in FIG. 1 (c), the address match detection circuit 19 outputs an access error signal ERR2 to the processor 3b,
It notifies that the access of the processor 3b has become an error.

Therefore, according to the third embodiment,
When either the processor 2b or the processor 3b writes data, the transfer end detection circuit 5b
Detects this and outputs an interrupt request signal to the other processor to which data has not been written, so that software processing such as polling becomes unnecessary, and data can be exchanged at high speed and efficiently.

Further, by using the shared memory 6a having the dual port function, two processors 2b,
Even if accesses occur simultaneously from 3b, it is possible to prevent one of the processes from being stalled due to the conflict, and to transfer data more efficiently.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, the circuit configuration of the data processing system shown in the first to third embodiments may be formed on a semiconductor chip and configured as one data processing semiconductor integrated circuit device.

Further, in the above embodiment, the data processing system used for the mobile phone has been described. However, the data processing system of an electronic device which processes various data at high speed, such as a portable game machine or a cable modem having a high transfer rate, is described. Can be used for the system.

[0118]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, data transfer between a plurality of microprocessors can be performed efficiently, so that the processing loads of the microprocessors can be equalized and the data processing speed can be greatly increased. Power consumption and the like can be reduced while improving.

(2) Further, according to the present invention, a high-performance microprocessor or the like required only for specific processing is not required, and a software development environment can be shared.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a circuit configuration of a data transfer processing system according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a transfer end detection circuit provided in the data transfer processing system according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of control logic in a transfer end detection circuit provided in the data transfer processing system according to the first embodiment of the present invention.

FIG. 4 is a signal timing chart of the data transfer processing system according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram illustrating a circuit configuration of a data transfer processing system according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a transfer end detection circuit provided in a data transfer processing system according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram of control logic in a transfer end detection circuit provided in a data transfer processing system according to a second embodiment of the present invention.

FIG. 8 is a signal timing chart of the data transfer processing system according to the second embodiment of the present invention.

FIG. 9 is an explanatory diagram illustrating a circuit configuration of a data transfer processing system according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram of a transfer end detection circuit provided in a data transfer processing system according to a third embodiment of the present invention.

11A is a diagram illustrating control logic in one address decoding circuit provided in a transfer end detection circuit according to a third embodiment of the present invention, and FIG. 11B is a diagram illustrating control logic provided in the transfer end detection circuit; FIG. 3C is an explanatory diagram of control logic in the other address decode circuit, and FIG. 3C is an explanatory diagram of control logic in an address match detection circuit provided in the transfer end detection circuit.

FIG. 12 is a signal timing chart of the data transfer processing system according to the third embodiment of the present invention.

[Explanation of symbols]

1 to 1b Data processing system 2 Master processor (first microprocessor) 2a, 2b Processor (first microprocessor) 3 Slave processor (second microprocessor) 3a, 3b Processor (second microprocessor) 4 Memory Access arbitration circuit 4a Memory access arbitration circuit (memory access arbitration means) 5-5b Transfer end detection circuit (transfer end detection means) 6, 6a Shared memory (semiconductor memory) 7-7c Address decode circuit 8-8b Logical product circuit 9- 9b AND circuit 10 to 10b Delay circuit 11 to 11b Delay circuit 12 to 12b Inverter 13 to 13b Inverter 14 to 14b AND circuit 15 to 15b AND circuit 16 Selector (first selector) 17 Selector (second selector) 18 Inn Data 19 Address match detection circuit B1 Common address bus (common bus) B2 Common data bus (common bus) AB1 Address bus (first bus) DB1 Data bus (first bus) AB2 Address bus (second bus) DB2 data bus (second bus) a1 address (first notification address) a2 address (second notification address) ADR1, ADR2 address decode signal WE1, WE2, WEm write enable signal CS1, CS2, CSm chip select signal BACK bus enable Signal BREQ Bus request signal IRQ1, IRQ2 Interrupt request signal SEL Control signal WAIT1, WAIT2 Wait signal ERR2 Access error signal

Continued on the front page (72) Inventor Andrew Fog Great Britain and Northern Ireland, SG86EE Hartford Shah, Royston, Melbourne, Cambridge Bridge Road, Melbourne Science Park, FTP Term in TTP Communications Limited Reference) 5B045 BB12 BB43 BB45 DD01 5B061 BA01 BB01 BC07 GG11 GG13 GG14

Claims (5)

[Claims] 1. A microprocessor, comprising: two or more microprocessors; a semiconductor memory accessible by the two or more microprocessors; and the two or more microprocessors.
When one of the microprocessors makes a write access to the semiconductor memory, it detects that notification data has been written to a preset notification address, and completes data transfer to the microprocessors that have not made a write access to the semiconductor memory. A data processing system comprising: a transfer end detecting unit that outputs a detection signal. 2. A first microprocessor, a second microprocessor, a semiconductor memory accessible by the first and second microprocessors, and one of the first and second microprocessors When the microprocessor makes a write access to the semiconductor memory, it detects that notification data has been written to a preset notification address, and detects data transfer completion to the microprocessor that has not made a write access to the semiconductor memory. A data processing system comprising: a transfer end detecting unit that outputs a signal. 3. A first microprocessor connected to a common bus, having a control right for the common bus, and having a function of transferring the control right of the common bus based on an input bus right request signal. A second microprocessor that is connected to the common bus and outputs a bus right request signal for requesting control of the common bus at the time of data transfer; and a first microprocessor and a second microprocessor connected to the common bus. A semiconductor memory that can be accessed by a microprocessor, and when the first microprocessor has made a write access to the semiconductor memory, the semiconductor memory detects that notification data has been written to a first notification address set in advance. A data transfer end detection signal is output to the second microprocessor that has not been write-accessed to the second microprocessor. When a write access is made to the memory, it is detected that the notification data has been written to the second notification address set in advance, and a data transfer end detection signal is sent to the first microprocessor which has not made a write access to the semiconductor memory. A data processing system, comprising: a transfer end detecting unit for outputting the data. 4. A first microprocessor connected to a first bus, a second microprocessor connected to a second bus, and a connection destination connected to the first bus, the connection destination being switched based on a control signal. A first selector, a second selector connected to the second bus, and switching a connection destination based on a control signal; a first selector connected to the first and second selectors;
A semiconductor memory that can be accessed by the microprocessor; and the first microprocessor, when the first microprocessor requests access to the semiconductor memory, such that the first microprocessor is connected to the semiconductor memory. A control signal is output to the selector, and when the second microprocessor requests access to the semiconductor memory, the second microprocessor sends the control signal to the second selector so that the second microprocessor and the semiconductor memory are connected. Outputting a control signal, and when there is a simultaneous access request from the first and second microprocessors, outputs a wait signal to a processor having a lower priority set in advance;
A memory access arbitration unit for accessing a microprocessor having a higher priority; and, when the first microprocessor performs a write access to the semiconductor memory, the notification data is written to a preset first notification address. A data transfer end detection signal is output to the second microprocessor that has not detected and has not made a write access to the semiconductor memory, and when the second microprocessor has made a write access to the semiconductor memory, a preset value is set. Transfer end detecting means for detecting that the notification data has been written to the second notification address and outputting a data transfer end detection signal to the first microprocessor which has not made write access to the semiconductor memory. Characteristic data processing system. 5. A first microprocessor connected to a first bus, a second microprocessor connected to a second bus, and a first microprocessor connected to the first and second buses. And a semiconductor memory having a dual-port function that can simultaneously access the microprocessor, and when the first microprocessor makes a write access to the semiconductor memory, the notification data is written to a preset first notification address. And outputs a data transfer end detection signal to the second microprocessor that has not made a write access to the semiconductor memory. When the second microprocessor has made a write access to the semiconductor memory, a preset value is set. Detecting that the notification data has been written to the specified second notification address, and performing write access to the semiconductor memory. A data transfer end detection signal is output to the first microprocessor, and if there is an access request to the same address of the semiconductor memory simultaneously from the first and second microprocessors, a preset microprocessor And a transfer end detecting means for outputting an access error signal for notifying an access error to the data processing system.