JP2002158645A - Data transmitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transmitter in which delay is synchronized automatically by transmission timing elements, the of phases of which are corrected even when the delay is generated in transmitted data, due to changes of cable length and temperature and the transmitted data is received precisely. SOLUTION: The delay is automatically synchronized, by automatically correcting the phase by the transmission timing elements STa, STb, STc, STd, the delays of which are corrected even if the delay is generated in the transmitted data SD, due to the changes of the cable length and the temperature and the transmitted data SD is received precisely, since the data transmitter is provided with a data interface means 2 having a clock-generating means 4, a double clock-generating means 5, an edge detecting means 6, a phase- converting means 7, a data change point detecting means 8, counting means 9A, 9B a judging means 10 and a phase-changing means 11, synchronous/ asynchronous state is judged by counting the change point of the transmitted data SD and the transmission timing elements STa, STb, STc, STd, the phases of which are automatically changed in correspondence with the delay of the transmitted data SD are generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission apparatus for preventing a reception error caused by a delay in transmission data transmitted from a data terminal apparatus.

[0002]

2. Description of the Related Art A conventional data transmission device having a serial synchronous communication function is known. FIG. 4 is a block diagram of a conventional data transmission device, and FIG. 5 is a data transmission timing diagram of the conventional data transmission device. The data transmission device 50 includes a central processing unit 51 and is connected to a data terminal device 53 via a data communication line 54.

[0003] When receiving the transmission data (SD) from the data terminal device 53, the central processing unit 51 transmits the transmission data (S).
The pulse-like transmission element timing (ST2) is set to the data terminal device 53 so that reception can be performed in synchronization with D).
To be sent to the server.

[0004] The data terminal device 53 transmits transmission data (SD) in synchronization with the transmission element timing (ST2). The central processing unit 51 takes in the transmission data (SD) at the falling edge of the pulse at the transmission element timing (ST2).

[0005] When the transmission data (SD) cannot be taken in (synchronization is impossible) at the falling edge of the pulse of the transmission element timing (ST2), the central processing unit 51 changes the synchronization setting. , Transmission data (SD) can be captured at the rising edge of the pulse at the transmission element timing (ST2).

As described above, the conventional data transmission device 50 having the serial synchronous communication function is capable of synchronously receiving transmission data (SD).

[0007]

The conventional data transmission device 50 detects the transmission data (SD) transmitted from the data terminal device 53 at the rising edge of the pulse of the transmission element timing (ST2), or detects the falling edge. Since only two modes, that is, detection at the edge, can be selected, the transmission data cannot be transmitted due to the influence of the length of the line (cable length) connecting the data transmission apparatus 50 and the data terminal apparatus 53 or the influence of the atmosphere such as temperature. When a delay occurs in (SD), a data fetch error occurs due to lack of synchronization, and there is a problem that transmission data (SD) cannot be accurately received.

Further, in the conventional data transmission apparatus 50, since the synchronization setting in the two modes is manually operated, the synchronization setting must be changed according to a change in cable length or a change in temperature.
There is a problem that setting work is troublesome.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to automatically correct the phase of a transmission element timing (ST2) in response to a delay of transmission data (SD) and to synchronize the transmission element timing (ST2). Taking and sending data (SD)
Is to provide a data transmission device capable of accurately receiving data.

[0010]

In order to solve the above-mentioned problems, a data transmission apparatus according to the present invention detects which phase of a transmission data change point is in a transmission timing element, and responds to the number of changes in the transmission data. Data interface means for determining whether the transmission data is synchronous or asynchronous and outputting a transmission timing element according to a change point of transmission data.

The data transmission apparatus according to the present invention includes the data interface means for outputting a transmission timing element having a phase corresponding to the change point of the transmission data, so that the transmission data is delayed due to a change in cable length or a change in temperature. Even if it occurs, synchronization can be automatically achieved with the transmission timing element having the phase corrected for the delay, and transmission data can be accurately received.

Further, the data interface means according to the present invention comprises: a data conversion point detecting means for detecting at which phase of the transmission timing element the change point of the transmission data is located; Counting means for counting the number of changes in the transmission data; determining means for determining whether to be synchronous or asynchronous based on the count signal supplied from the counting means; and a phase for changing the phase of the transmission timing element in response to the determination signal from the determining means. A change means is provided.

The data interface means according to the present invention includes data conversion point detecting means, counting means, synchronous / asynchronous judging means, and phase changing means. Judges and generates a transmission timing element whose phase is automatically changed according to the delay of the transmission data. Therefore, even if the transmission data is delayed due to a change in cable length or a change in temperature, the transmission with the delay corrected Synchronization can be achieved by automatically correcting the phase by the timing element, and transmission data can be received accurately.

[0014]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a schematic block diagram of an embodiment of a data transmission apparatus according to the present invention. In FIG. 1, a data transmission device 1 includes a data interface unit 2 and a data processing unit 3, is connected to a data terminal device 15 via a data communication line LD, and receives transmission data SD from the data terminal device 15.

The data interface means 2 transmits the transmission element timing ST2 to the data terminal device 15 via the data communication line LD so that the data terminal device 15 can synchronize when transmitting the transmission data SD.

The data interface means 2 determines the phase of the transmission element timing ST2 at which the change point of the transmission data SD, which is delayed due to a change in cable length or a change in temperature, transmitted from the data terminal device 15, is present. Is detected.

Further, the data interface means 2 comprises:
Changes in the transmission data SD existing in the same phase of the transmission element timing ST2 are counted, and the transmission data SD is changed according to the number of changes.
It is determined to which phase of the data is synchronized.

The data interface means 2 has a transmission element timing ST synchronized with the transmission data SD.
H is supplied to the data processing means 3. Data processing means 3
Is synchronized with the transmission element timing STH supplied from the data interface means 2 and the transmission data S
Since D is taken in, even if transmission data SD has a delay,
The transmission data SD can be accurately received by automatically compensating the phase.

The data processing means 3 has various arithmetic functions, processing functions, decoding (decoding) based on a microprocessor.
The transmission data S which is provided from the data terminal device 15 based on the transmission element timing STH supplied from the data interface means 2 having a function, a memory, etc.
D is received, and the transmission data SD is received.

The data processing means 3 decodes the received transmission data SD and executes various processes as analog signals (for example, audio signals), text and image signals.

As described above, the data transmission apparatus 1 according to the present invention includes the data interface means 2 for outputting the transmission timing element STH having a phase corresponding to the change point of the transmission data SD. , The transmission data SD can be automatically synchronized by the transmission timing element STH having the phase corrected for the delay, and the transmission data SD can be accurately received.

FIG. 2 is a block diagram of a main part of an embodiment of the data interface means according to the present invention. FIG.
, The data interface means 2 includes a clock generation means 4, a double clock generation means 5, an edge detection means 6, a phase conversion means 7, a data change point detection means 8, counting means 9A and 9B, a judgment means 10, a phase change means 11 is provided.

The clock generating means 4 includes a crystal oscillator, a PL
And a pulse-shaped transmission element timing ST2.
Through the data communication line LD.
It is supplied to the double clock generation means 5 and the phase conversion means 7. The clock generating means 4 is constituted by a frequency dividing circuit.
The transmission element timing ST2 may be generated by dividing the reference clock generated by the data processing means 3.

The double clock generation means 5 receives the transmission element timing ST2 supplied from the clock generation means 4.
, A clock STD having a double frequency is generated based on
To supply.

The edge detecting means 6 includes, for example, a single pulse generating circuit (one-shot multivibrator), and the one-shot pulse SDP is triggered by a change point of the transmission data SD and the clock STD supplied from the double clock generating means 5 as a trigger. Is generated and the one-shot pulse SDP indicating the transition point of the transmission data SD is provided to the data transition point detecting means 8.

The phase conversion means 7 includes a delay circuit, a memory such as a rewritable RAM, etc., and delays the transmission element timing ST2 supplied from the clock generation means 4 by the clock STD supplied from the double clock generation means 5 ( For example, every π / 2), four types of transmission element timings STa, STb, STc, STd having different phases are stored in a memory in correspondence with codes (for example, a, b, c, d). The phase conversion signal STx (STa, ST
b, STc, STd) are provided to the data change point detecting means 8. Further, the phase conversion means 7 supplies the transmission element timings STa, STb, STc, STd stored in the memory to the phase change means 11.

The data change point detecting means 8 includes a one-shot pulse SDP (change point of the transmission data SD) provided from the edge detecting means 6 and a phase conversion signal STx (STa, STb, STc) provided from the phase conversion means 7. , STd), the one-shot pulse SDP (change point of the transmission data SD) is converted into the phase conversion signal STx (STa, STb, STc, Sc).
Td), the phase detection signal DA,
DB is supplied to counting means 9A and 9B. It should be noted that the phase detection signal DA has a one-shot pulse SDP converted to the phase conversion signal ST.
x (STa, STb, STc, STd) is a signal that repeats only one arbitrary phase continuously, and the phase detection signal DB
Means that the one-shot pulse SDp has a phase conversion signal STx (S
Ta, STb, STc, STd) are randomly generated signals.

The counting means 9A and the counting means 9B are constituted by a counter, a logic operation circuit and the like, and count the number of times of the phase detection signal DA and the phase detection signal DB. Counting circuit 9A
Counts the phase detection signal DA and continuously outputs only the same phase (for example, the phase conversion signal STb) K times (for example, 4 times)
When counting is performed, for example, an H-level counting signal NA
Is supplied to the judgment means 10. Note that a sign (for example, sign b) that can specify the phase conversion signal STb is added to the count signal NA.

Further, the counting circuit 9A continuously counts only the same phase (for example, the phase conversion signal STb) K times (for example,
Before counting (four times), the other phases (STa, STc, S
Td) is counted, L is calculated by a logical circuit operation.
The level counting signal NA is supplied to the judging means 10. The counting circuit 9A supplies the counting signal NA at the H level to the judging means 10 and simultaneously outputs a reset signal to the counting circuit 9B to reset the counter of the counting circuit 9B.

The counting circuit 9B counts the phase detection signal DB, and generates each phase conversion signal STx (STa, STa,
One phase of STb, STc, STd) is N times (for example, 8
When the counting is performed, for example, an H-level counting signal NB (for example, a phase conversion signal STa) is supplied to the determination unit 10. Note that a sign (for example, sign a) that can specify the phase conversion signal STa is added to the count signal NB. Further, the counting circuit 9B outputs the counting signal NB at the H level to the determination means 10B.
And outputs a reset signal to the counting circuit 9A to reset the counter of the counting circuit 9A.

The judging means 10 includes a logical operation circuit and a code collating circuit, and outputs a count signal NA of H level and a phase conversion signal STx (STa, STb, ST) supplied from the counting means 9A.
Based on the code b specifying (c, STd), it is determined that the transmission data SD is synchronized with the phase conversion signal STb, and the determination signal Ho (for example, code b) is provided to the phase changing unit 11.

Further, the judgment means 10 is provided with an H level counting signal NB supplied from the counting means 9B and a phase conversion signal STx.
Based on the code a specifying (STa, STb, STc, STd), it is determined that the phase of the transmission data SD is closest to the phase of the phase conversion signal STa, and the determination signal Ho (for example, code a) is sent to the phase changing unit 11. provide.

The phase changing means 11 corresponds to the codes a and b from the memory of the phase conversion means 7 based on the codes a and b of the judgment signal Ho (codes a, b, etc.) supplied from the judgment means 10. The transmission element timings STa and STb are read and supplied to the data processing means 3 shown in FIG. 1 as transmission timing elements STH.

FIG. 3 is a data transmission timing chart of the data transmission apparatus according to the present invention. In the embodiment described with reference to FIG. 2 and FIG. 3, four types of transmission element timings STa, STb, ST in which the delay of transmission data SD is delayed by π / 2 from the phase of transmission element timing ST2, respectively.
Although the correction is made with c and STd, the correction is made with 2n types of subdivided transmission element timing STx in which the phase of the transmission element timing ST2 is delayed by π / n (n is an arbitrary natural number greater than 2). May be configured.

As described above, the data interface means 2 according to the present invention comprises the data conversion point detecting means 8 and the counting means 9
A, 9B, the determination means 10 and the phase change means 11 are provided, so that the change point of the transmission data SD is counted to determine the synchronization / asynchronization, and the phase is automatically adjusted in response to the delay of the transmission data SD. Changed transmission timing element ST
Since a, STb, STc, and STd are generated, even if a delay occurs in the transmission data SD due to a change in cable length or a change in temperature, the transmission timing element ST with the delay corrected.
a, STb, STc, STd can be automatically phase-corrected and synchronized, and the transmission data SD can be received accurately.

[0036]

As described above, the data transmission apparatus according to the present invention includes the data interface means for outputting the transmission timing element having a phase corresponding to the change point of the transmission data. , Even if a delay occurs in the transmission data due to the change in the transmission data, the synchronization can be automatically performed by the transmission timing element having the phase corrected for the delay, and the transmission data can be accurately received.

Further, the data interface means according to the present invention comprises a data conversion point detecting means, a counting means, a synchronous / asynchronous judging means, and a phase changing means. Asynchronous is determined, and a transmission timing element whose phase is automatically changed according to the delay of the transmission data is generated, so even if the transmission data is delayed due to a change in cable length or temperature, the delay is corrected. The phase can be automatically corrected and synchronized by the transmission timing element thus set, and transmission data can be received accurately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of an embodiment of a data transmission apparatus according to the present invention;

FIG. 2 is a block diagram of a main part of an embodiment of a data interface unit according to the present invention;

FIG. 3 is a data transmission timing diagram of the data transmission apparatus according to the present invention.

FIG. 4 is a block diagram of a conventional data transmission device.

FIG. 5 is a data transmission timing diagram of a conventional data transmission device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data transmission apparatus 2 Data interface means 3 Data processing means 4 Clock generation means 5 Double clock generation means 6 Edge detection means 7 Phase conversion means 8 Data change point detection means 9 Counting means 10 Judgment means 11 Phase change means

Claims (2)

[Claims] In a data transmission apparatus having a synchronous transmission function by a transmission timing element and receiving transmission data transmitted from a data terminal apparatus, it is possible to determine at which phase of the transmission timing element a transition point of the transmission data is located. A data transmission device comprising: a data interface unit that detects and determines whether the transmission data is synchronous or asynchronous according to the number of changes in the transmission data, and outputs a transmission timing element according to a change point in the transmission data. 2. The data interface means comprises: a data conversion point detection means for detecting a phase of a transmission timing element at which a change point of transmission data is present; and transmission data at each phase supplied from the data conversion point detection means. Counting means for counting the number of times of change, determining means for determining synchronization or non-synchronization based on the count signal supplied from the counting means, and a phase for changing the phase of the transmission timing element in response to the determination signal from the determining means 2. The data transmission device according to claim 1, further comprising changing means.