JP2002156398A - Time measuring device, test device, shift register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a time measuring device, capable of continuously and accurately measuring the time intervals between edges possessed by a digital signal. SOLUTION: The time measuring device comprises an input signal detection part for detecting a change of the three or more edges possessed by the input signal and outputting three or more detected signals in parallel which vary, based on each of the three or more edges; a conversion part for converting phase difference between each of the timings, when the detected signals vary and a clock edge in a reference clock to an analogue voltage value; a counting part for counting the number of clock edges included between the clock edges delayed by the phase difference, to which each of the at least two detected signals corresponds from the timing, when each of the at least two detected signals among the three or more detected signals changes; a calculating means for calculating the time intervals between the edges included in the three or more edges, based on the analogue voltage value and the number of the clock edges.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a time measuring device, a test device, and a shift register. In particular, the present invention relates to a time measuring device that can accurately measure a minute time interval between edges of a signal.

[0002]

2. Description of the Related Art Conventionally, as a time measuring device for measuring a period of a rectangular wave, a device for converting a period value of an input signal into a voltage value and outputting the voltage value disclosed in, for example, Japanese Patent Application Laid-Open No. 63-191970. was there. The device converts a period value of an input signal into a voltage value and outputs the voltage value.

[0003]

In recent years, the operating speed of semiconductor devices has been dramatically increased. For example, in a semiconductor memory device, a Rambus (registered trademark) DRAM (D
dynamic Random Access Memo
The operating frequency of ry) exceeds 400 MHz. The period of the clock output from the Rambus DRAM is 2.5 nanoseconds or less, and the accuracy of measurement is required to be at least 10 picoseconds.

The device described in Japanese Patent Application Laid-Open No. 63-197970 performs two operations such as analog arithmetic processing and sample hold on an input signal, and converts a cycle value of the input signal into a voltage value. I have. Therefore, in order to measure the clock cycle of the Rambus DRAM using the conventional time measuring device, the processing must be performed to 2.5 nanoseconds or less while maintaining the measurement accuracy of at least 10 picoseconds. However, in the conventional time measuring device, since continuous measurement and measurement accuracy are in a trade-off relationship,
It has been very difficult to continuously and accurately measure the period of the clock output from the Rambus DRAM.

Accordingly, an object of the present invention is to provide a time measuring device, a test device, and a shift register that can solve the above-mentioned problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.

[0006]

According to a first aspect of the present invention, a change in three or more edges of an input signal is detected, and three or more edges that change based on each of the three or more edges are detected. An input signal detection unit that outputs detection signals in parallel, and respective timings at which the detection signals change,
A converter for converting a phase difference between a clock edge of a reference clock operating at a predetermined cycle to an analog voltage value, and at least two of the three or more detection signals
A counting unit that counts the number of clock edges included between clock edges with at least two detection signals respectively corresponding to a phase difference delay from the timing at which each of the detection signals changes, the analog voltage value, A calculation unit for calculating a time interval between edges included between the three or more edges based on the number of clock edges.

Further, the conversion section outputs three or more timing signals that change based on the respective clock edges, and the counting section outputs a clock signal included between timings at which the three or more timing signals change. A digital-to-analog converter that counts the number of edges and converts the analog voltage value to a digital voltage value; and a voltage conversion unit that stores the converted digital voltage value. The unit preferably calculates the time interval based on the counted number of clock edges and the digital voltage value,
The digital conversion unit receives the three or more timing signals, and supplies the analog voltage value corresponding to the first changed timing signal among the received timing signals to the analog / digital converter. The supplied analog voltage value is
Based on the end of the operation of the digital converter for converting to the digital voltage value and the change in the timing signal,
It is preferable that the apparatus further includes a selection unit that sequentially selects the analog voltage values corresponding to the remaining timing signals from the received timing signals and sequentially supplies the analog voltage values to the analog-digital conversion unit.

Further, the counting section has a counter for counting the number of the clock edges and a clock memory for storing the counted number of the clock edges, and the received timing signal is the timing signal. It is preferable to indicate an address of a clock memory that stores the number of the clocks corresponding to the received timing signal in accordance with the order in which the received timing signals are received. On the basis of the,
Preferably, the apparatus further comprises an address encoder for encoding the address.

Further, the counting section counts the number of the clock edges included between a timing when the timing signal received first changes and a timing when a timing signal other than the timing signal received first changes. Preferably, it is counted and stored in the clock memory.

It is preferable that the arithmetic unit reads the digital voltage value stored in the voltage memory and the number of the clock edges stored in the clock memory, and calculates the time interval.

The input signal detection section outputs a positive detection signal which is the detection signal which changes based on a positive edge which is an edge when the input signal changes from L logic to H logic. A shift register and an inverted input signal obtained by inverting the input signal are input, and the inverted input signal is
A second shift register that outputs a negative detection signal that is the detection signal that changes based on a negative edge that is an edge when the logic changes from logic to H logic, and outputs the three or more detection signals in parallel. The shift register may be a shift register in which flip-flops having a data input and a trigger input are connected in a plurality of stages in series, and the flip-flop may be configured such that the input input to the trigger input is The data input to the data input is supplied to the data input of the next-stage flip-flop in response to a change in the edge of the signal or the inverted input signal, and the last one of the flip-flops connected in a plurality of stages is provided. The flip-flop of the first stage outputs the data obtained by inverting the data input to the data input according to the change of the edge. Tsu it is preferable to be supplied to the data input of the flop.

Further, the conversion unit receives the positive detection signal, and converts the phase difference between each timing at which the positive detection signal changes and a clock edge of a reference clock operating at a predetermined cycle with the analog voltage. A first timing voltage converter that converts the positive analog voltage value to a positive analog voltage value, and outputs the positive timing signal and the positive analog voltage value that are the timing signals that change based on the clock edge; Receiving and converting a phase difference between each timing at which the negative detection signal changes and a clock edge to a negative analog voltage value, which is the analog voltage value, and changing the timing signal based on the clock edge. A second time-to-voltage converter that outputs a negative timing signal and the negative analog voltage value. Good.

Further, the digital converter receives the positive analog voltage value and the positive timing signal and selects the positive analog voltage value to be converted into the digital voltage value. , A first analog-to-digital converter that is the analog-to-digital converter that converts the selected positive analog voltage value to a positive digital voltage value, and the voltage that stores the converted positive digital voltage value A first voltage digitizing unit having a first voltage memory that is a memory, receiving the negative analog voltage value and the negative timing signal, and selecting the negative analog voltage value to be converted to the digital voltage value; A second selector, which is a selector, and the analog digital converter for converting the selected negative analog voltage value into a negative digital voltage value. Second analog a barrel converter,
A second voltage digitizing unit having a digital converter and a second voltage memory that is the voltage memory that stores the converted negative digital voltage value may be provided.

The counting section receives the positive timing signal and counts the number of the clock edges included between the timings at which the positive timing signal changes. A first clock memory for storing the number of clock edges obtained
A first clock counting unit having a clock memory of
A second counter that receives the negative timing signal and counts the number of the clock edges included between timings at which the negative timing signal changes, and stores the counted number of the clock edges; A second clock counting unit having a second clock memory that is the clock memory, wherein the received change in the positive timing signal is received according to the order in which the changes in the positive timing signal are received. Indicates the address of the first clock memory that stores the number of the clock edges corresponding to the positive timing signal, and the change of the received negative timing signal is changed according to the order in which the change of the negative timing signal is received. The second clock source storing the number of the clock edges corresponding to the received negative timing signal. The re-of address may be indicated.

Further, it is preferable that the apparatus further comprises an edge difference counting section for counting the number of the clock edges included between the timing when the positive timing signal changes and the timing when the negative timing signal changes. The edge difference counting unit is configured to determine, when the first shift register is reset among the positive timing signals, a timing at which the first positive timing signal changes, and the second timing among the negative timing signals. Preferably, after the register is reset, the number of the clock edges included between the time when the first changed negative timing signal changes is counted.

Further, the first voltage digitizing section outputs a positive end signal which changes after all the positive digital voltage values to be stored in the first voltage memory are stored, and outputs the second voltage digitizing section. Outputs a negative end signal that changes after all the negative digital voltage values to be stored in the second voltage memory are stored, and the arithmetic unit outputs a positive end signal and an end signal based on the negative end signal. After receiving the change, data is read from the first voltage memory, the second voltage memory, the first clock memory, the second clock memory, and the edge difference counter, and the time interval is calculated. Is preferred.

According to a second aspect of the present invention, there is provided a test apparatus for testing an electronic device, comprising: a pattern generator for generating an input pattern signal to be input to the electronic device; A signal input / output unit that is in contact with, supplies the input pattern signal generated by the pattern generation unit to the electronic device, and receives an output pattern signal output by the electronic device based on the input pattern signal; and A detection unit that detects the output pattern signal to be output, wherein the detection unit detects a change in three or more edges of the output pattern signal, and changes the detection signal based on each of the three or more edges. An input signal detection unit that outputs
A converter that converts a phase difference between each timing at which the detection signal changes and a clock edge of a reference clock operating at a predetermined cycle into an analog voltage value; and at least two of the three or more detection signals. A counting unit that counts the number of clock edges included between the clock edges delayed by the phase difference corresponding to the at least two detection signals from the timing at which each of the two detection signals changes; and the analog voltage value. And a time measuring device including a calculating unit for calculating a time interval between edges included between the three or more edges based on the number of clock edges. .

Further, the test apparatus electrically connects the input signal detection unit and the conversion unit, and transmits a first transmission line for transmitting the three or more detection signals; A second transmission line that electrically connects the input signal detection unit and transmits the output pattern signal, and a transmission distance of the output pattern signal in the second transmission line is equal to the first distance. Is preferably shorter than the transmission distance of the three or more detection signals in the transmission line.

Further, the test apparatus electrically connects the input signal detection unit and the conversion unit, and transmits the three or more detection signals to the first transmission line; And a second transmission line that electrically connects the input signal detection unit and transmits the output pattern signal. The signal delay time of the output pattern signal in the second transmission line is the first Is preferably shorter than the signal delay time of the three or more detection signals in the transmission line.

Further, it is preferable that the first transmission line is a coaxial cable.

According to a third aspect of the present invention, a flip-flop having a data input and a trigger input is a shift register in which a plurality of stages are connected in series, and the flip-flop is input to the trigger input. In response to the trigger signal, the data input to the data input is supplied to the data input of the next-stage flip-flop, and the last one of the plurality of flip-flops connected in response to the trigger signal. A shift register that supplies inverted data of the data input to the data input to the data input of the first-stage flip-flop.

The above summary of the present invention does not enumerate all the necessary features of the present invention, and a sub-combination of these features can also be an invention.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the claimed invention and have the features described in the embodiments. Not all combinations are essential to the solution of the invention.

FIG. 1 shows a test apparatus 300 according to one embodiment of the present invention. The test apparatus 300 includes a pattern generation unit 302 that generates a signal having a desired pattern, a waveform shaping unit 304 that shapes a signal waveform, and a device under test 3.
08 is in electrical contact, and usually includes a signal input / output unit 306 installed in the test head, and a detection unit 310 including a time measurement device for measuring a time interval of a signal waveform. The time measurement device 100 includes an input signal detection unit, a conversion unit, a counting unit, and a calculation unit.

Next, the operation of the test apparatus 300 according to the present invention will be described. First, the pattern generation unit 302 generates an input pattern signal to be input to the device under test 308 according to the input characteristics of the device under test 308, and supplies the signal to the waveform shaping unit 304. The waveform shaping unit 304 shapes the waveform of the input pattern signal and supplies the waveform to the signal input / output unit 306.

The device under test 308 includes a signal input / output unit 3
06, an input pattern signal is received, and an output pattern signal is output based on the received input pattern signal. For example, if the device under test 308 is a memory device, data stored in the device under test 308 is output as an output pattern signal based on the input pattern signal. Is output as an output pattern signal. "Electronic devices"
The term “part” means a part that performs a predetermined action according to a current or a voltage, and is, for example, an IC (Integrated Circuit) or an LSI (Laser).
rge-Scale Integrated circuit). Further, these components may be provided on a wafer, or may be a component in which these components are combined into one package, or a predetermined function may be realized by mounting these components on a printed circuit board. Also includes components such as breadboards.

The time measuring device 10 included in the detecting unit 310
0 receives an output pattern signal as an input signal. The input signal detection unit detects a change in three or more edges of the input signal, and outputs a detection signal that changes based on each of the three or more edges in parallel. The conversion unit receives the detection signal, and converts a phase difference between each timing at which the detection signal changes and a clock edge of a reference clock operating at a predetermined cycle into an analog voltage value. The counting unit counts the number of clock edges included between the clock edges of at least two detection signals corresponding to the respective phase delays from the timing at which at least two of the three or more detection signals change, respectively. Count. Then, the calculation unit calculates a time interval between edges included between three or more edges based on the analog voltage value and the number of clock edges.

FIG. 2 shows a time measuring device 100 according to one embodiment of the present invention. The time measurement device 100 includes a clock generation unit 1 that generates a reference clock that operates at a predetermined cycle.
08 and an input signal detection unit 12 that detects changes in three or more edges of the input signal and outputs in parallel three or more detection signals that change based on each of the three or more edges.
0, the respective timings at which the detection signal changes, and the phase difference between the clock edge of the reference clock and the converter 140 that converts the phase difference into an analog voltage value.
From the timing at which each of at least two detection signals of the three or more detection signals changes, the number of clock edges included between the clock edges delayed by a corresponding phase difference between the at least two detection signals. A counting unit 150 for counting, and a control unit 102 that is a calculating unit that calculates a time interval between edges included between the three or more edges based on the analog voltage value and the number of clock edges. Prepare. In the present embodiment, the time measuring device 100 further includes a digital conversion unit 160 that converts the analog voltage value output from the conversion unit 140 into a corresponding digital voltage value.

The input signal detecting section 120 has n (n is a positive integer) positive detection signals which change based on a positive edge which is an edge when the input signal PS changes from L logic to H logic. A first shift register 122 that outputs signals (PE1 to PEn) and an inverted input signal NS obtained by inverting the input signal PS are input, and a negative edge that is an edge when the inverted input signal NS changes from L logic to H logic. A second shift register 142 that outputs m (m is a positive integer, m + n ≧ 3) negative detection signals (NE1 to NEm) that are detection signals that change based on edges.

The conversion section 140 includes a first shift register 1
22 receives the positive detection signals (PE1 to PEn) output in parallel, and calculates the phase difference between each timing when the positive detection signals (PE1 to PEn) change and the clock edge of the reference clock 12 operating at a predetermined cycle. , Positive analog voltage values (PV1 to P
Vn) and positive timing signals (PT1 to PT1) which are timing signals that change based on clock edges.
n) and the positive analog voltage values (PV1 to PVn) are output in parallel, and the first time-voltage conversion unit 124 outputs the negative detection signals (NE1 to NE) output from the second shift register 142.
m) in parallel and receive negative detection signals (NE1 to NEm)
Are converted into negative analog voltage values (NV1 to NVm), which are analog voltage values, respectively, and a negative timing signal (a timing signal that changes based on the clock edge) is converted. NT1 to NTm) and a negative analog voltage value (NV1)
To NVm) in parallel.
And 4.

The first time-to-voltage converter 124 receives one of the positive detection signals (PE1 to PEn) and converts the phase difference corresponding to the received positive detection signals (PE1 to PEn) to the positive analog voltage value (PE1 to PEn). PV1 to PVn),
N time-voltage converters (124-1 to 124-n) that output positive timing signals (PT1 to PTn) corresponding to the received positive detection signals (PE1 to PEn) and positive analog signals (PV1 to PVn) Having. Further, the second time-to-voltage converter 144 outputs a negative detection signal (NE1 to NEm).
And the received negative detection signal (NE1)
NEm) to the negative analog voltage values (NV1 to NVm), and the negative timing signal (NT) corresponding to the received negative detection signals (NE1 to NEm).
1 to NTm) and a negative analog signal (NV1 to NVm)
M time-to-voltage converters (144-1 to 144)
-M).

The digital conversion section 160 outputs a positive analog voltage value (PV) output from the first time-voltage conversion section 124.
1 to PVn) and a positive timing signal (PT1 to PTn), and a first unit that selects a positive analog voltage value (PV1 to PVn) to be converted into a digital voltage value.
And the selected positive analog voltage value (P
V1 to PVn) into a positive digital voltage value, a first voltage digitizing unit 126 having a first voltage memory storing the converted positive digital voltage value, 2 time-voltage converter 14
Negative analog voltage value output from 4 (NV1 to NVm)
And negative timing signals (NT1 to NTm)
Negative analog voltage value (NV) to be converted to digital voltage value
1 to NVm), a second multiplexer that is a selection unit that selects a selected negative analog voltage value, and a second analog / digital converter that converts the selected negative analog voltage value into a negative digital voltage value.
And a second voltage digitizing unit 146 having a second voltage memory that is a voltage memory for storing the converted negative digital voltage value.

The counting section 150 includes a first time-to-voltage conversion section 1
24 output from the positive timing signal (PT1-PT
n) and receives the positive timing signals (PT1 to PTn)
A first clock counting unit 128 having a first counter for counting the number of clock edges included between timings at which the clock signal changes, a first clock memory for storing the counted number of clock edges, 2 time-voltage converter 144
A second counter for receiving the negative timing signals (NT1 to NTm) output from the first counter and counting the number of clock edges included between the timings at which the negative timing signals (NT1 to NTm) change; And a second clock counter 148 having a second clock memory for storing the number of clocks.

Further, in the present embodiment, the time measuring device 100 determines the timing at which the positive timing signals (PT1 to PTn) change and the negative timing signals (NT1 to NT).
The apparatus further includes an edge difference counting unit 130 that counts the number of clock edges included between the timing when m) changes.

FIG. 3 shows a time measuring device 10 according to the present invention.
4 shows a timing chart of the operation of No. 0. With reference to FIG. 2, an operation of the time measuring device 100 that measures a time interval between edges included in the input signal PS will be described. In addition, as a specific example, an operation of detecting two positive edges and two negative edges included in the input signal PS and measuring a time interval between the detected four edges will be described.

First, in response to an instruction input from the operation unit 106, the control unit 102 sets the measurement start signal 1 indicating the start of measurement.
Change 0. The measurement start signal 10 may be a pulse signal. In response to a change in the measurement start signal 10, the first voltage digitizing unit 126 and the second voltage digitizing unit 14
6. Edge difference counting section 130, first time-voltage conversion section 12
4. The second time-to-voltage converter 144 and the flip-flop 210 accept the start of measurement. In addition, the clock generation unit 108 generates a clock that operates at a predetermined period T0, and generates a first time-voltage conversion unit 124, a second time-voltage conversion unit 144, a first clock counting unit 128, and a second time-voltage conversion unit 128. It is supplied to the clock counting section 148 and the edge difference counting section 130.

After receiving the change in the start signal 10, the flip-flop 210 inverts the input signal PS input to the time measuring device 100 in accordance with the change in the edge of the inverted input signal NS, and performs the first operation. Shift register 12
Signal 18 supplied to the second and second shift registers 142
Is changed, the first shift register 122 and the second shift register 142 are reset. In this embodiment, the time measuring device 100 includes a NOT circuit 20 that inverts and outputs an input signal, supplies the input signal PS to the first shift register 122, and inverts the input signal PS by the NOT circuit 20. Then, the inverted input signal NS is supplied to the second shift register 142. In another embodiment, the time measurement device 100 receives the input signal PS and the inverted input signal NS, and converts the input signal PS to the first shift register 122.
And supplies the inverted input signal NS to the second shift register 1
42.

The first shift register 122 receives the input signal PS, detects a positive edge which is an edge when the input signal PS changes from L logic to H logic, and the second shift register 142 Upon receiving the inverted input signal NS, a negative edge which is an edge when the input signal PS changes from H logic to L logic is detected based on a change in the edge of the inverted input signal NS. From the relation of the edge for inverting the flip-flop 210, the first shift register 12
After the second and second shift registers 142 are reset, the positive edge of the input signal PS is supplied to the first shift register 122.

After being reset, the first shift register 122 detects the positive edge of the received input signal PS, and the first shift register 122 is a positive detection signal that changes based on the positive edge of the input signal PS detected first. From the positive detection signal PE1 to the n-th positive detection signal, which is the n-th detected positive detection signal, are output in parallel. Also, the second shift register 14
2 is the inverted input signal NS received after reset.
(Corresponding to the negative edge of the input signal PS), and the first negative detection signal NE1 which is a negative detection signal that changes based on the positive edge of the inverted input signal NS detected first.
To the m-th negative detection signal NEm which is the m-th negative detection signal detected in parallel. In FIG. 2, after being reset, the first shift register 122 changes based on the positive edge of the input signal PS detected first.
Positive detection signal PE1 and the second detected input signal PS
Second positive detection signal PE2 that changes based on the positive edge of
Is output. In addition, the second shift register 142
After the reset, the first negative detection signal NE1 which changes based on the positive edge of the first detected inverted input signal NS (corresponding to the negative edge of the input signal PS) and the second detected inverted input signal NS A second negative detection signal NE2 that changes based on the positive edge is output.

The first time-to-voltage converter 124 receives the positive detection signals (PE1 to PEn) and outputs the positive detection signals (PE1 to PE1).
To PEn) and a fractional time which is a phase difference between the clock edge of the reference clock and the clock edge of the reference clock are converted into corresponding analog voltage values (PV1 to PVn). Then, the first time-to-voltage converter 124 outputs a positive timing signal (PT) indicating the timing of the clock edge corresponding to each of the positive detection signals (PE1 to PEn).
1 to PTn) and the positive analog voltage value (P
V1 to PVn). Specifically, the first time-voltage converter 124 includes n time-voltage converters (124-1)
１２４124-n), and the k-th time-to-voltage converter 124-k receives the k-th (k is an integer of 1 to n) positive detection signal PEk output from the first shift register 122. Is preferred. And the k-th time-to-voltage converter 12
4-k changes the k-th positive timing signal PEk,
Further, it is preferable to output the positive analog voltage value PVk. In the present embodiment, the first time-to-voltage converter 124-
1 outputs a positive analog voltage value PV1 corresponding to a fractional time Ta1, which is a phase difference between the first positive detection signal PE1 and a corresponding clock edge, and a _first signal indicating the timing of the clock edge. Vary the positive timing signal. The second time voltage converter 124-2, a second positive detection signal PE2, corresponding positive analog voltage value P corresponding to the fractional time Ta ₂ is a phase difference between the clock edges
V2, and changes the second positive timing signal indicating the timing of the clock edge.

Further, the second time-to-voltage converter 144 receives the negative detection signals (NE1 to NEm) and calculates the phase difference between the timing at which the negative detection signals (NE1 to NEm) change and the clock edge of the reference clock. For a certain fraction of time, the corresponding negative analog voltage values (NV1 to NV1)
m). Then, the second time-to-voltage converter 144
Changes the negative timing signals (NT1 to NTm) indicating the timings of the clock edges corresponding to the respective negative detection signals (NE1 to NEm), and outputs negative analog voltage values (NV1 to NVm). Specifically, the second time-to-voltage converter 144 includes m time-to-voltage converters (144-1 to 144-m), and outputs the h-th (h is 1) output from the second shift register 142. The positive detection signal NEh of (integer not less than m) is output to the h-th time-to-
Preferably 4-h receives. Then, the h-th time-to-voltage converter 144-h outputs the h-th negative timing signal NEh
And it is preferable to output a negative analog voltage value NVh. In this embodiment, the first time-to-voltage converter 144-1 outputs a negative analog voltage value NV 1 corresponding to a fractional time Tb ₁ that is a phase difference between the first negative detection signal NE 1 and a corresponding clock edge. Then, the first negative timing signal indicating the timing of the clock edge is changed. Also, the second time-to-voltage converter 144-2
It includes a second negative detection signal NE2, and outputs a negative analog voltage value NV2 corresponding to fractional time Tb ₂ is a phase difference between the corresponding clock edge, the second negative timing signal indicating the timing of the clock edge To change.

The timing signal generated by the time-to-voltage converter changes according to a predetermined clock edge after the detection signal changes, and generates an analog voltage value corresponding to a fractional time. The predetermined clock edge may be the same clock edge counted from the timing at which each detection signal changes. In this embodiment, in order to obtain a stable circuit operation of the time-voltage converter, each timing signal is generated at the second clock edge from the timing at which each detection signal changes.

The first clock counting section 128 receives the positive timing signals (PT1 to PTn) and counts the number of clock edges included between the timings at which the respective positive timing signals (PT1 to PTn) change. In the present embodiment, the first clock counting unit 128 determines the timing at which the first positive timing signal PT1 changes,
Counting the number alpha ₁₂ clock edge included between the timing of the positive timing signal PT2 varying. In the present invention, since the timing signal changes according to the clock edge, the change of the timing signal is slightly delayed with respect to the clock edge. Therefore, in this embodiment, the timing at which the first positive timing signal PT1 is changed, the number alpha ₁₂ clock edge included between the timing of the second positive timing signal PT2 is changed is 4.

The second clock counting section 148 receives the negative timing signals (NT1 to NTm) and counts the number of clock edges included between the timings at which the respective negative timing signals (NT1 to NTm) change. I do. In this embodiment. Second clock counting section 148
Counts the timing when the first negative timing signal NT1 is changed, the number beta ₁₂ clock edge included between the timing at which the second negative timing signal NT2 is changed. Number beta ₁₂ clock edge is 4.

The first voltage digitizing section 126 receives positive timing signals (PT1 to PTn) and positive analog voltage values (PV1 to PVn). Then, the first multiplexer selects a positive analog signal to be converted by the first analog-digital converter, and the first analog-digital converter converts the selected positive analog voltage value into a positive digital voltage value. Converted and stored in the first voltage memory.
Further, the first voltage digitizing section 126 outputs a positive end signal that changes after all the positive digital voltage values to be stored in the first voltage memory are stored.

The second voltage digitizing section 146 receives negative timing signals (NT1 to NTm) and negative analog voltage values (NV1 to NVm). Then, the second multiplexer selects a negative analog signal to be converted by the second analog-to-digital converter, and the second analog-to-digital converter converts the selected negative analog voltage value into a negative digital voltage value. Converted and stored in the second voltage memory.
Further, the second voltage digitizing section 146 outputs a negative end signal which changes after all the negative digital voltage values to be stored in the second voltage memory are stored.

In this embodiment, the positive end signal and the negative end signal are output by the digital conversion section 160, and the control section 102 is notified of the end of the measurement by an end signal based on the change of the positive end signal and the change of the negative end signal. . The end signal only needs to be output from the block that processes the data last, out of the blocks that process the data detected from the input signal PS necessary for the control unit 102 to perform the calculation. Then, it is preferable that the control unit 102 starts the calculation based on a change in the end signal output by the last block to be processed.

The edge difference counting unit 130 receives the positive timing signal and the negative timing signal, and counts the number of clock edges included between the timing at which the received positive timing signal changes and the timing at which the received negative timing signal changes. Is counted. In the present embodiment, the edge difference counting unit 130 counts the number γ of clock edges included between PT1 and NT1. In FIG. 3, the number γ of clock edges is two.

The control unit 102 includes a digital conversion unit 160
The calculation is started based on the end of the data processing. First, data stored in the first voltage memory, the second voltage memory, the first clock memory, the second clock memory, and the edge difference counting unit 130 are read out via a bus,
The time interval between edges included in the input signal PS is calculated. In this embodiment, the control unit 102 sets the fractional time T
digital voltage values corresponding to a ₁ , Ta ₂ , Tb ₁ , and Tb ₂ , and the number of clock edges α ₁₂ and β
₁₂ and the number γ of clock edges are read, and a time interval between edges included in the input signal PS is calculated.

Next, an embodiment of a circuit configuration for realizing the operation of each block included in the time measuring device 100 described with reference to FIGS. 2 and 3, and a detailed operation will be described.

FIG. 4 shows an embodiment of the shift register included in the input signal detection section 120. In FIG.
The configuration and operation of the shift register according to the present invention will be described using the first shift register 122 as an example. Second
Of the first shift register 12
It is preferable to have substantially the same configuration as 2.

In this example, the first shift register 12
2 has a configuration in which a plurality of flip-flops each having a data input terminal D and a trigger input terminal T are connected in series. The flip-flop 200 converts the data input to the data input terminal D into the data input terminal D of the next-stage flip-flop in response to a change in the edge of the input signal PS or the inverted input signal NS input to the trigger input terminal T. To supply. In addition, flip-flops 2 connected in a plurality of stages
00 of the final stage flip-flop (200- (n /
2)) is the input signal PS input to the trigger input terminal T
Or, according to a change in the edge of the inverted input signal NS,
The data obtained by inverting the data input to the data input terminal D is supplied to the data input terminal D of the first-stage flip-flop (200-1). In this example, the flip-flop 200 includes a reset input terminal R for receiving the signal 18,
It is preferably a D flip-flop having an output terminal Q and an inverted output terminal. In this example, the flip-flop 200, which is a D flip-flop, outputs the logical value of the signal received at the data input terminal D from the output terminal Q according to the rising edge of the signal received at the trigger input terminal T. In this example, the flip-flop 200
Is in a reset state while the signal 18 is at H logic, and outputs L logic from the output terminal Q.

FIG. 5 shows a timing chart of the operation of the first shift register 122 in this example. First,
The flip-flop 200 included in the first shift register 122 is reset according to the H logic of the signal 18. The flip-flop 200 outputs the L logic from the output terminal Q immediately after the reset is released, and outputs the H logic from the inverted output terminal.

After the first shift register 122 is reset, H logic is input to the data input terminal D of the first stage flip-flop (200-1), and the first positive edge of the input signal PS is Accordingly, the first-stage flip-flop (200-1) changes the inverted output as the first positive detection signal PE1 from H logic to L logic. At the same time, the first
The flip-flop (200-1) at the stage changes the (n / 2 + 1) th positive detection signal PE (n / 2 + 1), which is the output, from L logic to H logic, and outputs the output to the next-stage flip-flop. Is the second stage flip-flop (200
-2) to the data input terminal D. The second-stage flip-flop (200-2) inverts the H logic input to the data input terminal D as the inverted output in response to the second positive edge of the input signal PS input to the trigger input terminal T. The edge of the second positive detection signal PE2 is changed by outputting the output L logic.

The same operation is performed by sequentially shifting the output of the flip-flop 200 according to the positive edge of the input signal PS. The flip-flop (200- (n / 2)), which is the last-stage flip-flop, outputs the inverted output of the first-stage flip-flop in response to the positive edge of the next input signal PS whose H logic is input to the data input terminal D. Flip-flop (200-1)
To the data input. Then, the first-stage flip-flop (200-1) outputs the L logic inputted to the data input terminal D from the output terminal Q in response to the next positive edge of the input signal PS, thereby outputting the (n / The positive detection signal PE (n / 2 + 1) of (2 + 1) is changed from H logic to L logic.

First shift register 122 according to the present invention
Is obtained by feeding back the inverted output of the flip-flop (200- (n / 2)), which is the last-stage flip-flop, to the data input terminal D of the first flip-flop (200-1), whereby (n / 2) The n flip-flops can be used to output n detection signals. In another embodiment, z detection signals may be output using z (z is a positive integer) flip-flops.

FIG. 6 shows a time-to-voltage converter (124-1 to 124-1).
24-n, 144-1 to 144-n). The time-voltage converter 124-included in the first time-voltage converter 124-
1 will be described as an example. The time-to-voltage converter 124-1 is:
A timing generation circuit for generating a first positive timing signal PT1, a timing of the first positive detection signal PE1,
And an integrator circuit for converting a fractional time into a first positive analog voltage value PV1 between the positive timing signal PT1 and the positive timing signal PT1.
The integrating circuit includes an operational amplifier 212 and a capacitor 23.
0 and a resistor 220.

FIG. 7 shows a timing chart of the operation of the time-voltage converter 124-1. The operation of the time-to-voltage converter 124-1 will be described with reference to FIGS. First, in response to a change in the measurement start signal output from the control unit 102 (see FIG. 2), the flip-flop (20
2, 206, 208) are reset. Next, according to the change (negative edge) of the first positive detection signal PE1, the output signal 60 of the OR circuit 232 changes to L logic. The flip-flop 202 inverts the output and the inverted output 62 according to the negative edge of the output signal 60. The inverted output 62 is supplied to the trigger input T of the flip-flop 208. In response to the change of the inverted output 62, the output 68 of the flip-flop 208 changes from L logic to H logic. Then, in response to the change of the output 68, the switch 216 is opened, and the integration circuit starts charging. At this time, the switch 218 is short-circuited, and the reference voltage E is supplied to the resistor 220. The reference voltage may be a negative potential. Operational amplifier 214
Has a function of giving a predetermined amplification and offset to the output 70 of the integration circuit.

The change of the inverted output 62 of the flip-flop 202 from the H logic to the L logic cancels the reset of the flip-flop 204, so that the output 64 of the flip-flop 204 becomes L based on the negative edge of the clock 12. It changes from logic to H logic. Then, based on the next negative edge of the clock 12, the output 66 of the AND circuit 234 is output.
Changes from H logic to L logic. The negative edge is preferably a clock edge that determines a fractional time from the timing at which the first positive detection signal PE1 changes. In another embodiment, the positive edge is the first positive detection signal P
Any clock edge delayed by a predetermined phase from the timing at which E1 changes may be used. Next, the output 60 of the OR circuit 232 generates a negative edge based on the change of the output 66,
The output of the flip-flop 202 has L logic. Then, the flip-flop 206 outputs the positive timing signal PT
The output which is 1 is changed from L logic to H logic. Further, a change in the output of flip-flop 206 causes switch 218 to open. Then, the voltage value indicated by the output 70 of the integration circuit is held, and the first positive analog voltage value PV1 output from the operational amplifier 214 is held at a predetermined voltage value. Output from -1.

FIG. 8 shows a voltage digitizing section included in the digital conversion section. The first voltage digitizing unit 126 when n = 8 will be described as an example. The first voltage digitizing section 126 has a positive analog voltage value (PV1 to PVn).
(A / D converter) 236 for converting the analog voltage into a corresponding digital voltage value, a voltage memory 238 for storing the converted digital voltage value, and the received analog voltage value (PV1 to PVn). Among them, the analog voltage value (PV1 to P
Vn).

The positive analog signals (PV1 to PV8) supplied from the first time-to-voltage converter 124 are connected to the switches (2
54-1 to 254-8) via the first A / D converter 2
36. In this embodiment, the switch (254)
-1 to 254-8) are short-circuited when H logic is supplied,
The positive analog signals (PV1 to PV8) are supplied to the first A / D converter 236.

When a positive edge is input to the start input, the first A / D converter 236 converts the supplied positive analog voltage values (PV1 to PV8) into corresponding digital voltage values. To start. Then, when the A / D conversion ends, the first A / D converter 236 outputs a positive pulse from the end output.

FIG. 9 shows a timing chart of the operation of first voltage digitizing section 126 in FIG. The operation of the first voltage digitizing unit 126 will be described with reference to FIGS. First. In response to the change of the measurement start signal 10, the binary counter 242 and the flip-flop (24
4, 246) are reset. As for the output of the encoder 240, “0” becomes H logic and “1” to “7” becomes L logic. Then, the switches (254-2 to 254-
8) is opened, the switch 254-1 is short-circuited, and the first positive analog voltage value PV1 is changed to the first A / D converter 23.
6.

When the first positive timing signal PT1 supplied to the AND circuit 250-1 changes from L logic to H logic, the AND circuit 250-1 outputs H logic. Then, the first A / D converter 236 includes an OR circuit 248-1.
To start the A / D conversion of the supplied first positive analog voltage value PV1. When the A / D conversion ends, the first A / D converter 236 outputs a positive pulse from the end output. The positive pulse is supplied to the write control input WR of the first voltage memory 238, and the first voltage memory 238 becomes writable, and is A / D converted to the address “0” of the first voltage memory 238. The written data is written.

The positive pulse output from the end output of the first A / D converter 236 is supplied to a binary counter 242 and a flip-flop 246. Binary counter 242
Increases the count value from “0” to “1” according to the negative edge of the positive pulse. And encoder 2
As for the output of the switch 40, “1” becomes H logic, and the switch 254
-2 is short-circuited, and the second positive analog voltage value PV2 is supplied to the first A / D converter 236.

The output “1” of the encoder 240 is
The H logic is supplied to the AND circuit 250-2. Further, the flip-flop 246 outputs H logic from the output 88 in response to the negative edge of the positive pulse. Since the second positive timing signal PT2, which is the remaining input of the AND circuit 250-2, has already changed from L logic to H logic, the output of the AND circuit 250-2 changes from L logic to H logic. Let it. The positive edge output from the AND circuit 250-2 is passed through the OR circuit 248-8 to the delay circuit 252.
, And is further supplied to the first A / D converter 236 via the OR circuit 248-1. And
The first A / D converter 236 starts A / D conversion of the second positive analog voltage value PV2. The delayed positive edge is supplied to the reset of the flip-flop 246 via the OR circuit 248-3, and the flip-flop 2
Reset 46.

When the A / D conversion ends, the first A / D converter 236 outputs a positive pulse from the end output. The positive pulse is applied to the write control input WR of the first voltage memory 238.
And the first voltage memory 238 becomes writable, and the A / D-converted data is written to the address “1” of the first voltage memory 238.

The positive pulse output from the end output of the first A / D converter 236 is supplied to a binary counter 242 and a flip-flop 246. Binary counter 242
Increases the count value from “1” to “2” according to the negative edge of the positive pulse. And encoder 2
As for the output of the switch 40, “2” becomes H logic, and the switch 254
-3 is short-circuited, and the third positive analog voltage value PV3 is supplied to the first A / D converter 236. Also, encoder 2
The output "2" of 40 supplies H logic to the AND circuit 250-3. Further, the flip-flop 246 outputs H logic from the output 88 in response to the negative edge of the positive pulse. Then, the AND circuit 250-3 similarly supplies a positive edge to the start input of the first A / D converter 236 in response to the change of the third positive timing signal PT3 to the H logic, and The A / D converter 236 starts A / D conversion.

The same operation is repeated, and the multiplexer selects a positive analog voltage value to be A / D-converted, and the first A
The / D converter 236 performs A / D conversion, and the first voltage memory 238 stores the A / D converted data.
And the eighth positive analog voltage value to be converted is
H logic is supplied to the data input D of the flip-flop 244 according to the change of the positive analog voltage value PT8 from L logic to H logic. Then, the first A / D converter 23
6 responds to the negative edge of the positive pulse output when the A / D conversion of the eighth positive analog voltage value PV8 is completed, the flip-flop 244 causes the first A / D converter 236 to perform the A / D conversion. Positive analog voltage value to be converted (PV1 to PV8)
Of the A / D conversion is changed from L logic to H logic.

FIG. 10 shows a clock counting section included in the counting section. First clock counting section 128 when n = 8
Will be described as an example. The first clock counting unit 128
A first counter 262 for counting the number of clock edges included between the timings at which the received positive timing signals (PT1 to PT8) change, and a first clock memory 260 for storing the number of counted clock edges. A first clock memory 260 that encodes the address of the first clock memory 260 in which the counted number of clock edges is to be stored based on the change in the received timing signals (PT1 to PT8).
And an address encoder 264. The first address encoder 264 has an exclusive OR circuit (270-1 to 270-1).
270-4) and an OR circuit (272-1, 272-2)
And The first counter 262 is preferably a P-bit binary synchronous counter, where P is the counting capacity. The count capacity P (bits) of the δ-decimal counter is the minimum number that satisfies the following equation, where λ is the cycle of the reference clock, κ is the number of supplied positive timing signals, and 測定 is the measurement time. It is.

Δ ^P > (ξ / λ) × κ In the present embodiment, the counting capacity P is such that the reference clock cycle is 8 ns and the measurement is 1
If the calculation is performed up to the second, the counting capacity P becomes 30 bits.
By using the binary synchronous counter, the speed of writing to the first clock memory 260 can be increased. In other embodiments, the first counter 262 may not be synchronous and may not be binary.

FIG. 11 shows the first address encoder 26.
4 shows an example of the code conversion content of No. 4 and the data content stored in the first clock memory 260. FIG. 11 (a)
The content of encoding performed by the first address encoder 264 is shown. In the left table of FIG. 11A, when each of the positive timing signals (PT1 to PT8) indicates L logic, it is indicated by "0", and when it indicates H logic, it is indicated by "1". The positive timing signals (PT1 to PT8)
As shown in the left table, since the logic changes from L logic to H logic in order, eight states can be taken as a whole. FIG.
The table on the right side of (a) shows a state where the eight states are encoded. In the present embodiment, the first address encoder 264 has a function of encoding the truth table in the left table in FIG. 11A as shown in the right table.

FIGS. 11B and 11C show an example of the data contents stored in the first clock memory 260. FIG.
The first clock memory 260 preferably has a data width one bit larger than the counting capacity. In the present embodiment, the first clock memory 260 area which stores the counted number of clock edges _{(D 0 ~D p-1)}
When, and a region D _p which indicates whether the write operation has been performed at a predetermined address. The region D _p, preferably in advance "1" is written before starting measurement. And during the measurement, in the region D _p of the address which the writing operation has been performed "0" is written, The region D _p of the address writing operation is not performed remains "1".

FIG. 11B shows a state where the number of clock edges has been written to all addresses from # 0 to # 7. The number of each clock edge is written in the area _{(D 0 ~D p-1)} , and all the region D _p indicates that the write operation has been performed "0" is written. FIG.
(C) shows a state where the write operation is not performed in # 1, # 2, and # 4 to # 6. At this time, the number of clock edges of the address where the write operation has not been performed is determined by the area D _p
May be the same as the number of clock edges stored at the most recent upper address in which “0” is written to the address. For example, in FIG. 11C, the timing at which the first positive timing signal PT1 changes and the timing at which the sixth positive timing signal PT6 changes
The number of clock edges included between the timing at which the first positive timing changes and the timing at which the first positive timing changes,
This is the same as the number of clock edges included between the timing at which the fourth positive timing signal changes. Since the first clock memory 260 according to the present embodiment has the region _Dp , even if the time interval measured is shorter than the clock cycle, the time interval can be measured.

Next, the operation of the first clock counting section 128 will be described. In the present embodiment, the first clock counting unit 128 determines the timing at which the first positive timing signal PT1, which is the timing signal received first, changes, and the positive timing signals (PT2 to PT8) other than the first positive timing signal. ) Is counted and stored in the first clock memory 260.

First, according to the change of the measurement start signal 10,
First counter 262 and flip-flop 266 are reset. Next, the first positive timing signal PT1 becomes L
After changing from logic to H logic, the AND circuit 268 changes the H logic to the first counter 262 in response to the positive edge of the clock.
And the write control input WR of the first clock memory 260. The first counter 262 counts the number of negative edges of the clock, that is, the number of clock edges.
Is stored in the clock memory 260. At this time, the number of the clock edges is determined according to the H logic of the clock.
It is preferably stored in the first clock memory 260. In addition, it is preferable that the first counter 262 counts the number of clock edges in response to a negative edge of the clock. The change in the positive timing signals (PT1 to PT8) indicates the address of the first clock memory 260. For example, when the second positive timing signal PT2 changes from the L logic to the H logic, A0 is “1” in the corresponding address.
A1 indicates "0" and A2 indicates "0". The address is an address for storing the number of clock edges included between the timing at which the first positive timing signal PT1 changes and the timing at which the second positive timing signal PT2 changes (FIG. 11A). reference). Similarly, a positive timing signal (PT) other than the first positive timing signal PT1
2 to PT8), the number of clock edges included between the timing at which the first positive timing signal PT1 changes and the timing at which the other positive timing signals (PT2 to PT8) change. An address is specified, and the number of the clock edge is stored. At this time,
It is preferable that the count value before the count is advanced according to the negative edge of the clock is stored as the number of the clock edge. When the eighth positive timing signal PT8 changes from the L logic to the H logic, the inverted output of the flip-flop 266 is inverted by the negative edge of the output of the AND circuit 268 to supply the L logic to the AND circuit 268, Since the AND circuit 268 outputs L logic, the first counter 262
Does not count subsequent clock edges.

Since the clock counting section in this embodiment has an address encoder and a clock memory, only one counter is required, and the circuit efficiency is very good. In another embodiment, the clock counter may measure the number of clock edges by having a separate counter for each timing signal to be measured.

FIG. 12 shows the edge difference counting section 130.
The edge difference counting unit 130 includes a NOT circuit 284, an AND
A circuit 282 and a counter 280 are provided. Counter 280
Is preferably a binary counter having a predetermined counting capacity R. The edge difference counting unit 130 counts the number of clock edges included between the timing when the positive timing signals (PT1 to PTn) change and the timing when the negative timing signals (NT1 to NTm) change. In the present embodiment, the edge difference counting unit 130 determines the timing at which the first positive timing signal PT1, which is the first timing signal that has changed after the first shift register 122 has been reset, changes, and the second shift register After the reset of 142, the number of clock edges included between the timing at which the first negative timing signal NT1, which is the first negative timing signal that has changed, is changed is counted.

FIG. 13 is a timing chart of the operation of the edge difference counting section 130. The operation of the edge difference counting section 130 will be described with reference to FIGS. First, the counter 280 is reset by the change of the measurement start signal 10.

The first negative timing signal NT1 is NOT
The signal is inverted by the circuit 284 and supplied to the AND circuit 282. Then, after the first positive timing signal PT1 changes from L logic to H logic, AN
The D circuit 282 outputs a positive edge as the output 98.
The counter 280 counts the number of the clock edge according to the positive edge of the output 98 indicating the clock edge. Then, in response to the timing at which the first negative timing signal NT1 changes from L logic to H logic, the NOT circuit 2
84 supplies L logic to the AND circuit 282. Then, counter 280 holds a count value obtained by counting the number of clock edges included between the timing when first positive timing signal PT1 changes and the timing when first negative timing signal NT1 changes.

Referring to FIG. 2, control unit 102 includes control unit 1
02, among the blocks for processing data detected from the input signal PS necessary for the operation in the block 02, based on an end signal indicating that the processing in the last block for processing the data has been completed, It is preferable to receive In this embodiment, the positive end signal 92 output from the first voltage digitizing section 126 is output, and the negative end signal 94 output from the second voltage digitizing section 146 is output. Then, the AND circuit 40 supplies an end signal which is a logical product of the positive end signal 92 and the negative end signal 94 to the control unit 102. The control unit 102 changes the digital voltage value stored in the voltage memory, the number of clock edges stored in the clock memory, and the count value held by the counter of the edge difference counting unit 130 according to the change of the end signal. , Read via the bus. And the control unit 102
Calculates a fractional time from the digital voltage value, and calculates a time interval between edges of the input signal PS based on the fractional time, the number of clock edges, and the count value.

In this embodiment, the time measuring device 100
Detects the edge of the input signal PS continuously and detects the positive edge first. Therefore, the fractional time corresponding to the k-th positive detection signal PEk is Ta _k , the fractional time corresponding to the h-th negative detection signal is Tb _h , the timing at which the k-th positive timing signal PTk changes, and the k′-th positive The number of clock edges included between the timing when the timing signal PTk ′ (k <k ′ ≦ n) changes is α _{kk ′} , the timing when the hth negative timing signal PTh changes, and the h′th negative timing signal The number of clock edges included between the timing when NTh ′ (h <h ′ ≦ m) changes is β _{hh ′} , the timing when the first positive timing signal PT1 changes, and the timing when the first negative timing signal changes. Assuming that the number of clock edges included between the timings is γ, the kth positive edge and the k′th edge of the input signal PS have
The period that is the time interval with the th positive edge is the regular period k
k ′, a period that is the time interval between the hth negative edge and the h′th negative edge is a negative period hh ′, and a pulse that is the time interval between the kth positive edge and the kth negative edge. The width is defined as the positive pulse width k, and the h-th negative edge and (h + 1) th
Let the pulse width, which is the time interval with the th positive edge, be the negative pulse width h, they are expressed by

[0083]

(Equation 1) Then, the display unit 104 displays a time interval between edges of the input signal PS based on a calculation result of the control unit 102.

The time measuring device 100 according to the present invention can receive an edge of the input signal PS, detect the edge, and output the edge in parallel. Therefore, even when the time interval between edges is very short, The timing of the edge can be detected continuously. Also, by receiving the input signal PS only once, parameters necessary for measuring the time interval between edges can be obtained at the same time.
That is, there is no need to select a mode for detecting a positive edge and a mode for detecting a negative edge, or a mode for measuring a period and a mode for measuring a pulse width. It can be done easily.
Therefore, the time interval between the edges of the input signal PS can be measured continuously and very accurately.

FIG. 14 shows another embodiment of the time measuring device 100 in the test device 300. The time measuring device 100 of the present example is different from the time measuring device 100 shown in FIG. 2 in that the input signal detection unit 120 and the conversion unit 140 are electrically connected to each other and the detection signals (PE1 to PEn, NE1 to NE
m) is further provided. The first transmission line may be, for example, a cable. In this example, the first transmission line is a coaxial cable (400-1 to 400-4).
00-n, 410-1 to 410-m). The coaxial cable of this example is a first coaxial cable (4
00-1 to 400-n) and the second coaxial cable (410
-1 to 410-m). The first coaxial cable 400-a of this example (a is an integer satisfying 1 ≦ a ≦ n) transmits the a-th positive detection signal PEa. The second coaxial cable 410-b (b is an integer satisfying 1 ≦ b ≦ m) of the present example transmits the b-th negative detection signal PEb. Test apparatus 30 of this example
0 denotes a second transmission line which is a transmission line for electrically connecting the signal input / output unit 306 and the input signal detection unit 120 and transmitting an output pattern signal output from the device under test 308 which is an electronic device. Further provision. The transmission distance of the output pattern signal on the second transmission line is a coaxial cable (400-1 to 400-n, 410-1 to 410-m)
(PE1 to PEn, NE1 to NEm)
Is preferably shorter than the transmission distance. The signal delay time of the output pattern signal on the second transmission line is the same as the coaxial cable (400-1 to 400-n, 410-1 to 41-41).
0-m) (PE1 to PEn, NE1 to NE1)
NEm) is preferably shorter than the signal delay time. In this example, the second transmission line is a wiring on a printed circuit board.

In this example, the test head has a signal input / output unit 306 and an input signal detection unit 120. In this example, the semiconductor device test apparatus main body is
And a control unit 102 as a calculation unit and a digital conversion unit 160.

FIG. 15 shows an example of an embodiment of the first shift register 122 included in the input signal detection section 120 of this example. The second shift register 142 preferably has substantially the same configuration as the first shift register 122.

In this example, the first shift register 12
2 is n flip-flops (20
0-1 to 200-n). In this example, the flip-flop 200 includes a data input terminal D and an input signal P.
It is preferably a D flip-flop having a trigger input terminal T for receiving S, a reset input terminal R for receiving the signal 18, an output terminal Q, and an inverted output terminal.

In this example, the k-th stage (k is 1 ≦ k ≦ n
) Outputs a k-th positive detection signal PEk from the inverted output terminal. In this example, the k-th stage flip-flop 200-k receives the output signal of the (k-1) -th stage flip-flop 200- (k-1) at the data input terminal D. However, the first
The stage flip-flop 200-1 has a data input terminal D
Receives H logic. In this example, the flip-flop 200, which is a D flip-flop, outputs the logical value of the signal received at the data input terminal D from the output terminal Q according to the rising edge of the signal received at the trigger input terminal T. In this example, the flip-flop 200 is in the reset state while the signal 18 is at the H logic, and the output terminal Q
The L logic is output more.

FIG. 16 is a timing chart showing the operation of the first shift register 122 in this example. First, the flip-flop 200 included in the first shift register 122 is reset according to the H logic of the signal 18. The flip-flop 200 outputs the L logic from the output terminal Q immediately after the reset is released, and outputs the H logic from the inverted output terminal.

In this example, the first stage flip-flop (200-1) receives H logic at the data input terminal D. Therefore, the first-stage flip-flop (200-
In 1), after being reset, the inverted output as the first positive detection signal PE1 is changed from H logic to L logic in response to the first rising edge of the input signal PS. At the same time, the first
The stage flip-flop (200-1) changes the output from L logic to H logic and supplies the output to the data input terminal D of the second stage flip-flop (200-2) which is the next stage flip-flop. I do. In this example, the second-stage flip-flop (200-2) is connected to the trigger input terminal T
In response to the second rising edge of the input signal PS input to the second positive detection signal PE2.
Change from logic to L logic. At the same time, the second-stage flip-flop (200-2) changes the output from the L logic to the H logic and changes the output to the data input of the third-stage flip-flop (200-3) which is the next-stage flip-flop. Supply to terminal D.

Similarly, in this example, the k-th flip-flop (200-k) outputs the k-th positive detection signal in response to the k-th rising edge of the input signal PS input to the trigger input terminal T. The inverted output of the signal PE (k) is set to H
Change from logic to L logic. At the same time, the k-th stage flip-flop (200-k) changes the output from L logic to H logic.

As described above, in the present example, the shift register 122 responds to the (k) -th rising edge of the input signal PS in response to the (k) -th positive detection signal PE.
(M) is changed from H logic to L logic.

In this example, the coaxial cable (400-1)
To 400-n, 410-1 to 410-m) transmit detection signals (PE1 to PEn, NE1 to NEm) which are step signals having only one falling edge. Therefore, coaxial cables (400-1 to 400-n, 41
0-1 to 410-m).
The time measuring device 100 can also measure time with high accuracy even when the waveform that rises from H logic to L logic and the waveform that rises from L logic to H logic are different.

Therefore, according to the test apparatus 300 of this example,
Even when the output pattern signal, which is the input signal PS of the time measuring device 100, changes in a short cycle and is not suitable for long-distance transmission using a coaxial cable, the length using the coaxial cable from the test head to the main body of the device test apparatus can be improved. Distance transmission can be performed.

The coaxial cable of this example (400-1 to 400
-N, 410-1 to 410-m) may be a coaxial cable usable only in a frequency band lower than the frequency of the output pattern signal. In this example, coaxial cables (400-1 to 400-n, 410-1 to 410-m)
Is preferably a coaxial cable usable in a frequency band of about 100 MHz.

The input signal detection section 120 may have the first shift register 122 of the embodiment shown in FIG.
At this time, the second shift register 142 preferably has substantially the same configuration as the first shift register 122.
In this case, the number of flip-flops included in the input signal detection unit 120 can be reduced by half as compared with the case where the input signal detection unit 120 includes the shift register according to the embodiment illustrated in FIG. Therefore, according to this example, the signal detection unit 120
The mounting area can be reduced.

Although the present invention has been described with reference to the embodiment, the technical scope of the present invention is not limited to the scope described in the above embodiment. Various changes or improvements can be added to the above embodiment. It should be noted that such modified or improved embodiments may be included in the technical scope of the present invention.
It is clear from the description of the claims.

[0099]

As is apparent from the above description, according to the present invention, a minute time interval between edges of a signal can be accurately measured.

[Brief description of the drawings]

FIG. 1 shows a test apparatus 300 according to one embodiment of the present invention.

FIG. 2 is a time measuring device 100 according to an embodiment of the present invention.
Is shown.

FIG. 3 shows a timing chart of the operation of the time measuring device 100 according to the present invention.

FIG. 4 shows an embodiment of a shift register included in the input signal detection unit 120.

5 shows a timing chart of the operation of the first shift register 122. FIG.

FIG. 6 shows time-voltage converters (124-1 to 124-n, 1
44-1 to 144-m).

FIG. 7 shows a timing chart of the operation of the time-voltage converter 124-1.

FIG. 8 shows a voltage digitizing unit included in the digital conversion unit.

FIG. 9 shows a timing chart of the operation of the first voltage digitizing unit 126.

FIG. 10 shows a clock counting unit included in the counting unit.

11 shows an example of code conversion contents of the first address encoder 264 and data contents stored in the first clock memory 260. FIG.

FIG. 12 shows an edge difference counting unit 130.

13 shows a timing chart of the operation of the edge difference counting unit 130. FIG.

FIG. 14 is a time measuring device 10 according to an embodiment of the present invention.
Indicates 0.

FIG. 15 shows an embodiment of a shift register included in the input signal detection section 120.

16 shows a timing chart of the operation of the first shift register 122. FIG.

[Explanation of symbols]

100: time measuring device, 102: control unit, 12
0: input signal detection unit, 122: first shift register, 124: first time-voltage conversion unit, 126
.. A first voltage digitizing section, 128 a first clock counting section, 140 a conversion section, 142 a second shift register, 144 a second time voltage conversion section,
146: second voltage digitizing section, 148 ... second clock counting section, 150 ... counting section, 160 ...
.Digital conversion unit, 210: flip-flop,
236 ... first A / D converter, 238 ... first voltage memory, 260 ... first clock memory, 26
2 ... first counter, 300 ... test apparatus, 302
... Pattern generation part, 304 ... Waveform shaping part, 30
6 ... Signal input / output unit, 308 ... Device under test
310 ... detector, 400 ... first coaxial cable, 410 ... second coaxial cable,

Claims (20)

[Claims] An input signal detection unit that detects a change in three or more edges of the input signal and outputs in parallel three or more detection signals that change based on each of the three or more edges; A converting unit that converts a phase difference between each of the timings at which the reference clock changes and a clock edge of a reference clock operating at a predetermined cycle into an analog voltage value; and at least two of the three or more detection signals. A counting unit that counts the number of clock edges included between the clock edges delayed by the phase difference corresponding to the at least two detection signals, from the timing at which each of the signals changes, the analog voltage value; A calculating unit for calculating a time interval between edges included between the three or more edges based on the number of clock edges. A time measuring device comprising: 2. The conversion unit outputs three or more timing signals that change based on each of the clock edges, and the counting unit outputs a clock included between timings at which the three or more timing signals change. A digital conversion unit that counts the number of edges and converts the analog voltage value to a digital voltage value; and a voltage memory that stores the converted digital voltage value. The unit comprises: a number of the counted clock edges;
The time measuring device according to claim 1, wherein the time interval is calculated based on the digital voltage value. 3. The digital converter receives the three or more timing signals, and outputs the analog voltage value corresponding to the first changed timing signal among the received timing signals to the analog / digital converter. Of the received timing signal based on the end of the operation of converting the supplied analog voltage value to the digital voltage value by the analog / digital conversion unit and the change of the timing signal. 3. The image processing apparatus according to claim 2, further comprising a selection unit that sequentially selects the analog voltage values corresponding to the timing signal and sequentially supplies the analog voltage values to the analog / digital conversion unit.
2. The time measuring device according to 1. 4. The counting section has a counter for counting the number of clock edges, and a clock memory for storing the counted number of clock edges. The received timing signal is the timing signal 4. The time measuring device according to claim 2, wherein an address of a clock memory for storing the number of the clocks corresponding to the received timing signal is indicated in accordance with the order in which the changes in the time are received. 5. The time measuring device according to claim 4, wherein the counting unit further includes an address encoder that encodes the address based on a change in the received timing signal. 6. The counting section counts the number of clock edges included between a timing at which the timing signal received first changes and a timing at which timing signals other than the timing signal received first change. The time measuring device according to claim 4, wherein the time is counted and stored in the clock memory. 7. The arithmetic unit reads the digital voltage value stored in the voltage memory and the number of clock edges stored in the clock memory, and calculates the time interval. The time measuring device according to claim 4. 8. The first input signal detection unit outputs a positive detection signal, which is the detection signal that changes based on a positive edge that is an edge when the input signal changes from L logic to H logic. A shift register, and an inverted input signal obtained by inverting the input signal, and the negative detection signal being the detection signal that changes based on a negative edge when the inverted input signal changes from L logic to H logic. The time measurement device according to any one of claims 1 to 7, further comprising: a second shift register configured to output the three or more detection signals in parallel. 9. The shift register is a shift register in which flip-flops having a data input and a trigger input are connected in a plurality of stages in series, and the flip-flop is configured to receive the input signal input to the trigger input. Or supplying the data input to the data input to the data input of the next-stage flip-flop in response to a change in the edge of the inverted input signal; The flip-flop is configured to store data obtained by inverting data input to the data input in response to a change in the edge.
9. The time measuring device according to claim 8, wherein the data is supplied to a data input of the flip-flop of a stage. 10. The conversion unit receives the positive detection signal, and calculates a phase difference between each timing at which the positive detection signal changes and a clock edge of a reference clock operating at a predetermined period, using the analog voltage. To a positive analog voltage value,
A first timing voltage converter that outputs the positive timing signal and the positive analog voltage value that are the timing signal that changes based on the clock edge; and a first time-voltage converter that receives the negative detection signal and changes the negative detection signal. The phase difference between the timing and the clock edge is converted into a negative analog voltage value that is the analog voltage value, and the negative timing signal and the negative analog voltage value that are the timing signals that change based on the clock edge are output. The time measuring device according to claim 8, further comprising a second time-to-voltage converting unit. 11. The first selection unit, wherein the digital conversion unit receives the positive analog voltage value and the positive timing signal and selects the positive analog voltage value to be converted to the digital voltage value. Department and
A first analog-digital converter for converting the selected positive analog voltage value into a positive digital voltage value;
A first voltage digitizing section having an analog-to-digital converter, a first voltage memory serving as the voltage memory for storing the converted positive digital voltage value, and the negative analog voltage value and the negative timing signal. And a second selection unit that is the selection unit that selects the negative analog voltage value to be converted to the digital voltage value;
A second analog-digital converter for converting the selected negative analog voltage value to a negative digital voltage value.
And a second voltage digitizing unit having a second voltage memory which is the voltage memory for storing the converted negative digital voltage value. Time measuring device. 12. The first counter, wherein the first counter is the counter that receives the positive timing signal and counts the number of clock edges included between timings at which the positive timing signal changes. A first clock counting unit having a first clock memory that is the clock memory that stores the number of the clock edges obtained, the first clock counting unit receiving the negative timing signal, and being included between timings at which the negative timing signal changes. A second clock counting unit including a second counter as the counter for counting the number of the clock edges and a second clock memory as the clock memory for storing the counted number of the clock edges; The change of the received positive timing signal is received according to the order in which the change of the positive timing signal is received. Indicates the address of the first clock memory that stores the number of the clock edges corresponding to the removed positive timing signal; and the change in the received negative timing signal is the order in which the change in the negative timing signal is received. 10. The time measuring device according to claim 8, wherein an address of the second clock memory for storing the number of the clock edges corresponding to the received negative timing signal is indicated in response to the timing. 13. The apparatus according to claim 12, further comprising an edge difference counting unit that counts the number of clock edges included between a timing at which the positive timing signal changes and a timing at which the negative timing signal changes. Item 13. The time measuring device according to any one of Items 8 to 12. 14. The edge difference counting section according to claim 1, wherein, among the positive timing signals, a timing at which the first positive timing signal changed after the first shift register is reset, and a timing at which the negative timing signal changes. , The second
14. The time measuring apparatus according to claim 13, wherein after the shift register is reset, the number of the clock edges included between the timing when the negative timing signal changed first and the timing when the negative timing signal changed is counted. 15. The first voltage digitizing unit outputs a positive end signal that changes after all the positive digital voltage values to be stored in the first voltage memory are stored, and the second voltage digitizing unit Outputs a negative end signal that changes after storing all of the negative digital voltage values to be stored in the second voltage memory. The arithmetic unit outputs a positive end signal and an end signal based on the negative end signal. After receiving the change, data is read from the first voltage memory, the second voltage memory, the first clock memory, the second clock memory, and the edge difference counter, and the time interval is calculated. The time measuring device according to claim 13, wherein the time is measured. 16. A test apparatus for testing an electronic device, comprising: a pattern generating unit that generates an input pattern signal to be input to the electronic device; and the electronic device is in electrical contact with the electronic device. A signal input / output unit that supplies the generated input pattern signal to the electronic device and receives an output pattern signal output by the electronic device based on the input pattern signal; and detects the output pattern signal output by the electronic device. And a detection unit that detects a change in three or more edges of the output pattern signal and outputs a detection signal that changes based on each of the three or more edges in parallel. Unit, each timing when the detection signal changes, and a clock in a reference clock operating at a predetermined cycle. A conversion unit that converts a phase difference from the edge to an analog voltage value, and the at least two detection signals respectively correspond to at least two of the three or more detection signals from a timing at which each of the detection signals changes. A counting unit that counts the number of clock edges included between the clock edges delayed by the phase difference, based on the analog voltage value and the number of clock edges,
A test unit including a calculation unit for calculating a time interval between edges included between the three or more edges. 17. The test apparatus, comprising: a first transmission line that electrically connects the input signal detection unit and the conversion unit and transmits the three or more detection signals; A second transmission line that electrically connects the input signal detection unit and transmits the output pattern signal, wherein the transmission distance of the output pattern signal in the second transmission line is the first distance. 2. The transmission line of claim 1, wherein said transmission line is shorter than a transmission distance of said three or more detection signals.
7. The test apparatus according to 6. 18. The test apparatus, wherein the input signal detection unit, the conversion unit is electrically connected, a first transmission line for transmitting the three or more detection signals, the signal input and output unit, And a second transmission line that electrically connects the input signal detection unit and transmits the output pattern signal. The signal delay time of the output pattern signal in the second transmission line is the first 17. The test apparatus according to claim 16, wherein a signal delay time of the three or more detection signals in the transmission line is shorter than a signal delay time. 19. The test apparatus according to claim 17, wherein the first transmission line is a coaxial cable. 20. A shift register, wherein a flip-flop having a data input and a trigger input is a shift register in which a plurality of stages are connected in series, wherein the flip-flop operates according to a trigger signal input to the trigger input. The data input to the input is supplied to the data input of the next-stage flip-flop, and the last-stage flip-flop among the plurality of connected flip-flops is input to the data input in response to the trigger signal. A shift register for supplying inverted data to a data input of the flip-flop of the first stage.