JP2019176358A - Time digital conversion circuit and time digital conversion method - Google Patents

Abstract

To provide a time digital conversion circuit capable of normally converting a time interval between a clock signal and an object signal into a digital signal with resolution higher than a delay amount of each delay circuit.SOLUTION: A time digital conversion circuit comprises: a vernier form delay chain; a plurality of storage processing parts; and a controller controlling an output of the plurality of storage processing parts. Each of the plurality of storage processing parts includes a storage part capable of storing a capture result of a plural times of the vernier form delay chain, and the controller makes output data captured by the vernier form delay chain by one clock signal and containing a plurality of capture results stored in the plurality of storage processing parts to integrally output.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a time digital conversion circuit (TDC) and a time digital conversion method, and more particularly to a time digital conversion circuit and a time digital conversion method using a vernier delay chain.

  There has been a time digital conversion circuit for converting a time interval between a measurement target signal and a reference signal into a digital value using a delay chain. A typical delay chain includes a transmission line in which a plurality of delay circuits are connected in series, and a plurality of flip-flops provided corresponding to the plurality of delay stages of the transmission line. Each flip-flop captures the signal level of the corresponding delay stage of the transmission line in synchronization with the reference signal input simultaneously. In such a circuit, the target signal is input to the transmission path, and the reference signal is input to the plurality of flip-flops while the target signal travels through the transmission path. For example, when the reference signal is input at the timing when the high-level target signal reaches the x-th delay stage, the high-level signal is captured until the x-th stage flip-flop, and the flip-flops from the x + 1 stage onward Captures low level signals. Therefore, the output of the plurality of flip-flops reveals to which delay circuit in the transmission path the target signal has been input when the target signal has advanced. Then, the time interval between the target signal and the reference signal is obtained from the delay amount τ of each delay circuit. In the above example, x × τ is the time interval between the target signal and the reference signal. In such a circuit, the resolution of the measured time interval is the delay amount τ.

  Conventionally, a time digital conversion circuit using a vernier type delay chain that can convert a time interval into a digital value with a resolution higher than the delay amount of each delay circuit included in the delay chain is known. The vernier type delay chain is configured by connecting a plurality of delay circuits in series to the reference signal transmission path. The vernier-type delay chain uses two types of delay circuits having different delay amounts τ1 and τ2, so that the measurable time interval resolution becomes a delay amount difference | τ1−τ2 |.

  8 to 11 of Patent Document 1 show, as a technique related to the present invention, outputs of the flip-flops (12) of the delay stages of the delay chain included in the time digital conversion circuit are two flip-flops (L1, L2). ) Is disclosed.

International Publication No. 2010/013385

  A circuit using a vernier delay chain can measure the time interval between the target signal and the reference signal with high resolution by adding a delay to the reference signal in a plurality of stages. For this reason, there is a problem that the time required for measuring the time interval becomes longer than the maximum value of the measurable time interval. For example, each delay circuit of the transmission path through which the target signal is transmitted has a delay amount τ1, each delay circuit of the transmission path through which the reference signal is transmitted has a delay amount τ2, and the delay stage of each transmission path is n A step. Then, since the resolution becomes | τ1-τ2 |, the maximum measurable time interval is | τ1-τ2 | × n. On the other hand, the time required for one measurement is τ1 × n, which is the time required for transmitting the target signal along the transmission path, and the time required for the measurement is longer.

  For this reason, when the reference signal is input as a periodic clock signal and the measurement is repeatedly performed, when the clock cycle is adjusted to the time required for one measurement, the maximum measurable time interval is one in the clock cycle. It will be limited to the part period. In this case, the time interval cannot be measured even if the target signal is input in another period within the clock cycle. Also, when the clock period is set to the maximum measurable time interval, the next clock signal is input to the delay chain before one measurement is completed after one clock signal is input to the delay chain. The next measurement will start. For this reason, when outputting the digital value of the first measurement result, the digital value on the start end side is updated by the next clock signal, which may cause a problem that a normal result cannot be obtained (FIG. 9 and FIG. 9). (See description of comparative example). Such a problem is not solved by the technique of Patent Document 1.

  An object of the present invention is to provide a time digital conversion circuit capable of normally converting a time interval between a clock signal and a target signal into a digital value with a resolution higher than the delay amount of each delay circuit.

  The present invention for solving the above problems includes the following technical features or invention specific matters.

  In other words, according to one aspect of the present invention, a transmission path in which a plurality of delay circuits are connected in series and a signal to be measured is transmitted, and a plurality of clock delay circuits having a delay amount different from the delay circuit are connected in series. The clock transmission path, a plurality of delay stages of the transmission path and a plurality of delay stages of the clock transmission path, respectively, and based on the clock signal that has reached the corresponding delay stage of the clock transmission path, A plurality of capture units that capture the signal level of the corresponding delay stage of the transmission line, a plurality of vernier delay chains, a plurality of storage processing units provided corresponding to the plurality of capture units, and the plurality A controller for controlling the output of the storage processing unit, each of the plurality of storage processing units, and a storage unit capable of storing a plurality of capture results of the corresponding capture unit, A processing unit that sequentially stores the capturing results of the capturing unit in the storage unit, and the controller is captured by the plurality of capturing units when one clock signal is transmitted to the clock transmission path. And a time digital conversion circuit for outputting output data including a plurality of capture results stored in the plurality of storage processing units simultaneously from the plurality of storage processing units.

  Here, each of the plurality of storage processing units sequentially stores the capture results in synchronization with the clock signal that has reached the corresponding delay stage of the clock transmission path, and the controller sequentially stores the clock transmission path. The output data may be sequentially output in synchronization with a supplied clock signal.

  Further, the storage processing unit sequentially stores a plurality of holding circuits capable of holding the capture results of the corresponding capturing units based on a clock signal, and a clock signal that sequentially reaches the corresponding delay stage of the clock transmission path, A distribution unit that distributes to a plurality of holding circuits, and a multiplexer that outputs any of the plurality of capture results held in the plurality of holding circuits based on the control of the controller.

  Further, each of the plurality of storage processing units can store k times of acquisition results, and the controller stores the most recently stored acquisition result from the storage processing unit corresponding to the last delay stage of the transmission path. It may be configured to output.

  Furthermore, the period p of the clock signal, the number k of the capture results that can be stored in the storage unit, and the time T for the target signal to reach the last delay stage from the beginning of the transmission path are p × k. A relationship of ≧ T may be satisfied.

  Furthermore, the maximum time interval that can be converted into a digital value may be equal to or longer than the period of the clock signal.

  According to another aspect of the present invention, there is provided a clock in which a plurality of delay circuits are connected in series and a signal to be measured is transmitted, and a clock in which a plurality of clock delay circuits having different delay amounts from the delay circuits are connected in series. A transmission line, a plurality of delay stages of the transmission line, and a plurality of delay stages of the clock transmission line, respectively, and based on the clock signal reaching the corresponding delay stage of the clock transmission line, the transmission line Time digital conversion using a vernier delay chain having a plurality of capturing units that capture signal levels of corresponding delay stages, and a plurality of storage units provided corresponding to the plurality of capturing units, respectively In the method, each of the plurality of storage units sequentially stores a plurality of capture results of the corresponding capture unit, and is captured by the plurality of capture units based on one clock signal. One output data including the plurality of the plurality of capture results stored in the storage unit, to output simultaneously from said plurality of storage units, the time-digital conversion process.

  Here, in each of the plurality of storage units, the capture result is stored in synchronization with the clock signal that has reached the corresponding delay stage of the clock transmission path, while the clock sequentially supplied to the clock transmission path The output data may be sequentially output in synchronization with the signal.

  According to the present invention, the time interval between the clock signal and the target signal is normally converted into a digital value with a resolution higher than the delay amount of the delay circuit of the transmission path and the delay amount of the clock delay circuit of the clock transmission path. The effect that it can do is acquired.

It is a block diagram which shows an example of a structure of the time digital conversion circuit which concerns on one Embodiment of this invention. It is a block diagram which shows an example of a structure of the container of the time digital conversion circuit which concerns on one Embodiment of this invention. FIG. 3 is a circuit diagram illustrating an example of a configuration of the counter of FIG. 2. FIG. 3 is a circuit diagram illustrating an example of a configuration of a selector in FIG. 2. It is a timing chart which shows operation | movement of the container in the time digital conversion circuit which concerns on one Embodiment of this invention. It is a block diagram which shows an example of a structure of the controller of the time digital conversion circuit which concerns on one Embodiment of this invention. It is a circuit diagram which shows an example of a structure of the encoder of FIG. It is a timing chart which shows operation of a controller in a time digital conversion circuit concerning one embodiment of the present invention. It is a timing chart of each signal of the time digital conversion circuit of a comparative example. It is a timing chart of each signal of the time digital conversion circuit concerning one embodiment of the present invention. It is a block diagram which shows an example of a structure of the controller of the time digital conversion circuit which concerns on other embodiment of this invention.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a time digital conversion circuit according to an embodiment of the present invention. As illustrated in FIG. 1, the time digital conversion circuit 1 includes, for example, a vernier delay chain 11, a plurality of containers 13, and a controller 15. The time digital conversion circuit 1 receives a clock signal CLK having a predetermined period p and a measurement target signal from the outside, and converts the time interval of the input timing between the clock signal and the target signal into output data OUT0 to OUTn which are digital values. To do. Among the above components, the container 13 corresponds to an example of a storage processing unit according to the present invention.

  The delay chain 11 includes a transmission path 111 in which a plurality of delay circuits e are connected in series, and a clock transmission path 112 in which a plurality of delay circuits f are connected in series. A target signal is transmitted to the transmission path 111, and a clock signal is transmitted to the clock transmission path 112. Hereinafter, the input node of the transmission line 111 is defined as the 0th delay stage, and the output node of the uth delay circuit e (where u is any one of 1 to n) from the input side is defined as the uth delay stage. The total number of delay stages from the 0th stage to the uth stage is defined as u stage without counting the 0th stage. The same applies to the clock transmission path 112. The delay chain 11 further includes a flip-flop array 113. The flip-flop array 113 includes n + 1 flip-flops g corresponding to a plurality of delay stages from the 0th stage to the nth stage. Among the above components, the delay circuit f corresponds to an example of a clock delay circuit according to the present invention. The flip-flop g corresponds to an example of the capturing unit according to the present invention. Hereinafter, the flip-flop g corresponding to the u-th delay stage is also referred to as a u-th flip-flop g.

  The delay amount τ1 of each delay circuit e in the transmission path 111 is different from the delay amount τ2 of each delay circuit f in the clock transmission path 112. For example, τ1 = 38 ps and τ2 = 28 ps. In FIG. 1, signals sig1 to sign represent the delay stages from the first stage to the nth stage of the transmission path 111, respectively, and the clock signals ck1 to ckn are the first to nth delay stages of the clock transmission path 112, respectively. Each clock signal is shown.

  Each of the plurality of flip-flops g is connected so that the signal of the delay stage corresponding to the transmission path 111 is input to the data terminal and the signal of the delay stage corresponding to the clock transmission path 112 is input to the control terminal. As a result, the m-th (m is any one of 0 to n) flip-flop g captures the signal level of the m-th delay stage signal sigm based on the m-th delay stage clock signal ckm. . The m-th flip-flop g continues to output the supplemented signal level until the next clock signal ckm is input.

  Here, the principle of time measurement by the delay chain 11 will be described. When (delay amount τ1 of delay circuit e)> (delay amount τ2 of delay circuit f), the clock signal after the target signal is input becomes a reference signal for measuring the time interval. Due to the delay amount relationship τ 1> τ 2, the speed at which the clock signal as the reference signal travels through the clock transmission path 112 is faster than the speed at which the target signal travels through the transmission path 111. It is assumed that the clock signal catches up with the x-th delay stage of the clock transmission path 112 when the target signal reaches the x-th delay stage of the transmission path 111. In this case, before the x-th stage, when the clock signal arrives, the target signal has already been reached. Further, after the x-th stage, when the clock signal arrives, the target signal has not yet arrived. For this reason, assuming that the target signal is a signal that changes from a low level to a high level, the flip-flop g up to the x-th stage captures the high-level signal, and the flip-flop g in the subsequent stage from the (x + 1) -th stage is low. Capture level signal. Therefore, it is determined by the captured data (capture results) F0 to Fn of the plurality of flip-flops g when the target signal has advanced to which delay stage the clock signal has caught up. The timing at which the clock signal reaches the x-th delay stage is the timing at which the clock signal is input to the clock transmission path 112 + x × τ2. The timing at which the target signal reaches the x-th delay stage is the timing at which the target signal is input to the transmission path 111 + x × τ1. These can be regarded as the same timing. From these, the time interval [xx (τ1-τ2)] of the input timing between the target signal and the clock signal is obtained. Since x means a certain number of delay stages of the transmission path 111 and the clock transmission path 112, the measurable time interval resolution r is (τ1-τ2). If τ1 = 38 ps and τ2 = 28 ps, the resolution r is 10 ps, and the resolution r is smaller than the delay amounts τ1 and τ2 of the delay circuits e and f.

  The delay stage number n of the delay chain 11 is set so that the time interval between the clock signal and the target signal can be measured regardless of the timing of the clock signal p. That is, since the maximum measurable time interval (delay stage number n × resolution r) only needs to be equal to or greater than the clock period p, the delay stage number n is set to an integer equal to or greater than the clock period p / resolution r. Note that by setting the number of delay stages n = p / r (in the case of an integer) or = [an integer obtained by rounding up the first decimal place of p / r], redundancy of the delay stage is omitted. The clock signal may be configured to be supplied from the outside of the time digital conversion circuit 1, or the time digital conversion circuit 1 may include a clock generation circuit that generates a clock signal having such a cycle. Good.

  As shown in FIG. 1, the plurality of containers 13 correspond to the plurality of flip-flops g of the delay chain 11, that is, correspond to the plurality of delay stages from the 0th stage to the nth stage of the delay chain 11, respectively. Is provided. Hereinafter, the container 13 corresponding to the m-th delay stage (m is any one of 0 to n) is also referred to as the m-th container 13. Each of the plurality of containers 13 receives the clock signals ck0 to ckn that have reached the corresponding delay stage, the captured data F0 to Fn of the flip-flop g of the corresponding delay stage, and the selection signals SEL0 and SEL1 of the controller 15. . The plurality of containers 13 respectively store the captured data F0 to Fn for a plurality of times of the corresponding flip-flop g. Further, the plurality of containers 13 output any one of the stored captured data F0 to Fn as output data OUT0 to OUTn according to the selection signals SEL0 and SEL1 of the controller 15, respectively.

  FIG. 2 is a block diagram showing an example of the configuration of the container of the time digital conversion circuit according to the embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of the configuration of the counter of FIG. FIG. 4 is a circuit diagram showing an example of the configuration of the selector of FIG. FIG. 5 is a timing chart showing the operation of the container in the time digital conversion circuit according to the embodiment of the present invention.

  As shown in FIG. 2, the m-th container 13 includes, for example, a clock signal ckm that has reached the m-th delay stage, and captured data Fm of the flip-flop g corresponding to the m-th delay stage. Is entered. The container 13 includes a counter 131, an inverter IV, a plurality of selectors 132, a plurality of holding circuits 133, and multiplexers 134 and 135. The plurality of holding circuits 133 correspond to an example of a storage unit according to the present invention. The counter 131, the inverter IV, and the plurality of selectors 132 correspond to an example of a processing unit according to the present invention. The counter 131 and the plurality of selectors 132 correspond to an example of a distribution unit according to the present invention.

  The counter 131, the inverter IV, and the plurality of selectors 132 generate synchronization signals c <b> 0 to c <b> 3 in synchronization with the clock signal ckm and output the synchronization signals c <b> 0 to c <b> 3 to the holding circuit 133. As shown in FIG. 5, the synchronization signals c0 to c3 are signals that become a high level for about a half cycle of the clock signal in four clock cycles, and are set to a high level for each clock cycle in the order of the synchronization signals c0 to c3. This signal changes cyclically. The rising timing of the synchronization signals c0 to c3 is set so as to be delayed by about half of one clock cycle from the rising of the clock signal ckm.

  For example, as shown in FIG. 3, the counter 131 is configured by a state machine having four flip-flops a. The counter 131 is initialized so that any one of the four state signals s0 to s3 is at a high level, and the state signals s0 to s3 that are at a high level are synchronized with the clock signal ckm in this order. Change cyclically. As shown in FIG. 4, each selector 132 receives, for example, a state signal s0 to s3 corresponding to one input terminal, and an AND circuit b that receives the clock signal ckmb inverted by the inverter IV to the other input terminal. Composed. With such a configuration, the above-described synchronization signals c0 to c3 are generated.

  The plurality of holding circuits 133 function as a storage unit that sequentially stores captured data Fm for a plurality of times. The holding circuit 133 can be composed of, for example, a flip-flop. Each of the plurality of holding circuits 133 holds the captured data Fm based on the synchronization signals c0 to c3, and maintains the output of the holding data q0 to q3 until the next input of the synchronization signals c0 to c3. As shown in FIG. 5, the synchronization signals c0 to c3 that cyclically rise in one clock cycle cause the plurality of holding circuits 133 to sequentially cycle the captured data Fm “D0, D1,...” That change in one clock cycle. Keep on. The plurality of holding circuits 133 maintain the holding data q0 to q3 “D0, D1,...” For 4 clock cycles.

  The multiplexers 134 and 135 output any one of a plurality of times of retained data q0 to q3 stored in the plurality of retaining circuits 133 as output data OUTm according to the selection of the controller 15. The multiplexer 134 operates in synchronization with the selection signals SEL0 and SEL1 of the controller 15 asynchronously with the clock signal ckm.

  Note that FIG. 2 illustrates a case where the four holding circuits 133 are provided, but there may be a case where a number other than four is employed. In the following, a generalized case of k pieces will be described. In this case, the number of state signals s0 to sh of the counter 131 (h is k-1), the number of selectors 132, the number of synchronization signals c0 to ch, the number of retained data q0 to qh, and signals that can be selected by the multiplexers 134 and 135. The number is k. Then, the synchronization signals c0 to ch become a signal that becomes a high level for about a half cycle of the clock signal in the k clock cycle, and the target to be set to the high level every clock cycle in the order of the synchronization signals c0 to ch is cyclic. The signal changes to. Further, the k holding circuits 133 store the captured data Fm for k clock cycles at the same time, and each holding circuit 133 operates so as to continue outputting the holding data q0 to qh for the k clock cycles.

  The number k of holding circuits 133 provided in the container 13, that is, the number k of captured data Fm that can be held simultaneously is designed as follows. That is, the number k is set so that the k + 1th measurement is not started before one measurement time T elapses after the clock signal is input to the delay chain 11 and the measurement is started. Is done. Here, one measurement time T is defined as a time (n × τ1) from when the target signal is input to the transmission path 111 until it reaches the nth delay stage. If the (k + 1) th measurement is started before one measurement time T elapses, the captured data Fm from the first time to that time cannot be held in the container 13 on the start end side of the delay chain 11, Normal measurement results cannot be output. Such a situation can be avoided by the above setting. The time length from the start of the first measurement to the start of the (k + 1) th measurement is k × clock period p, and this may be equal to or longer than the one measurement time T. An integer greater than / p. The number of captured data k that can be held is T / p (in the case of an integer) or [an integer obtained by rounding up the first decimal place of T / p (in the case of a non-integer)], so that the container 13 The redundancy of the configuration can be omitted.

  FIG. 6 is a block diagram showing an example of the configuration of the controller of the time digital conversion circuit according to the embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of the configuration of the encoder of FIG. FIG. 8 is a timing chart showing the operation of the controller in the time digital conversion circuit according to the embodiment of the present invention. Here, a description will be given of a configuration in which four holding data q0 to q3 are held in each container 13, and the controller 15 selects one of the four holding data q0 to q3.

  The controller 15 outputs 2-bit selection signals SEL0 and SEL1 for selecting the outputs of the plurality of containers 13 in synchronization with the clock signal supplied to the delay chain 11. The selection signals SEL0 and SEL1 are output so that the holding data q0 to q3 are output in the same order as the order in which the plurality of holding circuits 133 of each container 13 capture the captured data Fm (m is any one of 0 to n). Generated. The selection signals SEL0 and SEL1 are output to the plurality of containers 13 asynchronously with the delayed clock signals ck1 to ckn and in synchronization with the clock signal before the delay is added.

  As shown in FIG. 6, the controller 15 includes a counter 151 that switches the four state signals s0 to s3 in synchronization with the clock signal, and an encoder 152 that generates selection signals SEL0 and SEL1 corresponding to the four state signals s0 to s3. It can comprise. The counter 151 can be configured similarly to the counter 131 of the container 13 in FIG. Further, as shown in FIG. 7, the encoder 152 can be composed of two OR circuits c that generate 2-bit selection signals SEL0 and SEL1 from the three state signals s1 to s3. In this case, the counter 151 sets the initial state so that the cycle in which the state signals s0 to s3 are to be switched to the high level is cyclically switched by one clock cycle compared with that of the counter 131 of the container 13. Is done. For example, during a period in which the state signal s0 of the counter 151 is at a high level (clock signals No. 3, No. 7, and No. 11), the state signal s3 of the counter 131 of the container 13 is selected to be at a high level (FIG. 5 and FIG. 8).

  When the container 13 holds k pieces of held data q0 to qh, the controller 15 selects (j + 1) -bit selection signals SEL0 to SELj that cyclically select one of them sequentially. Configured to generate. In this case, the counter 151 of FIG. 6 generates k state signals s0 to sh, and the encoder 152 of FIG. 6 generates (j + 1) -bit selection signals SEL0 to SELj for selecting the number of the high level state signal. Configured as follows. Even in this case, the encoder 152 can be configured by appropriately combining a plurality of logic gates.

<Measurement operation of comparative example>
First, the operation of the time digital conversion circuit of the comparative example using a vernier type delay chain will be described. FIG. 9 shows a timing chart of each signal of the time digital conversion circuit of the comparative example. The time digital conversion circuit delay chain of the comparative example is configured such that the plurality of containers 13 and the controller 15 are omitted from the configuration of FIG. 1 and the captured data F0 to Fn of the plurality of delay stages are output.

  In the delay chain 11 of the comparative example, the delay circuit e of the transmission line 111 transmitting the target signal exerts a delay amount τ1 = 38 ps, the delay circuit f of the clock transmission line 112 exerts a delay amount τ2 = 28 ps, and the resolution is τ1. -Τ2 = 10 ps. The delay chain 11 of the comparative example has 100 delay stages, and the input clock cycle is set to the maximum value of 1 ns of time intervals that can be measured by the delay chain 11 (= number of delay stages 100 × resolution 10 ps). Yes.

  In FIG. 9, target signals, sig1 to sig100, indicate the signal levels of the 0th stage, the 1st stage to the 100th stage of the transmission line 111, respectively. Clock signals ck1 to ck100 indicate the signal levels of the 0th stage, the 1st stage to the 100th stage of the clock transmission path 112, respectively. F0 to F100 indicate outputs of the 0th to 100th flip-flops g, respectively. In FIG. 9, the same number is written to the same clock signal passing through each delay stage.

  As shown in the target signals sig1 to sig100 in FIG. 9, the target signal is transmitted with a delay amount τ1 at each delay stage. Further, as indicated by the clock signals ck1 to ck100 in FIG. 9, the clock signal is transmitted with a delay amount τ2 at each delay stage. For this reason, compared with the 0th delay stage, in the 50th delay stage, the time interval between the target signal and the clock signal changes by half the clock cycle. In the 100th delay stage, the time interval between the target signal and the clock signal changes by the clock period.

  The flip-flop g of each delay stage captures the signal level of the corresponding delay stage of the transmission path 111 in synchronization with the rising edge of the clock signal of the corresponding delay stage of the clock transmission path 112, and then captures the captured signal level. Output. For this reason, the outputs of the flip-flops g from the 0th stage to the 100th stage are as shown by F0 to F100 in FIG.

  In such a time digital conversion circuit, for example, the result of the time interval measured with the second clock signal is a combination of the captured data F0 to F100 of each flip-flop g captured with the second clock signal (FIG. 9 is indicated by a round frame j2). However, at the timing t1 when the second clock signal reaches the 100th delay stage, the output of the flip-flop g of each delay stage on the start side is updated by the subsequent (third and fourth) clock signals. (Indicated by round frames j3 and j4 in FIG. 9). For this reason, at the timing t1 when the second clock signal reaches the 100th delay stage, even if the captured data is read simultaneously from the flip-flops g of the plurality of delay stages, it is updated by the subsequent clock signal. Captured data is included and normal measurement results cannot be obtained. For example, the captured data of the delay chains 11 in the first to third columns in FIG. 9 is updated to a low level (L) where it should be a high level (H).

<Measurement Operation of Embodiment>
FIG. 10 is a timing chart of each signal of the time digital conversion circuit according to the embodiment of the present invention. In FIG. 10, qm0 to qm3 (m is any one of 0 to n) indicate data held by the four holding circuits 133 in the m-th container 13. OUTm indicates output data of the m-th container 13. In FIG. 10, the same number is assigned to the same clock signal passing through each delay stage. Data values “D0-0, D0-1,..., Dn-8” are binary data of 1 or 0.

  In the flip-flop g at the 0th stage of the delay chain 11, the values “D0-0, D0-1,..., D0-10 based on the 0th to 10th clock signals as shown in the captured data F0 in FIG. Is captured every clock cycle. Further, in the first-stage flip-flop g of the delay chain 11, as shown in the captured data F1 in FIG. 10, the values “D1-0, D1-1,. -10 "is captured every clock cycle. Further, in the second-stage flip-flop g of the delay chain 11, as shown in the captured data F2 in FIG. 10, the values “D2-0, D2-1,. -10 "is captured every clock cycle. Further, in the n-th flip-flop g of the delay chain 11, the values “Dn-0, Dn−1,..., Dn based on the 0th to 8th clock signals as shown in the captured data Fn in FIG. -8 "is captured every clock cycle.

  Among these, for example, the time interval measured using the 0th clock signal as a reference signal is represented by the values “D0-0, D1-0,..., Dn-0” of the captured data F0 to Fn. The time interval measured using the first clock signal as a reference signal is represented by the values “D0-1, D1-1,..., Dn-1” of the captured data F0 to Fn. Similarly, the time interval measured using the eighth clock signal as the reference signal is represented by the values “D0-8, D1-8,..., Dn-8” of the captured data F0 to Fn.

  In each delay stage, each flip-flop g captures the signal level of the transmission line 111 based on the delayed clock signals ck1 to ckn. Therefore, the captured data F0 to Fn captured by the clock signal with the same number is stored in the nth stage. The captured data Fn is determined with the latest delay.

  As described above, the container 13 at each stage holds four of the captured data F0 to Fn of the flip-flop g at each delay stage from the latest one at that time for a period of four clocks ( (See retained data q00 to qn3 in FIG. 10).

  Here, attention is paid to the timing t10 (FIG. 10) in which the captured data Fn = “Dn-0” captured with the latest delay by the 0th clock signal is held in the container 13. Then, during the clock period from the timing t10, the values “D0-0, D1-0,..., Dn-0” of all the captured data F0 to Fn captured by the 0th clock signal are stored in the plurality of containers 13. It is found that the data is held in the 0th holding circuit 133. Similarly, the measurement results “D0-1, D1-1,..., Dn-1” captured by the first clock signal during the clock period from the next timing t11 after the clock period are stored in the plurality of containers 13. It is held in the first holding circuit 133. Thus, the value of the measurement result based on the next clock signal is cyclically held from the 0th holding circuit 133 to the third holding circuit 133 of the plurality of containers 13 for each clock cycle.

  Then, the controller 15 outputs the next selection signals SEL0 and SEL1 at the timing matched with the n-th container 13 that performs the holding operation of the captured data Fn with the latest delay based on the clock signal of the same number. That is, the selection signals SEL0 and SEL1 are selected so that the held data is selected from the holding circuits 133 of the same number in all the containers 13 for one clock cycle from the timing when the captured data Fn is held in the nth container 13. Is generated. As a result, the data having the same number in all the containers 13 is output simultaneously as output data OUT0 to OUTn. Similarly, the controller 15 cyclically switches the selection from the first held data to the third held data and the 0th held data every clock cycle.

  As a result, as shown in the selection signals SEL0 and SEL1 in FIG. 10, the 0th is synchronized with the third, seventh, and eleventh clock signals (the clock signal before the delay) held by the third holding circuit 133. The output of the holding circuit 133 is controlled to be selected. Then, the selection is switched cyclically in the clock cycle. That is, the controller 15 generates the selection signals SEL0 and SEL1 so that the data held in the holding circuit 133 in the order in which the captured data is held by the next clock signal is selected by the previous clock signal. By such synchronous control, stable output data OUT0 to OUTn can be obtained.

  By such an operation, the time digital conversion circuit 1 sequentially outputs output data OUT0 to OUTn representing the time interval between the clock signal and the target signal in synchronization with the clock signal.

  When the number k of holding circuits 133 provided in the container 13 is other than 4, k times of captured data F0 to Fn are held in each container 13 for k clock cycles. Therefore, the controller 15 may be configured so that the selection is cyclically switched in the order of the holding data q0 to qh (h = k−1) at the timing as described above. As a result, as in the case of k = 4, output data OUT0 to OUTn that normally indicate the time interval between the clock signal and the target signal are sequentially obtained.

  The storage control of the captured data F0 to Fn and the selection control of the output data OUT0 to OUTn of the delay chain 11 realized by the container 13 and the controller 15 correspond to an example of the time digital conversion method according to the present invention.

  As described above, according to the time digital conversion circuit 1 and the time digital conversion method according to the present embodiment, the time interval between the clock signal and the target signal is set to a resolution higher than the delay amounts τ1 and τ2 of the delay circuits e and f. And it can be converted into a digital value normally.

  Furthermore, according to the time digital conversion circuit 1 and the time digital conversion method according to the present embodiment, such an operation can be realized by using one vernier delay chain 11. Therefore, the circuit area can be reduced.

(Other embodiments)
FIG. 11 is a block diagram showing an example of the configuration of the controller of the time digital conversion circuit according to another embodiment of the present invention. The controller 15 in FIG. 1 may be configured by a frequency divider 15A having two flip-flops a1 and two inverters IV2 as shown in FIG. In such a circuit, the selection signals SEL0 and SEL1 can be similarly generated.

  Further, the container 13 of FIG. 2 includes a holding circuit 133 configured by a flip-flop as a configuration for storing captured data, but various types of memories may be applied as a component for storing captured data. . The memory may be configured such that writing and reading can be performed asynchronously.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, a specific feature (technical matter) in one embodiment is appropriately improved and added to another embodiment or the other implementation. Specific features in the form can be substituted, and such form is also included in the gist of the present invention.

  The present invention can be widely used in the field of TOF (Time of Flight), laser radar, and other devices that require an operation for converting a time interval into a digital value.

1 Time digital conversion circuit 11 Vernier delay chain 13 Container (memory processing unit)
15 Controller 131 Counter 132 Selector 133 Holding Circuit (Storage Unit)
134, 135 Multiplexer IV Inverter ck1-ckn Clock signal F0-Fn Captured data q0-q3, q00-qn3 Holding data OUT0-OUTn Output data

Claims (8)

A transmission path in which a plurality of delay circuits are connected in series and a signal to be measured is transmitted; a clock transmission path in which a plurality of clock delay circuits having delay amounts different from the delay circuit are connected; and the transmission A plurality of delay stages of the path and a plurality of delay stages of the clock transmission path, respectively, and based on a clock signal reaching the corresponding delay stage of the clock transmission path, the corresponding delay stage of the transmission path A vernier delay chain having a plurality of capture units for capturing signal levels;
A plurality of storage processing units respectively provided corresponding to the plurality of capturing units;
A controller for controlling the output of the plurality of storage processing units,
Each of the plurality of storage processing units includes a storage unit capable of storing a plurality of capture results of the corresponding capture unit, and a processing unit for sequentially storing the capture results of the corresponding capture unit in the storage unit. Have
The controller outputs output data including a plurality of capture results captured by the plurality of capture units and stored in the plurality of storage processing units when one clock signal is transmitted to the clock transmission path, To output simultaneously from multiple storage processing units,
Time digital conversion circuit. Each of the plurality of storage processing units sequentially stores the capture results in synchronization with the clock signal that has reached the corresponding delay stage of the clock transmission path,
The controller sequentially outputs the output data in synchronization with a clock signal sequentially supplied to the clock transmission path;
The time digital conversion circuit according to claim 1. The storage processing unit
A plurality of holding circuits capable of holding the capture results of the corresponding capture units based on a clock signal;
A distribution unit that sequentially distributes the clock signal that sequentially reaches the corresponding delay stage of the clock transmission path to the plurality of holding circuits;
A multiplexer that outputs one of the plurality of capture results held in the plurality of holding circuits based on the control of the controller;
A time digital conversion circuit according to claim 1 or 2, further comprising: Each of the plurality of storage processing units can store k times of capture results;
The controller outputs the latest stored acquisition result from the storage processing unit corresponding to the last delay stage of the transmission path;
The time digital conversion circuit according to any one of claims 1 to 3. The period p of the clock signal, the number k of the capture results that can be stored in the storage unit, and the time T for the target signal to reach the last delay stage from the beginning of the transmission path are:
satisfying the relationship of p × k ≧ T.
The time digital conversion circuit according to any one of claims 1 to 4. The maximum time interval that can be converted to a digital value is equal to or greater than the period of the clock signal;
The time digital conversion circuit according to any one of claims 1 to 5. A transmission path in which a plurality of delay circuits are connected in series and a signal to be measured is transmitted; a clock transmission path in which a plurality of clock delay circuits having different delay amounts from the delay circuits are connected in series; and A signal level of a corresponding delay stage of the transmission path is provided based on a clock signal provided corresponding to each of a plurality of delay stages and a plurality of delay stages of the clock transmission path and reaching the corresponding delay stage of the clock transmission path. A vernier delay chain having a plurality of capture portions,
A plurality of storage units provided corresponding to the plurality of capture units, respectively, and a time digital conversion method using the storage unit,
In each of the plurality of storage units, a plurality of capture results of the corresponding capture unit are sequentially stored,
A time-to-digital conversion method in which output data including a plurality of capture results captured by the plurality of capture units and stored in the plurality of storage units based on one clock signal is simultaneously output from the plurality of storage units. Each of the plurality of storage units stores the capture result in synchronization with a clock signal that has reached the corresponding delay stage of the clock transmission path,
The output data is sequentially output in synchronization with a clock signal sequentially supplied to the clock transmission path.
The time digital conversion method according to claim 7.

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