JP2002151687A - High breakdown-strength mos field effect transistor - Google Patents
High breakdown-strength mos field effect transistorInfo
- Publication number
- JP2002151687A JP2002151687A JP2000348225A JP2000348225A JP2002151687A JP 2002151687 A JP2002151687 A JP 2002151687A JP 2000348225 A JP2000348225 A JP 2000348225A JP 2000348225 A JP2000348225 A JP 2000348225A JP 2002151687 A JP2002151687 A JP 2002151687A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor region
- region
- type
- type semiconductor
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 159
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 9
- 230000015556 catabolic process Effects 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、誘電体分離構造
を用いたパワーＩＣの高耐圧ＭＯＳ電界効果トランジス
タに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high withstand voltage MOS field effect transistor of a power IC using a dielectric isolation structure.
【０００２】[0002]
【従来の技術】ＳＯＩ基板を用いた、誘電体分離による
パワーＩＣの出力素子として、横形のＭＯＳ電界効果ト
ランジスタ（以下ＭＯＳＦＥＴ）が使用される場合があ
る。このＭＯＳＦＥＴでは、シリコンの破壊電界強度に
よって耐圧が制限されるため、高耐圧化するには、図３
（ａ）に示す構造において、ｎ- 型ドリフト領域１０１
の不純物の低濃度化とｎ- 型ドリフト領域１０１の距離
を長くする必要がある。2. Description of the Related Art In some cases, a lateral MOS field effect transistor (hereinafter referred to as a MOSFET) is used as an output element of a power IC using an SOI substrate by dielectric isolation. In this MOSFET, the breakdown voltage is limited by the breakdown electric field strength of silicon.
In the structure shown in FIG.
It is necessary to reduce the concentration of the impurities and increase the distance between the n − -type drift regions 101.
【０００３】[0003]
【発明が解決しようとする課題】しかし、ＭＯＳＦＥＴ
のオン抵抗は、ｎ- 型ドリフト領域の不純物の低濃度化
とｎ- 型ドリフト領域の距離が長くなる関係で、以下の
式（１）に従って指数関数的に悪化する。However, MOSFETs
Is exponentially degraded according to the following equation (1) due to the relationship between the low concentration of impurities in the n − -type drift region and the increase in the distance between the n − -type drift regions.
【０００４】 Ｒｂ ＝ Ｋ(ＢＶｄｓ)２．６ …（１） なお、Ｒｂはｎ- 型ドリフト領域の不純物濃度と距離で
決まるバルク抵抗、Ｋは定数、ＢＶｄｓはドレイン−ソ
ース間のブレイクダウン電圧である。図３（ａ）中のＥ
ｃは、シリコン（Ｓｉ）の破壊電界強度を示す。Rb = K (BVds) 2.6 (1) where Rb is a bulk resistance determined by the impurity concentration and distance of the n − -type drift region, K is a constant, and BVds is a breakdown voltage between drain and source. is there. E in FIG. 3 (a)
c indicates the breakdown electric field strength of silicon (Si).
【０００５】このため、ＭＯＳＦＥＴの高耐圧化はチッ
プ面積を増大させることになり、結果的に高価格化及び
ドライブエネルギの増大を招いている。For this reason, increasing the withstand voltage of the MOSFET increases the chip area, which results in higher cost and higher drive energy.
【０００６】これを解決する手段として、図３（ｂ）に
示す断面図のように、ｎ型ドリフト領域１１１を囲むよ
うにｐ型ピラー１１２を形成し、このｐ型ピラー１１２
で囲まれたｎ型ドリフト領域１１１のｎ型ドープ濃度を
高めることで、大幅にオン抵抗を低減するという手段が
ある。なお、ｐ型ピラー１１２の外側には、ｎ- 型半導
体領域１１３が形成されている。As a means for solving this, as shown in a sectional view of FIG. 3B, a p-type pillar 112 is formed so as to surround an n-type drift region 111, and the p-type pillar 112 is formed.
There is a method of greatly reducing the on-resistance by increasing the n-type doping concentration of the n-type drift region 111 surrounded by. Note that an n − type semiconductor region 113 is formed outside the p type pillar 112.
【０００７】図３（ｂ）に示す構造のＭＯＳＦＥＴで
は、オフ時には図３（ｃ）に示すように、ｎ- 型半導体
領域１１３の濃度と等価になり高耐圧化でき、オン時に
は図３（ｄ）に示すように、ｎ型ドリフト領域１１１の
濃度で低オン抵抗化できる。In the MOSFET having the structure shown in FIG. 3B, when turned off, as shown in FIG. 3C, the concentration becomes equivalent to the concentration of the n − type semiconductor region 113, and the breakdown voltage can be increased. As shown in (), the on-resistance can be reduced by the concentration of the n-type drift region 111.
【０００８】しかし、シリコン基板の表面から裏面に向
かって電流が流れる現在の縦形ＭＯＳ構造に前記手段を
適用した場合には、薄いｎ型領域あるいはｐ型領域を縦
に重ね合わせてｎ型ピラーあるいはｐ型ピラーを形成す
る必要がある。縦に重ね合わせてｎ型ピラーあるいはｐ
型ピラーを形成するためには、数段階のエピタキシャル
成長工程を繰り返し、その都度、マスク合わせ及びｐ型
の不純物拡散、ｎ型の不純物拡散を必要とする。特に、
ｎ型及びｐ型の不純物濃度は精度良く合わせる必要があ
る。However, when the above means is applied to a current vertical MOS structure in which a current flows from the front surface to the back surface of a silicon substrate, a thin n-type region or a p-type region is vertically overlapped to form an n-type pillar or It is necessary to form p-type pillars. N-type pillar or p
In order to form the mold pillar, several stages of epitaxial growth steps are repeated, and each time, mask alignment, p-type impurity diffusion, and n-type impurity diffusion are required. In particular,
It is necessary to precisely match the n-type and p-type impurity concentrations.
【０００９】したがって、先の段階でエピタキシャル成
長したｐ型及びｎ型のピラーは、後の段階のエピタキシ
ャル成長によって、より長く熱工程を通ることになる。
このため、不純物拡散が進み、ピラーの下から上まで不
純物濃度を一様化するのが難しく、その上ｐ型の不純物
拡散とｎ型の不純物拡散の速度も違うため、デバイスの
構造設計、及び工程管理が大変難しいものとなってい
る。Therefore, the p-type and n-type pillars epitaxially grown in the earlier stage will pass through the thermal process longer due to the epitaxial growth in the later stage.
For this reason, impurity diffusion progresses, and it is difficult to make the impurity concentration uniform from the bottom to the top of the pillar. Further, the speeds of the p-type impurity diffusion and the n-type impurity diffusion are also different. Process management is very difficult.
【００１０】そこでこの発明は、前記課題に鑑みてなさ
れたものであり、チップ面積を増大させることなく高耐
圧化でき、高耐圧化に伴うオン抵抗の急激な増大を抑え
ることができる製造が容易なＭＯＳＦＥＴを提供するこ
とを目的とする。Therefore, the present invention has been made in view of the above-mentioned problems, and it is possible to increase the breakdown voltage without increasing the chip area, and it is easy to manufacture which can suppress a rapid increase in on-resistance due to the increase in breakdown voltage. It is an object to provide a simple MOSFET.
【００１１】[0011]
【課題を解決するための手段】前記目的を達成するため
に、この発明に係るＭＯＳ電界効果トランジスタは、第
１導電型の半導体基体と、前記半導体基体に、互いに離
間して形成された第２導電型の第１半導体領域、第１導
電型の第２半導体領域と、前記第１半導体領域に形成さ
れた第１導電型の第３半導体領域と、前記第１半導体領
域と第２半導体領域との間の前記半導体基体に、前記第
１半導体領域及び第２半導体領域に接するように形成さ
れた第１導電型の第４半導体領域と、前記第１半導体領
域と第２半導体領域との間の前記半導体基体に、前記第
１半導体領域、第２半導体領域、及び前記第４半導体領
域に接するように形成された第２導電型の第５半導体領
域と、前記半導体基体上に形成され、前記第３半導体領
域に電気的に接続された第１電流通路電極と、前記半導
体基体上に形成され、前記第２半導体領域に電気的に接
続された第２電流通路電極と、前記第４、第５の半導体
領域と前記第３半導体領域との間の前記第１半導体領域
上に、絶縁膜を介して形成されたゲート電極とを具備す
ることを特徴とする。To achieve the above object, a MOS field-effect transistor according to the present invention comprises a semiconductor substrate of a first conductivity type and a second semiconductor substrate formed on the semiconductor substrate at a distance from each other. A first semiconductor region of the conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the first conductivity type formed in the first semiconductor region, the first semiconductor region and the second semiconductor region; A fourth semiconductor region of a first conductivity type formed so as to be in contact with the first semiconductor region and the second semiconductor region, between the first semiconductor region and the second semiconductor region; A second conductive type fifth semiconductor region formed in contact with the first semiconductor region, the second semiconductor region, and the fourth semiconductor region on the semiconductor substrate, and a fifth semiconductor region formed on the semiconductor substrate; Electrically connected to three semiconductor regions A first current path electrode, a second current path electrode formed on the semiconductor substrate, and electrically connected to the second semiconductor region, the fourth and fifth semiconductor regions, and the third semiconductor A gate electrode formed on the first semiconductor region between the first semiconductor region and an insulating film via an insulating film.
【００１２】このように構成されたＭＯＳ電界効果トラ
ンジスタでは、第４半導体領域と第５半導体領域の不純
物が同数になるように形成されているため、このトラン
ジスタのオフ時には第４半導体領域と第５半導体領域と
が打ち消し合って、第４半導体領域、第５半導体領域、
及び半導体基体からなる領域は回路の見かけ上ｎ- 型化
する。また、第４半導体領域と第５半導体領域の不純物
が同数で、かつ第４半導体領域の不純物ドープ濃度を高
めることにより、大幅にオン抵抗を低減できる。これに
より、ＭＯＳ電界効果トランジスタのオフ時における耐
圧を高耐圧化できると共に、オン抵抗を低減できる。In the MOS field-effect transistor thus configured, the fourth semiconductor region and the fifth semiconductor region have the same number of impurities. Therefore, when the transistor is off, the fourth semiconductor region and the fifth semiconductor region are not connected. The semiconductor regions cancel each other, and the fourth semiconductor region, the fifth semiconductor region,
And the region consisting of the semiconductor substrate becomes apparently n-type in the circuit. Further, the on-resistance can be significantly reduced by increasing the number of impurities in the fourth semiconductor region and the fifth semiconductor region and increasing the impurity doping concentration in the fourth semiconductor region. As a result, the withstand voltage of the MOS field-effect transistor when it is off can be increased, and the on-resistance can be reduced.
【００１３】[0013]
【発明の実施の形態】以下、図面を参照してこの発明の
実施の形態について説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１４】図１は、この発明の実施の形態のＭＯＳＦ
ＥＴの構造を示す断面図であり、図２は前記ＭＯＳＦＥ
Ｔを上方からみた上面図である。FIG. 1 shows a MOSF according to an embodiment of the present invention.
FIG. 2 is a sectional view showing the structure of the ET, and FIG.
It is the top view which looked at T from the upper part.
【００１５】図１に示すように、ｎ- 型シリコン半導体
基板１１には、絶縁膜（誘電体膜）、例えばシリコン酸
化膜（ＳｉＯ２）１２で分離された素子領域が形成され
ている。この素子領域には、図２に示すように、ｎ型半
導体領域１３とｐ型半導体領域１４とがストライプ状に
交互に形成されている。ストライプ状に配列されたｎ型
半導体領域１３及びｐ型半導体領域１４の外側には、ｎ
- 型半導体領域１５が形成されている。As shown in FIG. 1, an element region separated by an insulating film (dielectric film), for example, a silicon oxide film (SiO 2) 12 is formed on an n − type silicon semiconductor substrate 11. In this element region, as shown in FIG. 2, n-type semiconductor regions 13 and p-type semiconductor regions 14 are alternately formed in a stripe shape. Outside the n-type semiconductor region 13 and the p-type semiconductor region 14 arranged in stripes, n
A type semiconductor region 15 is formed.
【００１６】前記シリコン酸化膜１２と、このシリコン
酸化膜１２上に形成されたｎ型半導体領域１３及びｐ型
半導体領域１４とで、ＳＯＩ基板を構成している。シリ
コン酸化膜１２の膜厚は２μｍ〜４μｍ程度であり、シ
リコン酸化膜１２上のｎ型半導体領域１３及びｐ型半導
体領域１４の膜厚は７μｍ程度である。The silicon oxide film 12, an n-type semiconductor region 13 and a p-type semiconductor region 14 formed on the silicon oxide film 12 constitute an SOI substrate. The thickness of the silicon oxide film 12 is about 2 μm to 4 μm, and the thickness of the n-type semiconductor region 13 and the p-type semiconductor region 14 on the silicon oxide film 12 is about 7 μm.
【００１７】前記ｎ型半導体領域１３及びｐ型半導体領
域１４の長手方向の両端側には、ｎ- 型半導体領域１５
が形成されている。一方のｎ- 型半導体領域１５上に
は、ｐ型半導体領域（ベース領域）１７が形成され、こ
のｐ型半導体領域１７中の上層にはｎ+ 型半導体領域
（ソース領域）１８が形成されている。At both ends of the n-type semiconductor region 13 and the p-type semiconductor region 14 in the longitudinal direction, n-type semiconductor regions 15 are provided.
Are formed. A p-type semiconductor region (base region) 17 is formed on one n − -type semiconductor region 15, and an n + -type semiconductor region (source region) 18 is formed in an upper layer in the p-type semiconductor region 17. I have.
【００１８】前記ｐ型半導体領域（ベース領域）１７上
には、ｎ+ 型半導体領域１８に電気的に接続されたソー
ス電極１９が形成されている。ソース電極１９には、ソ
ース端子Ｓが接続されている。On the p-type semiconductor region (base region) 17, a source electrode 19 electrically connected to the n + -type semiconductor region 18 is formed. The source terminal 19 is connected to the source electrode 19.
【００１９】前記ｎ型半導体領域１３及びｐ型半導体領
域１４とｎ+ 型半導体領域１８との間のｐ型半導体領域
１７上には、ゲート絶縁膜２０を介してゲート電極２１
が形成されている。ゲート電極２１には、ゲート端子Ｇ
が接続されている。A gate electrode 21 is formed on the p-type semiconductor region 17 between the n-type semiconductor region 13 and the p-type semiconductor region 14 and the n + -type semiconductor region 18 via a gate insulating film 20.
Are formed. The gate electrode 21 has a gate terminal G
Is connected.
【００２０】他方のｎ- 型半導体領域１５中の上層に
は、ｎ+ 型半導体領域（ドレイン領域）２２が形成され
ている。さらに、ｎ- 型半導体領域１５上には、ｎ+ 型
半導体領域２２に電気的に接続されたドレイン電極２３
が形成されている。ドレイン電極２３には、ドレイン端
子Ｄが接続されている。ソース電極１９とドレイン電極
２３との間には、パッシベーション膜２４が形成されて
いる。なお、図２はゲート電極２１を省略した状態を示
している。An n + type semiconductor region (drain region) 22 is formed in an upper layer in the other n − type semiconductor region 15. Further, a drain electrode 23 electrically connected to the n + -type semiconductor region 22 is formed on the n − -type semiconductor region 15.
Are formed. The drain terminal 23 is connected to the drain electrode 23. A passivation film 24 is formed between the source electrode 19 and the drain electrode 23. FIG. 2 shows a state where the gate electrode 21 is omitted.
【００２１】ストライプ状に配列される前記ｎ型半導体
領域１３とｐ型半導体領域１４は、活性層表面からｐ型
またはｎ型の不純物を注入し、拡散することにより形成
する。ｎ型半導体領域１３及びｐ型半導体領域１４は、
前述したｐ型半導体領域（ベース領域）１７とｎ+ 型半
導体領域（ドレイン領域）２２に接触するとともに、Ｓ
ＯＩ基板の中間酸化膜（前記シリコン酸化膜１２）に接
触している。さらに、前記ｎ型半導体領域１３とｐ型半
導体領域１４の体積が同一の場合は、前記ｎ型半導体領
域１３とｐ型半導体領域１４の不純物濃度は同一になる
ように形成する。あるいは、前記ｎ型半導体領域１３と
ｐ型半導体領域１４の不純物は同数になるように形成す
る。The n-type semiconductor regions 13 and p-type semiconductor regions 14 arranged in stripes are formed by injecting and diffusing p-type or n-type impurities from the surface of the active layer. The n-type semiconductor region 13 and the p-type semiconductor region 14
While contacting the aforementioned p-type semiconductor region (base region) 17 and n + -type semiconductor region (drain region) 22,
It is in contact with the intermediate oxide film (the silicon oxide film 12) of the OI substrate. Further, when the n-type semiconductor region 13 and the p-type semiconductor region 14 have the same volume, the n-type semiconductor region 13 and the p-type semiconductor region 14 are formed to have the same impurity concentration. Alternatively, the impurities in the n-type semiconductor region 13 and the p-type semiconductor region 14 are formed so as to have the same number.
【００２２】このように構成されたＭＯＳＦＥＴでは、
ｎ型半導体領域１３とｐ型半導体領域１４の不純物濃度
が同一になるように形成されているため、このＭＯＳＦ
ＥＴのオフ時にはｎ型半導体領域１３とｐ型半導体領域
１４とが打ち消し合って、ｎ型半導体領域１３、ｐ型半
導体領域１４、及びｎ- 型半導体領域１５からなる領域
は、回路の見かけ上、ｎ- 型化する。また、ｎ型半導体
領域１３とｐ型半導体領域１４の不純物濃度が同一で、
かつｎ型半導体領域１３のｎ型ドープ濃度を高めること
により、大幅にオン抵抗を低減できる。これにより、Ｍ
ＯＳＦＥＴのオフ時の耐圧を高耐圧化できると共に、オ
ン抵抗を低減できる。In the MOSFET configured as described above,
Since the n-type semiconductor region 13 and the p-type semiconductor region 14 are formed to have the same impurity concentration, this MOSF
When the ET is off, the n-type semiconductor region 13 and the p-type semiconductor region 14 cancel each other out, and the region including the n-type semiconductor region 13, the p-type semiconductor region 14, and the n − -type semiconductor region 15 n-type. Further, the n-type semiconductor region 13 and the p-type semiconductor region 14 have the same impurity concentration,
In addition, the on-resistance can be significantly reduced by increasing the n-type doping concentration of the n-type semiconductor region 13. This gives M
The on-state breakdown voltage of the OSFET can be increased while the on-state resistance can be reduced.
【００２３】ここで仮に、ｎ型半導体領域１３よりｐ型
半導体領域１４の不純物濃度が高い場合は、耐圧が悪く
なる。これは、オフ時にｎ型半導体領域１３とｐ型半導
体領域１４からなるドリフト領域がｐ型領域となり、ｐ
型半導体領域（ベース領域）１７とドリフト領域との間
で耐圧が保てなくなるからである。一方、ｐ型半導体領
域１４よりｎ型半導体領域１３の不純物濃度が高い場合
は、耐圧が高くなるが、オン抵抗も高くなってしまう。Here, if the impurity concentration of the p-type semiconductor region 14 is higher than that of the n-type semiconductor region 13, the breakdown voltage becomes worse. This is because the drift region composed of the n-type semiconductor region 13 and the p-type semiconductor region 14 becomes a p-type region when off,
This is because the breakdown voltage cannot be maintained between the type semiconductor region (base region) 17 and the drift region. On the other hand, when the impurity concentration of the n-type semiconductor region 13 is higher than that of the p-type semiconductor region 14, the withstand voltage increases, but the on-resistance also increases.
【００２４】以上説明したようにこの実施の形態によれ
ば、高耐圧化を行っても指数関数的にオン抵抗が増大せ
ず、耐圧の増加に対してオン抵抗の増大がリニアな横形
ＭＯＳＦＥＴが実現できる。また、薄い活性層のＳＯＩ
基板上に、図１及び図２に示す構造の横形ＭＯＳＦＥＴ
を形成するこの実施の形態では、細いｐ型半導体領域１
４とｎ型半導体領域１３とのストライプは表面からの不
純物拡散で造り込むことが可能であるため、製造が容易
である。As described above, according to this embodiment, even if the withstand voltage is increased, the on-resistance does not increase exponentially, and the increase in the withstand voltage is linear. realizable. Also, the SOI of the thin active layer
A horizontal MOSFET having the structure shown in FIGS. 1 and 2 on a substrate
In this embodiment, a thin p-type semiconductor region 1 is formed.
Since the stripes of 4 and the n-type semiconductor region 13 can be formed by impurity diffusion from the surface, the manufacture is easy.
【００２５】また、この実施の形態の横形ＭＯＳＦＥＴ
は、ＳＯＩ基板上に形成するため、ストライプ状のｐ型
半導体領域１４とｎ型半導体領域１３が接するものはシ
リコン酸化膜１２のみとなり、ｐｎ接合分離よりも簡単
に図１及び図２に示す構造の横形ＭＯＳＦＥＴが形成で
きる。Further, the lateral MOSFET of this embodiment
Is formed on an SOI substrate, only the silicon oxide film 12 is in contact with the striped p-type semiconductor region 14 and the n-type semiconductor region 13, and the structure shown in FIGS. 1 and 2 is easier than the pn junction isolation. Can be formed.
【００２６】[0026]
【発明の効果】以上述べたようにこの発明によれば、チ
ップ面積を増大させることなく高耐圧化でき、高耐圧化
に伴うオン抵抗の急激な増大を抑えることができる製造
が容易なＭＯＳＦＥＴを提供することが可能である。As described above, according to the present invention, it is possible to provide a MOSFET which can be easily manufactured which can increase the withstand voltage without increasing the chip area and can suppress a rapid increase in on-resistance due to the increase in the withstand voltage. It is possible to provide.
【図１】この発明の実施の形態のＭＯＳＦＥＴの構造を
示す断面図である。FIG. 1 is a sectional view showing a structure of a MOSFET according to an embodiment of the present invention.
【図２】この発明の実施の形態のＭＯＳＦＥＴを上方か
らみた上面図である。FIG. 2 is a top view of the MOSFET according to the embodiment of the present invention as viewed from above.
【図３】従来のＭＯＳＦＥＴの断面を示す概略図であ
る。FIG. 3 is a schematic view showing a cross section of a conventional MOSFET.
１１…ｎ- 型シリコン半導体基板 １２…シリコン酸化膜（ＳｉＯ２） １３…ｎ型半導体領域 １４…ｐ型半導体領域 １５…ｎ- 型半導体領域 １６…ｎ- 型半導体領域 １７…ｐ型半導体領域（ベース領域） １８…ｎ+ 型半導体領域（ソース領域） １９…ソース電極 ２０…ゲート絶縁膜 ２１…ゲート電極 ２２…ｎ+ 型半導体領域（ドレイン領域） ２３…ドレイン電極 ２４…パッシベーション膜 11 n-type silicon semiconductor substrate 12 silicon oxide film (SiO2) 13 n-type semiconductor region 14 p-type semiconductor region 15 n-type semiconductor region 16 n-type semiconductor region 17 p-type semiconductor region (base) Region) 18 n + type semiconductor region (source region) 19 source electrode 20 gate insulating film 21 gate electrode 22 n + type semiconductor region (drain region) 23 drain electrode 24 passivation film
Claims (8)
型の第１半導体領域、第１導電型の第２半導体領域と、 前記第１半導体領域に形成された第１導電型の第３半導
体領域と、 前記第１半導体領域と第２半導体領域との間の前記半導
体基体に、前記第１半導体領域及び第２半導体領域に接
するように形成された第１導電型の第４半導体領域と、 前記第１半導体領域と第２半導体領域との間の前記半導
体基体に、前記第１半導体領域、第２半導体領域、及び
前記第４半導体領域に接するように形成された第２導電
型の第５半導体領域と、 前記半導体基体上に形成され、前記第３半導体領域に電
気的に接続された第１電流通路電極と、 前記半導体基体上に形成され、前記第２半導体領域に電
気的に接続された第２電流通路電極と、 前記第４、第５の半導体領域と前記第３半導体領域との
間の前記第１半導体領域上に、絶縁膜を介して形成され
たゲート電極と、 を具備することを特徴とするＭＯＳ電界効果トランジス
タ。A first conductive type semiconductor substrate; a second conductive type first semiconductor region, a first conductive type second semiconductor region formed on the semiconductor substrate so as to be separated from each other; A third semiconductor region of a first conductivity type formed in a semiconductor region; and a semiconductor substrate between the first semiconductor region and the second semiconductor region, in contact with the first semiconductor region and the second semiconductor region. A first semiconductor region, a second semiconductor region, and a fourth semiconductor region formed on the semiconductor substrate between the first semiconductor region and the second semiconductor region; A fifth semiconductor region of the second conductivity type formed so as to be in contact with the first semiconductor device; a first current path electrode formed on the semiconductor substrate and electrically connected to the third semiconductor region; And electrically connected to the second semiconductor region. A second current path electrode connected thereto; and a gate electrode formed on the first semiconductor region between the fourth and fifth semiconductor regions and the third semiconductor region via an insulating film. A MOS field-effect transistor, comprising:
電体膜によって分離された島領域であることを特徴とす
る請求項１に記載のＭＯＳ電界効果トランジスタ。2. The MOS field effect transistor according to claim 1, wherein the semiconductor substrate is an island region separated by a dielectric film formed on the substrate.
域とは、同一の不純物濃度からなることを特徴とする請
求項１または２に記載のＭＯＳ電界効果トランジスタ。3. The MOS field effect transistor according to claim 1, wherein said fourth semiconductor region and said fifth semiconductor region have the same impurity concentration.
域とは、同数の不純物を有していることを特徴とする請
求項１または２に記載のＭＯＳ電界効果トランジスタ。4. The MOS field-effect transistor according to claim 1, wherein the fourth semiconductor region and the fifth semiconductor region have the same number of impurities.
域とは交互にストライプ状に配列されていることを特徴
とする請求項１乃至４のいずれかに記載のＭＯＳ電界効
果トランジスタ。5. The MOS field effect transistor according to claim 1, wherein said fourth semiconductor region and said fifth semiconductor region are alternately arranged in a stripe shape.
領域は、前記誘電体膜に接していることを特徴とする請
求項２に記載のＭＯＳ電界効果トランジスタ。6. The MOS field effect transistor according to claim 2, wherein the fourth semiconductor region and the fifth semiconductor region are in contact with the dielectric film.
り不純物濃度が高く、前記第２、第３半導体領域は前記
第４半導体領域より不純物濃度が高いことを特徴とする
請求項１または２に記載のＭＯＳ電界効果トランジス
タ。7. The semiconductor device according to claim 1, wherein the fourth semiconductor region has a higher impurity concentration than the semiconductor substrate, and the second and third semiconductor regions have a higher impurity concentration than the fourth semiconductor region. A MOS field-effect transistor as described.
半導体領域はドレイン、前記第３半導体領域はソースで
あることを特徴とする請求項１または２に記載のＭＯＳ
電界効果トランジスタ。8. The semiconductor device according to claim 1, wherein the first semiconductor region is a base,
3. The MOS according to claim 1, wherein the semiconductor region is a drain, and the third semiconductor region is a source.
Field effect transistor.
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|---|---|---|---|
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000348225A JP2002151687A (en) | 2000-11-15 | 2000-11-15 | High breakdown-strength mos field effect transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101440389B1 (en) | 2012-10-12 | 2014-09-15 | 미쓰비시덴키 가부시키가이샤 | Lateral high-voltage transistor and method for manufacturing the same |
-
2000
- 2000-11-15 JP JP2000348225A patent/JP2002151687A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101440389B1 (en) | 2012-10-12 | 2014-09-15 | 미쓰비시덴키 가부시키가이샤 | Lateral high-voltage transistor and method for manufacturing the same |
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