TWI434388B - Trenched power semiconductor device and fabrication method thereof - Google Patents

Description

Trench type power semiconductor component and manufacturing method thereof

The present invention relates to a power semiconductor device and a method of fabricating the same, and more particularly to a trench power semiconductor device and a method of fabricating the same.

A planar power semiconductor component (such as a power MOS field-effect transistor (MOSFET)) has a gate disposed on a surface of the substrate, the current path of which flows along a parallel substrate surface, which occupies the area of the substrate and causes adjacent The separation distance of cells cannot be arbitrarily reduced. In contrast, the trench type power semiconductor device has the gates disposed in the trenches, so that the current channels are changed to the vertical direction, thereby shortening the separation distance between the cells and improving the integration.

Figure 1 is a schematic cross-sectional view of a typical trench type MOS field effect transistor. As shown in the figure, the trench type MOS field-effect transistor has an N-type heavily doped substrate 10, an N-type lightly doped epitaxial layer 12, a plurality of gate trenches 14, and a plurality of gate structures. 16. A plurality of P-type well regions 17, a plurality of source doped regions 18 and an interlayer dielectric layer 19. The N-type lightly doped epitaxial layer 12 is disposed on the N-type heavily doped substrate 10, and the gate trench 14 is located in the N-type lightly doped epitaxial layer 12. The gate structure 16 is located within the gate trench 14. The P-type well region 17 is located above the N-type lightly doped epitaxial layer 12 and surrounds the gate trench 14. The gate structure 16 is surrounded by a gate dielectric layer 15 to be separated from the P-type well region 17 and the N-type lightly doped epitaxial layer 12. The source doped region 18 is located in the surface layer of the P-type well region 17 and surrounds the gate trench 14. An interlayer dielectric layer 19 is overlying the gate structure 16. A plurality of source contact windows are formed in the interlayer dielectric layer 19 to expose the source doped regions 18.

Generally, the source voltage of the trench MOS field-effect transistor is applied to the source doping region 18 through a source metal layer (not shown) formed over the interlayer dielectric layer 19, the gate The voltage is applied to the gate structure 16 through a gate metal layer (not shown) formed over the interlayer dielectric layer 19, and the drain voltage is transmitted through a drain metal formed under the N-type heavily doped substrate 10. A layer (not shown) is applied to the N-type heavily doped substrate 10. Therefore, the wafer package needs to be connected to the electrodes on the upper and lower surfaces of the substrate at the same time, which causes a limitation in packaging technology.

Therefore, how to simplify the structure and manufacturing method of the existing trench type power semiconductor device is an important subject in the technical field.

In view of this, the main object of the present invention is to provide a trench power semiconductor device and a method for fabricating the trench power semiconductor device, which can simplify the process and reduce the manufacturing cost.

To achieve the above object, the present invention provides a trench type power semiconductor device. The trench power semiconductor device has a lightly doped substrate of a first conductivity type, at least two trenches, a gate structure, a well region of a second conductivity type, and a first doping region of a first conductivity type At least two heavily doped regions at the bottom of the trench, a contact window and a conductive structure. Wherein the trench is on the lightly doped substrate. Also, at least one of the gate trenches is included in the trenches. The gate structure is located in the aforementioned gate trench. The well area surrounds the gate structure. The surface doped region is located above the well region. A heavily doped region at the bottom of the trench is formed at the bottom of the trenches, and the heavily doped regions at the bottom of the trench are interconnected. The contact window is located on the lightly doped substrate and is maintained at a predetermined distance from the aforementioned trench. The conductive structure is filled into the contact window to electrically connect the heavily doped regions at the bottom of the trench.

In an embodiment of the invention, the trench includes at least one first trench and a second trench, the first trench is for receiving a gate wire, and the second trench is for receiving a terminal. structure.

In an embodiment of the present invention, a heavily doped region at the bottom of the contact window further including a first conductivity type is formed at the bottom of the contact window, and the conductive structure is electrically connected to the bottom of the trench through the heavily doped region at the bottom of the contact window. Doped area.

In an embodiment of the invention, at least two heavily doped epitaxial structures are further included, respectively filling a lower portion of the trench to form a corresponding heavily doped region at the bottom of the trench in the lightly doped substrate.

In an embodiment of the invention, at least two heavily doped epitaxial structures of the second conductivity type are further filled into the lower portion of the trench, and the gate structure is located above the heavily doped epitaxial structure.

In an embodiment of the invention, the opening of the contact window and the trench is located on an upper surface of the lightly doped substrate.

In one embodiment of the invention, the contact window is located on one side of the lightly doped substrate.

In one embodiment of the invention, the heavily doped region at the bottom of the trench is of a first conductivity type to produce a power MOS field effect transistor.

In one embodiment of the invention, the heavily doped region at the bottom of the trench is of a second conductivity type to produce an insulated gate bipolar transistor.

The present invention also provides a method of fabrication in accordance with the aforementioned trench power semiconductor device. The manufacturing method comprises at least the following steps: a method for manufacturing a trench power semiconductor device, comprising at least the steps of: (a) providing a lightly doped substrate of a first conductivity type; (b) forming at least two trenches for light On the doped substrate, the trenches include at least one gate trench; (c) forming a contact window on the lightly doped substrate; (d) forming at least two trench bottom heavily doped regions in the corresponding trench Bottom; (e) applying a thermal diffusion process to interconnect the heavily doped regions at the bottom of the trench; (f) forming a gate structure in the gate trench; (g) forming a second conductivity type well region surrounding a gate structure; (h) forming a first doped region of the first conductivity type above the well region; and (i) filling a conductive structure in the contact window to electrically connect the heavily doped region at the bottom of the trench.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

The main technical feature of the trench power semiconductor device of the present invention is that the heavily doped region required by the conventional fabrication method is replaced by the fabrication of the heavily doped region at the bottom of the trench, and the epitaxial layer on the heavily doped substrate can be omitted. In order to achieve a simplified structure and reduce manufacturing costs.

2A to 2G are views showing a first embodiment of the method of manufacturing the trench type power semiconductor device of the present invention. This embodiment is exemplified by a power metal oxide half field effect transistor. However, the invention is not limited thereto. The invention is also applicable to the fabrication of other power semiconductor components, such as insulated gate bipolar transistors (IGBTs).

As shown in FIG. 2A, firstly, unlike the conventional method for manufacturing a gold oxide half field effect transistor, an N-type epitaxial layer is formed on a N-type heavily doped substrate as a substrate, and this embodiment directly utilizes a N. The lightly doped substrate 110 is used as a substrate to eliminate the fabrication of the N-type epitaxial layer. Subsequently, a pattern layer 115 is formed on the N-type lightly doped substrate 110 to define the position of the trench. In this embodiment, the pattern layer 115 is on the N-type lightly doped substrate 110, and the gate structure, the gate wire, the termination structure and a contact window are sequentially defined from the inside to the outside.

Next, as shown in FIG. 2B, the N-type lightly doped substrate 110 is etched through the pattern layer 115 to form at least one gate trench 122, at least one first trench 124 to accommodate the gate conductor, at least one second The trench 126 is configured to receive the termination structure and the at least one contact window 128 on the N-type lightly doped substrate 110. The contact window 128 can be a complete trench or a stepped structure. Subsequently, as shown in FIG. 2C, a high concentration of N-type doping is implanted into the gate trench 122, the first trench 124, the second trench 126, and the bottom of the contact window 128 through the pattern layer 115 to form a plurality The heavily doped regions 132 at the bottom of the trench are exposed to the bottom of each of the trenches 122, 124, 126 and a heavily doped region 134 at the bottom of the contact window at the bottom of the contact window 128. Then, a thermal diffusion process is applied to interconnect the heavily doped regions 132 at the bottom of each trench with the heavily doped regions 134 at the bottom of the contact window to form a conductive via 130. In this embodiment, the conductive via region 130 is used to pass the drain potential.

Subsequently, as shown in FIG. 2D, a gate structure 150, a gate conductor 160, and a termination structure 170 are formed in the gate trench 122, the first trench 124, and the second trench 126, respectively. In this embodiment, before the step of forming the gate structure 150, the gate wiring 160 and the termination structure 170 in the respective trenches 122, 124, 126, a dielectric layer 140 is formed to cover the inner surfaces of the trenches 122, 124, 126 to isolate the gate structure 150. The gate conductor 160, the termination structure 170 and the conductive via region 130 therebelow. In the present embodiment, the gate structure 150, the gate wiring 160, and the termination structure 170 are formed in the same step, but the present invention is not limited thereto. In a preferred embodiment, the termination structure 170 can also take a different design than the gate structure 150.

Then, as shown in FIG. 2E, a P-type doped N-type lightly doped substrate 110 is implanted by ion implantation to form a P-type well region 152 between adjacent gate structures 150. It is worth noting that the P-type well region 152 needs to maintain a certain distance from the conductive channel region 130 below it to maintain a sufficient breakdown voltage. Next, as shown in FIG. 2F, an N-type surface doped region 154 is formed in the P-type well region 152 to pass through the source potential. Then, an interlayer dielectric layer 180 is formed on the N-type lightly doped substrate 110. The interlayer dielectric layer 180 has a plurality of openings to expose the well region 152, the N-type surface doped region 154, the gate conductor 160, and the contact window 128. Subsequently, a P-type heavily doped region 156 is formed in the well region 152. It should be noted that in the step of fabricating the opening in the interlayer dielectric layer 180, the dielectric layer 140 originally covering the inner surface of the contact window 128 is simultaneously removed to expose the conductive via region 130 at the bottom of the contact window 128.

Then, as shown in FIG. 2G, three independent conductive structures 192, 194 and 196 are formed on the interlayer dielectric layer 180. The conductive structures 192, 194, 196 are electrically connected to the surface doping region through the openings of the interlayer dielectric layer. 154. The gate wire 160 and the conductive channel region 130 are connected to the potentials of the source, the gate and the drain.

It should be noted that the P-type and the N-type described in this embodiment are merely illustrative and are not intended to limit the present invention. The fabrication method of the present invention can also be applied to fabricating a trench type MOS field effect transistor on a P-type lightly doped substrate.

Next, as shown in FIGS. 2B and 2C, in the present embodiment, in the step of etching the trenches 122, 124, 126, the contact window 128 is simultaneously formed at the edge of the lightly doped substrate 110. In the subsequent step of forming the trench bottom heavily doped region 132 by ion implantation, a heavily doped region 134 at the bottom of the contact window is simultaneously formed at the bottom of the contact window 128. The heavily doped region 132 at the bottom of the trench is electrically connected to the conductive structure 196 through the heavily doped region 134 at the bottom of the contact window. However, the invention is not limited thereto. For example, the contact window 128 can be formed on the lightly doped substrate 110 after the gate structure 150 is completed. In addition, by appropriately adjusting the position of the contact window 128, the contact window 128 can also be directly extended into the heavily doped region 132 at the bottom of the trench without additionally forming a heavily doped region 134 at the bottom of the contact window at the bottom of the contact window 128. For example, by partially cutting away the material of the portion of the substrate 110 from the side of the lightly doped substrate 110, a contact window can be formed to expose the heavily doped region at the bottom of the trench.

Compared with the conventional method for manufacturing a trench type MOS field effect transistor, the N-type lightly doped substrate 110 is used to replace the N-type epitaxial layer required by the conventional manufacturing method, and is heavily doped at the bottom of the trench. The region 132 serves as a conductive path between the source and the drain, so that the formation of the N-type epitaxial layer can be omitted, and at the same time, the conductive metal layer is not required to be formed on the back surface of the substrate. Secondly, the conductive via region 130 for introducing the drain potential in the embodiment is immediately adjacent to the bottom of the trenches 122, 124, 126, so that the N-type lightly doped region between the surface doped region 154 and the conductive via region 130 can be shortened. Thickness helps reduce on-resistance. In addition, in this embodiment, the gate conductive structure originally located on the back surface of the substrate is formed on the front surface of the substrate to facilitate the subsequent packaging process.

3A and 3B are views showing a second embodiment of the method of manufacturing the trench type MOS field effect transistor of the present invention. The fabrication steps of Figure 3A are followed by the fabrication steps of Figure 2B. Different from the first embodiment of the present invention, the trench bottom heavily doped region 132 is formed at the bottom of the gate trench 122, the first trench 124 and the second trench 126 by ion implantation, which is the first embodiment. An N-type heavily doped epitaxial structure 231 is partially filled under each of the trenches 122, 124, 126. Subsequently, a thermal diffusion process is applied to diffuse the dopants in the heavily doped epitaxial structure 231 to form a plurality of interconnected trench bottom heavily doped regions 232 in the N-type lightly doped substrate 110. Next, as shown in FIG. 3B, a gate structure 250, a gate conductor 260, and a termination structure 270 are formed directly in the gate trench 122, the first trench 124, and the second trench 126, respectively. The subsequent production steps are similar to the first embodiment of the present invention, and are not described herein.

4A and 4B are views showing a third embodiment of the method of manufacturing the trench type MOS field effect transistor of the present invention. The fabrication step of Figure 4A is followed by the fabrication steps of Figure 2C. After the step of forming the conductive via region 130 in the N-type lightly doped substrate 110 by a thermal diffusion process, an epitaxial structure 336 is partially filled under each of the trenches 122, 124, 126. The epitaxial structure 336 can be P-type doped or N-type lightly doped. Subsequently, as shown in FIG. 4B, a gate structure 350, a gate conductor 360, and a termination structure 370 are formed directly over the epitaxial structure 336. The subsequent production steps are similar to the first embodiment of the present invention, and are not described herein.

5A and 5B are views showing a fourth embodiment of the method of manufacturing the trench type MOS field effect transistor of the present invention. The fabrication step of Figure 5A is followed by the fabrication steps of Figure 2C. After the step of forming the conductive via region 130 in the N-type lightly doped substrate 110 by a thermal diffusion process, a thick oxide layer 440 is formed on the bottom of each of the trenches 122, 124, 126. The thick oxide layer 440 may be selectively grown on the bottom of each of the trenches 122, 124, 126 by wet oxidation, or may be filled with yttrium oxide in each of the trenches 122, 124, 126, and then the thick oxide layer 440 may be formed by etch back. Subsequently, as shown in FIG. 5B, a conductive structure 442 is formed on portions below the trenches 122, 124, 126. The side of the conductive structure 442 is separated from the conductive via region 130 by a dielectric layer 443. Then, a gate structure 450, a gate wire 460 and a termination structure 470 are formed on the gate trench 122, the first trench 124 and the second trench 126, respectively. The potential of the conductive structure 442 previously exposed within the gate trench 122 is offset by the potential of the gate structure 450 above it.

Figure 6 shows a preferred embodiment of the invention for use in the fabrication of an insulated gate bipolar transistor. Compared with the first embodiment of the present invention, the trench bottom doped region 132 formed at the bottom of the trenches 122, 124, 126 is N-type heavily doped, and its conductivity type is the same as that of the lightly doped substrate 110; in this embodiment The heavily doped regions 532 at the bottom of the trenches formed at the bottom of the trenches 122, 124, 126 and the heavily doped regions 534 at the bottom of the contact window formed at the bottom of the contact window 128 are all P-type heavily doped. Thus, a PNPN alternating insulated gate bipolar transistor structure is formed between the conductive via region 530 and the N-type surface doped region 554 formed over the P-type well region 152. In the insulated gate bipolar transistor structure, the N-type surface doped region 554 is electrically connected to an emitter through the conductive structure 592, and the heavily doped region 532 at the bottom of the trench is formed through the contact window. The conductive structure 596 in 128 is electrically connected to a collector.

Secondly, various embodiments of the method for fabricating the trench-type MOS field-effect transistor can adjust the conductivity type of the heavily doped region at the bottom of the trench according to the manner disclosed in FIG. Polar crystal. However, in the embodiment of Figures 4A and 4B, the epitaxial structure 336 filled in the lower portion of the trenches 122, 124, 126 is limited to the heavily doped region 532 at the bottom of the trench and can only be N-doped.

Fig. 7 is a view showing a preferred embodiment of the arrangement position of the drain contact window of the trench type MOS field effect transistor of the present invention. The corners of the lightly doped substrate 110 are shown. In the present embodiment, the element area A1 is located at the center of the lightly doped substrate 110, and the wire area A2 and the terminal area A3 are sequentially located outside the element area A1. The contact window 128 is stepped around the periphery of the lightly doped substrate 110. However, the invention is not limited thereto. The contact window 128 may surround only a portion of the side of the lightly doped substrate or may be formed on the surface of the lightly doped substrate 110.

Next, referring to FIG. 2G, in the foregoing embodiments, the heavily doped region 132 at the bottom of the trench under the gate structure 150 sequentially passes through the bottom of the trench under the gate wire 160 and the termination structure 170. The heavily doped region 132 is electrically connected to the conductive structure 196. However, the invention is not limited thereto. With the change of the arrangement position of the element, the gate line 160, the termination structure 170 and the contact window 128 on the lightly doped substrate, the heavily doped region 132 at the bottom of the trench under the gate structure 150 can also be directly electrically connected to The conductive structure 196 does not pass through the heavily doped region 132 at the bottom of the trench below the gate conductor 160 and the termination structure 170.

In addition, as shown in FIG. 2G, in the foregoing embodiments, the opening of the contact window 128 and the opening of each of the trenches 122, 124, 126 are located on the same side of the lightly doped substrate 110. However, the invention is not limited thereto. The contact window 128 may also be formed on the lower surface of the lightly doped substrate 110 or on the side of the lightly doped substrate 110.

Compared with the conventional trench type MOS field effect transistor, the present invention has the following advantages:

1. The method for manufacturing a trench type power semiconductor device according to the present invention can eliminate the fabrication of an epitaxial layer and contribute to a reduction in manufacturing cost.

2. The trench type power semiconductor device of the present invention can make the respective electrodes of the transistor, that is, the power metal oxide half field effect transistor, that is, the source conductive structure 192, the gate conductive structure 194 and the drain conductive structure 196, They are all located on the upper surface of the substrate, which is beneficial to the subsequent packaging process.

3. The trench power semiconductor device provided by the present invention can shorten the thickness of the lightly doped region between the well region 152 and the conductive via region 130, and help to reduce the on-resistance.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

10. . . Heavy doped substrate

12. . . Lightly doped epitaxial layer

14. . . Gate trench

15. . . Gate dielectric layer

16. . . Gate structure

17. . . Well area

18. . . Source doping region

19. . . Interlayer dielectric layer

110. . . Lightly doped substrate

115. . . Pattern layer

122. . . Gate trench

124. . . First groove

126. . . Second groove

128. . . Contact window

132,232,532. . . Heavily doped region at the bottom of the trench

134,534. . . Heavy doped area at the bottom of the contact window

130,530. . . Conductive channel area

150,250,350,450. . . Gate structure

160,260,360,460. . . Gate wire

170,270,370,470. . . Terminal structure

152. . . Well area

154,554. . . Surface doped region

156. . . Heavily doped region

180. . . Interlayer dielectric layer

192,194,196,592,594,596. . . Conductive structure

231. . . Heavy doped epitaxial structure

336. . . Epitaxial structure

440. . . Thick oxide layer

442. . . Conductive structure

443. . . Dielectric layer

A1. . . Component area

A2. . . Wire area

A3. . . Terminal area

Figure 1 is a schematic cross-sectional view of a typical trench type MOS field effect transistor.

2A to 2G are views showing a first embodiment of a method of manufacturing a trench type MOS field effect transistor of the present invention.

3A and 3B are views showing a second embodiment of the method of manufacturing the trench type MOS field effect transistor of the present invention.

4A and 4B are views showing a third embodiment of the method of manufacturing the trench type MOS field effect transistor of the present invention.

5A and 5B are views showing a fourth embodiment of the method of manufacturing the trench type MOS field effect transistor of the present invention.

Figure 6 shows a preferred embodiment of the invention applied to an insulated gate bipolar transistor (IGBT).

Fig. 7 shows a preferred embodiment of the arrangement position of the drain contact window of the trench type MOS field effect transistor of the present invention.

110. . . Lightly doped substrate

130. . . Conductive channel area

160. . . Gate wire

152. . . Well area

154. . . Surface doped region

156. . . Heavily doped region

180. . . Interlayer dielectric layer

192,194,196. . . Conductive structure

A1. . . Component area

A2. . . Wire area

A3. . . Terminal area

Claims (16)

A trench type power semiconductor device comprising: a lightly doped substrate of a first conductivity type; at least two trenches on the lightly doped substrate, the trenches including at least one gate trench; and a gate a structure, located in the gate trench; a second conductivity type well region surrounding the gate structure; a first conductivity type first doped region located above the well region; at least two heavily doped Lei a crystal structure filled in a bottom of one of the trenches, wherein the dopant in the heavily doped epitaxial structure is outwardly diffused to form a corresponding heavily doped region in the bottom of the trench in the lightly doped substrate, And the heavily doped regions at the bottom of the trenches are interconnected; a contact window is disposed on the lightly doped substrate and maintained at a predetermined distance from the trenches; and a conductive structure is filled in the contact window to electrically The heavily doped regions at the bottom of the trench are connected. The trench power semiconductor device of claim 1, wherein the trenches comprise at least one first trench to accommodate a gate wire. The trench power semiconductor device of claim 1, wherein the trenches comprise at least one second trench to accommodate a termination structure. The trench power semiconductor device of claim 1, further comprising a heavily doped region at the bottom of the contact window formed at the bottom of the contact window. The trench power semiconductor device of claim 1, further comprising at least two epitaxial structures filled in a lower portion of the trenches, the gate structure being located above the epitaxial structure, the epitaxial structure Is the second conductivity type or the first Conductive type lightly doped. The trench power semiconductor device of claim 1, wherein the contact window surrounds at least one side of the lightly doped substrate. The trench power semiconductor device of claim 1, wherein the heavily doped region at the bottom of the trench is of the first conductivity type and is connected to a drain through the conductive structure. The trench power semiconductor device of claim 1, wherein the heavily doped region at the bottom of the trench is the second conductivity type and is connected to a collector through the conductive structure. A method for manufacturing a trench power semiconductor device, comprising the steps of: providing a lightly doped substrate of a first conductivity type; forming at least two trenches on the lightly doped substrate, the trenches including at least one gate Forming a contact window on the lightly doped substrate; forming at least two trench bottom heavily doped regions at corresponding bottoms of the trench; applying a thermal diffusion process to heavily doped the trench bottoms The cells are interconnected; a gate structure is formed in the gate trench; a second conductivity type well region is formed around the gate structure; and a first doped region of the first conductivity type is formed above the well region And filling a conductive structure in the contact window to electrically connect the heavily doped region at the bottom of the trench. The method of manufacturing a trench power semiconductor device according to claim 9, wherein the trenches comprise at least one first trench to accommodate a gate wire, and the gate structure and the gate wire Was formed simultaneously in the gate trench With the first groove. The method of manufacturing a trench power semiconductor device according to claim 9, wherein the trenches comprise at least one second trench to accommodate a termination structure, and the gate structure is simultaneously with the terminal structure Formed in the gate trench and the second trench. The method for manufacturing a trench type power semiconductor device according to claim 9, wherein the step of forming the heavily doped region at the bottom of the trench in the step corresponding to the bottom of the trench simultaneously forms a bottom doping of the contact window The miscellaneous area is at the bottom of the contact window. The method for manufacturing a trench power semiconductor device according to claim 9, wherein the heavily doped regions at the bottom of the trench are formed by ion implantation at the bottom of the corresponding trench. The method for manufacturing a trench type power semiconductor device according to claim 9, wherein the step of forming the heavily doped region at the bottom of the trench at the bottom of the corresponding trench comprises: forming at least two heavily doped Lei a crystal structure at one of the bottoms of the trenches; and applying a thermal diffusion process to diffuse dopants in the heavily doped epitaxial structure to form corresponding heavily doped regions in the light doping Inside the substrate. The method for fabricating a trench power semiconductor device according to claim 9 further includes forming at least two epitaxial structures under one of the trenches before the step of forming the gate structure in the gate trench In part, the epitaxial structure is lightly doped with the second conductivity type or the first conductivity type. The method of manufacturing a trench power semiconductor device according to claim 9, wherein the contact window and the trench are formed simultaneously on the lightly doped substrate.