JP2002150766A - Method for driving ferroelectric nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for driving a ferroelectric nonvolatile semiconductor memory where the influence of deterioration of a data holding state caused by disturbance is relatively reduced. SOLUTION: A ferroelectric nonvolatile semiconductor memory comprises a bit line BL, a transistor for selection, M-pieces of memory cells MC1M, and M-pieces of plate lines PLm; each memory cell being composed of a 1st electrode, a ferroelectric layer, and a 2nd electrode; in each memory unit, the 1st electrode CN of the memory cell being common to each memory unit, and connected with the bit line BL via the transistor TR for selection; and the 2nd electrode being connected with the common plate line PLm. After a data has been written in a selected memory cell MC1, a higher potential is applied to the plate lines PL2, PL3,..., PL8 connected with the unselected memory cells MC2, MC3,..., MC8, respectively, and thereby the potential of the 1st electrode CN in a common floating state is increased on the basis of the capacitive coupling between the common 1st electrode CN and the plate lines PL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for driving a ferroelectric nonvolatile semiconductor memory (a so-called FERAM).
In particular, the present invention relates to a method for driving a ferroelectric nonvolatile semiconductor memory in which the data holding state is unlikely to be degraded due to disturbance.

[0002]

2. Description of the Related Art In recent years, researches on large-capacity ferroelectric nonvolatile semiconductor memories have been actively conducted. A ferroelectric nonvolatile semiconductor memory (hereinafter sometimes abbreviated as a nonvolatile memory) is capable of high-speed access, and
It is non-volatile, small in size and low in power consumption, and also resistant to shocks. For example, various electronic devices having file storage and resume functions, such as portable computers, mobile phones, and game machines It is expected to be used as a storage device or as a recording medium for recording audio and video.

This nonvolatile memory utilizes a high-speed polarization inversion of a ferroelectric thin film and its residual polarization to detect a change in the amount of stored charge in a memory cell (capacitor portion) having a ferroelectric layer. This is a rewritable non-volatile memory, and basically includes a memory cell and a selection transistor (switching transistor). The memory cell includes, for example, a lower electrode, an upper electrode, and a ferroelectric layer interposed between these electrodes. Writing and reading of data in this nonvolatile memory are performed by applying a ferroelectric PE hysteresis loop shown in FIG. That is, when an external electric field is applied to the ferroelectric layer and then the external electric field is removed, the ferroelectric layer exhibits spontaneous polarization. And the remanent polarization of the ferroelectric layer is
The -P _r when when positive direction of the external electric field is applied + P _r, the negative direction of the external electric field is applied. Here, the case where the remanent polarization is + P _r (see “D” in FIG. 21) is “0”, and the case where the remanent polarization is −P _r (see “A” in FIG. 21) is “1”. And

In order to determine the state of “1” or “0”, for example, an external electric field in the positive direction is applied to the ferroelectric layer. As a result, the polarization of the ferroelectric layer is in the state of “C” in FIG. At this time, if the data is “0”, the polarization state of the ferroelectric layer changes from “D” to “C”. On the other hand, if the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” via “B”. When the data is “0”, no polarization inversion of the ferroelectric layer occurs. On the other hand, when the data is “1”, polarization inversion occurs in the ferroelectric layer. As a result, a difference occurs in the amount of charge stored in the memory cell. By turning on the selection transistor of the selected nonvolatile memory, this accumulated charge is detected as a signal current. If the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric layer becomes the state of “D” in FIG. 21 regardless of whether the data is “0” or “1”. That is, at the time of reading, the data “1” is temporarily destroyed. Therefore, when the data is “1”, an external electric field in the negative direction is applied,
The state of “A” is set via the paths “D” and “E”, and data “1” is written again.

[0005] The structure and operation of a non-volatile memory that is currently mainstream are described in US Pat. Shefilled et al.
This nonvolatile memory has a circuit diagram as shown in FIG.
It is composed of two non-volatile memory cells. In FIG. 22, one nonvolatile memory is surrounded by a dotted line.
Each nonvolatile memory cell includes, for example, selection transistors TR ₁₁ and TR ₁₂ and capacitor units FC ₁₁ and FC ₁₂ .

A two- or three-digit suffix, for example, a suffix “11”, is a suffix that should be displayed as a suffix “1,1”. For example, “111” is a suffix “11,1”. Is to be displayed, but for simplicity of display, it is displayed with a two-digit or three-digit subscript. The subscript “M” is used, for example, when displaying a plurality of memory cells and plate lines collectively, and the subscript “m” is used, for example, when displaying a plurality of memory cells and plate lines individually. , The suffix “N” is used, for example, when the selection transistor and the sub memory unit are collectively displayed, and the suffix “n” is used.
For example, it is used when individually displaying a selection transistor and a sub memory unit.

Then, one bit is stored by writing complementary data into each nonvolatile memory cell. In FIG. 22, reference numeral "WL" indicates a word line, reference numeral "BL" indicates a bit line, and reference numeral "PL" indicates a plate line. Focusing on one nonvolatile memory, the word line W ₁ is a word line decoder / driver WD
It is connected to the. The bit lines BL ₁ and BL ₂ are connected to a differential sense amplifier SA. Furthermore, the plate line PL ₁ is connected to a plate line decoder / driver PD.

When reading stored data in a nonvolatile memory having such a structure, the word line W
When L ₁ is selected and the plate line PL ₁ is driven,
Complementary data is stored in a pair of capacitor units FC ₁₁ , F
A voltage (bit line potential) is applied to the paired bit lines BL ₁ and BL ₂ from C ₁₂ via the selection transistors TR ₁₁ and TR _12.
Appear as. The paired bit lines BL ₁ and BL ₂
(Bit line potential) is detected by the differential sense amplifier SA.

One nonvolatile memory has a word line W
L ₁ and a region surrounded by a pair of bit lines BL ₁ and BL ₂ . Therefore, if the word lines and the bit lines are arranged at the shortest pitch, the minimum area of one nonvolatile memory is 8F ² when the minimum processing dimension is F. Therefore, the minimum area of the nonvolatile memory having such a structure is 8F ² .

When an attempt is made to increase the capacity of a non-volatile memory having such a structure, the only way to realize it is to rely on miniaturization of processing dimensions. Further, two selection transistors and two capacitor units are required to constitute one nonvolatile memory. Further, it is necessary to arrange the plate lines at the same pitch as the word lines. Therefore, it is almost impossible to arrange nonvolatile memories at the minimum pitch,
In reality, the area occupied by one nonvolatile memory is 8F
It will increase significantly than ² .

Furthermore, it is necessary to arrange the word line decoder / driver WD and the plate line decoder / driver PD at the same pitch as that of the nonvolatile memory. In other words, two decoders / drivers are needed to select one row address. Therefore, the layout of the peripheral circuit becomes difficult, and the area occupied by the peripheral circuit becomes large.

One of the means for reducing the area of the nonvolatile memory is
One is known from Japanese Patent Application Laid-Open No. 9-121032.
As shown the equivalent circuit in FIG. 23, the nonvolatile memory disclosed in this patent publication, one memory cell MC in each one end connected to the selection transistor plurality of memory cells in parallel with the one end of the TR _{1 1M} (e.g., M = 4) consists, also non-volatile memory that has become such a non-volatile memory and pair one end of each of the plurality of memory cells are connected in parallel to one end of the selection transistor TR ₂ It is composed of memory cells _MC2M . The other ends of the selection transistors TR ₁ and TR ₂ are respectively connected to bit lines B
L ₁ and BL ₂ . Paired bit line BL
₁ and BL ₂ are connected to a differential sense amplifier SA.
Further, the memory cells MC _1m and MC _2m (m = 1, 2,...)
The other end of M) is connected to the plate line PL _m, the plate line PL _m is connected to a plate line decoder / driver PD. Further, the word line WL is connected to a word line decoder / driver WD.

The paired memory cells MC _1m , M ₁
Complementary data is stored in C _2m (m = 1, 2,... M). For example, the memory cells MC _1m and MC _2m (where m
When reading data stored in (1, 2, 3, 4), the word line WL is selected, and a voltage of (1/2) V _cc is applied to the non-selected plate line PL _k (k ≠ m). while applying a drives the plate line PL _m. Where V
_cc is, for example, a power supply voltage. As a result, complementary data appears as a voltage (potential) from the paired memory cells MC _1m and MC _2m to the paired bit lines BL ₁ and BL ₂ via the selection transistors TR ₁ and TR _2. . Then, the voltages (potentials) of the paired bit lines BL ₁ and BL ₂ are detected by the differential sense amplifier SA.

A pair of nonvolatile memories in a pair
Selection transistor TR₁And TR_TwoAre the word lines WL,
And the paired bit lines BL₁, BL_TwoSurrounded by
Occupies an area. Therefore, if the word lines and bit
If the conductors are arranged at the shortest pitch,
A pair of selection transistors TR in a volatile memory ₁
And TR_TwoArea is 8F^TwoIt is. However,
A pair of selection transistors TR₁, TR_TwoWith M pairs
Memory cell MC_1m, MC_2m(M = 1, 2 ...
M), the selection transformer per bit
Jista TR₁, TR_TwoFewer words and words
Since the arrangement of the lines WL is loose, the size of the nonvolatile memory can be reduced.
It is easy to plan. In addition, one word
Line decoder / driver WD and M plate line decoders
The M bit can be selected by the DA / driver PD.
Therefore, by adopting such a configuration, the cell area is reduced.
8F^TwoLayout that is close to that of a DRAM.
Chip size can be realized.

A method for writing data to a nonvolatile memory disclosed in Japanese Patent Application Laid-Open No. 9-121032 will be described below. Incidentally, as an example, a pair of memory cells M
It is assumed that data is written to C ₁₁ and MC ₂₁ , data “1” is written to memory cell MC ₁₁ , and data “0” is written to memory cell MC ₂₁ . FIG. 24 shows operation waveforms. In FIG. 24, the numbers in parentheses correspond to the numbers of the steps described below.

(1) In the standby state, the word lines and all the plate lines are at 0 volt. Also, the bit lines BL ₁ ,
BL ₂ are equalized to 0 volts. It is assumed that data to be written is held in the differential sense amplifier SA. (2) At the start of data writing, a high voltage _{V BL-H (= V cc} ) is applied to the bit line BL _1, and applies a low potential V _BL-L (= 0 volt) to the bit line BL _2. Here, V _cc is a power supply voltage. (3) Next, by setting the word line WL to a high level, the selection transistors TR ₁ and TR ₂ are turned on. In addition, a high potential V to a selected plate line PL _{1
P LH} (= V _cc ) is applied, and unselected plate lines PL _k (k
= 2,3,4) has an intermediate potential V _PL-M [= (1/2)
_Vcc ]. Thus, in the memory cell MC _21, the potential of the selected plate line PL ₁ is a high potential V _PL-H
, And the the potential of the bit line BL ₂ is a low potential V _BL-L Thus, data "0" is written. (4) Then, the selected plate line PL ₁ low potential V
_PL-L (= 0 volt). Thus, in the memory cell MC ₁₁ is the potential of the selected plate line PL ₁ is low potential V _PL-L, the potential of the bit lines BL ₁ a high potential V _BL-H
Therefore, data "1" is written. (5) To finish reading data,
By setting the word line WL to low level to turn off the selection transistors TR ₁ and TR ₂ , the bit line BL ₁ is discharged to 0 volt, and the non-selected plate line PL _k
(K = 2, 3, 4) to 0 volts.

In the above-described write operation, (1/2) V _cc is applied to the non-selected plate lines PL _k (k = 2, 3, 4).
Is applied. Therefore, the unselected memory cells MC _1k , MC _1k
In _2k (k = 2,3,4), the voltage of ± (1/2) V _cc is applied. Therefore, the unselected memory cells MC _1k , MC _1k
Depending on the data stored in _2k (k = 2, 3, 4), an electric field is applied to the ferroelectric layers constituting the memory cells of the unselected memory cells MC _1k and MC _2k in the direction in which the polarization is inverted. In addition, the data holding state may be degraded due to the disturbance. Here, the disturb means that an electric field is applied to a ferroelectric layer constituting a memory cell of an unselected memory cell in a direction in which polarization is inverted, that is, in a direction in which stored data is deteriorated or destroyed. Refers to the added phenomenon.

In the above example, the voltage V _PL-H applied to the selected plate line for writing data is used.
(For convenience, write voltage) is V _cc , and voltage V _PL-M (for convenience, disturb voltage) applied to unselected plate lines is (１ ／) V _cc , but (write voltage) As the ratio of / (disturb voltage) is higher, the influence of the deterioration of the data holding state due to the disturb can be relatively reduced, and a highly reliable data holding state can be obtained.

For that purpose, the above-mentioned Japanese Patent Application Laid-Open No.
In the nonvolatile memory disclosed in Japanese Patent Publication No.
A method of driving a nonvolatile memory using two intermediate potentials of (/ 3) _Vcc and (2/3) _Vcc is also disclosed. In this driving method, three types of voltages are applied to the bit lines: 0 volt, (（) V _cc , and V _cc . Further, the write voltage applied to the selected plate line PL ₁ V
_cc, and the disturb voltage applied to the non-selected plate lines PL _k (k = 2, 3, 4) is (2/3) V _cc .

[0020]

According to such a driving method, an excellent method capable of relatively reducing the influence of the deterioration of the data holding state due to the disturbance and obtaining a highly reliable data holding state. It is. However, the driving of the differential sense amplifier SA is [0, (1/3) V
_cc , _Vcc ]. For example,
At the time of a write operation, it is necessary to drive bit lines complementarily. Therefore, in the latch circuit including two CMOS inverters constituting the differential sense amplifier SA, NM
It is necessary to set the potential of the source region of the OS transistor, which should be 0 volt, to (１ ／) _Vcc . Such a potential setting is completely different from the potential setting at the time of the read operation, and deviates from the optimum operating voltage of the NMOS transistor constituting the differential sense amplifier SA. In the worst case, the NMOS transistor operates. Disappears.

Accordingly, it is an object of the present invention to provide a ferroelectric nonvolatile semiconductor which can relatively reduce the influence of deterioration of a data holding state due to disturbance and can obtain a highly reliable data holding state. An object of the present invention is to provide a method for driving a memory.

[0022]

To achieve the above object, a method of driving a ferroelectric nonvolatile semiconductor memory according to the present invention comprises (A) a bit line, (B) a selection transistor, and (C) A sub-memory unit composed of M (where M ≧ 2) memory cells, and a memory unit composed of (D) M plate lines, each memory cell having a first electrode and a ferroelectric A first electrode of a memory cell comprising a body layer and a second electrode is common to the sub memory unit, and the common first electrode is connected to a bit through a selection transistor. In the ferroelectric nonvolatile semiconductor memory connected to the plate line, the second electrode is connected to the plate line when writing one of the binary data to one selected memory cell. A method of driving a ferroelectric nonvolatile semiconductor memory in which data is not written in the remaining non-selected memory cells constituting the memory cell, wherein (a) the selection transistor is turned off and connected to the selected memory cell A high potential V _PL-H is applied to the plate line, and the first intermediate potential V _PL-H is
_{Apply PL-M1} and apply a low potential V _BL-L or high potential V to the bit line, depending on the data to be written to the selected memory cell.
Applying _BL-H ; and (b) turning on the select transistor, connecting the common first electrode and the bit line via the select transistor, and then connecting the plate line connected to the selected memory cell. Applying a low potential V _PL-L to the selected memory cell, thereby writing data to the selected memory cell; (c) turning off the selecting transistor and bringing the common first electrode into a floating state; d) A second intermediate potential V _PL-M2 (> V _PL-M1 ) is applied to the plate line connected to the non-selected memory cell, and floating occurs based on the capacitive coupling between the common first electrode and the plate line. Increasing the potential of the first electrode in a common state.

When the low potential V _BL-L is applied to the bit line in the step (a), the selecting transistor is turned on in the step (b) to connect the common first electrode and the bit line. When the connection is made via the selection transistor, data “0” is applied to the selected memory cell because the high potential V _PL-H is applied to the plate line connected to the selected memory cell.
Is written. Thereafter, in the step (b), even if the low potential V _PL-L is applied to the plate line connected to the selected memory cell, the data “0” written in the selected memory cell does not change.

On the other hand, when the high potential V _BL-H is applied to the bit line in the step (a), the selecting transistor is turned on in the step (b), and the common first electrode and the bit line are connected. When connected via a selection transistor,
High potential V _PL-H is applied to the plate line connected to the selected memory cell.
Is not applied to the selected memory cell. Thereafter, in the step (b), data “1” is written to the selected memory cell by applying the low potential V _PL-L to the plate line connected to the selected memory cell.

In the method for driving a ferroelectric nonvolatile semiconductor memory according to the present invention (hereinafter sometimes abbreviated as the present invention), in step (d), the potential of the common first electrode in a floating state is increased. Therefore, in the selected memory cell in which the data “1” is written, the potential difference (write voltage) between the first electrode and the second electrode increases. Therefore, the potential difference (disturb voltage) between the first electrode and the second electrode of the non-selected memory cell in the step (b),
The potential difference (disturb voltage) between the first electrode and the second electrode of the unselected memory cell in the step (d) does not change to the left. Therefore, the ratio of (write voltage) / (disturb voltage) can be increased, and as a result, the influence of the degradation of the data retention state due to the disturbance can be relatively reduced, and a highly reliable data retention state can be obtained. Becomes possible.

In the present invention, the first intermediate potential V _PL-M1
The value substantially equal to the value of _{[V PL-L + (V} PL-H -V PL- L) / 2], the value of the second intermediate potential V _PL-M2 is the value of V _PL-H The configurations can be substantially equal. In this case, when the power supply voltage is _Vcc , the values of _VPL-H and _VBL-H are substantially equal to _Vcc, and the values of _VPL-L and _VBL-L are 0 volt. Is preferred.

Alternatively, in the present invention, the value of the first intermediate potential V _PL-M1 is [V _PL-L + (V _PL-H −V _PL-L )
/ 3], and the value of the second intermediate potential V _PL-M2 is substantially equal to the value of [V _PL-L +2 (V _PL-H −V _PL-L ) / 3]. be able to. In this case, the power supply voltage is V
_cc , the value of V _PL-H is approximately equal to V _cc , the value of V _BL-H is approximately equal to (（) V _cc, and the values of V _PL-L and V _BL-L are 0 volts. Is preferable.

Here, the concept of “substantially equal” includes variations in potential that may occur due to variations in the manufacturing process of the ferroelectric nonvolatile semiconductor memory.

As a configuration of the ferroelectric nonvolatile semiconductor memory of the present invention, (A-1) a first bit line;
(B-1) N (where N ≧ 1) first selection transistors and (C-1) M each (where M ≧ 2)
(D-1) M first memory cells that are common to the N first sub memory units and the (D-1) N sub memory units that constitute the N sub memory units, respectively. A first memory unit comprising: a plate line of
And (A-2) a second bit line, (B-2) N second selection transistors, and (C-2) each including M second memory cells. (D-2) M memory cells which are common to the second memory cells constituting each of the (D-2) N sub memory units, and which constitute the first memory unit A second plate line consisting of a common plate line and M plate lines
, And each memory cell has the first memory unit.
, A ferroelectric layer, and a second electrode. In the first memory unit, the n-th (where n = 1, 2,...)
..N), the first electrode of the first memory cell constituting the first sub-memory unit is common to the n-th first sub-memory unit, and the common first electrode is The first through the n-th first selection transistor
, And the second electrode is connected to a common plate line. In the second memory unit, the first of the second memory cells constituting the n-th second sub-memory unit is connected. Are common in the n-th second sub-memory unit, and the common first electrode is
A configuration in which the second electrode is connected to a second bit line via an n-th second selection transistor, and the second electrode is connected to a common plate line can be given.

In the ferroelectric nonvolatile semiconductor memory having such a configuration, when reading data stored in the first memory cell, the first selection transistor is turned on and the second selection transistor is turned on. Turning off the transistor, applying a reference potential to the second bit line,
When reading data stored in a memory cell, the second selection transistor is turned on, the first selection transistor is turned off, and a reference potential is applied to the first bit line. It can be.
Note that such a driving method of the ferroelectric nonvolatile semiconductor memory is referred to as a driving method according to the first configuration for convenience. With the driving method according to the first configuration, the first memory cell and the n-th second memory cell that constitute the n-th first sub-memory unit sharing a plate line (ie, a pair) One bit can be stored in each of the second memory cells included in the sub memory unit, whereby high integration of the ferroelectric nonvolatile semiconductor memory can be achieved.

Alternatively, the m-th (where m = 1, 2,...) Constituting the n-th first sub-memory unit
M) A pair of complementary data is stored in the first memory cell and the m-th second memory cell forming the n-th second sub-memory unit. Can be. Note that such a driving method of the ferroelectric nonvolatile semiconductor memory is referred to as a driving method according to the second configuration for convenience. By the driving method according to the second configuration,
A first memory cell forming the n-th first sub-memory unit and a second memory cell forming the n-th second sub-memory unit sharing a plate line (ie, a pair) , One bit of a complementary data structure can be stored.

Further, as a structure of the ferroelectric nonvolatile semiconductor memory having such a configuration, the first structure of the ferroelectric nonvolatile semiconductor memory in order to achieve higher integration.
Memory unit and a first memory unit constituting a ferroelectric nonvolatile semiconductor memory adjacent to the ferroelectric nonvolatile semiconductor memory in a direction in which the first bit line extends, via an interlayer insulating layer A second memory unit which is stacked to form a ferroelectric nonvolatile semiconductor memory; and a ferroelectric nonvolatile semiconductor memory adjacent to the ferroelectric nonvolatile semiconductor memory in a direction in which the second bit line extends. A structure in which the constituent second memory unit is stacked with an interlayer insulating layer interposed therebetween can be given.

Alternatively, as the structure of the ferroelectric nonvolatile semiconductor memory having such a structure, each of the first sub-memory units constituting the first memory unit is provided with an interlayer insulating film in order to achieve higher integration. A structure in which each of the second sub-memory units forming the second memory unit is stacked with a layer interposed therebetween with an interlayer insulating layer interposed therebetween. Alternatively, a structure in which each of the first sub-memory unit forming the first memory unit and the second sub-memory unit forming the second memory unit is stacked via an interlayer insulating layer may be mentioned. Can be.

It is sufficient that M ≧ 2 is satisfied.
Can be given by an exponent of 2, for example. In particular, when M = 8 or M = 16, the common floating state is established based on the capacitive coupling between the common first electrode and the plate line. This is preferable from the viewpoint that the potential of the first electrode is surely increased to a desired value. Further, it suffices to satisfy N ≧ 1. As a practical value of N, a power of 1 or 2 (1,
2, 4, 8, 16,...).

As a material constituting the ferroelectric layer in the present invention, a bismuth layered compound, more specifically, a Bi-based layered structure perovskite type ferroelectric material can be exemplified. The Bi-based layered structure perovskite type ferroelectric material belongs to a so-called nonstoichiometric compound, and has tolerance to a composition deviation at both sites of a metal element and an anion (O or the like) element. Also, it is not uncommon for the composition to exhibit optimal electrical characteristics at a position slightly deviating from the stoichiometric composition. The Bi-based layered structure perovskite ferroelectric material can be represented by, for example, the general formula (Bi ₂ O ₂ ) ²⁺ (A _m-1 B _m O _{3m + 1} ) ^2- . Here, “A” is Bi, Pb, Ba, Sr,
Represents one type of metal selected from the group consisting of metals such as Ca, Na, K, and Cd, and “B” represents Ti, Nb,
One type selected from the group consisting of Ta, W, Mo, Fe, Co, and Cr, or a combination of a plurality of types at an arbitrary ratio. M is an integer of 1 or more.

[0036] Alternatively, the material for constituting the ferroelectric _{layer, (Bi X, Sr 1-} X) 2 (Sr Y, Bi 1-Y) (Ta Z, Nb 1-Z) 2 O d (1 (However, 0.9 ≦ X ≦ 1.0, 0.7 ≦ Y ≦ 1.0, 0
≦ Z ≦ 1.0, 8.7 ≦ d ≦ 9.3) It is preferable to include a crystal phase represented as a main crystal phase. Alternatively, the material for constituting the ferroelectric _{layer, Bi X Sr Y Ta 2 O} d (2) (wherein, X + Y = 3,0.7 ≦ Y ≦ 1.3,8.7 ≦ d
≤ 9.3) as a main crystal phase. In these cases, the crystal phase represented by the formula (1) or (2) is used as a main crystal phase.
% Is more preferable. Note that equation (1)
Among the meanings of _{(Bi X, Sr 1-X} ) is the site occupied by the original in the crystal structure and Bi Sr occupies the proportion of Bi and Sr at this time X: means that it is (1-X) . Further, the meaning of (Sr _Y , Bi _1-Y ) means that Bi occupies a site originally occupied by Sr in the crystal structure, and the ratio of Sr and Bi at this time is Y: (1-Y). . Materials constituting the ferroelectric layer containing the crystal phase represented by the formula (1) or (2) as a main crystal phase include oxides of Bi, oxides of Ta and Nb, and oxides of Bi, Ta and Nb. In some cases, the composite oxide may be slightly contained.

Alternatively, the material constituting the ferroelectric layer is represented by the following formula: Bi _x (Sr, Ca, Ba) _Y (Ta _Z , Nb _{1 -Z} ) ₂ O _d Formula (3) (where 1.7 ≦ X ≦ 2.5, 0.6 ≦ Y ≦ 1.2, 0
≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0). "(Sr, Ca, Ba)"
Means one element selected from the group consisting of Sr, Ca and Ba. If the composition of the material constituting the ferroelectric layer represented by each of these formulas is represented by a stoichiometric composition, for example, Bi ₂ SrTa ₂ O ₉ , Bi ₂ SrNb ₂ O ₉ ,
Bi ₂ BaTa ₂ O ₉ and Bi ₂ SrTaNbO ₉ can be exemplified. Alternatively, as a material constituting the ferroelectric layer, Bi ₄ SrTi ₄ O ₁₅ , Bi ₄ Ti ₃ O ₁₂ , Bi ₂
PbTa ₂ O _{9 and the} like can be exemplified, but also in these cases, the ratio of each metal element can be changed to such an extent that the crystal structure does not change. That is, there may be a composition deviation at both sites of the metal element and the oxygen element.

Alternatively, as a material constituting the ferroelectric layer, PbTiO ₃ , P having a perovskite structure may be used.
Lead zirconate titanate [PZT, Pb (Zr _1-y , Ti _y ) O ₃ (provided that it is a solid solution of bZrO ₃ and PbTiO ₃
0 <y <1)], and PZT-based compounds such as PLZT, which is a metal oxide obtained by adding La to PZT, and PNZT, which is a metal oxide obtained by adding Nb to PZT.

In order to obtain a ferroelectric layer, the ferroelectric thin film may be patterned in a step after the formation of the ferroelectric thin film. In some cases, patterning of the ferroelectric thin film is unnecessary. The ferroelectric thin film can be formed by, for example, a method suitable for a material constituting the ferroelectric thin film, such as a MOCVD method, a pulse laser ablation method, a sputtering method, or a sol-gel method. Also,
The patterning of the ferroelectric thin film can be performed by, for example, an anisotropic ion etching (RIE) method.

First and Second Electrodes in the Present Invention
As a material constituting, for example, Ir, IrO_2-X, I
r / IrO_2-X, SrIrO_Three, Ru, RuO_2-X, Sr
RuO _Three, Pt, Pt / IrO_2-X, Pt / RuO_2-X,
Pd, Pt / Ti laminated structure, Pt / Ta laminated structure,
Laminated structure of Pt / Ti / Ta, La_0.5Sr_0.5CoO_Three
(LSCO), Pt / LSCO laminated structure, YBa_TwoC
u_ThreeO₇Can be mentioned. Here, the value of X is 0 ≦
X <2. In addition, in the laminated structure, before "/"
The listed materials constitute the upper layer and are listed after the “/”.
The material used constitutes the lower layer. First electrode and second electrode
May be composed of the same material,
May be composed of different materials
May be. Forming a first electrode or a second electrode
To do so, the first electrode material layer or the second electrode material
In the step after forming the layer, the first electrode material layer
Alternatively, the second electrode material layer may be patterned. First
Formation of the second electrode material layer or the second electrode material layer
For example, sputtering, reactive sputtering, electron beam evaporation,
MOCVD or pulsed laser ablation
Constituting the first electrode material layer and the second electrode material layer.
Can be carried out by a method suitable for the material. Also,
Patterning of the first and second electrode material layers
Is performed by ion milling or RIE, for example.
Can be.

Silicon oxide (SiO ₂ ), silicon nitride (SiN), SiON, and the like are used as a material for forming an insulating layer and an interlayer insulating layer in a ferroelectric nonvolatile semiconductor memory.
SOG, NSG, BPSG, PSG, BSG and LTO
Can be exemplified.

In the present invention, the first under the ferroelectric layer
And the second electrode is formed on the ferroelectric layer (that is, the first electrode corresponds to the lower electrode, and the second electrode corresponds to the upper electrode). A configuration in which a first electrode is formed on a ferroelectric layer and a second electrode is formed below a ferroelectric layer (that is, the first electrode corresponds to an upper electrode, The electrode corresponds to the lower electrode). The plate line may be configured to extend from the second electrode, or may be formed separately from the second electrode and connected to the second electrode. In the latter case, for example, aluminum or an aluminum-based alloy can be exemplified as a wiring material forming the plate line. As a structure in which the first electrode is common,
Specifically, a configuration in which a stripe-shaped first electrode is formed and a ferroelectric layer is formed so as to cover the entire surface of the stripe-shaped first electrode can be given. In such a structure, an overlapping area of the first electrode, the ferroelectric layer, and the second electrode corresponds to a memory cell. As a structure in which the first electrode is common, a structure in which a ferroelectric layer is formed in a predetermined region of the first electrode and a second electrode is formed on the ferroelectric layer, or Each first electrode is formed in a predetermined surface area of the wiring layer,
A structure in which a ferroelectric layer is formed on each of the first electrodes and a second electrode is formed on the ferroelectric layer can be given, but the present invention is not limited to these structures.

The selection transistor (switching transistor) is, for example, a well-known MIS type FET or MOS transistor.
It can be composed of a type FET. Examples of a material forming the bit line include polysilicon doped with impurities and a high melting point metal material. The electrical connection between the common first electrode and the first or second selection transistor is established by an insulating layer formed between the common first electrode and the first or second selection transistor. Through the provided connection holes (contact holes) or
Connection holes (contact holes) provided in such an insulating layer
And via a wiring layer formed on the insulating layer. In addition, as a material constituting the insulating layer, silicon oxide (SiO ₂ ), silicon nitride (SiN), SiON, S
OG, NSG, BPSG, PSG, BSG and LTO can be exemplified.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments of the invention (hereinafter abbreviated as embodiments).

Embodiment 1 Embodiment 1 relates to a method of driving a ferroelectric nonvolatile semiconductor memory (hereinafter abbreviated as “nonvolatile memory” for convenience) of the present invention. FIG. 1 shows a circuit diagram of the nonvolatile memory according to the first embodiment, and FIG. 2 shows a schematic partial sectional view.

The nonvolatile memory according to the first embodiment has the following (A)
A bit line BL, (B) a selection transistor TR,
(C) M-number (where a M ≧ 2, in the first embodiment, M = 8) and sub-memory unit SMU which is composed of the memory cells MC _M of, (D) M plate lines PL
_m (m = 1, 2,..., M)
U.

Then, each memory cell MC _m (m = 1, 2)
.. M) include a first electrode (lower electrode) 21, a ferroelectric layer 22, and a second electrode (upper electrode) 23. Further, the memory cells M forming the sub-memory unit SMU
The first electrode 21 of C _m is common in sub-memory unit SMU, (sometimes referred to as a common node CN) a first electrode 21 of the common, the selection transistor TR
Via is connected to the bit line BL, and the second electrode 23 is connected to a plate line PL _m. Note that FIG. 2 also shows the selection transistor TR and the memory cell MC and a part of the selection transistor TR ′ and the memory cell MC ′ adjacent to each other in the direction in which the bit line BL extends.

The plate line in the memory cell MC _m PL _m
Are connected to a plate line decoder / driver PD. Further, the gate electrode of the selection transistor TR is connected to a word line WL, and the word line WL is connected to a word line decoder / driver WD. Further, the bit line BL is connected to the sense amplifier SA.

The method of driving the nonvolatile memory according to the first embodiment for writing data to the nonvolatile memory will be described below. As an example, it is assumed that data is written into the memory cell MC _1. FIG. 3 shows operation waveforms. FIG.
In the figure, the numbers in parentheses correspond to the numbers of the steps described below.

In the first embodiment, the first intermediate power
Rank V_PL-M1Is [V_PL-L+ (V_{P LH}-V_PL-L) /
2], and the second intermediate potential V_PL-M2The value of
V_PL-HIs approximately equal to the value of Further, when the power supply voltage is V_ccMade
When V_PL-HAnd V_BL-HIs V _ccApproximately equal to_PL-L
And V_BL-LIs 0 volts. Therefore, the first intermediate
Potential V_PL-M1Is (1/2) V_ccIt is.

(1A) In the initial state, the bit lines, word lines, and all plate lines are at 0 volt. Further, the common node CN is also in a floating state at 0 volt.

(2A) At the start of data writing, select
With the transistor TR turned off, the selected memory cell
Le MC₁Plate line (selection plate line) P connected to
L₁High potential V_PL-H(= V_cc) Apply and unselect memory
Cell MC_k(However, k = 2,3 ... 8)
Plate line (unselected plate line) PL_k(However,
k = 2, 3,... 8)._PL-M1
[= V_PL-L+ (V_PL-H-V_{P LL}) / 2 = (1/2)
V_cc] To select the selected memory cell MC₁Should write to
Depending on the data, a low potential V is applied to the bit line BL._BL-L(= 0
Volts) or high potential V _BL-H(= V_cc) Is applied.
The common node CN of the sub memory unit SMU is in a floating state.
The plate line PL_MWith capacitive coupling
Approximately (1/2) V_ccPotential.

(3A) Next, by setting the word line WL to high level, the selection transistor TR is turned on, and the common node CN of the sub memory unit SMU and the bit line BL are connected via the selection transistor TR. Connecting.

(4A) Thereafter, a low potential V _PL-L (= 0 volt) is applied to the selected plate line PL ₁ .

In the step (2A), the bit line BL
When the low potential V _BL-L (= 0 volts) is applied to the gate, in step (3A), the selection transistor TR is turned on, and the common node CN and the bit line BL are connected via the selection transistor TR. When the selection plate line PL
_Since high potential V _PL-H (= V _cc ) is applied to 1,
Data "0" is written in the selected memory cell MC _1.
Thereafter, in step (4A), the selected plate line PL ₁
To be applied to low potential V _PL-L (= 0 volt), data "0" written in the selected memory cell MC ₁ is never changed.

On the other hand, in the step (2A), the bit line B
High potential V at L_BL-HIs applied in step (3A)
To turn on the selection transistor TR,
And the bit line BL via the selection transistor TR
When connected, select plate line PL₁High potential V
_PL-HIs applied, the selected memory cell MC₁To
Does not write data. Then, in step (4A)
And select plate line PL ₁Low potential V_PL-L(= 0 Vol
) Is applied to the selected memory cell MC.₁To
Data "1" is written.

(5A) Next, by setting the word line WL to low level, the selection transistor TR is turned off, and the common node CN is set in a floating state. The potential of the common node CN in this case, when data "0" is written to the selected memory cell MC ₁ is V _BL-L (= 0 volt), data "1 in the selected memory cell MC ₁ Is written as V _BL-H (= V _cc ).

(6A) Thereafter, the non-selected plate lines PL _k
Is applied with a second intermediate potential V _PL-M2 (= V _cc ). still,
Low potential V _PL-L (= 0 volt) is applied to selected plate line PL ₁
Is applied. As a result, the potential of the floating common node CN rises based on the capacitive coupling between the common node CN and the plate lines PL ₁ and PL _k . Specifically, when M = 8, the increase in the potential of the common node CN is about (1/1 /
2) _Vcc .

Therefore, the potential of the common node CN at this time is
Is the selected memory cell MC₁Data "0" is written to
, About (1/2) V_ccAnd select memory
Cell MC₁If data "1" was written to
Is about (3/2) V_ccBecomes Selection plate line PL₁To
Is the low potential V_PL-L(= 0 volts) is applied,
Selected memory cell MC₁Data "0" is written to
If the selected plate line PL₁And the common node CN
Is about (1/2) V_ccThe selected memory cell
Le MC₁No change occurs in the data “0” stored in the storage device.
On the other hand, the selected memory cell MC₁Data "1" is written to
If the selection plate line PL₁And common node
The potential difference with CN is about (3/2) V_ccAnd select
Morisel MC ₁Is strongly written to the data.

(7A) When the above operation is completed, the non-selected plate line PL _k is returned to V _PL-L (= 0 volt),
May be completed the write operation, in order to perform the next access smoothly, back to the potential of the non-selected plate line PL _K first intermediate potential _{V PL-M1 [= (1/2} ) V cc] Is preferred.

(8A) After that, the word line WL is set to the high level again, whereby the selecting transistor TR is set.
Is turned on, the common node CN of the sub memory unit SMU and the bit line BL are connected via the selection transistor TR, and the potential of the common node CN is set to 0 volt.

(9A) Finally, by setting the word line WL to low level, the selection transistor TR is turned off, and the common node CN of the sub memory unit SMU is set.
And the bit line BL is disconnected, and the unselected plate line PL _k is returned to V _PL-L (= 0 volt) to complete the write operation.

Thereafter, the memory cell MC _m (m = 2, 3,...)
Steps (1A) to (9A) are sequentially performed for 8).

In the above steps, it is only necessary to apply V _BL-H or V _BL-L to the bit line BL, and the intermediate potential is only V _PL-M applied to the unselected plate line PL _k . In addition, although the disturbance is ± (1/2) _Vcc, which is the same as the conventional driving method, data “1” can be written more strongly than the conventional driving method.

Hereinafter, a method for manufacturing the nonvolatile memory according to the first embodiment will be described.

First, a MOS transistor functioning as a selection transistor TR in a nonvolatile memory is formed on a semiconductor substrate 10. For that purpose, for example, LOCO
An element isolation region 11 having an S structure is formed based on a known method. Note that the element isolation region may have a trench structure or a combination of a LOCOS structure and a trench structure. After that, the surface of the semiconductor substrate 10 is oxidized by, for example, a pyrogenic method to form the gate insulating film 12. Next, after a polysilicon layer doped with impurities is formed on the entire surface by a CVD method, the polysilicon layer is patterned to form a gate electrode 13. This gate electrode 13 also serves as a word line WL. Incidentally, instead of forming the gate electrode 13 from the polysilicon layer, the gate electrode 13 may be formed from polycide or metal silicide.
Next, ions are implanted into the semiconductor substrate 10 to form an LDD structure. Thereafter, a SiO ₂ layer is formed on the entire surface by the CVD method, and then the SiO ₂ layer is etched back to form a gate sidewall (not shown) on the side surface of the gate electrode 13. Next, after ion implantation is performed on the semiconductor substrate 10, the source / drain regions 14A and 14B are formed by performing activation annealing treatment of the ion-implanted impurities.

Next, the lower insulating layer made of SiO ₂ is
After being formed by the VD method, one of the source / drain regions 1
An opening is formed in the lower insulating layer above 4A by RIE. Then, a polysilicon layer doped with impurities is formed on the lower insulating layer including the inside of the opening by a CVD method. Thereby, the connection hole (contact hole) 1
5 can be obtained. Next, by patterning the polysilicon layer on the lower insulating layer, the bit line BL
To form Then, the upper insulating layer made of BPSG is replaced with C
It is formed on the entire surface by the VD method. After forming the upper insulating layer made of BPSG, for example, at 900 ° C. in a nitrogen gas atmosphere.
It is preferable to reflow the upper insulating layer for × 20 minutes. Further, if necessary, it is desirable to planarize the upper insulating layer by chemically and mechanically polishing the top surface of the upper insulating layer by, for example, a chemical mechanical polishing method (CMP method).
Note that the lower insulating layer and the upper insulating layer are collectively referred to as an insulating layer 16.

Next, the other source / drain region 14B
After an opening 17 is formed in the insulating layer 16 above the opening 17 by RIE, the inside of the opening 17 is filled with impurity-doped polysilicon to form a contact hole (contact hole).
18 is completed. The bit line BL extends over the lower insulating layer,
It extends so as not to contact the connection hole 18 in the left-right direction of the drawing.

The connection hole 18 is formed in the opening 17 formed in the insulating layer 16 by, for example, tungsten, Ti, P
t, Pd, Cu, TiW, TiNW, WSi ₂ , MoS
It can also be formed by embedding a metal wiring material made of refractory metal or metal silicide of i ₂ and the like. The top surface of the connection hole 18 may be substantially on the same plane as the surface of the insulating layer 16, or the top of the connection hole 18 may extend on the surface of the insulating layer 16. Opening 17 with tungsten
Table 1 below shows conditions for forming the connection holes 18 by burying
An example is shown below. It is preferable that a Ti layer and a TiN layer are sequentially formed on the insulating layer 16 including the inside of the opening 17 by, for example, a magnetron sputtering method before filling the opening 17 with tungsten. Here, the reason why the Ti layer and the TiN layer are formed is to obtain an ohmic low contact resistance, to prevent the semiconductor substrate 10 from being damaged by the blanket tungsten CVD method, and to improve the adhesion of tungsten.

[Table 1] Sputtering condition of Ti layer (thickness: 20 nm) Process gas: Ar = 35 sccm Pressure: 0.52 Pa RF power: 2 kW Heating of substrate: None Sputtering condition of TiN layer (thickness: 100 nm) Process Gas: N ₂ / Ar = 100/35 sccm Pressure: 1.0 Pa RF power: 6 kW Substrate heating: None Conditions for forming tungsten by CVD Gas used: WF ₆ / H ₂ / Ar = 40/400/2250
Sccm pressure: 10.7 kPa Formation temperature: 450 ° C. Etching conditions for tungsten layer, TiN layer, and Ti layer First stage etching: Tungsten layer etching Gas used: SF ₆ / Ar / He = 110: 90: 5 scc
m Pressure: 46 Pa RF power: 275 W Second stage etching: TiN layer / Ti layer etching Gas used: Ar / Cl ₂ = 75/5 sccm Pressure: 6.5 Pa RF power: 250 W

Next, it is desirable to form an adhesion layer (not shown) made of TiN on the insulating layer 16. And
A first electrode material layer constituting a first electrode (lower electrode) 21 made of Ir is formed on the adhesion layer by, for example, a sputtering method, and the first electrode material layer and the adhesion layer are formed by photolithography and dry etching. By patterning based on the etching technique, the first electrode 21 (common node CN)
Can be obtained.

Thereafter, for example, by the MOCVD method,
A ferroelectric thin film made of a Bi-based layered structure perovskite ferroelectric material (specifically, for example, Bi ₂ SrTa ₂ O ₉ ) is formed on the entire surface. Thereafter, after performing a drying treatment in air at 250 ° C., a heat treatment is performed for one hour in an oxygen gas atmosphere at 750 ° C. to promote crystallization and obtain the ferroelectric layer 22.

Next, an IrO _2-x layer and a Pt layer are sequentially formed on the entire surface by a sputtering method, and then the Pt layer, the IrO
_2-X layer, are sequentially ferroelectric layer 22, and patterned to form a second electrode 23 and the ferroelectric layer 22 serving also as a plate line PL _m. If the ferroelectric layer 22 is damaged by the etching, heat treatment may be performed at a temperature required for the damage recovery. After that, the upper insulating layer 26A is formed on the insulating layer 16 and the second electrode 23.

Each second electrode 23 is connected to a plate line PL _m
It is not necessary to also serve as. In this case, after forming the upper insulating layer on the insulating layer 16 and the ferroelectric layer 22, the plate line PL _m is formed on the upper insulating layer, together, the second electrode 23 and the plate line PL _{and m} may be connected by a connection hole (via hole) provided in the upper insulating layer.

For example, the conditions for forming a ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ are shown in Table 2 below. In Table 2, “thd” is an abbreviation for tetramethylheptanedionate. Further, the source materials shown in Table 2 are dissolved in a solvent containing tetrahydrofuran (THF) as a main component.

[Table 2] Formation by MOCVD method Source material: Sr (thd) ₂ -tetraglyme Bi (C ₆ H ₅ ) ₃ Ta (O-iC ₃ H ₇ ) ₄ (thd) Formation temperature: 400 to 700 ° C. Process gas: Ar / O ₂ = 1000/1000 cm ³ Formation rate: 5 to 20 nm / min

Alternatively, a ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ is formed by a pulse laser ablation method,
It can also be formed over the entire surface by a gel method or an RF sputtering method. The forming conditions in these cases are shown in Table 3 below.
Examples are shown in Tables 4 and 5. When a thick ferroelectric thin film is formed by a sol-gel method, spin coating and drying, or spin coating and firing (or annealing) may be repeated a desired number of times.

[Table 3] Formation by pulsed laser ablation method Target: Bi ₂ SrTa ₂ O ₉ Laser: KrF excimer laser (wavelength 248 nm,
(Pulse width 25 ns, 5 Hz) Forming temperature: 400 to 800 ° C. Oxygen concentration: 3 Pa

[Table 4] Formation by sol-gel method Raw material: Bi (CH ₃ (CH ₂ ) ₃ CH (C ₂ H ₅ ) COO) ₃ [Bismuth-2-ethylhexanoic acid, Bi (OOc) ₃ ] Sr ( CH ₃ (CH ₂ ) ₃ CH (C ₂ H ₅ ) COO) ₂ [Strontium · 2ethylhexanoic acid, Sr (OO
c) ₂ ] Ta (OEt) ₅ [tantalum ethoxide] Spin coating conditions: 3000 rpm × 20 seconds Drying: 250 ° C. × 7 minutes Firing: 400-800 ° C. × 1 hour (RT if necessary)
A processing is added)

[Table 5] Formation by RF sputtering target: Bi ₂ SrTa ₂ O ₉ ceramic target RF power: 1.2 W to 2.0 W / target 1 cm ² Atmospheric pressure: 0.2 to 1.3 Pa Forming temperature: room temperature゜ 600 ° C. Process gas: Ar / O ₂ flow rate ratio = 2/1 to 9/1

When the ferroelectric layer is made of PZT or PLZT, PZT by magnetron sputtering is used.
Table 6 below shows conditions for forming T or PLZT. Alternatively, PZT or PLZT is prepared by reactive sputtering, electron beam evaporation, sol-gel, or MOCVD.
It can also be formed by a method.

[Table 6] Target: PZT or PLZT Process gas: Ar / O ₂ = 90% by volume / 10% by volume Pressure: 4 Pa Power: 50 W Forming temperature: 500 ° C.

Further, PZT or PLZT can be formed by a pulse laser ablation method. The forming conditions in this case are shown in Table 7 below.

[Table 7] Target: PZT or PLZT Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 ns, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Forming temperature: 550 to 600 ° C. Oxygen concentration: 40 to 120 Pa

(Embodiment 2) Embodiment 2 is a modification of Embodiment 1. In the second embodiment, the driving method of the nonvolatile memory described in the first embodiment is applied to data rewriting after reading data from a memory cell. The configuration of the nonvolatile memory can be similar to that of the first embodiment. Hereinafter, a method for driving the nonvolatile memory according to the second embodiment will be described. As an example,
Reading data from the memory cell MC _1, then it is assumed to rewrite data. FIG. 4 shows operation waveforms. In FIG. 4, the numbers in parentheses correspond to the numbers of the steps described below.

Note that also in the second embodiment, the value of the first intermediate potential V _PL-M1 is [V _PL-L + (V _PL-H −V _PL-L ) /
2], and the value of the second intermediate potential V _PL-M2 is
It is almost equal to the value of _{VPL- H} . Further, when the power supply voltage is V _cc , the values of V _PL-H and V _BL-H are substantially equal to V _cc and V _PL-L
And the value of V _BL-L is 0 volts. Therefore, the value of the first intermediate potential V _PL-M1 is (１ ／) V _cc .

[0087] First, data is read in the memory cell MC _1, which is selected.

(1B) In the initial state, the bit lines, word lines, and all plate lines are at 0 volt. Further, the common node CN is also in a floating state at 0 volt.

(2B) At the start of data reading, the selection transistor TR is turned on by setting the word line WL to high level. As a result, the common node CN of the sub memory unit SMU is connected to the bit line BL. Note that the bit line BL is set in a floating state.

(3B) Next, the selected plate line PL
Applying a _{V PL-H (= V cc} ) to _one. Unselected plate line P
L _k is kept at V _PL-L (= 0 volt). At this time,
When the data "1" is written to the selected memory cell MC ₁ is poled in the ferroelectric layer occurs, the potential of the common node CN increases. On the other hand, the selected memory cell M
When data “0” is written in C ₁ , no polarization inversion occurs in the ferroelectric layer and the selected plate line PL
_Due to the capacitive coupling between ₁ and the common node CN, the potential of the common node CN is slightly higher than 0 volt.

(4B) Thereafter, the word line WL is set to the low level to turn off the selection transistor TR, and the common node CN of the sub memory unit SMU is set.
Is disconnected from the bit line BL.

(5B) Next, the sense amplifier SA is activated to determine the data, read the data, and charge / discharge the bit line BL.

[0093] Next, rewriting of data in the memory cell MC _1, which is selected.

(6B) At the start of data rewriting, the selection transistor TR is off. Also,
A high potential V _PL-H (= V _cc ) is applied to the plate line PL ₁ connected to the selected memory cell MC ₁ . In this state, the plate line P connected to the non-selected memory cell MC _k
A first intermediate potential V _PL-M1 [= (１ ／) V _cc ] is applied to L _k . Incidentally, depending on the data to be rewritten to the selected memory cell MC _1, a low potential V _BL-L (= 0 volt) or a high potential _{V BL-H (= V cc} ) is applied to the bit line.

(7B) Thereafter, the operations of steps (3A) to (9A) in the method of driving the nonvolatile memory according to the first embodiment are performed. Thus, the rewriting of data into the selected memory cell MC ₁ is completed.

Further, a memory cell MC _m (m = 2, 3...)
Steps (1B) to (7B) are sequentially performed for 8).

(Embodiment 3) Embodiment 3 is also a modification of Embodiment 1. In the third embodiment, the value of the first intermediate potential V _PL-M1 is [V _PL-L + (V _PL-H −
V _PL-L ) / 3], and the second intermediate potential V
The value of _PL-M2 is [V _PL-L +2 (V _PL-H −V _PL-L ) / 3]
Is approximately equal to the value of When the power supply voltage is _Vcc ,
The value of _PL-H is approximately equal to _Vcc, and the value of _VBL-H is (2/3) V
Approximately equal to _cc , the values of V _PL-L and V _BL-L are 0 volts. Therefore, the value of the first intermediate potential V _PL-M1 is (１ ／)
V _cc , and the value of the second intermediate potential V _PL-M2 is (2/3)
_Vcc .

The method of driving the nonvolatile memory according to the third embodiment, in which data is written to the nonvolatile memory, will be described below. However, the method according to the third embodiment is applied to the rewriting of data described in the second embodiment. Methods can also be applied.
Incidentally, it is assumed that the write data as an example, the memory cell MC _1. FIG. 5 shows operation waveforms. In FIG. 5,
The numbers in parentheses correspond to the numbers of the steps described below.

(1C) In the initial state, the bit lines, word lines, and all plate lines are at 0 volt. Further, the common node CN is also in a floating state at 0 volt.

[0100] (2C) at the start of data write, leave the selection transistor TR off, a plate line connected to the selected memory cell MC ₁ (selected plate line) P
A high potential V _PL-H (= V _cc ) is applied to L ₁ , and a first intermediate potential V _PL-M [= is applied to a plate line (unselected plate line) PL _k connected to the unselected memory cell MC _k. V _PL-L + (V
_{PL-H -V PL-L)} / 3 = (1/3) V cc] is applied to, depending on the data to be written into the selected memory cell MC _1, the bit line BL low potential V _BL-L (= 0 V) or a high potential V _BL-H [= (2/3) V _cc ]. Common node CN sub-memory unit SMU is a floating state, therefore, the capacitive coupling between the plate line PL _M, becomes roughly (1/3) V _cc potential.

(3C) Next, by setting the word line WL to high level, the selection transistor TR is turned on, and the common node CN and the bit line BL are connected via the selection transistor TR.

(4C) Thereafter, a low potential V _PL-L (= 0 volt) is applied to the selected plate line PL ₁ .

In the step (2C), when a low potential V _BL-L (= 0 volt) is applied to the bit line, the step (3C)
In C), when the selection transistor TR is turned on and the common node CN and the bit line BL are connected via the selection transistor TR, the selection plate line PL ₁
Is applied with the high potential V _PL-H (= V _cc ), data “0” is written to the selected memory cell MC ₁ . Thereafter, in step (4C), it also applies a low potential V _PL-L (= 0 volt) to the selected plate line PL _1, data "0" written in the selected memory cell MC ₁ is to be changed Absent.

On the other hand, in step (2C), bit line B
High potential V at L_BL-H[= (2/3) V _cc] Field is applied
In step (3C), the selection transistor TR is
Turn on, select common node CN and bit line BL
Selected when connected via the transistor TR
High potential V_PL-HIs selected,
Recell MC₁No data is written to. After that,
In step (4C), the selected plate line PL₁Low potential V
_PL-L(= 0 volts), the selection memo
Recell MC₁"1" is weakly written in

(5C) Next, the word line WL is set to a low level, thereby turning off the selection transistor TR and bringing the common node CN into a floating state. The potential of the common node CN in this case, when data "0" is written to the selected memory cell MC ₁ is V _BL-L (= 0 volt), data "1 in the selected memory cell MC ₁ Is written, V _BL-H [= (2/3)
_Vcc ].

(6C) Thereafter, the non-selected plate lines PL _k
To the second intermediate potential V _PL-M2 [= (2/3) V _cc ]. Note that the selected plate line PL ₁ low potential V _PL-L (=
0 volts). As a result, the common node C
The potential of the floating common node CN rises based on the capacitive coupling between N and the plate lines PL ₁ and PL _k . Specifically, when M = 8, the increase in the potential of the common node CN is about (１ ／) _Vcc .

Therefore, the potential of the common node CN at this time is
Is the selected memory cell MC₁Data "0" is written to
About (1/3) V_ccAnd select memory
Cell MC₁If data "1" was written to
Is about V_ccBecomes Selection plate line PL₁Has a low potential V
_PL-L(= 0 volt) is applied, the selected memory
Cell MC₁If data "0" has been written to
Is the selection plate line PL₁And the common node CN
The difference is about (1/3) V_ccAnd the selected memory cell MC ₁
No change occurs in the data “0” stored in the storage device. On the other hand,
Select memory cell MC₁Data "1" was written to
In the case, select plate line PL₁And the common node CN
Potential difference between_ccAnd the selected memory cell MC₁To
Data "1" is reliably written.

(7C) When the above operation is completed, the non-selected plate line PL _k is returned to V _PL-L (= 0 volt),
May be completed the write operation, in order to perform the next access smoothly, back to the potential of the non-selected plate line PL _K first intermediate potential _{V PL-M1 [= (1/3} ) V cc] Is preferred.

(8C) After that, the word line WL is set to the high level again, whereby the selecting transistor TR is set.
Is turned on, and the common node CN and the bit line BL are connected via the selection transistor TR.
Is 0 volt.

(9C) Finally, by turning the word line WL to low level, the selection transistor TR is turned off, and the common node CN of the sub memory unit SMU is set.
And the bit line BL is disconnected, and the unselected plate line PL is disconnected.
_{Return k} to V _PL-L (= 0 volts) to complete the write operation.

Thereafter, the memory cell MC _m (m = 2, 3,...)
Steps (1C) to (9C) are sequentially performed for 8).

In the above steps, the bit line BL
V_BL-H[= (2/3) V_cc] Or V _BL-L(= 0 volt)
Only needs to be applied. Therefore, the sense amplifier SA has 2
This is a simple operation of the value, and sufficient operation margin can be secured.
And a stable operation can be realized. Moreover,
Disturbance is ± (1/3) V_ccAnd in Embodiment 1
Drive method is lower than the conventional drive method.
Data "1" can be written reliably
You.

(Embodiment 4) Embodiment 4 relates to a driving method according to the first configuration. FIG. 6 is a circuit diagram of the nonvolatile memory according to the fourth embodiment, and FIG. 7 is a schematic partial cross-sectional view.

The non-volatile memory according to the fourth embodiment has the structure (A-
1) and the first bit line BL _1, (B-1) N pieces (however,
N ≧ 1, and in the fourth embodiment, specifically, N = 1)
The first selection transistor TR _1N of, (C-1) respectively are M (where a M ≧ 2, in the fourth embodiment, M = 8) first memory cell MC _{1 nM} of (n = 1
2)... N) and the first memory cells M constituting each of the N first sub memory units SMU _1N and (D-1) N sub memory units SMU _1N
A first memory unit MU ₁ composed of M plate lines PL _m shared by C _{1 nm} (m = 1, 2,... M);
And, the (A-2) a second bit line BL _2, (B-
2) N second selection transistors TR _2N and (C−
2) each of which is composed of M second memory cell MC _{2 nM,} N-number of the second sub-memory unit SMU
_2N and (D-2) M plates common to the second memory cells MC _{2 nm} forming each of the _N sub-memory units SMU _2N and forming the first memory unit MU ₁ M plate lines P common to line PL _m
L _m , and a second memory unit MU ₂ .

In the fourth embodiment, N = 1
Therefore, the suffixes “N” and “n” are omitted and the first selection
Transistor TR_1NTo the first selection transistor TR₁
And the first memory cell MC_1nM, MC_1nmThe first
Memory cell MC_1M, MC_1mAnd the first sub-memory
Unit SMU_1NThe sub memory unit SMU₁And expression
And the second selection transistor TR_2NTo the second selection
Transistor TR_TwoAnd the second memory cell MC_2nM,
MC_2nmTo the second memory cell MC_2M, MC_2mIs expressed as
Second sub memory unit SMU_2NTo the second sub memory
Unit SMU _TwoIs expressed as

In the schematic partial sectional view of FIG. 7, the second bit line BL ₂ , the second selection transistor TR ₂ and the second memory cell MC _2m are connected to the first bit line BL ₁ a first selection transistor TR ₁ and the first memory cell MC _{1 m,} adjacent in the direction perpendicular to the paper surface. Also,
Figure In 7, a first selection transistor TR ₁ and the first memory cell MC _{1 m,} the first selection transistor TR adjacent to a direction of extension of the first bit line BL ₁ '
₁ and a part of the first memory cell MC ′ _1m are also shown. The first memory cells MC _1m , MC ′ _1m ... Adjacent in the direction in which the first bit line BL ₁ extends
Bit line BL ₁ is common.

Then, each of the memory cells MC _1m and MC _2m is
It comprises a first electrode 21 (lower electrode), a ferroelectric layer 22 and a second electrode (upper electrode) 23. In the first memory unit MU _1, the n-th (where, n = 1, 2 ·
..N, and in the fourth embodiment, the first electrode 21 of the first memory cell MC _1m constituting the _first sub-memory unit SMU1 (n = 1) is the n-th first memory cell MC _1m . of a common in sub-memory unit SMU _1, (sometimes referred to as a common node CN ₁₎ a first electrode 21 of the common, the first through the n-th of the first selection transistor TR ₁ The second electrode 2 connected to the bit line BL ₁
3 are connected to a common plate line PL _m. on the other hand,
In the second memory unit MU ₂ , the first of the second memory cells MC _2m constituting the n-th (n = 1 in the fourth embodiment) second sub memory unit SMU ₂
Electrode 21 is connected to the n-th second sub memory unit S
MU _{2 and} the common first electrode 21
(Sometimes called a common node CN ₂ ) is connected to the _second bit line BL ₂ via the n-th second selection transistor TR ₂ , and the second electrode 23 is connected to the common plate line PL Connected to _m .

Plate line PL in memory cell MC _2m
m is shared with the plate line PL _m in the memory cell MC _1m, and is connected to the plate line decoder / driver PD. Further, the first selection transistor TR
_First gate electrode is connected to a word line WL _1, the second gate electrode of the selection transistor TR ₂ second word line W
Is connected to L _2, word lines WL _1, WL ₂ is connected to a word line decoder / driver WD. Further, the first bit line BL ₁ and the second bit line BL ₂ are connected to a differential sense amplifier SA.

Incidentally, the number (M) of memory cells constituting the sub memory unit of the nonvolatile memory is not limited to four.
In general, the number can be 2 × M (where M = 1, 2, 3,...). However, the value of M may be 2 or more, and for example, is preferably a power of 2 (2, 4, 8, 16,...).

[0120] In the nonvolatile memory of the fourth embodiment, sharing the plate line PL _m (i.e., paired)
1-bit data is stored in each of the memory cells MC _1m and MC _2m (m = 1, 2,..., M).

[0121] When the read out data stored in the first memory cell MC _{1 m,} the first transistor for selection TR ₁ is turned on, the second transistor for selection TR ₂ is turned off, and the reference potential is applied to the second bit line BL _2, when reading data stored in the second memory cell MC _2m, the second transistor for selection TR ₂ is turned on, selecting a first the use transistor TR ₁ is turned off, and applies a reference potential to the first bit line BL _1.

A method for driving a nonvolatile memory for writing data to the nonvolatile memory according to the fourth embodiment will be described below. Here, data writing corresponds to the method for driving a nonvolatile memory of the present invention. As an example, sharing the plate line PL ₁ (i.e., paired) memory cells M
It is assumed that data is written to each of C ₁₁ and MC ₂₁ . FIG. 8 shows operation waveforms. In FIG. 8, the numbers in parentheses correspond to the numbers of the steps described below.

First, the selected first memory cell MC ₁₁
Write data to

(1D) In the initial state, all bit lines, all word lines, and all plate lines are at 0 volt. Further, the common nodes CN ₁ and CN ₂ are also floating at 0 volt.

(2D) At the start of data writing, the first selection transistor TR ₁ and the second selection transistor TR ₂ are turned off. The high potential V _PL-H (= V _cc ) is applied to the selected plate line PL ₁ connected to the selected memory cell MC ₁₁ , and the high potential V _PL-H (= V _cc ) is applied to the non-selected plate line PL _k connected to the non-selected memory cell MC _k. When the first intermediate potential V _PL-M1 [= (１ ／) V _cc ] is applied and the data to be written to the selected memory cell MC ₁₁ is “1”, the first bit line BL ₁ To the high potential V _BL-H (=
V _cc ), and when the data to be written is “0”, the first bit line BL _{1 is set} to the low potential V _BL-L (= 0 volt). Common node CN ₂ of the common node CN ₁ and the second sub-memory unit SMU ₂ of the first sub-memory unit SMU ₁ is therefore is a floating state, the capacitive coupling between the plate line PL _M, approximately (1 / 2) The potential becomes _Vcc .

[0126] (3D) Next, by the word line WL ₁ and the high level, the first selection transistor TR
₁ is turned on, and the common node CN ₁ and the first bit line B
And L ₁ through a first selection transistor TR ₁ is connected.

(4D) Thereafter, a low potential V _PL-L (= 0 volt) is applied to the selected plate line PL ₁ .

When the low potential V _BL-L (= 0 volt) is applied to the first bit line BL ₁ in the step (2D), in the step (3D), the first selection transistor TR ₁ to the oN state, the common node CN ₁ and when the first bit line BL ₁ is connected through a first selection transistor TR _1, a high potential V _{PL -H} to a selected plate line PL ₁
(= V _cc ), the selected memory cell M
Data "0" is written in the C _11. Then, step (4)
In D), the low potential V to a selected plate line PL _{1
Even if PL-L} (= 0 volt) is applied, the selected memory cell MC
Data “0” written in ₁₁ does not change.

On the other hand, if the high potential V _BL-H is applied to the first bit line BL ₁ in step (2D), the first selection transistor TR ₁ is turned on in step (3D). , Common node CN ₁ and first bit line BL ₁
When the door is connected through a first selection transistor TR _1, because the high-potential V _PL-H is applied to the selected plate line PL _1, data is not written to the selected memory cell MC _11. Thereafter, in step (4D), by applying a low potential V _PL-L (= 0 volt) to the selected plate line PL _1, data "1" into the selected memory cell MC ₁₁ are written.

[0130] In the step (2D) ~ step (4D), although the second selection transistor TR ₂ is off, therefore, the common node CN ₂ of the second sub-memory unit SMU ₂ is in suspension , The potential of the common node CN ₂ is
A potential of approximately (1/2) _Vcc is maintained.

[0131] (5D) Then, by the word line WL ₁ and the low level, the first selection transistor TR
₁ is turned off, the common node CN ₁ into a floating state.
The potential of the common node CN ₁ at this time, when data "0" is written to the selected memory cell MC ₁₁ is V
_BL-L is (= 0 volt), when data "1" is written to the selected memory cell MC ₁₁ is, V _BL-H (= V
_cc ).

Next, the selected second memory cell MC ₂₁
Write data to

(6D) At the start of data writing, a high potential V _PL-H (= V _cc ) is applied to the selected plate line PL ₁ connected to the selected memory cell MC ₂₁ , and the non-selected memory cell MC _k , The first intermediate potential V _PL-M1 [= (１ ／) V _cc ] is continuously applied to the non-selected plate line PL _k connected to the selected memory cell MC ₁₁ and the data to be written to the selected memory cell MC ₁₁ is “1”. In some cases, the second bit line BL _{2 is set} to the high potential V _BL-H (= V _cc ), and the data to be written is “0”.
, The second bit line BL _{2 is set} to the low potential V _{BL- L}
(= 0 volt). (7D) Next, by the word line WL ₂ to the high level, the second transistor for selection TR ₂ is turned on, the common node CN ₂ and the first bit line BL ₂ and the first
Connected through a transistor for selection TR _1. (8D) Then, the low potential V _{PL-L is applied} to the selected plate line PL _1.
(= 0 volts).

In the step (6D), when the low potential V _BL-L (= 0 volt) is applied to the second bit line BL ₂ , in the step (7D), the second selection transistor TR ₂ is turned on, the common node CN ₂ and when the second bit line BL ₂ and connected to the second via the selection transistor TR _2, a high potential V _{PL -H} to a selected plate line PL ₁
(= V _cc ), the selected memory cell M
Data "0" is written in the C _21. Then, step (8)
In D), the low potential V to a selected plate line PL _{1
Even if PL-L} (= 0 volt) is applied, the selected memory cell MC
Data “0” written in ₂₁ does not change.

On the other hand, when the high potential V _BL-H is applied to the second bit line BL ₂ in step (6D), the second selection transistor TR ₂ is turned on in step (7D). , Common node CN ₂ and second bit line BL ₂
DOO When the connected second through the selection transistor TR _2, because the high-potential V _PL-H is applied to the selected plate line PL _1, data is not written to the selected memory cell MC _21. Thereafter, in step (8D), by applying a low potential V _PL-L (= 0 volt) to the selected plate line PL _1, data "1" in the selected memory cell MC ₂₁ are written.

[0136] (9D) Next, by the word line WL ₂ to a low level, the second selection transistor TR
₂ is turned off, and the common node CN ₂ is set in a floating state.
The potential of the common node CN ₂ at this time, when data "0" is written to the selected memory cell MC ₂₁ is V
_BL-L is (= 0 volt), when data "1" is written to the selected memory cell MC ₂₁ is, V _BL-H (= V
_cc ).

[0137] In the step (5D) ~ step (8D), the first selection transistor TR ₁ is because it is off, the common node CN ₂ of the first sub-memory unit SMU ₁ is in suspension . Therefore, in the step (5D) ~ step (8D), the potential of the common node CN _1, the potential in step (5D), i.e., when data "0" is written to the selected memory cell MC ₁₁ is V _BL-L (=
0 volts), when data "1" is written to the selected memory cell MC ₁₁ continues to hold the _{V BL-H (= V cc} ).

(10D) Next, the non-selected plate lines PL _k
Is applied with a second intermediate potential V _PL-M2 (= V _cc ). still,
Low potential V _PL-L (= 0 volt) is applied to selected plate line PL ₁
Is applied. As a result, the common nodes CN ₁ and CN ₂
And based on the capacitive coupling between the plate line PL _1, PL _k, the potential of the common node CN _1, CN ₂ in a floating state rises. Specifically, when M = 8, the increase in the potential of the common nodes CN ₁ and CN ₂ is about (１ ／) _Vcc .

Therefore, the common nodes CN ₁ and C at this time
When the data “0” is written in the selected memory cells MC ₁₁ and MC ₂₁ , the potential of N ₂ becomes approximately (１ ／) V _cc.
And data “1” is stored in the selected memory cells MC ₁₁ and MC _21.
Is about (3/2) _Vcc . Since the low potential V _PL-L (= 0 volt) is applied to the selected plate line PL ₁ , the selected memory cells MC ₁₁ , M
When the data "0" is written in the C _21, the potential difference between the selected plate line PL ₁ and the common node CN ₁ is about (1/2) V _cc, the selected memory cell MC _11, MC _{twenty one}
No change occurs in the data “0” stored in the storage device. On the other hand, when data “1” has been written to the selected memory cells MC ₁₁ and MC ₂₁ , the potential difference between the selected plate line PL ₁ and the common node CN ₁ is about (3/2) _Vcc , Data “1” is strongly written into the selected memory cells MC ₁₁ and MC ₂₁ .

(11D) When the above operations are completed,
The unselected plate line PL _k may be returned to V _PL-L (= 0 volt) to complete the write operation. However, in order to smoothly perform the next access, the potential of the unselected plate line PL _K is set to the first potential. It is preferable to return to the intermediate potential V _PL-M1 [= (1/2) V _cc ].

(12D) Thereafter, the word line W
By setting L ₁ and WL ₂ to a high level, the first selection transistor TR ₁ and the second selection transistor TR ₂ are turned on, and the common node CN ₁ and the first bit line BL ₁ are connected to the _first bit line BL ₁ . 1 via the selection transistor TR ₁ is connected, the potential of the common node CN ₁ and 0 volts, connected to the common node CN ₂ and the second bit line BL ₂ second through the selection transistor TR ₂ and, the potential of the common node CN ₂ and 0 volts.

(13D) Finally, the word lines WL ₁ and WL ₂
The by a low level, the first transistor for selection TR ₁ and the second transistor for selection TR ₂ is turned off, the sub-memory unit SMU _1, SMU ₂ common node CN _1, CN ₂ and the first The connection between the bit line BL ₁ and the second bit line BL ₂ is released, the unselected plate line PL _k is returned to V _PL-L (= 0 volt), and the write operation is completed.

Thereafter, the memory cells MC _1m and C _2m (m = 2,
3... 8) are sequentially performed in steps (1D) to (13).
Perform operation D).

In the above steps, it is only necessary to apply V _BL-H or V _BL-L to the bit line BL, and the intermediate potential is only V _PL-M which is applied to the non-selected plate line PL _k . In addition, although the disturbance is ± (1/2) _Vcc, which is the same as the conventional driving method, data “1” can be written more strongly than the conventional driving method.

The driving method described in the third embodiment can be applied to the driving method of the first configuration in the fourth embodiment.

(Embodiment 5) Embodiment 5 relates to a driving method according to the second configuration. FIG. 9 shows a circuit diagram of the nonvolatile memory according to the fifth embodiment. The structure of the nonvolatile memory according to the fifth embodiment is the same as the structure of the nonvolatile memory according to the fourth embodiment whose schematic partial cross-sectional view is shown in FIG. However, in the fifth embodiment in that a first gate electrode of the selection transistor TR ₁ and the second gate electrode of the selection transistor TR ₂ is connected to the same word line WL, the embodiment Different from 4. Further, in the method of driving the nonvolatile memory according to the fifth embodiment, the first memory cells MC _1m constituting the _first sub memory unit SMU ₁ sharing the plate line (that is, paired).
And a second constituting the second sub-memory unit SMU ₂
In the memory cell _MC2m , one bit having a complementary data structure is stored, or one bit having a complementary data structure is written (or rewritten).

A method of driving a nonvolatile memory for reading data from the nonvolatile memory of Embodiment 5 and rewriting data will be described below. Here, the data rewriting operation corresponds to the driving method of the nonvolatile memory of the present invention. As an example, it is assumed that data is read from the memory cells (MC ₁₁ , MC ₂₁ ) sharing the plate line PL ₁ (that is, a pair) and rewritten. Here, the first memory cell MC ₁₁ is stored in the data "1", the second memory cells MC ₂₁ and that the data "0" is stored. FIG. 10 shows operation waveforms. In FIG. 10, the numerals in parentheses correspond to the numbers of the steps described below.

First, the selected memory cell (MC ₁₁ , M
Reading data of C _21).

(1E) In the initial state, all bit lines, all word lines, and all plate lines are at 0 volt. Further, the common nodes CN ₁ and CN ₂ are also floating at 0 volt.

(2E) At the start of data reading, the word line WL is set to the high level, whereby the first selection transistor TR ₁ and the second selection transistor TR _{2 are set.}
Is turned on. Thus, the common node CN ₁ of the first sub-memory unit SMU ₁ is the first bit line BL
It is connected to _one common node CN ₂ of the second sub-memory unit SMU ₂ is connected to the second bit line BL _2. still,
The first bit line BL ₁ and the second bit line BL ₂ is kept in a floating state.

(3E) Next, the selected plate line PL
Applying a _{V PL-H (= V cc} ) to _one. Unselected plate line P
L _k is kept at V _PL-L (= 0 volt). At this time,
Since the data "1" is written in the first selected memory cell MC _11, cause polarization inversion in the ferroelectric layer,
The potential of the common node CN ₁ and the first bit line BL ₁
Potential rises. On the other hand, the second selected memory cell MC ₂₁
Since the data "0" is written to without developing the polarization inversion in the ferroelectric layer, the common node CN ₂ potential,
Furthermore, the second potential of the bit line BL ₂ becomes slightly higher degree than 0 volts. Thereby, the first bit line B
L ₁ and a potential difference occurs between the second bit line BL _2.

(4E) Thereafter, the word line WL is set to the low level, whereby the first selection transistor TR is set.
Turning off the _first and second selection transistors TR ₂ ,
The connection between the common node CN ₁ of the sub memory unit SMU ₁ and the first bit line BL ₁ is disconnected, and the sub memory unit S
Solving the connection between the common node CN ₂ and the second bit line BL ₂ for MU _2.

(5E) Next, the differential sense amplifier SA is activated to determine the data, read the data, and charge / discharge the first bit line BL ₁ and the second bit line BL ₂ .

Next, the selected memory cells (MC ₁₁ , M
Rewrite the data in C ₂₁ ).

(6E) At the start of data rewriting, the first selection transistor TR ₁ and the second selection transistor TR ₂ are off. Further, a high potential V _PL-H (= V _cc ) is applied to the plate line PL ₁ connected to the first and second selected memory cells MC ₁₁ and MC ₂₁ . In this state, the non-selected memory cells MC _1k, a first intermediate potential V connected to the plate line PL _k to MC _2k
PL-M1 [= (1/2) V _cc ] is applied. The data to be rewritten to the first selected memory cell MC ₁₁ is "1"
Therefore, the first bit line BL ₁ is at the high potential V _BL-H (=
V _cc ) and the data to be rewritten to the second selected memory cell MC ₂₁ is “0”, so that the second bit line BL ₂ is set to the low potential V _BL-L (= 0 volt). Has become.

(7E) Next, by setting the word line WL to high level, the first selection transistor TR _{1 is set.}
And a second transistor for selection TR ₂ is turned on,
The common node CN ₁ of the sub memory unit SMU ₁ is connected to the first bit line BL ₁ via the _first selection transistor TR _1, and the common node CN ₂ of the sub memory unit SMU ₂ is connected to the second bit line and BL ₂ second through the selection transistor TR ₂ is connected.

(8E) Thereafter, a low potential V _PL-L (= 0 volt) is applied to the selected plate line PL ₁ .

In step (6E), the first bit
Line BL₁High potential V_BL-H(= V_cc) Is applied
In the step (7E), the first selection transistor
TR ₁Is turned on, and the common node CN₁And the first bit
Line BL₁And the first selection transistor TR₁Contact through
When connected, select plate line PL₁High potential V_PL-H(=
V_cc) Is applied to the first selected memory cell
MC₁₁No data is written to. Then, step (8)
In E), the selection plate line PL₁Low potential V
_PL-L(= 0 volts), the first selected memory
Cell MC₁₁Is rewritten with data "1".

On the other hand, since the low potential V _BL-L is applied to the second bit line BL ₂ in the step (6E), the second selection transistor TR ₂ is turned on in the step (7E). , Common node CN ₂ and second bit line BL ₂
DOO When the connected second through the selection transistor TR _2, because the high-potential V _PL-H is applied to the selected plate line PL _1, the second selected memory cell MC ₂₁ data "0" Is rewritten. Thereafter, in the step (8E), the low potential V _PL-L (= 0 volt) is applied to the selected plate line PL ₁ , but the data “0” written in the second selected memory cell MC ₂₁ changes. There is no.

(9E) Next, the word line WL is set to low level.
As a result, the first selection transistor TR₁
And the second selection transistor TR_TwoTo the off state,
Common node CN₁, CN_TwoIn a floating state. At this time
Common node CN₁Of the first selected memory cell MC
₁₁Since data “1” is written in_BL-H(=
V _cc). On the other hand, the common node CN at this time_TwoNo electricity
The position is the second selected memory cell MC_{twenty one}Data "0" is written
V_BL-L(= 0 volts).

(10E) Next, the non-selected plate lines PL _k
Is applied with a second intermediate potential V _PL-M2 (= V _cc ). still,
Low potential V _PL-L (= 0 volt) is applied to selected plate line PL ₁
Is applied. As a result, the common nodes CN ₁ and CN ₂
And based on the capacitive coupling between the plate line PL _1, PL _k, the potential of the common node CN _1, CN ₂ in a floating state rises. Specifically, when M = 8, the increase in the potential of the common nodes CN ₁ and CN ₂ is about (１ ／) _Vcc .

[0162] Thus, the potential of the common node CN ₁ at this time, the first selected memory cells MC ₁₁ to the data "1" of is written, it is about (3/2) V _cc. Since the low potential V _PL-L (= 0 volt) is applied to the selected plate line PL ₁ , data “1” is strongly written to the selected memory cell MC ₁₁ . On the other hand, the potential of the common node CN ₂ at this time, the second selected memory cells MC ₂₁ to the data "0" is in written to is approximately (1/2) V _cc.

(11E) When the above operations are completed,
The non-selected plate line PL _k may be returned to V _PL-L (= 0 volt) to complete the rewriting operation. However, in order to smoothly perform the next access, the potential of the non-selected plate line PL _K is set to the first level. It is preferable to return to the intermediate potential V _PL-M1 [= (1/2) V _cc ].

(12E) Thereafter, the word line WL is set to the high level again to turn on the first selection transistor TR ₁ and the second selection transistor TR ₂ , and the common nodes CN ₁ and CN ₂ And the first and second bit lines BL ₁ , BL ₂ are connected via first and second selection transistors TR ₁ , TR ₂ to form common nodes CN ₁ , C 2
The potential of the N ₂ and 0 volts.

(13E) Finally, by setting the word line WL to low level, the first selection transistor T
R ₁ and the second selection transistor TR ₂ is turned off, solving the connection between the common node CN _1, CN ₂ and the first and second bit lines BL _1, BL _2, the non-selected plate line PL _k
To V _PL-L (= 0 volt) to complete the rewrite operation.

Thereafter, the memory cells (MC _1m , MC _2m ) (m
= 2,3... 8), sequentially from step (1E) to
Perform the operation of (13E).

In the above steps, the bit lines BL ₁ , BL ₁
The BL ₂ need only apply a V _BL-H or V _BL-L, an intermediate potential is also only V _PL-M that is applied to the non-selected plate line PL _k. Moreover, the disturbance is ± (1/2) V _cc ,
In spite of no difference from the conventional driving method, data “1” can be written more strongly than the conventional driving method.

When writing new data, in the step (6E), the low potential V _BL-L (= 0 volt) or the low potential V _{BL-L is applied} to the first bit line BL ₁ depending on the data to be written. A high potential V _BL-H (= V _cc ) is applied, and a high potential V _BL-H (= V _cc ) or a low potential V _BL-L is applied to the second bit line BL _2.
(= 0 volts). Then, from step (6E)
The operation of (13E) may be performed.

Further, the driving method described in the third embodiment can be applied to the driving method having the second configuration in the fifth embodiment.

(Embodiment 6) In Embodiment 6,
Is the same as that described in the fourth or fifth embodiment.
5 shows a modification of the volatile memory. Non-volatile of Embodiment 6
The memory is a first memory unit constituting a non-volatile memory.
MU₁And the nonvolatile memory and the first bit line B
L₁A non-volatile memory adjacent in the direction in which
First memory unit MU '₁And the interlayer insulating layer 26
Second memory which forms a nonvolatile memory by stacking through
Unit MU_TwoAnd the nonvolatile memory and the second bit
Line BL_TwoNonvolatile memory adjacent in the direction in which
First memory unit MU '₁And the interlayer insulating layer 2
6 are laminated. Embodiment 6
FIG. 11 is a schematic partial cross-sectional view of the nonvolatile memory shown in FIG.
You. However, in FIG. 11, the first memory unit M
U₁, MU '₁Only illustrated. Second memory unit M
U _Two, MU '_TwoAre adjacent to each other in the direction perpendicular to the paper of FIG.
You. Note that the first memory unit MU '₁The components of
The reference numerals to be referred to are denoted by “′”.

More specifically, in the nonvolatile memory shown in FIG. 11, an element isolation formed of a LOCOS structure, a shallow trench structure, or a combination of a LOCOS structure and a shallow trench structure formed on a p-type silicon semiconductor substrate 10. In the active region surrounded by the region 11, selection transistors TR ₁ and TR ′ ₁ each formed of a MOS FET are formed. The selection transistors TR ₁ and TR ′ ₁ are:
A gate insulating film 12 made of, for example, a silicon oxide film formed on the surface of the silicon semiconductor substrate 10, and a gate electrode 13 (word line WL ₁ ,
WL ' ₁ ) and silicon semiconductor substrate 1
The source / drain regions 14A and 14B are formed in the active region 0 and contain n ⁺ -type impurities.

Then, a bit line BL ₁ is formed on a lower insulating layer formed on the entire surface, and the bit line BL ₁ is connected to a selection transistor via a contact hole (contact hole) 15 formed in the lower insulating layer. TR _1, is connected to one of source / drain regions 14A of TR _'1. Further, the upper insulating layer is formed on the lower insulating layer including the bit line BL _1. In the drawings, the lower insulating layer and the upper insulating layer are collectively represented as an insulating layer 16. Also, the bit line BL ₁
11 extend in the left-right direction of FIG. 11 so as not to contact a connection hole (contact hole) 18 described later.

On the insulating layer 16, a first electrode (lower electrode)
21, a ferroelectric layer 22 is formed on the first electrode 21, and a second electrode (upper electrode) is formed on the ferroelectric layer 22.
23 are formed, and these constitute a memory cell _MC1M . The first electrode 21 is common to the memory cells _MC1M and has a stripe-shaped planar shape. The first electrode 21 is connected to the other source / drain region 14B of the selection transistor TR ₁ through a connection hole 18 provided in the opening 17 formed in the insulating layer 16. Incidentally, the common first electrode 21, shown at a common node CN _1. The ferroelectric layer 22 is formed in substantially the same pattern as the second electrode 23.

Further, on the memory cell MC _1M and the insulating layer 16, an interlayer insulating layer 26 is formed. Then, a first electrode (lower electrode) 21 'is formed on the interlayer insulating layer 26, a ferroelectric layer 22' is formed on the first electrode 21 ', and a first electrode (lower electrode) 21' is formed on the ferroelectric layer 22 '. 2 electrodes (upper electrode) 2
3 'is formed, the memory cell MC by these' _1M is constructed. The first electrode 21 'is connected to the memory cell M
It is common to C ′ _1M and has a stripe-shaped planar shape. The first electrode 21 ′ is formed in the connection hole 28 provided in the opening 27 formed in the interlayer insulating layer 26, the pad portion 25 formed on the insulating layer 16, and the insulating layer 16. and through the connection hole 18 provided in the opening 17, it is connected to the other of the source / drain region 14B of the selection transistor TR _'1. Note that 'a common node CN' common first electrode 21 shown in _1. Ferroelectric layer 2
2 'is formed in substantially the same pattern as the second electrode 23'. Further, an upper insulating layer 36A is formed on the memory cell _MC'1M and the interlayer insulating layer 26.

The word lines WL ₁ and WL ′ ₁ extend in the direction perpendicular to the plane of FIG. Also, the second electrodes 23, 23 '
Is a memory cell M adjacent to the memory cell M in FIG.
It is common to C _2m and MC ′ _2m and also serves as the plate line PL _m . The memory cell MC _1M and the memory cell MC ′ _1M
And are aligned in the vertical direction. With such a structure, the area occupied by the memory cells can be reduced, and the degree of integration can be improved.

(Embodiment 7) Embodiment 7 also shows a modification of the nonvolatile memory described in Embodiment 4 or 5. 12 and 13 show circuit diagrams of the nonvolatile memory according to the seventh embodiment, and FIG. 14 shows a schematic partial cross-sectional view. Note that, in the nonvolatile memory configured from the circuit diagram illustrated in FIG. 12, the driving method according to the first configuration (see Embodiment 4) can be executed, and the nonvolatile memory configured from the circuit diagram illustrated in FIG. In the nonvolatile memory described above, the driving method according to the second configuration (Embodiment 5)
See). In the nonvolatile memory whose circuit diagram is shown in FIG.
Selection transistor TR connected to MU ₁₁ and SMU _21
11 and the gate electrode of TR ₂₁ are connected to the word line WL ₁
And the gate electrodes of the selection transistors TR ₁₂ and TR ₂₂ connected to the sub memory units SMU ₁₂ and SMU ₂₂ are connected to the word line WL ₂ .
On the other hand, in the nonvolatile memory whose circuit diagram is shown in FIG. 13, the sub memory units SMU ₁₁ , SMU ₁₂ , SM
U ₂₁ and selection transistor T connected to SMU ₂₂
Each of the gate electrodes of _{R 11, TR 12, TR 21} , TR 22, is connected to the word line _{WL 11, WL 12, WL 21} , WL 22.

The nonvolatile memory according to the seventh embodiment includes (A-
1) and the first bit line BL _1, (B-1) N pieces (however,
N ≧ 1, and in the seventh embodiment, specifically, N =
2) the first selection transistor TR _1N and (C-1)
Each of the M first memory cells MC _1nM (where M ≧ 2 and M = 8 in the seventh embodiment) (n = 8)
N, where N ≧ 2
In the seventh embodiment, N = 2) first sub memory units SMU _1N and (D-1) N first memory cells MC _1nm forming _N sub memory units SMU _1N respectively. A _first memory unit MU ₁ composed of M plate lines PL _m shared by (m = 1, 2,... M), and (A-2) a second bit line BL ₂ ;
(B-2) N second selection transistors TR _2N ,
(C-2) M second memory cells MC _{2nM each}
N second sub-memory units SM
U _2N and (D-2) N sub memory units SMU _2N
Is the common second memory cell MC _2nm constituting each, and consists of the first of the M constituting the memory unit MU ₁ and the plate line PL _m common M plate lines PL _m, and a second memory unit MU _2.

In the schematic partial cross-sectional view of FIG. 14, these second bit line BL ₂ , second selection transistors TR ₂₁ and TR ₂₂ and second memory unit MU are shown.
₂ is adjacent to the first bit line BL ₁ , the first selection transistors TR ₁₁ , TR _12, and the first memory unit MU ₁ in the direction perpendicular to the paper.

Then, each memory cell MC_1nm(m = 1, 2
... M, n = 1, 2,.
In state 7, m = 1, 2,... 8, n = 1, 2)
Are first electrodes (lower electrodes) 21 and 31 and a ferroelectric layer
22, 32 and second electrodes (upper electrodes) 23, 33
Consisting of Then, the first memory unit MU₁smell
And the n-th (where n = 1, 2,... N) first
Memory unit SMU _1nFirst memory cell constituting
MC_1nmOf the first electrodes 21 and 31 of the
Sub memory unit SMU_1nAre common in
First electrodes 21 and 31 (common node CN)_1nPlace to call
) Is the n-th first selection transistor T
R_1nVia the first bit line BL₁Connected to the second
The electrodes 23 and 33 are connected to a common plate line PL._mConnected to
I have. On the other hand, the second memory unit MU_TwoIn the
n-th second sub-memory unit SMU_2nMake up
Second memory cell MC_2nmOf the first electrodes 21 and 31
N-th second sub-memory unit SMU_2nAt
Common, and the common first electrodes 21 and 31 (common node)
De CN_2n) Is the n-th second choice
Transistor TR_2nVia the second bit line BL_TwoTo
And the second electrodes 23 and 33 are connected to a common plate line P
L_mIt is connected to the.

Incidentally, the number of memory cells constituting the memory unit of the non-volatile memory is not limited to eight.
The number can be 2 × M (where M = 1, 2, 3,...). However, the value of M may be 2 or more, and for example, is preferably a power of 2 (2, 4, 8, 16,...).

The memory cells MC _11m , MC _12m , MC _21m ,
The plate line PL _m in the MC _22m is shared,
It is connected to a plate line decoder / driver PD.
Furthermore, the gate electrode of the first transistor for selection TR ₁₁ is the gate electrode of the second transistor for selection TR ₂₁ is connected to the word line WL _1, a first selection transistor TR
The gate electrode and the gate electrode of the second selection transistor TR ₂₂ of ₁₂ is connected to the word line WL _2, the word line WL _1,
WL ₂ is connected to a word line decoder / driver WD. Further, the first bit line BL ₁ and the second bit line BL ₂ are connected to a differential sense amplifier SA.

In the nonvolatile memory according to the seventh embodiment, each of first sub memory units SMU ₁₁ and SMU ₁₂ constituting _first memory unit MU ₁ is stacked with interlayer insulating layer 26 interposed therebetween. Second sub memory unit SM forming _second memory unit MU ₂
Each of U ₂₁ and SMU ₂₂ is laminated via an interlayer insulating layer 26. That is, the first sub memory unit SMU ₁₁ and the second sub memory unit SMU ₁₂ constituting the _first memory unit MU ₁ are stacked via the interlayer insulating layer 26. Furthermore, the first sub memory unit SMU constituting the _second memory unit MU _2
21 and the second sub memory unit SMU ₂₂ are also stacked via an interlayer insulating layer 26. Thus, high integration of the nonvolatile memory can be achieved.

Since the driving method of the nonvolatile memory of the seventh embodiment can be the same as that described in the fourth or fifth embodiment, a detailed description is omitted.

The details of the nonvolatile memory of the seventh embodiment will be described below. In the following description, a description will be given of a first memory unit MU _1, the second memory unit MU ₂ has the same structure.

More specifically, in the nonvolatile memory shown in FIG. 14, an element isolation formed of a LOCOS structure, a shallow trench structure, or a combination of a LOCOS structure and a shallow trench structure formed on a p-type silicon semiconductor substrate 10 is used. In the active region surrounded by the region 11, the first selection transistors TR ₁₁ and TR
₁₂ are formed. First selection transistor T
R ₁₁ and TR ₁₂ are gate insulating films 1 formed on the surface of the silicon semiconductor substrate 10 and made of, for example, a silicon oxide film.
2. Gate electrode 13 formed on gate insulating film 12
(Also serving as word lines WL ₁ and WL ₂ ) and source / drain regions 14 A and 14 B formed in the active region of the silicon semiconductor substrate 10 and containing n ⁺ -type impurities.

Then, a bit line BL ₁ is formed on a lower insulating layer formed on the entire surface, and the bit line BL ₁ is connected to a selection transistor via a contact hole (contact hole) 15 formed in the lower insulating layer. It is connected to one of source / drain regions 14A of TR _11, TR _12. Further, the upper insulating layer is formed on the lower insulating layer including the bit line BL _1. In the drawings, the lower insulating layer and the upper insulating layer are collectively represented as an insulating layer 16. Also, the bit line BL ₁
Extend in the left-right direction of FIG. 14 so as not to contact a connection hole (contact hole) 18 described later.

On the insulating layer 16, a first electrode (lower electrode)
21, a ferroelectric layer 22 is formed on the first electrode 21, and a second electrode (upper electrode) is formed on the ferroelectric layer 22.
23 are formed, and these constitute a memory cell MC _11M . Further, the first sub-memory unit SM
U ₁₁ is configured. The first electrode 21 is common to the memory cells _MC11M and has a stripe-shaped planar shape. The first electrode 21, the other source / drain region 14 of the selection transistor TR ₁₁ via the contact hole 18 provided in the opening 17 formed in the insulating layer 16
B. Incidentally, the common first electrode 21, shown at a common node CN _11. The ferroelectric layer 22 is formed in substantially the same pattern as the second electrode 23.

Further, on the memory cell MC _11M (sub-memory unit SMU ₁₁ ) and the insulating layer 16, an interlayer insulating layer 2
6 are formed. Then, a first electrode (lower electrode) 31 is formed on the interlayer insulating layer 26, and the first electrode 31 is formed.
A ferroelectric layer 32 is formed thereon, and a second electrode (upper electrode) 33 is formed on the ferroelectric layer 32, and these constitute a memory cell _MC12M. A unit SMU ₁₂ is configured. The first electrode 31 is common to the memory cells _MC12M and has a stripe-shaped planar shape. And the first electrode 31
A connection hole 28 provided in an opening 27 formed in the interlayer insulating layer 26, a pad portion 25 formed on the insulating layer 16;
And, via the connecting hole 18 provided in the opening 17 formed in the insulating layer 16, and is connected to the other source / drain region 14B of the selection transistor TR _12.
Incidentally, the first electrode 31 of the common, indicated by a common node CN _12. The ferroelectric layer 32 is formed in substantially the same pattern as the second electrode 33. Further, an upper insulating layer 36A is formed on the memory cell MC _12M and the interlayer insulating layer 26.

The word lines WL ₁ and WL ₂ extend in the direction perpendicular to the plane of FIG. In addition, the second electrode 23 is provided in FIG.
Of the second memory unit MU ₂ adjacent to the second memory unit
A common memory cell MC _21m of the first sub-memory unit SMU ₂₁ constituting the also serves as a plate line PL _m. Further, the second electrode 33 is also connected to the memory cell M of the second sub memory unit SMU ₂₂ constituting the _second memory unit MU ₂ adjacent in the direction perpendicular to the plane of FIG.
C _22m and are common also serves as a plate line PL _m. These plate lines PL _m shared by the memory cells MC _11m , MC _12m , MC _21m , and MC _22m extend in the direction perpendicular to the plane of FIG. 14 and are connected via connection holes in a region (not shown). I have. The memory cells _MC11M and _MC12M are aligned in the vertical direction. With such a structure, the area occupied by the memory cells can be reduced, and the degree of integration can be improved.

Then, by writing complementary data to the memory cells MC _{1 nm} and MC _{2 nm} sharing the plate line PL _m , one bit can be stored in each of them, or one bit can be stored in each of them. can do. That is, the four selection transistors TR _{11 to} TR ₂₂
And 32 memory cells MC _{1 nm} and MC _{2 nm}
One memory unit (access unit unit) is configured to store 32 bits (see the circuit diagram of FIG. 13) or 16 bits (see the circuit diagram of FIG. 12).

(Eighth Embodiment) In the eighth embodiment,
Are the same as those described in the fourth or fifth embodiment.
5 shows a modification of the volatile memory. Implemented in FIGS. 16 and 17
FIG. 15 shows a circuit diagram of the nonvolatile memory according to the eighth embodiment, and FIG.
1 shows a schematic partial sectional view. Incidentally, from the circuit diagram shown in FIG.
In the configured nonvolatile memory, the nonvolatile memory according to the first configuration is used.
Drive method (see Embodiment 4) can be executed.
And a nonvolatile memory configured from the circuit diagram shown in FIG.
In the driving method according to the second configuration (Embodiment 5)
See). The circuit diagram is shown in FIG.
In the nonvolatile memory shown, the sub memory unit S
MU₁₁, SMU_{twenty one}Selection transistor TR connected to
₁₁, TR_{twenty one}Each of the gate electrodes of the word lines WL₁To
Connected, sub-memory unit SMU₁₂, SMU_{twenty two}Contact
Continued selection transistor TR₁₂, TR_{twenty two}Gate power
Each of the poles is a word line WL_TwoConnected to the sub memory
Unit SMU₁₃, SMU_{twenty three}Selection transformer connected to
Jista TR₁₃, TR_{twenty three}Each of the gate electrodes of the word
Line WL_ThreeAnd the sub memory unit SMU₁₄, S
MU_{twenty four}Selection transistor TR connected to₁₄, TR_{twenty four}
Each of the gate electrodes of the word lines WL_FourConnected to
I have. On the other hand, the nonvolatile memory shown in the circuit diagram of FIG.
And the sub memory unit SMU₁₁, SMU₁₂, SM
U₁₃, SMU₁₄, SMU_{twenty one}, SMU _{twenty two}, SMU_{twenty three}, SM
U_{twenty four}Selection transistor TR connected to₁₁, TR₁₂,
TR ₁₃, TR₁₄, TR_{twenty one}, TR_{twenty two}, TR_{twenty three}, TR_{twenty four}No
Each of the gate electrodes is connected to a word line WL.₁₁, WL₁₂, WL
₁₃, WL₁₄, WL_{twenty one}, WL_{twenty two}, WL_{twenty three}, WL_{twenty four}Connected to
Have been. In FIGS. 16 and 17, the first video
Line BL₁And the second bit line BL_TwoConnected differential
Illustration of the sense amplifier SA is omitted.

In the nonvolatile memory of the eighth embodiment, four sub memory units SMU ₁₁ , SMU ₁₂ , SMU ₁₃ , SMU ₁₄ constituting _first memory unit MU ₁ have four memory units.
Stacked in tiers. Although not shown, the sub memory unit SMU constituting the _second memory unit MU _2
21 , SMU ₂₂ , SMU ₂₃ , and SMU ₂₄ are also stacked in four layers.

The nonvolatile memory according to the eighth embodiment has the structure (A-
1) First bit line BL₁And (B-1) N (however,
N ≧ 1, and in the eighth embodiment, specifically, N =
4) First selection transistor TR_1N(TR₁₁, TR
₁₂, TR₁₃, TR₁₄) And (C-1) each M
(However, M ≧ 2, and in the eighth embodiment, M =
8) First memory cell MC_1nM(MC_11M, MC_12M,
MC_13M, MC_14M) Consisting of N first sub-
Memory unit SMU_1N(SMU₁₁, SMU ₁₂, SMU
₁₃, SMU₁₄) And (D-1) N sub-memory units.
SMU_1nOf the first memory cell MC configuring each of
_1nm(MC_11m, MC_12m, MC_12m, MC_14m) And common
M plate lines PL_m, A first memory consisting of
Unit MU₁And (A-2) the second bit line B
L_TwoAnd (B-2) N second selection transistors T
R_2N(TR_{twenty one}, TR_{twenty two}, TR_{twenty three}, TR_{twenty four}) And (C-
2) Each of the M second memory cells MC_2nM(MC
_21M, MC_22M, MC_23M, MC_24MN)
Second sub-memory units SMU_2N(SMU_{twenty one}, S
MU_{twenty two}, SMU_{twenty three}, SMU_{twenty four}) And (D-2) N
Memory unit SMU_2nOf each of the second
Memory cell MC_2nm(MC_21m, MC_22m, MC_22m, MC
_24m) And the first memory unit
M plate lines common to the M plate lines constituting
PL_m, A second memory unit MU comprising_TwoComposed of
Have been.

That is, the nonvolatile memory of Embodiment 8
The sub memory unit constituting the memory unit has a four-layer configuration. The number of memory cells forming the sub memory unit is not limited to eight, and the number of memory cells forming the memory unit is not limited to 32.

Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. Specifically, each of the memory cell MC _11M and the memory cell MC _21M
, A ferroelectric layer 22, and a second electrode 23. Further, the memory cell MC _12M and the memory cell MC
Each of _22M has a first electrode 31 and a ferroelectric layer 32.
And a second electrode 33. Further, the memory cell M
Each of the C _13M and the memory cell MC _23M includes a first electrode 41, a ferroelectric layer 42, and a second electrode 43. Each of the memory cells _MC14M and _MC24M includes a first electrode 51, a ferroelectric layer 52, and a second electrode 53.

[0196] In the first memory unit MU _1, the first electrode of the first memory cell MC _1nm constituting the n-th first sub-memory unit SMU _1n of (n = 1,2 ··· N) 21, 31, 41, 51 are common to the n-th first sub-memory unit SMU _1n , and the common first electrodes 21, 31, 41, 51 are connected to the n-th first selection unit. the first is connected to the bit line BL ₁ via the use transistor TR _1n, the second electrode 23,33,43,5
3 are connected to a common plate line PL _m.

In the second memory unit MU ₂ , the first electrodes 21, 31, 4 of the second memory cell MC _{2 nm} constituting the n-th second sub memory unit SMU _{2 n}
1, 51 are the n-th second sub memory unit SM
U _{2n and} the common first electrodes 21 and 3
1,41,51 is connected to the second bit line BL ₂ through the n-th second transistor for selection TR _2n, the second electrode 23,33,43,53 common plate line P
It is connected to L _m.

More specifically, in the nonvolatile memory shown in FIG. 15, an element isolation formed of a LOCOS structure, a shallow trench structure, or a combination of a LOCOS structure and a shallow trench structure formed on a p-type silicon semiconductor substrate 10 is used. In the active region surrounded by the region 11, the first selection transistors TR ₁₁ and TR
_12, TR _13, TR ₁₄ are formed. The first selection transistors TR ₁₁ , TR ₁₂ , TR ₁₃ , and TR ₁₄ are formed on the gate insulating film 12 made of, for example, a silicon oxide film, and formed on the surface of the silicon semiconductor substrate 10. The gate electrode 13 (word lines WL ₁ , WL ₂ ,
WL ₃ , WL ₄ ) and source / drain regions 14A and 14B formed in the active region of the silicon semiconductor substrate 10 and containing n ⁺ -type impurities.

Then, on the lower insulating layer formed on the entire surface,
Bit line BL₁Is formed, and the bit line BL₁Is the lower insulation
Through the connection hole 15 formed in the layer, the first and second
-Th first selection transistor TR₁₁, TR₁₂One of
Source / drain regions 14A, and third and
Fourth first selection transistor TR₁₃, TR ₁₄of
It is connected to one source / drain region 14A.
Also, the bit line BL ₁Upper insulation on the lower insulation layer containing
A layer is formed. Bit line BL₁Is the connection
Extending in the left-right direction of FIG.
I have.

On the insulating layer 16, a first electrode (lower electrode)
21, a ferroelectric layer 22 is formed on the first electrode 21, and a second electrode (upper electrode) is formed on the ferroelectric layer 22.
23 are formed, these form a memory cell MC _11M , and form a sub-memory unit SMU ₁₁ . The first electrode 21 is common to the sub-memory unit SMU _11, having a stripe-shaped planar shape. The first electrode 21, the other source / drain region 1 of the first selection transistor TR ₁₁ via the contact hole 18 provided in the opening 17 formed in the insulating layer 16
4B. Note that the common first electrode 21 is
It is shown by the common node CN _11. The ferroelectric layer 22 is formed in substantially the same pattern as the second electrode 23.

Further, a first interlayer insulating layer 26 is formed on sub memory unit SMU ₁₁ and insulating layer 16. Then, a first electrode (lower electrode) 31 is formed on the first interlayer insulating layer 26, a ferroelectric layer 32 is formed on the first electrode 31, and a second electrode (lower electrode) 31 is formed on the ferroelectric layer 32. (Upper electrode) 33 are formed, and these constitute a memory cell MC _12M and a sub memory unit SMU ₁₂ . The first electrode 31 is common to the memory cells _MC12M and has a stripe-shaped planar shape. And the first
The electrode 31 has a connection hole 28 provided in an opening 27 formed in the first interlayer insulating layer 26, a pad portion 25 formed on the insulating layer 16, and an opening formed in the insulating layer 16. through a connection hole 18 provided in the part 17, and is connected to the second other source / drain region 14B of the selection transistor TR _12. Incidentally, the common first electrode 3
1 shows a common node CN _12. The ferroelectric layer 32 is formed in substantially the same pattern as the second electrode 33.

Further, a second interlayer insulating layer 36 is formed on the sub memory unit SMU ₁₂ and the first interlayer insulating layer 26. Then, a first electrode (lower electrode) 41 is formed on the second interlayer insulating layer 36, and the first electrode 41 is formed.
Are ferroelectric layer 42 is formed thereon, strong second electrode (upper electrode) 43 is formed on the dielectric layer 42, the memory cell MC _13M, the sub-memory unit SMU ₁₃ is constituted by these. The first electrode 41 is connected to the memory cell MC _13M
And has a stripe planar shape. The first electrode 41 includes a connection hole 38 provided in an opening 37 formed in the second interlayer insulating layer 36, a pad portion 35 formed on the first interlayer insulating layer 26, A connection hole 28 provided in an opening 27 formed in the interlayer insulating layer 26, a pad portion 25 formed on the insulating layer 16, and
Through a connection hole 18 provided in an opening 17 formed in the insulating layer 16, a third selection transistor TR ₁₃
Is connected to the other source / drain region 14B. Incidentally, the first electrode 41 of the common, indicated by a common node CN _13. The ferroelectric layer 42 is formed in substantially the same pattern as the second electrode 43.

Further, on the sub memory unit SMU ₁₃ and the second interlayer insulating layer 36, a third interlayer insulating layer 46 is formed. Then, a first electrode (lower electrode) 51 is formed on the third interlayer insulating layer 46, and the first electrode 51 is formed.
A ferroelectric layer 52 is formed thereon, and a second electrode (upper electrode) 53 is formed on the ferroelectric layer 52. These form a memory cell MC _14M and a sub memory unit S
The MU ₁₄ is configured. The first electrode 51 is common to the memory cells _MC14M and has a stripe-shaped planar shape. The first electrode 51 is formed on the third interlayer insulating layer 4.
6, a connection hole 48 provided in an opening 47 formed in
Pad portion 45 formed on second interlayer insulating layer 36, connection hole 38 provided in opening 37 formed in second interlayer insulating layer 36, formed on first interlayer insulating layer 26 Pad portion 35, connection hole 28 provided in opening 27 formed in first interlayer insulating layer 26, pad portion 25 formed on insulating layer 16, and opening formed in insulating layer 16. through a connection hole 18 provided in the part 17, it is connected to the other of the source / drain region 14B of the fourth transistor for selection TR _14. In addition, the common first electrode 5
1, it may be referred to as the common node CN _14. The ferroelectric layer 52 is formed in substantially the same pattern as the second electrode 53. Further, an upper insulating layer 56A is formed on the memory cell MC _14M and the third interlayer insulating layer 46.

[0204] Word line WL₁, WL_Two, WL_Three, WL_FourIs
It extends in the direction perpendicular to the plane of FIG. Also, the second electrode
Reference numeral 23 denotes a memory cell M adjacent in the direction perpendicular to the paper of FIG.
C_{twenty one m}And the plate line PL_mAlso serves as. Change
In addition, the second electrodes 33, 43, 53 are also perpendicular to the paper of FIG.
Memory cell MC immediately adjacent to_22m, MC_23m, MC
_24mAnd the plate line PL_mAlso serves as. Each method
Morisel MC_11m, MC_{1 2m}, MC_13m, MC_14m, MC
_21m, MC_22m, MC_23m, MC_24mThese shared by
Each plate line PL_mExtends in the direction perpendicular to the plane of FIG.
And are connected via connection holes in an area (not shown).
ing. Also, the memory cell MC_11MAnd memory cell MC_12M
And memory cell MC_13MAnd memory cell MC_14MIs vertical
It is aligned. With such a structure,
The occupied area of the molycell can be further reduced,
The degree of integration can be further improved.

In this nonvolatile memory, the first
Selection transistor TR₁₁, TR _{twenty one}Is the word line WL₁
, The second selection transistor TR
₁₂, TR_{twenty two}Is the word line WL_TwoConnected to the third
Eye selection transistor TR_{1 Three}, TR_{twenty three}Is the word line WL
_ThreeAnd the fourth selection transistor T
R₁₄, TR_{twenty four}Is the word line WL_FourIt is connected to the.

[0206] Then, the plate line PL _m memory cells MC _11m which share, MC _21m, the plate line PL _m memory cells MC _12m which share, MC _22m, MC shared plate line PL _{m 13m,} MC _23m, the plate line By writing complementary data to the memory cells MC _14m and MC _24m sharing the PL _m , one bit is stored in each of them. The structure of the second selection transistors TR ₂₁ , TR ₂₂ , TR ₂₃ , TR ₂₄ and the memory cells MC _{21 m} , MC _22m , MC _23m , MC _24m
Is the same as the structure shown in FIG. 15, and is adjacent in the direction perpendicular to the plane of FIG. Moreover, eight of the selection transistor _{TR 11 ~TR 14, TR 21 ~TR} 24, 64 memory cells MC _11m to MC _14m, the MC _21m to MC _24m, 1 single memory unit (access units) is configured , 32 bits (see FIG. 16) or 64 bits (see FIG. 17).

The word lines WL ₁ , WL ₂ , WL ₃ , WL ₄ are connected to a word line decoder / driver WD. The bit lines BL ₁ and BL ₂ are connected to a differential sense amplifier (not shown). Further, the plate line PL
_m is connected to the plate line decoder / driver PD.

In an actual nonvolatile memory, this 3
A set of nonvolatile memories storing 2 bits or 64 bits is arranged in an array as an access unit.

Ninth Embodiment A nonvolatile memory according to the ninth embodiment is a modification of the nonvolatile memory according to the eighth embodiment. Nonvolatile memory in Example 9 is different from the non-volatile memory of the eighth embodiment, the memory cells of the first sub-memory unit SMU ₁₁ MC _11m and second memory cell sub-memory unit SMU ₁₂ the second electrode (plate line) is shared by MC _12m, a second electrode in the third sub-memory unit SMU ₁₃ memory cells MC _13m and the memory cells MC _14m in the fourth sub-memory unit SMU ₁₄ (Plate line) is common.
Further, the memory cell MC _21m of the first sub-memory unit SMU ₂₁ and the second sub-memory unit SMU ₂₂
Of the second electrode in the memory cell MC _22m (plate line) is the common, third sub-memory unit memory cell MC _23m and fourth sub-memory unit SM of SMU ₂₃
Second electrode in the memory cell MC _24m of U ₂₄ (plate line)
Is common.

The nonvolatile memory according to the ninth embodiment, whose partial cross-sectional view is schematically shown in FIG. 18, has a memory cell MC _11m (first electrode 21A, ferroelectric layer 22A, and second electrode 23). m = 1, 2, 3,
· A 7,8, _{specifically, MC 111, MC 11 2,} M
C ₁₁₃ ... MC ₁₁₇ and MC _118, which are sub memory units SMU ₁₁ ), and a memory cell MC _12m (m = 1) including a first electrode 21B, a ferroelectric layer 22B, and a second electrode 23. , 2,3 ・
· A 7,8, _{specifically, MC 121, MC 12 2,} M
MC _123, MC ₁₂₇ , MC ₁₂₈ and the sub-memory unit SMU ₁₂ ), a memory cell MC _13m (m = 1) including a first electrode 31A, a ferroelectric layer 32A, and a second electrode 33 , 2,3 ・
· A 7,8, _{specifically, MC 131, MC 13 2,} M
C ₁₃₃ · · · MC _137, an MC _138, a sub-memory unit SMU _13), and a first electrode 31B and the ferroelectric layer 32B and the memory cell MC _14m consisting of the second electrode 33 (m = 1,2,3
· A 7,8, _{specifically, MC 141, MC 14 2,} M
C ₁₄₃ ... MC ₁₄₇ , MC ₁₄₈ and the sub memory unit SMU ₁₄ ).

That is, the nonvolatile memory of Embodiment 9
Each memory unit has a four-layer sub memory unit. Note that the number of memory cells constituting the memory unit is not limited to eight, and the number of memory cells constituting the nonvolatile memory is not limited to 32.

Selection transistor TR₁₁, TR₁₂, TR
₁₃, TR₁₄, TR_{twenty one}, TR_{twenty two}, TR _{twenty three}, TR_{twenty four}Structure of
Shows the configuration of the nonvolatile memory described in the eighth embodiment.
Since it is the same as the structure, detailed description is omitted.

The first electrode 21 is formed on the insulating layer 16.
A is formed, and a ferroelectric layer 22A is formed on the first electrode 21A.
Are formed, and a second electrode 23 is formed on the ferroelectric layer 22A, thereby forming the memory cell _MC11M . The first electrode 21A is common to the memory cells _MC11M and has a stripe-shaped planar shape. And
The first electrode 21 </ b> A is formed in the opening 1 formed in the insulating layer 16.
Through a connection hole 18 provided in 7 it is connected to the other of the source / drain region 14B of the selection transistor TR _11. The ferroelectric layer 22A is formed in substantially the same pattern as the second electrode 23.

Furthermore, the memory cell MC _11M and the insulating layer 16
A ferroelectric layer 22B is formed thereon, and a first
Electrode 21B is formed. And the first electrode 2
1B, the ferroelectric layer 22B and the second electrode 23 constitute a memory cell _MC12M . First electrode 21B
_Are common to the memory cells _MC12M and have a stripe-shaped planar shape. The first electrode 21B is connected to the connection hole 1 provided in the opening 17 formed in the insulating layer 16.
8 through, and is connected to the other source / drain region 14B of the selection transistor TR _12. Ferroelectric layer 2
2B is formed in substantially the same pattern as the first electrode 21B.

Further, the memory cell MC _12M and the insulating layer 16
An interlayer insulating layer 26 is formed thereon. Then, a first electrode 31A is formed on the interlayer insulating layer 26,
A ferroelectric layer 32A is formed on the electrode 31A, and a second electrode 33 is formed on the ferroelectric layer 32A. These constitute a memory cell _MC13M . The first electrode 31A is common to the memory cells _MC13M and has a stripe-shaped planar shape. Then, the first electrode 31A
Are the connection holes 28 provided in the openings 27 formed in the interlayer insulating layer 26, and the pad portions 2 formed on the insulating layer 16
5 and a connection transistor 18 provided in an opening 17 formed in the insulating layer 16 through the selection transistor TR _21.
Is connected to the other source / drain region 14B. The ferroelectric layer 32 </ b> A is formed in substantially the same pattern as the second electrode 33.

Further, a ferroelectric layer 32B is formed on the memory cell _MC13M and the interlayer insulating layer 26, and a first electrode 31B is formed thereon. The first electrode 31B, the ferroelectric layer 32B and the second electrode 33 constitute a memory cell _MC14M . First electrode 3
1B is common to the memory cells _MC14M and has a stripe-shaped planar shape. And the first electrode 31B is
A connection hole 28 provided in an opening 27 formed in the interlayer insulating layer 26, a pad portion 25 formed on the insulating layer 16;
And, via the connecting hole 18 provided in the opening 17 formed in the insulating layer 16, and is connected to the other source / drain region 14B of the selection transistor TR _22. The ferroelectric layer 32B is formed in substantially the same pattern as the first electrode 31B. Further, an upper insulating layer 36A is formed on the memory cell MC _14M and the interlayer insulating layer 26.

The memory cells MC _11M , MC _12M , MC _13M, and MC _14M are aligned in the vertical direction. With such a structure, the area occupied by the memory cells can be further reduced, and the degree of integration can be further improved.

The memory unit MU_TwoIs the same as
can do. Ninth Non-volatile Memory of Embodiment 9
The road map is the same as that shown in FIG. 16 or FIG. Change
Has a word line WL₁~ WL_FourOr the word line WL
₁₁~ WL_{twenty four}, Plate line PL _mStructure of Embodiment 8
Can be substantially the same as
Omitted.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these embodiments. The structure of the nonvolatile memory, the materials used, the various forming conditions, the circuit configuration, the driving method, and the like described in the embodiment of the invention are merely examples, and can be changed as appropriate. For example, as shown in FIG. 19, as a modified example of the nonvolatile memory of the sixth embodiment, the first electrode 21 can be an upper electrode and the second electrode 23 can be a lower electrode. Such a structure can be applied to the non-volatile memory according to another embodiment of the present invention. In FIG. 19, reference numerals 126A and 126B indicate a lower layer and an upper layer of the first interlayer insulating layer, respectively, and reference numerals 136A and 136B indicate
The lower and upper layers of the upper insulating layer are shown, respectively.

A modification of the nonvolatile memory described in the fourth or fifth embodiment is shown in a schematic partial sectional view of FIG. In this nonvolatile memory, the first
The first sub-memory unit SMU ₁₁ constituting the memory unit MU ₁ (memory cell MC _11M), SMU ₁₂ second sub-memory unit SMU ₂₁ constituting the (memory cell MC _12M) and the second memory unit MU ₂ Each of (memory cell MC _21M ) and SMU ₂₂ (memory cell MC _22M ) are stacked via interlayer insulating layers 26, 36, 46. Except for this point, the structure of this non-volatile memory can be the same as the structure of the non-volatile memory described in the fourth or fifth embodiment, and a detailed description thereof will be omitted. Note that such a structure can be applied to the nonvolatile memory described in the other embodiments.

Further, similarly to a so-called flash memory, memory cells connected to a plate line can be rewritten collectively. In this case, the reading operation is omitted, and the operation can be simplified and the rewriting can be speeded up. That is, data "0" may be once written to all memory cells in the memory unit, and then data "1" may be written to predetermined memory cells.

The ferroelectric layer may have substantially the same planar shape as the first electrode and may be formed so as to cover the first electrode, depending on the method of manufacturing the nonvolatile memory. Alternatively,
A configuration in which the ferroelectric layer is not patterned may be adopted.

[0223]

According to the method of driving a ferroelectric nonvolatile semiconductor memory of the present invention, the ratio of (write voltage) / (disturb voltage) can be increased by adding only a few steps to the conventional operation steps. As a result, the influence of the degradation of the data holding state due to the disturbance can be relatively reduced, and a highly reliable data holding state can be obtained. Further, the circuit configuration is simple, the increase in the circuit scale is small, and the operation overhead and delay are small. Furthermore, since the sense amplifier can be operated in a simple binary operation, a sufficient operation margin of the sense amplifier can be secured, and stable operation can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to a first embodiment of the present invention;

FIG. 2 is a schematic partial cross-sectional view of the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the present invention;

FIG. 3 is a diagram showing operation waveforms in the method of driving the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the present invention;

FIG. 4 is a diagram showing operation waveforms in a method of driving a ferroelectric nonvolatile semiconductor memory according to a second embodiment of the invention;

FIG. 5 is a diagram showing operation waveforms in a method of driving a ferroelectric nonvolatile semiconductor memory according to a third embodiment of the present invention;

FIG. 6 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to a fourth embodiment of the present invention;

FIG. 7 is a schematic partial sectional view of a ferroelectric nonvolatile semiconductor memory according to a fourth embodiment of the present invention;

FIG. 8 is a diagram showing operation waveforms in a method for driving a ferroelectric nonvolatile semiconductor memory according to a fourth embodiment of the present invention;

FIG. 9 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to a fifth embodiment of the present invention;

FIG. 10 is a diagram showing operation waveforms in a method of driving a ferroelectric nonvolatile semiconductor memory according to a fifth embodiment of the present invention;

FIG. 11 is a schematic partial sectional view of a ferroelectric nonvolatile semiconductor memory according to a sixth embodiment of the present invention;

FIG. 12 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to Embodiment 7 of the present invention;

FIG. 13 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to Embodiment 7 of the present invention;

FIG. 14 is a schematic partial cross-sectional view of a ferroelectric nonvolatile semiconductor memory according to Embodiment 7 of the present invention;

FIG. 15 is a schematic partial sectional view of a ferroelectric nonvolatile semiconductor memory according to Embodiment 8 of the present invention;

FIG. 16 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to Embodiment 8 of the present invention;

FIG. 17 is a circuit diagram of a modification of the ferroelectric nonvolatile semiconductor memory according to the eighth embodiment;

FIG. 18 is a schematic partial sectional view of a ferroelectric nonvolatile semiconductor memory according to a ninth embodiment of the invention;

FIG. 19 is a schematic partial cross-sectional view of a modification of the ferroelectric nonvolatile semiconductor memory according to Embodiment 6 of the present invention;

FIG. 20 is a schematic partial cross-sectional view of a modification of the ferroelectric nonvolatile semiconductor memory according to Embodiment 5 of the present invention;

FIG. 21 is a PE hysteresis loop diagram of a ferroelectric substance.

FIG. 22 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory disclosed in US Pat. No. 4,873,664.

FIG. 23 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory disclosed in Japanese Patent Application Laid-Open No. 9-121032.

FIG. 24 is a diagram showing operation waveforms in the ferroelectric nonvolatile semiconductor memory disclosed in Japanese Patent Application Laid-Open No. 9-121032.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Silicon semiconductor substrate, 11 ... Element isolation region, 12 ... Gate insulating film, 13 ... Gate electrode,
14 source / drain regions, 15, 18, 28,
38, 48 ... connection holes, 16, 26, 26A, 36,
36A, 56, 56A, 66A, 126A, 126B,
136A, 136B ... insulating layer, 17, 27, 37,
47... Openings, 21, 21A, 21B, 31, 31
A, 31B, 41, 51 ... first electrode, 22, 22
A, 22B, 32, 32A, 32B, 42, 52 ...
Ferroelectric layer, 23, 33, 43, 53... Second electrode, MU... Memory unit, SMU... Sub memory unit, MC... Memory cell, TR... ... word line, BL ... bit line, PL ... plate line, WD ... word line decoder / driver, SA ... sense amplifier or differential sense amplifier, PD ... plate line decoder / Driver, C
N: Common node

Claims (5)

[Claims] (A) a bit line; (B) a selection transistor; (C) a sub-memory unit composed of M memory cells (where M ≧ 2); and (D) M memory cells. Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode, and the first electrode of the memory cell forming the sub-memory unit is In a memory unit, the common first electrode is connected to a bit line via a selection transistor, and the second electrode is connected to a plate line in a ferroelectric nonvolatile semiconductor memory. When writing one of the binary data to one selected memory cell, no data is written to the remaining unselected memory cells constituting the sub memory unit. A driving method, (a) in advance of the selection transistor in the off state, a high potential V _PL-H is applied to a plate line connected to the selected memory cell, a plate line connected to the unselected memory cells Applying a first intermediate potential V _PL-M1 to the bit line and applying a low potential V _BL-L or a high potential V _BL-H to the bit line depending on data to be written to the selected memory cell; ) The selection transistor is turned on, and the common first
After connecting the electrode and the bit line via a selection transistor, applying a low potential V _PL-L to a plate line connected to the selected memory cell, thereby writing data to the selected memory cell; (C) The selection transistor is turned off and the common first
(D) placing a second electrode on a plate line connected to an unselected memory cell;
Of the first common potential V _PL-M2 (> V _PL-M1 )
Raising the potential of the common first electrode in a floating state based on the capacitive coupling between the electrode and the plate line, the method for driving a ferroelectric nonvolatile semiconductor memory. 2. The value of the first intermediate potential V _PL-M1 is [V _PL-L
+ (V _PL-H −V _PL-L ) / 2], and the value of the second intermediate potential V _PL-M2 is substantially equal to the value of V _PL-H. 2. The method for driving a ferroelectric nonvolatile semiconductor memory according to item 1. 3. When the power supply voltage is _Vcc , _VPL-H and _VPL-H
The value of _BL-H is approximately equal to _Vcc, and the values of _VPL-L and _VBL-L are 0.
3. The method of driving a ferroelectric nonvolatile semiconductor memory according to claim 2, wherein the voltage is volts. 4. The value of the first intermediate potential V _PL-M1 is [V <sub>PL-L
+ (V PL-H -V PL</sub> -L) / 3] approximately equal to the value of the value of the second intermediate potential V _{PL-M2 is, [V PL-L +2 (} V PL- H -
_VPL-L ) / 3], and the driving method of the ferroelectric nonvolatile semiconductor memory according to claim 1, wherein 5. A power supply voltage of V_ccAnd V_PL-HThe value of
V_ccApproximately equal to _BL-HIs (2/3) V_ccAbbreviation
, V_PL-LAnd V_BL-LIs characterized by 0 volts
5. The ferroelectric nonvolatile semiconductor memo according to claim 4, wherein
Drive method.