JP2002149136A - Picture processing circuit and picture data processing method, optoelectronic device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a block ghost when displaying by sequentially selecting a plurality of grouped data lines block by block. SOLUTION: Pixel data Da are delayed by a delay unit Ud, and are outputted as pixel data Db. A 1st correction unit Uh1 generates a 1st correction data Dh1 based on a 1st average data Dw1 obtained by averaging a difference between the picture data Da and the picture data Db for one unit time. A 2nd correction unit Uh2 generates a 2nd correction data Dh2 based on a 2nd average data Dw2 obtained by averaging a difference between the picture data Da and the reference data Dref for one unit time. A subtracter circuit 45 subtracts the 1st and 2nd correction data Dh1, Dh2 from the picture data Da to generate corrected picture data Dout.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal which is divided into a plurality of systems and which is extended on a time axis and maintains a constant signal level per unit time to each of the data lines at a predetermined timing. The present invention relates to an image processing circuit and an image data processing method suitable for use in an electro-optical device, an electro-optical device using the same, and an electronic apparatus.

[0002]

2. Description of the Related Art A conventional electro-optical device, for example, an active matrix type liquid crystal display device will be described with reference to FIGS.

First, as shown in FIG. 11, a conventional liquid crystal display device includes a liquid crystal display panel 100, a timing circuit 200, and an image signal processing circuit 300. Among these, the timing circuit 200 outputs a timing signal (to be described later as necessary) used in each unit. Further, the D / A conversion circuit 301 in the image signal processing circuit 300 converts the image data Da supplied from the external device from a digital signal to an analog signal and outputs it as an image signal VID. Further, the phase expansion circuit 30
Reference numeral 2 designates, when one system image signal VID is input, expands it into an N-phase (N = 6 in the figure) image signal and outputs it. Here, the reason why the image signal is expanded to the N-phase is that the application time of the image signal supplied to the thin film transistor (hereinafter, referred to as “TFT”) is increased in a sampling circuit described later, and the TF is increased.
This is to ensure a sufficient sampling time and charge / discharge time for the data signal of the T panel.

On the other hand, the amplifying / inverting circuit 303 inverts the polarity of the image signal under the following conditions, amplifies the image signal appropriately, and then converts the image signal into the phase-developed image signals VID1 to VID6.
00 is supplied. Here, the polarity inversion means to alternately invert the voltage level using the amplitude center potential of the image signal as a reference potential. Whether to invert is determined depending on whether the data signal application method is a scan line unit polarity inversion, a data signal line unit polarity inversion, or a pixel unit polarity inversion. ,
The inversion cycle is set to one horizontal scanning period or dot clock cycle.

Next, the liquid crystal display panel 100 will be described. The liquid crystal display panel 100 has a configuration in which an element substrate and a counter substrate face each other with a gap, and liquid crystal is sealed in the gap. Here, the element substrate and the counter substrate are made of a quartz substrate, hard glass, or the like.

In the element substrate, a plurality of scanning lines 112 are arranged in parallel in the X direction in FIG. 12, and a plurality of scanning lines 112 are arranged in parallel in the Y direction orthogonal to the scanning direction. Two data lines 114 are formed. Here, each data line 114 is divided into blocks in units of six, and these are referred to as blocks B1 to Bm. Hereinafter, for convenience of explanation, when a general data line is pointed out, the reference numeral is indicated as 114, but when a specific data line is indicated, the reference numeral is indicated as 114a to 114f.

At each intersection between the scanning line 112 and the data line 114, as a switching element, for example, the gate electrode of each TFT 116 is connected to the scanning line 112, while the source electrode of the TFT 116 is connected to the data line 11.
4 and the drain electrode of the TFT 116 is connected to the pixel electrode 118. Each pixel is composed of a pixel electrode 118, a common electrode formed on a counter substrate, and a liquid crystal interposed between these electrodes. At each intersection of the scanning line 112 and the data line 114, a matrix is formed. It will be arranged in a shape. In addition, a storage capacitor (not shown) is formed so as to be connected to each pixel electrode 118.

The scanning line driving circuit 120 is formed on an element substrate, and generates a pulse-like scanning signal based on a clock signal CLY from the timing circuit 200, its inverted clock signal CLYinv, a transfer start pulse DY, and the like. The data is sequentially output to each scanning line 112. Specifically, the scanning line driving circuit 120 sequentially shifts the transfer start pulse DY supplied at the beginning of the vertical scanning period in accordance with the clock signal CLY and its inverted clock signal CLYinv and outputs it as a scanning line signal. The scanning lines 112 are sequentially selected.

On the other hand, the sampling circuit 130 has a sampling switch 131 at one end of each data line 114 for each data line 114. This switch 131 is formed by a TF formed on the element substrate.
The image signal VID1 to VID6 is input to the source electrode of the switch 131 via the image signal supply lines L1 to L6. Then, the data line 11 of the block B1
The gate electrodes of the six switches 131 connected to 4a to 114f are connected to signal lines to which the sampling signal S1 is supplied, and the data lines 114a to 114 of the block B2.
The gate electrodes of the six switches 131 connected to f
Connected to a signal line to which the sampling signal S2 is supplied,
Similarly, the data lines 114a to 114b of the block Bm
The gate electrodes of the six switches 131 connected to f
It is connected to a signal line to which the sampling signal Sm is supplied. Here, the sampling signals S1 to Sm are signals for sampling the image signals VID1 to VID6 for each block within the horizontal effective display period.

The shift register circuit 140 is also formed on an element substrate, and receives the clock signal CLX from the timing circuit 200 and its inverted clock signal CLXin.
v. It sequentially outputs the sampling signals S1 to Sm based on the transfer start pulse DX and the like. More specifically, the shift register circuit 140 sequentially shifts the transfer start pulse DX supplied at the beginning of the horizontal scanning period according to the clock signal CLX and its inverted clock signal CLXinv and sequentially outputs the sampling signals S1 to Sm. It is.

In such a configuration, when the sampling signal S1 is output, the image signal VID1 is applied to the six data lines 114a to 114f belonging to the block B1.
~ VID6 are sampled and these image signals VID1 ~
VID6 is written into the six pixels on the currently selected scanning line by the TFT 116, respectively.

Thereafter, when the sampling signal S2 is output, the six data lines 1 belonging to the block B2 are output.
The image signals VID1 to VID6 are sampled on the pixels 14a to 114f, respectively, and these image signals VID1 to VID6 are applied to the six pixels on the selected scanning line at that time.
16 respectively.

Similarly, the sampling signals S3,
When S4,..., Sm are sequentially output, blocks B3, B
6,..., Bm, six data lines 114a to 114
At f, the image signals VID1 to VID6 are sampled, respectively, and these image signals VID1 to VID6 are respectively written to the six pixels on the selected scanning line at that time. Then, after that, the next scanning line is selected, and similar writing is repeatedly performed in the blocks B1 to Bm.

In this driving method, the sampling circuit 13
The number of stages of the shift register circuit 140 that drives and controls the switch 131 at 0 is reduced to 1/6 as compared with the method of driving each data line in a dot-sequential manner. Further, since the frequency of the clock signal CLX to be supplied to the shift register circuit 140 and the inverted clock signal CLXinv need only be １ ／, the power consumption can be reduced along with the reduction in the number of stages.

[0015]

However, in a system in which one system of image signals is expanded into a plurality of systems and the liquid crystal display panel is driven by using the plurality of systems of image signals, a floor to be originally displayed in block units is used. There is a problem that a gray scale deviated from the key is displayed (hereinafter, this phenomenon is referred to as a block ghost).

For example, in a liquid crystal display panel operating in a normally white mode, as shown in FIG. 13A, one screen is composed of blocks B1 to B7, and areas of blocks B1 to B3 and block B4. b4
1 displays black while the area b42 of the block B4 and halftones are displayed in the blocks B5, B6 and B7, the area b42 becomes slightly brighter than the halftone, and the next block B5 becomes darker than the halftone. Slightly darkens.

As a result of repeated experiments and studies on such a block ghost, the inventor of the present application found that the following two main factors were found.

First, the liquid crystal display panel 100 shown in FIG.
, The equivalent circuit for the i-th block Bi is
This is shown in FIG. In the figure, R is the equivalent resistance of the counter electrode (common electrode). Further, since liquid crystal is sandwiched between the image signal supply lines L1 to L6 and the counter electrode, a parasitic capacitance is generated. Cxa to Cxf represent this parasitic capacitance as an equivalent capacitance. Furthermore, 131a-
131f is a sampling switch 131 corresponding to each of the image signal supply lines L1 to L6. In addition, Cy
a to Cyf represent the parasitic capacitance of the data lines 114a to 114f (mainly generated between the counter electrodes) and the pixel capacitance as equivalent capacitances.

The first factor is that a differentiation circuit is formed by the equivalent capacitances Cxa to Cxf and the resistance R, and therefore the image signal V
When ID1 to VID6 are input to the liquid crystal display panel 100, a waveform corresponding to the amount of voltage change of the image signals VID1 to VID6 is generated on the counter electrode.

The second factor is a change in the voltage of the common electrode due to charge and discharge of the electric charge when the block Bi is selected. That is, the block Bi is selected, and the switches 131a to 131a are selected.
When 131f is turned on, the equivalent capacitances Cya to Cyf
Include an initial voltage Vs (equivalent capacitances Cya to Cyf and a switch 113a at the start of the selection period of the block Bi).
To the image signal VID1
Charges and discharges are performed until the voltage reaches VID6. The second factor is that a differential waveform is generated on the counter electrode by the charging / discharging current at this time.

The differential waveform voltage distortion caused by the first and second factors occurs at the start of the selection period of the block Bi and attenuates with time. Assuming that the error voltage remaining on the counter electrode at the end of the selection period of the block Bi is Ve, display unevenness occurs unless Ve = 0. This is because the switches 113a to 113a
113f is turned off, and the voltage affected by the error voltage Ve is held in the pixel capacitance.

First, the first error voltage V due to the first factor
e1 is given by the following equation 1. Here, α is a constant. Vk, i represents an image signal to be supplied to the k-th data line in the i-th block.

[0023]

(Equation 1) The second error voltage Ve2 due to the second factor is given by the following equation (2). Here, β is a constant.

[0024]

(Equation 2) Therefore, the error voltage Ve obtained by summing both is expressed by the following equation (3).
Given by

[0025]

(Equation 3) Using these Equations 1 to 3, a change in luminance from block B3 to block B5 shown in FIG. Here, as shown in FIG.
The black level Vb is supplied to the four data lines from the left among the six data lines 114a to 114f constituting the area No. 4 (area b).
41) The halftone level Vc is supplied to the two data lines from the right (region b42), and the initial voltage Vs is assumed to match the halftone level Vc.

First, let us consider a change in the luminance level of the block B3 with i = 3. As shown in FIG. 13A, the block B2 immediately before the block B3 displays black in the same manner as the block B3. Therefore, Vk, i and Vk, i-1 in the equation 1 are both at the black level Vb, and Ve1 = 0. Becomes Further, since the initial voltage Vs matches the halftone level Vc, Ve2
= 6β (Vb−Vc)> 0. Therefore, the error voltage Ve becomes positive, and the block B3 becomes bright. However, the human eye perceives even a slight change in luminance in the halftone, but does not feel much change in the luminance in black, so that the person hardly perceives the block B3 as bright.

Next, in the block B4, black is displayed in the 2/3 area b41, and halftone is displayed in the remaining 1/3 area b42. Therefore, Ve1 = −2α (Vb−
Vc) <0, and Ve2 = 4β (Vb−Vc)> 0.
Whether Ve takes a positive value or a negative value depends on the values of α and β. Generally, the values of the equivalent capacitances Cya to Cyf are larger than the values of the equivalent capacitances Cxa to Cxf, so that β> α is often the case. Therefore, normally, the error voltage Ve becomes positive, and the block B4 becomes bright overall. However, due to the above-described visual characteristics, a person hardly feels that the brightness of the region b41 displaying black has become bright, but feels that it has become bright in the region b42 displaying the halftone.

Next, in block B5, a half tone is displayed, so that Ve1 = -4α (Vb-Vc) <0, Ve2 = 0
Since the error voltage Ve takes a negative value, the block B
5 darkens.

The present invention has been made in view of the above-described circumstances, and when a gray level to be displayed changes in the middle of a block, the remaining area of the block (for example, b42) and the next block (for example, B5) In this case, the display ghost is greatly improved by removing the block ghost in the above.

[0030]

(1) In order to achieve the above object, a first image processing circuit according to the present invention comprises a plurality of scanning lines, a plurality of data lines, each of the scanning lines and each of the data lines. A switching element provided corresponding to the intersection of lines, and an image processing circuit used in an electro-optical device having a pixel electrode electrically connected to the switching element,
A delay circuit that delays image data supplied from the outside by a unit time and outputs it as delayed image data, and based on data obtained by averaging the difference between the image data and the delayed image data for each unit time. First correction data generation means for generating first correction data, and second correction data based on data obtained by averaging a difference between the image data and predetermined reference data for each unit time. Second correction data generation means, correction means for correcting the delayed image data based on the first correction data and the second correction data to generate corrected image data, and A phase development circuit for dividing the data into development image signals and supplying the divided data to the plurality of data lines.

In the electro-optical device according to the present invention,
An image is displayed based on the phase-expanded image signal divided into a plurality of systems, but an image signal supply line up to each data line is accompanied by a parasitic capacitance. Further, the data line itself has a parasitic capacitance and each pixel capacitance is provided. In addition, the counter electrode has a distributed resistance. Therefore, a differentiating circuit is equivalently formed between the image signal supply line and the counter electrode, and a differential circuit is equivalently formed between the data line and the counter electrode.
Therefore, when the signal level of the image signal supplied to the electro-optical device changes, a first error voltage is induced in the common electrode by a differentiating circuit formed between the image signal supply line and the common electrode. Further, when a certain data line is selected, charge and discharge occur, so that the second error voltage of the counter electrode changes. Ghosts occur due to these factors.

According to the present invention, the first correction data generation means generates the first correction data by averaging the first difference data for each unit time, which corresponds to the first error voltage. The second correction data generating means averages the second difference data for each unit time to generate second correction data, which corresponds to a second error voltage. That is, the first
The second correction data is obtained by predicting a voltage change of the common electrode in advance. Since the corrected image data is generated by correcting the image data based on the first and second correction data, by generating an image signal based on the corrected image data, the first and second counter electrodes are generated. These error voltages can be canceled even if they occur. As a result, block ghosts can be significantly reduced, and the quality of the displayed image can be dramatically improved.

(2) In the above-mentioned invention, the first correction data generation means calculates a difference between the image data and the delayed image data as first difference data, A first averaging circuit that generates first averaged data obtained by averaging the difference data for each unit time, and a first coefficient circuit that generates first correction data by multiplying the first averaged data by a coefficient. It is desirable to provide.

(3) In addition, more specifically, the first averaging circuit includes a cumulative addition circuit that cumulatively adds the first difference data for each unit time, and a cumulative addition result that is the input image data. It is preferable to include a division circuit for dividing the signal by the number of divisions.

(4) In the above-mentioned invention, the second correction data generating means includes a second subtraction circuit for calculating a difference between the image data and the reference data as second difference data, A second averaging circuit that generates second averaged data obtained by averaging data for each unit time;
Preferably, a second coefficient circuit is provided for multiplying the second averaged data by a coefficient to generate second correction data.

(5) In addition, more specifically, the second averaging circuit comprises: a cumulative addition circuit for cumulatively adding the second difference data for each unit time; and a cumulative addition result for the input image signal. And a division circuit for dividing by the number of divisions.

According to the present invention, since the cumulative addition result is divided by the number of divisions (the number of phase developments), the first and second difference data averaged for each block can be calculated.

(6) Further, the reference data may correspond to an initial voltage applied to the pixel electrode, a counter electrode facing the pixel electrode, and a pixel capacitor including an electro-optical material.

(7) Alternatively, the reference data may be a precharge voltage applied to the pixel electrode, a counter electrode facing the pixel electrode, and a pixel capacitor including an electro-optical material.

Since the above-mentioned second error voltage is caused by charge / discharge of electric charge, a problem is a change in the voltage of the data line or the pixel capacitance. Therefore, the initial voltage and the precharge voltage can be used as the reference data. However, in an actual electro-optical device, these optimum values may deviate from these values due to various factors. Therefore, it is essential to set the reference data so that the block ghost is visually minimized.

(8) Further, the electro-optical device samples a plurality of the phase-expanded image signals in accordance with a sampling signal, and supplies the sampled image signals to the data lines;
In a case where each of the switch elements is provided with each image signal supply line for supplying each of the image signals, the first coefficient of the first coefficient circuit includes at least a parasitic capacitance component associated with each of the image signal supply lines and It is desirable to determine based on the resistance component of the counter electrode.

Thus, ghost caused by the first error voltage can be effectively canceled.

(9) Preferably, the second coefficient of the second coefficient circuit is determined based on at least a parasitic capacitance component associated with each of the data lines and a resistance component of the common electrode.

As a result, the ghost caused by the second error voltage can be effectively canceled.

(10) A second image processing circuit according to the present invention further comprises a delay circuit for delaying image data supplied from the outside by a unit time and outputting the delayed image data as delayed image data. First correction data generating means for generating first correction data based on data obtained by averaging a difference between the image data and the unit time, and calculating a difference between the image data and predetermined reference data in the unit. Second correction data generating means for generating second correction data based on data obtained by averaging every time, and correcting the delayed image data based on the first correction data and the second correction data Correction means for generating processed image data.

According to the present invention, the first correction data generation means generates the first correction data by averaging the first difference data for each unit time, which corresponds to the first error voltage. The second correction data generating means averages the second difference data for each unit time to generate second correction data, which corresponds to a second error voltage. That is, the first
The second correction data is obtained by predicting a voltage change of the common electrode in advance. Since the corrected image data is generated by correcting the image data based on the first and second correction data, by generating an image signal based on the corrected image data, the first and second counter electrodes are generated. These error voltages can be canceled even if they occur. As a result, block ghosts can be significantly reduced, and the quality of the displayed image can be dramatically improved.

(11) Further, the electro-optical device according to the present invention comprises:
A plurality of scanning lines, a plurality of data lines, a switching element provided corresponding to the intersection of each scanning line and each data line, a pixel electrode electrically connected to the switching element, A delay circuit that delays supplied image data by a unit time and outputs the delayed image data as delayed image data;
First correction data generation means for generating first correction data based on data obtained by averaging a difference between the image data and the delayed image data for each unit time; A second correction data generation unit configured to generate second correction data based on data obtained by averaging a difference from the data for each unit time, and the delay based on the first correction data and the second correction data; Correction means for correcting the image data to generate corrected image data, and a phase expansion circuit which divides the corrected image data into a plurality of phase expansion image signals and supplies the plurality of phase expansion image signals to the plurality of data lines. Features.

According to this electro-optical device, it is possible to greatly reduce block ghosts and dramatically improve the quality of a displayed image.

(12) The above-described electro-optical device further includes a data line driving circuit for sequentially generating a sampling signal, and samples the phase-expanded image signal based on the sampling signal and supplies the sampled phase-expanded image signal to each of the data lines. It is desirable to provide a sampling circuit that performs the processing.

According to this electro-optical device, the quality of the displayed image can be greatly improved, and the time for supplying the image signal to the data line can be lengthened.

(13) Next, an electronic apparatus according to the present invention includes the above-described electro-optical device, and includes, for example, a video projector, a notebook personal computer, and a mobile phone.

(14) Next, a first image data processing method according to the present invention is an image data processing method used for an electro-optical device for supplying an image signal to a plurality of data lines, and is supplied from outside. Generating delayed image data by delaying the image data by a unit time, generating a difference between the image data and the delayed image data as first difference data,
The first difference data is averaged for each unit time to generate first averaged data.
Multiplying a coefficient to generate first correction data; generating a difference between the image data and predetermined reference data as second difference data; averaging the second difference data for each unit time; Generating second averaged data; multiplying the second averaged data by a second coefficient to generate second correction data; and calculating the delayed image data based on the first correction data and the second correction data. Is corrected to generate corrected image data, the corrected image data is divided into a plurality of phase-developed image signals, and supplied to the plurality of data lines.

According to the present invention, the first correction data is the first correction data.
And the second correction data corresponds to the second error voltage. Therefore, the first and second correction data are obtained by predicting the voltage change of the common electrode in advance. Since the corrected image data is generated by correcting the image data based on the first and second correction data, by generating an image signal based on the corrected image data, the first and second counter electrodes are generated. These error voltages can be canceled even if they occur. As a result, block ghosts can be significantly reduced, and the quality of the displayed image can be dramatically improved.

(15) Next, a second image data processing method according to the present invention generates delayed image data by delaying externally supplied image data by a unit time, and generates the delayed image data and the delayed image data. A difference from the data is generated as first difference data, the first difference data is averaged for each unit time to generate first averaged data, and the first averaged data is multiplied by a first coefficient. To generate the first correction data,
Generating a difference between the image data and predetermined reference data as second difference data; averaging the second difference data for each unit time to generate second averaged data; Generating second correction data by multiplying the converted data by a second coefficient, and correcting the delayed image data based on the first correction data and the second correction data to generate corrected image data. Features.

According to this image data processing method, block ghosts can be greatly reduced, and the quality of a displayed image can be dramatically improved.

[0056]

Embodiments of the present invention will be described below with reference to the drawings.

<1. Overview of Liquid Crystal Display> First, an active matrix type liquid crystal display will be described as an example of the electro-optical device according to the present invention.

FIG. 1 is a block diagram showing the entire configuration of the liquid crystal display device. The liquid crystal display device according to the present embodiment is the same as the conventional liquid crystal display device shown in FIG. 11 except that a ghost removal circuit 304 is provided in a stage preceding the D / A converter 301 in the image signal processing circuit 300A. It is configured. Note that the image data Da in this example is an 8-bit parallel format, is a data string whose sampling cycle is the cycle of the dot clock signal DCLK, and is supplied from an external device (not shown).

The ghost elimination circuit 304 uses the first
And the block ghost component generated by the second factor is predicted in advance, and the image data D
is corrected to generate corrected image data Dout.

The phase expansion circuit 302 outputs the corrected image data D
out is subjected to serial-to-parallel conversion on the image signal VID obtained by DA conversion, and the phase-expanded image signals VID1 to VI expanded into 6 phases.
Generate D6. Specifically, the phase expansion circuit 302 samples and holds the image signal VID based on the six-phase sample-and-hold pulses SP1 to SP6 and SS that are activated every six periods of the dot clock signal DCLK, and Is extended by a factor of six, and divided into six systems to generate the phase-deployed image signals VID1 to VID6.

Each of the phase developed image signals VID1 to VID6 is obtained by converting the corrected image data Dout synchronized with the dot clock signal DCLK to D.
Since the value of the original corrected image data Dout changes every dot clock cycle because it is generated based on the A-converted image signal VID, each phase expanded image signal VID1 to VID6 becomes 6
It changes every dot clock cycle. Therefore, each of the phase developed image signals VID1 to VID6 is a signal that changes with a time determined by a product of the number of phase developed (the number of systems to be divided) and one cycle of the dot clock signal DCLK as one unit time.

Next, the liquid crystal display panel 100 is the same as that used in the conventional liquid crystal display device shown in FIG.

<2. Ghost Elimination Circuit> Next, the ghost elimination circuit 304 will be described in detail. FIG. 2 is a circuit diagram of the ghost removal circuit 304. As shown in this figure, the ghost removal circuit 304 includes a delay unit Ud, a first correction unit Uh1, a second correction unit Uh2, and an addition circuit 30.

First, the delay unit Ud is constituted by connecting six latch circuits LAT1 to LAT6 in series, and outputs image data Db by delaying image data Da by a predetermined time. Here, each of the latch circuits LAT1 to LAT6 latches 8-bit input data based on the dot clock signal DCLK.

The dot clock signal DCLK is a master clock of the liquid crystal display device, and is generated in the timing circuit 200. Further, the timing circuit 200 divides the frequency of the dot clock signal DCLK to generate a clock signal CLX for driving the data line driving circuit of the liquid crystal display panel 100 and a clock signal CLY for driving the scanning line driving circuit. I have. In this example, the phase expansion circuit 302 performs six phase expansion. Therefore, the clock signal CLX
Is generated by dividing the dot clock signal DCLK by six.

The delay unit Ud is provided with a dot clock signal
Since the six latch circuits LAT1 to LAT6 driven by DCLK are connected in series, the image data Db is data delayed by six dot periods from the image data Da.

As described above, each of the phase developed image signals VID1 to VID6 has a time determined by the product of the number of phase developed (the number of systems into which the image signal VID is divided) and one cycle of the dot clock signal DCLK. This signal changes as one unit time.
In this example, one unit time has a period of 6 dots, which coincides with the delay time of the delay unit Ud. In other words, the delay unit Ud delays the image data Da by a time corresponding to one unit time (selection period of a certain block) of the phase expanded image signals VID1 to VID6 obtained by phase expansion (serial / parallel conversion). Generate the image data Db. Here, assuming that the image data Da is current data, the image data Db is past data for one unit time.

Next, the first correction unit Uh1 includes a first subtraction circuit 41, a first averaging circuit 42, a first coefficient circuit 43,
And a latch circuit 44, and generates first correction data Dh1 corresponding to the above-described first error voltage Ve1.

First, the first subtraction circuit 41 outputs the image data Da
The first difference data Dx is generated by subtracting the image data Db (past) from (current).

Next, the first averaging circuit 42 averages the first difference data Dx for each block to generate first averaged data Dw1. The averaging circuit 42 has an adding circuit 421 and a latch circuit 422. The latch circuit 422 latches the output signal of the adding circuit 421 based on the dot clock signal DCLK. On the other hand, the addition circuit 4
The first difference data Dx is supplied to one of the input terminals 21 and the output data of the latch circuit 422 is fed back to the other input terminal. Therefore, the addition circuit 421 and the latch circuit 422 function as a cumulative addition circuit. The reset terminal R of the latch circuit 422 has a reset signal RS with a period of 6 dot clocks.
Is supplied. Therefore, the first difference data Dx is reset every unit time and is cumulatively added.

The first averaging circuit 42 further includes a division circuit 423 and a latch circuit 424. The division circuit 423 divides data obtained by accumulating the first difference data Dx in block units by “6” (the number of phase expansions).
The latch circuit 424 latches the output data of the division circuit 423 with the block clock signal BCLK that becomes active for each unit time, and outputs this as the first averaged data Dw1. The block clock signal BCLK is generated by the timing circuit 200 shown in FIG.

Next, the first coefficient circuit 43 has a multiplier, and multiplies the first averaged data Dw1 by the first coefficient K1 and outputs the result. In addition, the latch circuit 44 is used for time alignment, latches the output data of the coefficient circuit 43, and outputs the first correction data Dh1.

As described above, in the first correction unit Uh1, the image data Db of the immediately preceding block is subtracted from the image data Da of the current block, the subtraction result is integrated in block units, and the integration result is phase-expanded. The first correction data Dh1 is obtained by dividing by a number (the number of divisions) and multiplying the division result by a first coefficient K1. Therefore, if K1 / 6 = α, the first correction data Dh1 is equal to the above-described first error voltage Vh.
e1. Here, it is desirable that the first coefficient K1 be determined based on at least a parasitic capacitance component associated with each of the image signal supply lines L1 to L6 and a resistance component of the counter electrode.

Next, the second correction unit Uh2 includes a second subtraction circuit 51, a second averaging circuit 52, a second coefficient circuit 53,
And the latch circuit 54, and generates the second correction data Dh2 corresponding to the above-described second error voltage Ve2.

First, the second subtraction circuit 51 outputs the image data Da
Is subtracted from the reference data Dref to generate second difference data Dy. Here, the reference data Dref
Can be determined experimentally to minimize block ghosts.

It is desirable to select, as the reference data Dref, the initial voltage Vs written in the pixel capacitance of the pixel belonging to a certain block when the block is selected. As described above, the second factor is generated in a process in which the initial voltage Vs of the pixel capacitance or the like changes to the voltages of the image signals VID1 to VID6.

The liquid crystal display panel 100 is driven by an AC driving method so as not to apply a DC voltage to the liquid crystal. For this reason, when focusing on a certain pixel, it is necessary to invert the polarity of the voltage applied to the liquid crystal between the even field and the odd field with the voltage of the counter electrode as the center voltage. Since an image has high correlation between fields, if a certain pixel displays black in an even field, black is often displayed in the next odd field. In this case, it is necessary to greatly change the voltage applied to the pixel capacitance between fields. However, since the data line 114 and the pixel capacitance are capacitive loads, the voltage of the pixel capacitance may not be changed to the target voltage during the block selection period. Therefore, a constant voltage may be applied to the pixel capacitance in advance during a vertical blanking period, a horizontal blanking period, or the like. This voltage is called a precharge voltage and is selected, for example, at a halftone level. In the driving method of applying the precharge voltage, the precharge voltage becomes the initial voltage Vs, so that the precharge voltage may be used as the reference data Dref.

Next, like the first averaging circuit 42, the second averaging circuit 52 includes an addition circuit 521 for performing cumulative addition for each block, a latch circuit 522, a division circuit 523, and a latch circuit 524. I have. Then, the second averaging circuit 52 averages the second difference data Dy for each block to generate second averaged data Dw2.

Next, the second coefficient circuit 53 has a multiplier, and multiplies the second averaged data Dw2 by a second coefficient K2 and outputs the result. In addition, the latch circuit 54 is used for time adjustment, latches the output data of the second coefficient circuit 53, and outputs it as the second correction data Dh2.

As described above, in the second correction unit Uh2, the reference data Dref is subtracted from the image data Da of the current block, the result of the subtraction is integrated for each block, and the integration result is calculated as the number of phase developments (the number of divisions). ), And the result of the division is multiplied by a second coefficient K2 to obtain second correction data Dh2. Therefore, if K2 / 6 = β, the second correction data Dh2 matches the above-described second error voltage Ve2. Here, the second coefficient K2 is at least equal to each data line 1
It is desirable to determine based on the parasitic capacitance component and the resistance component of the counter electrode attached to 14a to 114f. According to the second correction unit Uh2, for example, even when the luminance changes from black to halftone in the middle of a certain block, the value of the second correction data Dh2 is adjusted according to the area of black in the block. can do.

Next, the subtraction circuit 45 subtracts the first correction data Dh1 and the second correction data Dh2 from the image data Db and outputs the result as corrected image data Dout. As described above, since the first correction data Dh1 and the second correction data Dh2 correspond to the error voltages Ve1 and Ve2, by subtracting these from the image data Db, a block ghost component opposite to the image data Db is obtained. Can be generated. This makes it possible to remove the block ghost generated by the first and second factors.

In this embodiment, the reason why the image data Da before the phase expansion is corrected is that the signal after the phase expansion is divided into six systems, so that the ghost removal is performed for each system. This is because if a circuit is provided, the circuit configuration becomes complicated, but if the image data Da is corrected, the ghost can be removed by one circuit. Therefore, according to the present embodiment, ghosts can be effectively removed with a simple configuration.

<3. Phase Expansion Circuit> Next, the phase expansion circuit 30
2 will be described. FIG. 3 is a block diagram showing a main configuration of the phase expansion circuit. As shown in this figure, the phase expansion circuit 302 has a first sample hold unit USa provided with sample hold circuits SHA1 to SHA6, and a second sample hold unit USb provided with sample hold circuits SHb1 to SHb6. I have.

First, the first sample hold unit US
The sample-and-hold circuits SHA1 to SHA6 of a are configured to sample and hold the image signal VID based on the sample-and-hold pulses SP1 to SP6 supplied from the timing circuit 200 to generate signals vid1 to vid6. Here, each of the sum hold pulses SP1 to SP6
Is equivalent to six times the period of the dot clock signal DCLK, and the phase of each pulse is equal to the dot clock signal DCLK.
Are shifted by one period. Therefore, the signals vid1 to vid6
Is a signal in which the time axis is extended six times with respect to the image signal VID and the phase is sequentially shifted by the dot clock signal period.

Next, the second sample hold unit US
b sample-and-hold circuits SHb1 to SHb6 sample and hold the signals vid1 to vid6 based on the sample-and-hold pulse SS supplied from the timing circuit 200, and output the results through a buffer circuit (not shown) to a phase-developed image signal. The data is output as VID1 to VID6.
The sample hold pulse SS is a pulse having a unit time period. Therefore, the phases of the signals vid1 to vid6 are aligned at the timing when the sample hold pulse SS becomes active, and the phase developed image signals VID1 to VID6 having the aligned phases are generated.

<4. Operation of Liquid Crystal Display> Next, the operation of the liquid crystal display will be described step by step. First, the operation from the input of the image data Da to the generation of the corrected image data Dout by the ghost removal circuit 304 will be described. FIG. 4 is a timing chart for explaining the operation of the ghost removal circuit 304. In this figure, the subscript X when represented as DX, Y indicates the number of the data line 114 corresponding to one block in the scanning direction of the block, while the subscript Y indicates what number. It is assumed that it is the th block. For example, D
1, n + 1 corresponds to the first data line 114a in the block, and indicates that the block is the (n + 1) th data line.

First, the operation of the first correction unit Uh1 will be described. The ghost removal circuit 30
4, the delay unit Ud outputs the image data D
a is delayed by one unit time (6 dot cycle)
Output as b.

Thus, for the image data Da, 1
The image data Db before the unit time is obtained. For example, FIG.
Paying attention to the period Tx shown in FIG.
And corresponds to the data line 114b of the block Bn. On the other hand, the image data Db is D2, n-1 and corresponds to the data line 114b of the block Bn-1. An image signal supply line L2 is connected to the data line 114b of each block.
The image signal VID2 is supplied via the. That is, the image data Da and the image data Db in the period are both the image signal VID2 supplied via the image signal supply line L2.
It corresponds to. Further, since the image data Da and the image data Db correspond to adjacent blocks, they are data before and after the signal level of the image signal VID2 is switched.

The image data Da and Db are converted by the first subtraction circuit 41
Is supplied to the first subtraction circuit 41, the image data Da
The first difference data Dx is generated by subtracting the image data Db (past: one block before) from (current). For example, in the period Tx shown in the figure, the image data Da is “D2,
n "and the image data Db is" D2, n-1 ", so the first difference data Dx is" D2, n-D2, n-1 ".

As shown in FIG. 14, the image signal supply line L1
To L6 are capacitively coupled, so that when the image signal VID applied to any one of the image signal supply lines L1 to L6 changes, a first error voltage Ve1 is induced in the counter electrode, and the entire block Is affected. First averaging circuit 42
Is used to reflect the change in another image signal because the entire block is affected by a change in the image signal supplied to a certain image signal supply line.

The first difference data Dx is supplied to the first averaging circuit 4
2 is cumulatively added by the adder circuit 421 and the latch circuit 422, so that the output data of the latch circuit 422 corresponding to the last timing in each block is obtained by accumulating the first difference data Dx in each block. It will be. For example, during the period from time t10 to time t12 shown in FIG. 4, the output data of the latch circuit 422 is Dx1, n
+ Dx2, n +... + Dx6, n.

The output data of latch circuit 422 is divided by division circuit 423, and latch circuit 424 latches the division result based on block clock signal BCLK. Therefore, before the output data of latch circuit 422 is reset. , The latch circuit 424 outputs the first averaged data Dw1
Generate In the example shown in the figure, when the block clock signal BCLK rises from a low level to a high level at time t11, the latch circuit 424 generates the first averaged data Dw1 in synchronization with the rising edge. Thereafter, at time t12, the reset signal R
Since S becomes active (high level), the output data of the latch circuit 422 is reset, and the latch circuit 422 prepares for accumulation of the first difference data Dx of the next block.

When the first averaged data Dw1 is supplied to the coefficient circuit 43, the first averaged data Dw1 is added to the first averaged data Dw1.
The coefficient K1 is multiplied. However, this data
The phase is shifted from the image data Db. Therefore, the latch circuit 44 latches the data output from the coefficient circuit 43 with the dot clock signal DCLK, and outputs the first correction data Dh1 having the same phase as the image data Db.

Next, the operation of the second correction unit Uh2 will be described. The figure is a timing chart showing the operation of the second correction unit. When the image data Da is supplied to the second subtraction circuit 51, the second subtraction circuit 51 subtracts the reference data Dref from the image data Da (current) to generate second difference data Dy. For example, in the period Tx shown in the figure, the second difference data Dy is "D2, n-Dref".

As shown in FIG. 14, data lines 114a to 114a
Since the equivalent capacitance constituted by the parasitic capacitance and the pixel capacitance of 114f is capacitively coupled, when the voltage applied to each equivalent capacitance changes, an error voltage Ve2 corresponding to the change amount is obtained.
Occurs on the counter electrode and affects the entire block. The second averaging circuit 52 is used to reflect in advance the image signal because the entire block is affected by a voltage change of certain data lines 114a to 114f.

The second averaging circuit 52 includes the first averaging circuit 4
2 averages the first difference data Dx,
The difference data Dy is averaged for each block to generate second averaged data Dw2. When the second averaged data Dw2 is supplied to the coefficient circuit 53, the second averaged data Dw2 is multiplied by the second coefficient K2, and the output data is out of phase with the image data Db as shown in FIG. ing. Therefore, the latch circuit 54 latches the output data with the dot clock signal DCLK, and outputs the second correction data Dh2 having the same phase as the image data Db.

Then, the corrected image data Dout is generated by subtracting the first and second correction data Dh1 and Dh2 from the image data Db, and the corrected image data Dout is converted into an analog signal via the AD converter 301. The converted image signal VID is supplied to the phase expansion circuit 302.

Next, the operation until the phase expanded image signals VID1 to VID6 are generated based on the image signal VID will be described. FIG. 6 is a timing chart showing the operation of the phase expansion circuit.

When the image signal VID is supplied to the phase expansion circuit 302, the sample-and-hold circuits SHA1 to SHA6 extend the image signal VID by a factor of six in synchronization with each of the sample-and-hold pulses SP1 to SP6. To generate the signals vid1 to vid6 shown in FIG. further,
The sample and hold circuits SHA1 to SHA6 sample and hold the signals vid1 to vid6 in synchronization with each sample and hold pulse SS to generate image signals VID1 to VID6.

Now, the operation of canceling the ghost will be specifically described. FIG. 7 shows a phase developed image signal when the image data Da is supplied to the D / A converter 301 and phase developed without using the ghost removal circuit 304.
5 is a timing chart of corrected image data Dout generated using VID1 to VID6 and a ghost removal circuit 304.
In FIG. 7, in order to facilitate understanding, each data value is converted into an analog signal level and shown, and a delay time associated with phase expansion is ignored. In this example, it is assumed that the same display as in FIG. 13 is performed, and the initial voltage Vs is the halftone level Vc.

As shown in FIG. 7, time t0 to time t10
, The image data Da is the black level Vb and the time t10
At time t18, a data value corresponding to the halftone level Vc is obtained. For this reason, the phase development image signals VID1 to VID4 transition from Vb to Vc at the switching time t12 between the selection period of the block B4 and the selection period of the block B5. On the other hand, the phase expanded image signals VID5 and VID6 transition from Vb to Vc at the switching time t6 between the selection period of the block B3 and the selection period of the block B4.

The voltage Vcom1 induced on the counter electrode by the first factor is generated according to the change of the phase development image signals VID1 to VID6. Therefore, the waveform of the induced voltage Vcom1 becomes a differential waveform at time t6 and time t12 as shown in the figure.

The voltage Vcom2 induced at the counter electrode by the second factor is generated according to the change of the phase development image signals VID1 to VID6. Therefore, the waveform of the induced voltage Vcom2 becomes a differential waveform at time t6 and time t12 as shown in the figure. However, its polarity is opposite to that of Vcom1.

The voltage Vcom actually induced on the counter electrode
Is given by the sum of the induced voltage Vcom1 and the induced voltage Vcom2, and Vco at the time when the selection period of each block ends.
The value of m becomes the error voltage Ve. Therefore, block B
The absolute value of the error voltage Ve of 4 is 4β (Vb−Vc) −2α
(Vb−Vc), and the absolute value of the error voltage Ve of the block B5 is 4α (Vb−Vc).

Ghost removal circuit 304 according to the present embodiment
In this case, as described above, the first correction unit Uh1 generates the first correction data Dh1 based on the first factor, and the second correction unit Uh2 generates the second correction data Dh2 based on the second factor. And the first and second correction data Dh1 and Dh2 are the error voltages Ve1 and De1, respectively.
Ve2.

Here, the difference between the common electrode voltage Vcom at time t6, t12, and t18 and its center voltage is represented by Ve.
a, Veb, and Vec, the ghost removal circuit 304
The corrected image data Dout obtained as shown in FIG. 7 is as shown in FIG. Also in this case, the phase expansion image signals VID1 to VID6
, And a voltage is induced in the common electrode in accordance with the black level ratio in a certain block. However, as shown in FIG. 7, the corrected image data Dout includes Vea, Veb,
Since the correction in consideration of Vec is performed, the induced voltage of the counter electrode can be canceled. Therefore,
Even in the case where the black level changes from the black level to the halftone level in the block, the block ghost appearing in the block and the next block can be canceled, and the quality of the display image can be greatly improved.

<5. Modifications> Next, modifications of the above-described embodiments will be described.

(1) In the embodiment described above, the D / A converter 301 is provided between the ghost removal circuit 304 and the phase expansion circuit 302, but the phase expansion circuit 302 and the amplification / inversion circuit 303 One of them may be constituted by a digital circuit, and a D / A converter 301 may be provided at the output.

(2) In the above embodiment, the phase expansion circuit 302 includes the first sample and hold unit USa and the second sample and hold unit USb shown in FIG.
Although the phases of vid1 to vid6 are aligned, the second sample and hold unit USb may be omitted. In this case, the signals vid1 to vid1 which are shifted in phase every dot clock cycle
What is necessary is just to output vid6 as phase development image signals VID1 to VID6.

<6. Application Examples> Next, some examples in which the liquid crystal display device described in each of the above embodiments is used in electronic equipment will be described.

<6-1: Projector> First, a projector using this liquid crystal display device as a light valve will be described. FIG. 8 is a plan view showing a configuration example of the projector.

As shown in FIG.
Inside 0, a lamp unit 1102 composed of a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 1102 is
The light is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light 104, and is incident on liquid crystal panels 1110R, 1110B and 1110G as light valves corresponding to the respective primary colors.

The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal display panel 100 described above, and are driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). Now,
Light modulated by these liquid crystal panels enters a dichroic prism 1112 from three directions. In the dichroic prism 1112, the R and B lights are refracted at 90 degrees, while the G light travels straight. Therefore, as a result of combining the images of each color, the projection lens 1
Through 114, a color image is projected on a screen or the like.

The liquid crystal panels 1110R, 1110B
And 1110G have a dichroic mirror 1108
Accordingly, light corresponding to each of the primary colors of R, G, and B enters, so that it is not necessary to provide a color filter on the opposite substrate.

As described above, since the ghost removal circuit 304 or 305 is used in the image processing circuit 300 of the liquid crystal display device, the first or second ghost can be canceled, and the quality of the displayed image can be greatly reduced. Can be improved.

<6-2: Mobile Computer> Next, an example in which the liquid crystal display device is applied to a mobile computer will be described. FIG. 9 is a front view showing the configuration of the computer. In the figure, a computer 1200 includes a main unit 12 having a keyboard 1202.
04 and a liquid crystal display 1206. The liquid crystal display 1206 is configured by adding a backlight to the back of the liquid crystal display panel 100 described above.

<6-3: Mobile Phone> Further, an example in which the liquid crystal display device is applied to a mobile phone will be described. FIG.
1 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 includes a plurality of operation buttons 1302 and a reflective liquid crystal panel 1005. In the reflection type liquid crystal panel 1005, a front light is provided on the front surface as needed.

In addition to the electronic devices described with reference to FIGS. 8 to 10, a liquid crystal television, a viewfinder type,
Examples include a monitor-directed video tape recorder, a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a POS terminal, and a device equipped with a touch panel. It goes without saying that the present invention can be applied to these various electronic devices.

[0119]

As described above, according to the present invention, each image signal which divides an input image signal into a plurality of systems and expands the time axis to maintain a constant signal level per unit time is determined in advance. When supplying to the data lines at the timing, even if the luminance level changes in the middle of the block, a ghost appearing in the display image is predicted in advance, and the image data is corrected so as to cancel the ghost. Can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a ghost removal circuit in the liquid crystal display device.

FIG. 3 is a block diagram illustrating a configuration of a phase expansion circuit in the liquid crystal display device.

FIG. 4 is a timing chart showing an operation of a first correction unit of the ghost removal circuit.

FIG. 5 is a timing chart showing an operation of a second correction unit of the ghost removal circuit.

FIG. 6 is a timing chart showing an operation of a phase expansion circuit in the liquid crystal display device.

FIG. 7 is a timing chart of a phase-developed image signal when image data is phase-expanded without using a ghost removal circuit and corrected image data generated using the ghost removal circuit.

FIG. 8 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 9 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 10 is a perspective view showing a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 11 is a block diagram showing an overall configuration of a conventional liquid crystal display device.

FIG. 12 is a block diagram illustrating an electrical configuration of a liquid crystal display panel in a conventional liquid crystal display device.

FIG. 13 is an explanatory diagram illustrating an example of a ghost.

FIG. 14 is a circuit diagram showing an equivalent circuit in a certain block.

[Explanation of symbols]

41, 51 ... 1st subtraction circuit, 2nd subtraction circuit 42, 52 ... 1st averaging circuit, 2nd averaging circuit 43, 53 ... 1st coefficient circuit, 2nd coefficient circuit 45 ... Subtraction circuit 100 ... Liquid crystal display panel 112... Scanning lines 114 a to 114 f... Data lines 116... TFTs 118... Pixel electrodes 300... Image processing circuits 302. 1 difference data, 2nd difference data Dh1, Dh2 ... first correction data, 2nd correction data Dw1, Dw2 ... 1st averaged image data, 2nd averaged image data Dout ... corrected image data Da ... Image data Ud: delay units Uh1, Uh2: first correction unit, second correction unit K1, K2: first coefficient, second coefficient

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 632 G09G 3/20 632Z 641 641G F-term (Reference) 2H092 JA24 JB22 JB31 JB61 NA25 PA01 PA06 PA13 RA05 2H093 NA16 NC22 NC23 NC26 NC34 ND15 NE01 NG02 5C006 AC21 AF46 AF71 BB16 BC16 BF07 EC05 EC11 EC13 FA18 FA25 FA36 FA37 5C080 AA10 BB05 DD05 EE29 GG09 JJ02 JJ03 JJ04 JJ06 KK02 KK07 KK43

Claims (15)

[Claims] 1. A plurality of scanning lines, a plurality of data lines, a switching element provided corresponding to an intersection of each of the scanning lines and each of the data lines, and a pixel electrically connected to the switching element. An image processing circuit used in an electro-optical device having electrodes, a delay circuit that delays image data supplied from the outside by a unit time and outputs the delayed image data as delayed image data, and the image data and the delayed image data. First correction data generating means for generating first correction data based on data obtained by averaging the difference of the image data for each unit time, and calculating the difference between the image data and predetermined reference data for each unit time. Based on the data obtained by averaging
A second correction data generation unit that generates correction data; a correction unit that corrects the delayed image data based on the first correction data and the second correction data to generate corrected image data; An image processing circuit, comprising: a phase expansion circuit that divides data into a plurality of phase expansion image signals and supplies the data to the plurality of data lines. A first subtraction circuit that calculates a difference between the image data and the delayed image data as first difference data; and a first subtraction circuit that calculates the first difference data for each unit time. A first averaging circuit for generating averaged first averaged data, and a first coefficient circuit for generating first correction data by multiplying the first averaged data by a coefficient. Item 2. The image processing circuit according to item 1. 3. The first averaging circuit, wherein the first averaging circuit accumulates the first difference data for each unit time,
3. The image processing circuit according to claim 2, further comprising a dividing circuit for dividing a result of the cumulative addition by a division number for dividing the input image signal. A second subtraction circuit for calculating a difference between the image data and the reference data as second difference data; and averaging the second difference data for each unit time. A second averaging circuit for generating the second averaged data, and a second coefficient circuit for multiplying the second averaged data by a coefficient to generate second correction data. 2. The image processing circuit according to 1. 5. The second averaging circuit, wherein a cumulative addition circuit that cumulatively adds the second difference data for each unit time,
5. The image processing circuit according to claim 4, further comprising: a dividing circuit for dividing a result of the cumulative addition by a division number of the input image signal. 6. The apparatus according to claim 1, wherein the reference data corresponds to an initial voltage applied to the pixel electrode, a counter electrode facing the pixel electrode, and a pixel capacitor including an electro-optical material. 3. The image processing circuit according to claim 1. 7. The method according to claim 1, wherein the reference data is a precharge voltage applied to the pixel electrode, a counter electrode facing the pixel electrode, and a pixel capacitor including an electro-optical material. Image processing circuit. And a plurality of switch elements for sampling the phase-deployed image signals in accordance with the sampling signals and supplying the sampled signals to the data lines, and image signal supply lines for supplying the image signals to the switch elements. 3. The image processing apparatus according to claim 2, wherein the first coefficient of the first coefficient circuit is determined based on at least a parasitic capacitance component associated with each of the image signal supply lines and a resistance component of a counter electrode. 4. circuit. 9. The image processing apparatus according to claim 4, wherein the second coefficient of the second coefficient circuit is determined based on at least a parasitic capacitance component associated with each of the data lines and a resistance component of a common electrode. circuit. 10. An image processing circuit used in an electro-optical device, comprising: a delay circuit for delaying image data supplied from the outside by a unit time and outputting the delayed image data as delayed image data; First correction data generating means for generating first correction data based on data obtained by averaging the difference between the image data and the unit time, and calculating the difference between the image data and predetermined reference data in the unit time Second based on the data obtained by averaging every
A second correction data generating unit configured to generate correction data; and a correction unit configured to correct the delayed image data based on the first correction data and the second correction data to generate corrected image data. Characteristic image processing circuit. 11. A plurality of scanning lines, a plurality of data lines, switching elements provided corresponding to intersections of the respective scanning lines and the respective data lines, and pixels electrically connected to the switching elements. An electrode, a delay circuit that delays image data supplied from the outside by a unit time and outputs the delayed image data as delayed image data, and data obtained by averaging a difference between the image data and the delayed image data for each unit time. A first correction data generating means for generating first correction data based on the data, and a second correction data generating means based on data obtained by averaging a difference between the image data and predetermined reference data for each unit time.
A second correction data generation unit that generates correction data; a correction unit that corrects the delayed image data based on the first correction data and the second correction data to generate corrected image data; An electro-optical device, comprising: a phase expansion circuit that divides data into a plurality of phase expansion image signals and supplies the data to the plurality of data lines. 12. A data line driving circuit for sequentially generating a sampling signal, and a sampling circuit for sampling the phase-expanded image signal based on the sampling signal and supplying the sampled signal to each of the data lines. The electro-optical device according to claim 11, wherein 13. An electronic apparatus comprising the electro-optical device according to claim 11. 14. An image data processing method used in an electro-optical device for supplying an image signal to a plurality of data lines, the method comprising: delaying image data supplied from the outside by a unit time to generate delayed image data; Generating a difference between the image data and the delayed image data as first difference data; averaging the first difference data for each unit time to generate first averaged data; Is multiplied by a first coefficient to generate first correction data, a difference between the image data and predetermined reference data is generated as second difference data, and the second difference data is generated for each unit time. Averaging to generate second averaged data; multiplying the second averaged data by a second coefficient to generate second correction data; based on the first correction data and the second correction data, Late By correcting the image data to generate corrected image data, the corrected image data divided into a plurality of phase expansion image signal, the image data processing method characterized by supplying to the plurality of data lines. 15. An image data processing method used in an electro-optical device, comprising: delaying image data supplied from outside by a unit time to generate delayed image data; Generating a difference as first difference data; averaging the first difference data for each unit time to generate first averaged data; multiplying the first averaged data by a first coefficient to obtain a first averaged data; Generating correction data, generating a difference between the image data and predetermined reference data as second difference data, and averaging the second difference data for each unit time to generate second averaged data Multiplying the second averaged data by a second coefficient to generate second correction data; correcting the delayed image data based on the first correction data and the second correction data to obtain a corrected image Day Image data processing method and generates a.