JP3800926B2 - Image data processing method, image data processing circuit, electro-optical device, and electronic apparatus - Google Patents

Description

但し、(1)式において、ζは定数であり、Ｖi-1,jは、ブロックＢi-1が選択された時に対応するデータ線に供給した電圧である。
【００３７】
同様に要因２による対向電極に発生する誤差電圧は、次の(2)式で示される。
【００３８】
【数２】

但し、(2)式において、ξは定数であり、Ｖpreは、プリチャージ電圧である。よって、対向電極に発生する全誤差電圧は、次の(3)式で示される。
【００３９】
【数３】

ここで、ブロックＢiが選択終了直前では、一定の減衰係数ｋを乗じて、次式のように、画像信号を変数とした関数（以降、誤差関数ｆerrと称する）で表すことが出来る。
【００４０】
【数４】

さて、この誤差関数ｆerrで、図２０で示した前ゴーストを説明する。前ゴーストのブロックの左の画素は総て中間調なので、電圧Ｖi-1,jを例えば電圧Ｖpreと考えると、当該ブロックについても電圧Ｖi,jは電圧Ｖpreかそれ以上であり、第２項、第３項ともに非負である。そして、Ｖi,j＞Ｖpreとなる画素が多くなると、即ち黒窓がブロックにかかる幅が広くなると、式の第２項、第３項ともに増加して正の誤差が大きくなって、明るいむらとなることが解る。
【００４１】
後ゴーストについても、黒窓がブロックにかかる幅が広くなると明るいむらとなる。しかし、第２項は非負であるが、黒窓が狭くなると第３項は負の値をとる。よって、黒窓がブロックにかかる幅が狭くなると第３項が優勢となって、暗い表示となる。
【００４２】
次ゴーストでは、第２項が０となり、第３項は正にはならない。よって暗いむらが生じる。
【００４３】
以上のようにして、前ゴースト、後ゴースト、及び、次ゴーストが発生する。なお、ｈが１の場合、言い換えれば、いわゆる点順次走査駆動の場合でも、(4)式から解るようにゴーストが発生する。
【００４４】
結局、いずれにせよ、このようなゴーストが発生して、表示画像の品質が劣化してしまうといった問題があった。
【００４５】
本発明は、このような問題点に鑑みてなされたものであり、その目的は、ゴーストを除去して高い品質の画像表示を可能とする画像データ処理方法及び画像データ処理回路、これを用いた電気光学装置ならびに電子機器を提供することにある。
【００４６】
【課題を解決するための手段】
上記目的を達成するために、複数の走査線と複数のデータ線と、前記各走査線と前記各データ線の交差する部分に対応して設けられるトランジスタ及び画素電極とを具備し、前記データ線を複数本毎にまとめた各ブロックに対応する各サンプリング信号に基づいて、前記ブロックに含まれる前記各データ線に画像データ信号に基づいた電圧が同時に供給される電気光学装置に用いられる、前記画像データ信号を生成するための画像データ信号処理方法であって、一の前記ブロックに対応する基準画像データ信号を１ブロック期間遅延させた信号に補正電圧データを加算したものを当該一のブロックに対応する前記画像データ信号として出力し、前記一のブロックを対象ブロックとし、該対象ブロックより前に選択されたブロックを参照ブロックとしたとき、前記補正電圧データは、少なくとも前記対象ブロックに対応する前記基準画像データ信号と、前記参照ブロックに対応する前記画像データ信号とを用いたブロック毎の演算により生成され、前記対象ブロックと前記参照ブロックとの間での前記画像データ信号の電圧変化に基づく表示のゴーストを補正するものであることを特徴とする。
【００４７】
画素に書き込まれる電圧の誤差は、対象ブロックと参照ブロックに対応する画像データによって概ね既定されるので電圧の誤差が予測可能で、本来書き込むべき画素電圧に対応する基準画像データ信号に、予測される誤差電圧の影響を相殺させる補正電圧データを付け加えることによって、書き込み電圧の誤差を無くすることが出来、ゴーストが無くなる。
【００４８】
詳細に説明すると、本来書き込むべき基準画像信号Ｖi,j（j=1,2,…,h）の代わりに、補正電圧Ｖcmpを付け加えた画像信号Ｖi,j＋Ｖcmpを用いると、選択されている走査線行上の参照ブロックＢiのj番目の画素電圧Ｖpi,jは、次の(5)式のように表される。
【００４９】
【数５】

ここで、画素電圧Ｖpi,jが、基準画素信号Ｖi,jと等しくなれば良い。すなわち、次の(6)式を満たせば良い。
【００５０】
【数６】

これを、補正電圧Ｖcmpについて解くと、次の(7)式が成立する。
【００５１】
【数７】

なお、補正電圧Ｖcmpは、参照ブロックＢiが選択し終わった直後の対向電極に残る誤差電圧Ｖε1と一致するので、この補正電圧Ｖcmpを基準画像信号Ｖi,jに加算すればゴーストが解消するはずである。従って、予め、補正電圧Ｖcmpに対応する補正電圧データＤcmpを、基準画像データ信号Ｄintに加算した画像データ信号Ｄmodを供給することによってゴーストを解消することが可能となる。
【００５２】
さて、本件の画像データ処理方法における所定の演算方法としては、前記対象ブロックの前記基準画像データ信号のそれぞれから第１の所定の値を引いた値の総和に第２の所定の値を掛けた値と、前記対象ブロックの前記基準画像データ信号のそれぞれから対応する前記参照ブロックの前記画像データ信号のそれぞれの値を引いた値の総和に第３の所定の値を掛けた値と、前記参照ブロックの前記画像データ信号で用いた前記補正電圧データに第４の所定の値を掛けた値とを加える方法とすることが望ましい。
【００５３】
上述の補正電圧Ｖcmpを求める式の定数部分をax、（ｘは添字）で表すと、次の(8)式となる。
【００５４】
【数８】

この方法は、この(8)式に基づいて補正電圧Ｖcmpを求め、これに対応する補正電圧データＤcmpを、基準画像データ信号Ｄintに加算した画像データ信号Ｄmodを供給することによってゴーストを解消することを可能とするものである。
【００５５】
また、本件の画像データ処理方法における所定の演算方法としては、前記対象ブロックの前記基準画像データ信号のそれぞれから第１の所定の値を引いた値の総和に第２の所定の値を掛けた値と、前記対象ブロックの前記基準画像データ信号のそれぞれから対応する前記参照ブロックの前記基準画像データ信号のそれぞれの値を引いた値の総和に第３の所定の値を掛けた値と、前記参照ブロックの前記画像データ信号で用いた前記補正電圧データに第４の所定の値を掛けた値とを加える方法とすることが望ましい。
【００５６】
この方法では、先の方法で用いられる参照ブロックの画像データ信号の代わりに基準画像データ信号を用いて演算を行っている。ここで、画像データ信号と基準画像データ信号の差は、補正電圧分であり、一般にこの差は小さいので、同様の効果が得られる。
【００５７】
一方、本件の画像データ処理方法における所定の演算方法としては、前記対象ブロックの前記基準画像データ信号のそれぞれから第１の所定の値を引いた値の総和に第２の所定の値を掛けた値と、前記対象ブロックの前記基準画像データ信号のそれぞれから対応する前記参照ブロックの前記画像データ信号のそれぞれの値を引いた値の総和に第３の所定の値を掛けた値とを加える方法であることが望ましい。
【００５８】
この方法では、補正電圧データに第４の所定の値を掛けた値を用いないで演算を行う。ここで、補正電圧データに第４の所定の値を掛けた値は、一般に小さいので、同様の効果が得られるとともに演算を簡素化することが出来る。
【００５９】
さて、本件の画像データ処理方法における所定の演算方法としては、前記対象ブロックの前記基準画像データ信号のそれぞれから第１の所定の値を引いた値の総和に第２の所定の値を掛けた値と、前記対象ブロックの前記基準画像データ信号のそれぞれから対応する前記参照ブロックの前記基準画像データ信号のそれぞれの値を引いた値の総和に第３の所定の値を掛けた値とを加える方法であることが望ましい。
【００６０】
この方法では、補正電圧データに第４の所定の値を掛けた値を用いないで演算を行う。ここで、補正電圧データに第４の所定の値を掛けた値は、一般に小さいので、同様の効果が得られるとともに演算を簡素化することが出来る。
【００６１】
また、本件の画像データ処理方法における所定の演算方法としては、前記対象ブロックの前記基準画像データ信号のそれぞれ値の総和に第５の所定の値を掛けた値と、前記参照ブロックの前記画像データ信号のそれぞれの値の総和に第６の所定の値を掛けた値と、第７の所定の値と、前記参照ブロックの前記画像データ信号で用いた前記補正電圧データに第４の所定の値を掛けた値とを加える演算方法であることが望ましい。
【００６２】
補正電圧Ｖcmpを求める式を、Ｖi,jとＶi-1,jがそれぞれ独立した和の形になるように変形し、定数部分をax、（ｘは添字）で表すと、次の(9)式となる。
【００６３】
【数９】

この方法は、この(9)式に基づいて補正電圧Ｖcmpを求め、これに対応する補正電圧データＤcmpを、基準画像データ信号Ｄintに加算した画像データ信号Ｄmodを供給することによってゴーストを解消することを可能とするものである。
【００６４】
一方、本件の画像データ処理方法における所定の演算方法としては、前記対象ブロックの前記基準画像データ信号のそれぞれ値の総和に第５の所定の値を掛けた値と、前記参照ブロックの前記基準画像データ信号のそれぞれの値の総和に第６の所定の値を掛けた値と、第７の所定の値と、前記参照ブロックの前記基準画像データ信号で用いた前記補正電圧データに第４の所定の値を掛けた値とを加える方法であることが望ましい。
【００６５】
この方法では、参照ブロックの画像データ信号の代わりに基準画像データ信号を用いて演算を行っている。ここで、画像データ信号と基準画像データ信号の差は、補正電圧分であり、一般にこの差は小さいので、同様の効果が得られる。
【００６６】
また、本件の画像データ処理方法における所定の演算方法としては、前記対象ブロックの前記基準画像データ信号のそれぞれ値の総和に第５の所定の値を掛けた値と、前記参照ブロックの前記画像データ信号のそれぞれの値の総和に第６の所定の値を掛けた値と、第７の所定の値とを加える方法であることが望ましい。
【００６７】
この方法では、補正電圧データに第４の所定の値を掛けた値を用いないで演算を行う。ここで、補正電圧データに第４の所定の値を掛けた値は、一般に小さいので、同様の効果が得られるとともに演算を簡素化することが出来る。
【００６８】
また、本件の画像データ処理方法における所定の演算方法としては、前記対象ブロックの前記基準画像データ信号のそれぞれ値の総和に第５の所定の値を掛けた値と、前記参照ブロックの前記基準画像データ信号のそれぞれの値の総和に第６の所定の値を掛けた値と、第７の所定の値とを加える方法であることが望ましい。
【００６９】
この方法では、補正電圧データに第４の所定の値を掛けた値を用いないで演算を行う。ここで、補正電圧データに第４の所定の値を掛けた値は、一般に小さいので、同様の効果が得られるとともに演算を簡素化することが出来る。
【００７０】
結局、本件の画像データ処理方法における所定の演算方法としては、請求項２乃至９記載のいずれかの演算方法と同じ演算結果となる演算方法であれば良い。すなわち、演算方法としては、上述した各種の方法に限定されるものではなく、同じ演算結果が得られれば、ゴーストを解消することが出来る。
【００７１】
次に、上記目的を達成するために、本発明は、複数の走査線と複数のデータ線と、前記各走査線と前記各データ線の交差する部分に対応して設けられるトランジスタ及び画素電極とを具備し、前記データ線を複数本毎にまとめた各ブロックに対応する各サンプリング信号に基づいて、前記ブロックに含まれる前記各データ線に画像データ信号に基づいた電圧が同時に供給される電気光学装置に用いられる、前記画像データ信号を生成する画像データ信号処理回路であって、一の前記ブロックに対応する基準画像データ信号を１ブロック期間遅延させた信号に補正電圧データを加算したものを当該一のブロックに対応する前記画像データ信号として出力し、前記一のブロックを対象ブロックとし、該対象ブロックより前に選択されたブロックを参照ブロックとしたとき、少なくとも前記対象ブロックに対応する基準画像データ信号と前記参照ブロックに対応する前記画像データ信号とを用いてブロック毎に演算して生成された、前記対象ブロックと前記参照ブロックとの間での前記画像データ信号の電圧変化に基づく表示のゴーストを補正するための前記補正電圧データを求める演算処理回路を具備することを特徴とする。
本発明は、上記画像データ処理方法を具現する回路であり、画像データ処理方法について先に述べた同様な効果が得られる。
【００７２】
さて、本件の画像データ処理回路における演算処理回路としては、前記対象ブロックの前記基準画像データ信号のそれぞれから第１の所定の値を引いた値の総和に第２の所定の値を掛けた値と、前記対象ブロックの前記基準画像データ信号のそれぞれから対応する前記参照ブロックの前記画像データ信号のそれぞれの値を引いた値の総和に第３の所定の値を掛けた値と、前記参照ブロックの前記画像データ信号で用いた前記補正電圧データに第４の所定の値を掛けた値とを加える演算を行う回路である構成が望ましい。この構成は、上記画像データ処理方法を具現する回路であり、この構成によれば、画像データ処理方法について先に述べた同様な効果が得られる。
【００７３】
また、本件の画像データ処理回路における演算処理回路としては、前記対象ブロックの前記基準画像データ信号のそれぞれから第１の所定の値を引いた値の総和に第２の所定の値を掛けた値と、前記対象ブロックの前記基準画像データ信号のそれぞれから対応する前記参照ブロックの前記基準画像データ信号のそれぞれの値を引いた値の総和に第３の所定の値を掛けた値と、前記参照ブロックの前記画像データ信号で用いた前記補正電圧データに第４の所定の値を掛けた値とを加える演算を行う回路である構成が望ましい。この構成は、上記画像データ処理方法を具現する回路であり、この構成によれば、画像データ処理方法について先に述べた同様な効果が得られる。
【００７４】
一方、本件の画像データ処理回路における演算処理回路としては、前記対象ブロックの前記基準画像データ信号のそれぞれから第１の所定の値を引いた値の総和に第２の所定の値を掛けた値と前記対象ブロックの前記基準画像データ信号のそれぞれから対応する前記参照ブロックの前記画像データ信号のそれぞれの値を引いた値の総和に第３の所定の値を掛けた値とを加える演算を行う回路である構成が望ましい。この構成は、上記画像データ処理方法を具現する回路であり、この構成によれば、画像データ処理方法について先に述べた同様な効果が得られる。
【００７５】
さて、本件の画像データ処理回路における演算処理回路としては、前記対象ブロックの前記基準画像データ信号のそれぞれから第１の所定の値を引いた値の総和に第２の所定の値を掛けた値と、前記対象ブロックの前記基準画像データ信号のそれぞれから対応する前記参照ブロックの前記基準画像データ信号のそれぞれの値を引いた値の総和に第３の所定の値を掛けた値とを加える演算を行う回路である構成が望ましい。この構成は、上記画像データ処理方法を具現する回路であり、この構成によれば、画像データ処理方法について先に述べた同様な効果が得られる。
【００７６】
また、本件の画像データ処理回路における演算処理回路としては、前記対象ブロックの前記基準画像データ信号のそれぞれ値の総和に第５の所定の値を掛けた値と、前記参照ブロックの前記画像データ信号のそれぞれの値の総和に第６の所定の値を掛けた値と、第７の所定の値と、前記参照ブロックの前記画像データ信号で用いた前記補正電圧データに第４の所定の値を掛けた値とを加える演算を行う回路である構成が望ましい。この構成は、上記画像データ処理方法を具現する回路であり、この構成によれば、画像データ処理方法について先に述べた同様な効果が得られる。
【００７７】
一方、本件の画像データ処理回路における演算処理回路としては、前記対象ブロックの前記基準画像データ信号のそれぞれ値の総和に第５の所定の値を掛けた値と、前記参照ブロックの前記画像データ信号のそれぞれの値の総和に第６の所定の値を掛けた値と、第７の所定の値と、前記参照ブロックの前記基準画像データ信号で用いた前記補正電圧データに第４の所定の値を掛けた値とを加える演算を行う回路である構成が望ましい。この構成は、上記画像データ処理方法を具現する回路であり、この構成によれば、画像データ処理方法について先に述べた同様な効果が得られる。
【００７８】
また、本件の画像データ処理回路における演算処理回路としては、前記対象ブロックの前記基準画像データ信号のそれぞれ値の総和に第５の所定の値を掛けた値と、前記参照ブロックの前記画像データ信号のそれぞれの値の総和に第６の所定の値を掛けた値と、第７の所定の値とを加える演算を行う回路である構成が望ましい。この構成は、上記画像データ処理方法を具現する回路であり、この構成によれば、画像データ処理方法について先に述べた同様な効果が得られる。
【００７９】
また、本件の画像データ処理回路における演算処理回路としては、前記対象ブロックの前記基準画像データ信号のそれぞれ値の総和に第５の所定の値を掛けた値と、前記参照ブロックの前記基準画像データ信号のそれぞれの値の総和に第６の所定の値を掛けた値と、第７の所定の値とを加える演算を行う回路である構成が望ましい。この構成は、上記画像データ処理方法を具現する回路であり、この構成によれば、画像データ処理方法について先に述べた同様な効果が得られる。
【００８０】
結局、本件の画像データ処理回路における演算処理回路としては、請求項１２乃至１９記載のいずれかと同じ演算結果となる回路構成であれば良い。すなわち、演算処理回路の構成は、上述した各種の構成に限定されるものではなく、同じ演算結果が得られれば、ゴーストを解消することが出来る。
【００８１】
次に、上記目的を達成するために、本件の電気光学装置は、請求項１１乃至２０記載の画像データ処理回路と、該画像データ処理回路の出力するデジタル信号である画像データ信号をアナログ信号に変換するＤ／Ａ変換回路と、該Ｄ／Ａ変換回路が出力する画像信号を、前記ブロックを構成する画像信号線の数に応じて時間軸伸張するとともに並列化する並列化回路と、前記走査線を順次選択する走査線駆動回路と、前記画像信号線を複数本毎にまとめたブロックを順次選択する各サンプリング信号を生成するデータ線駆動回路と、各サンプリング信号に基づいて前記並列化画像信号を、選択されたブロックに属するデータ線の各々に供給する画像信号供給回路とを備えたことを特徴としている。
【００８２】
この電気光学装置によれば、表示画像の品質を大幅に向上させることができるとともに、ブロック単位でデータ線に画像信号を供給することができるので、データ線駆動回路の構成を簡易にすることができ、かつその消費電力を低減することが出来る。
【００８３】
同様に、上記目的を達成するために、本件の別の電気光学装置は、請求項１１乃至２０記載の画像データ処理回路と、画像データ処理回路の出力する画像データ信号を、前記ブロックを構成する画像信号線の数に応じて時間軸伸張するとともに並列化する並列化回路と、該並列化回路の出力する画像データ信号をアナログ信号に変換するＤ／Ａ変換回路と、前記走査線を順次選択する走査線駆動回路と、前記画像信号線を複数本毎にまとめたブロックを順次選択する各サンプリング信号を生成するデータ線駆動回路と、各サンプリング信号に基づいて前記並列化画像信号を選択されたブロックに属するデータ線の各々に供給する画像信号供給回路とを備えたことを特徴としている。
【００８４】
この電気光学装置によれば、表示画像の品質を大幅に向上させることができるとともに、ブロック単位でデータ線に画像信号を供給することができるので、データ線駆動回路の構成を簡易にすることができ、かつその消費電力を低減することが出来る。
【００８５】
さらに、上記目的を達成するために、本件の電子機器は、請求項２１または２２に記載の電気光学装置を備えたことを特徴としている。このような電子機器としては、例えば、ビデオプロジェクタや、ノート型パーソナルコンピュータ、携帯電話機等が該当する。
【００８６】
【発明の実施の形態】
以下、本発明の実施形態について図面を参照して説明をする。
【００８７】
＜第１の実施形態＞
まず、電気光学装置の一例として、本発明の第１実施形態に係るアクティブマトリクス型液晶表示装置について説明する。
【００８８】
図１は、本発明の液晶表示装置の全体構成を示すブロック図である。図において、１００は液晶表示パネル、２００はタイミング回路、３００Ａは画像信号処理回路であり、これらで液晶表示装置が構成されている。このうち、タイミング回路２００は、各部で使用されるタイミング信号（必要に応じて後述する）を出力するものである。
【００８９】
また、３０１はＤ／Ａ変換回路、３０２は相展開回路、３０３が増幅・反転回路、３１０Ａはデータ補正回路で、これらで画像信号処理回路３００Ａが構成されている。本実施形態に係る液晶表示装置は、画像信号処理回路３００Ａにおいて、データ補正回路３１０ＡをＤ／Ａ変換回路３０１の前段に設けた点を除いて、図１６に示す従来の液晶表示装置と同様に構成されているので、共通部分には、同一符号を付して説明の重複を避ける。なお、Ｄintは、図示せぬ外部装置等から供給される基準画像データ信号であり、Ｄmodは、データ補正回路３１０Ａから出力される画像データ信号である。ここで、従来技術の説明にあっては、Ｄintを画像データ信号と呼称したが、以後、このように呼称を変更する。また、基準画像データ信号Ｄintは、通常、複数ビットからなる。
【００９０】
そして、Ｄ／Ａ変換回路３０１は、画像データＤmodをアナログ信号に変換して画像信号VIDとして出力する。更に、相展開回路３０２は、一連の画像信号VIDを入力すると、ｈ相の画像信号に展開して出力するものである。本実施形態では、ｈは、６の場合について説明をするが、無論これに限定するものではなく、一以上の整数の任意の数で構わない。
【００９１】
また、反転・増幅回路３０３は、画像信号を所定の規則に従って極性反転させ、あるいは、そのままで適宜、増幅して、相展開された画像信号VID1〜VID6として液晶表示パネル１００に供給するものである。
【００９２】
図２はデータ補正回路３１０Ａの一構成例を示す図である。この図において、４０１は減算を行う演算回路であり、基準画像データ信号から所定の数値a1を引く。４０２は加算器であり、演算回路４０１の出力値を累積加算する。後で詳細説明する。４０３は乗算を行う演算回路であり、加算器４０２の出力値に所定の係数a2を掛けた値を出力する。本実施形態では、これを、読み出し専用メモリ等を用いた参照表等で構成してある。即ち、加算器４０２の出力値をメモリのアドレスとし、当該アドレス上のデータをアドレス値に係数a2を掛けた値にしてある。
【００９３】
一方、４０４は遅延回路であり、基準画像データＤintを取り込み、遅延して出力する。本実施形態では、６段のシフトレジスタ回路からなる。遅延して出力されるデータ信号を遅延基準データ信号と呼称し、記号Ｄdlyで表すことにする。そして、４０５は加算を行う演算回路であり、遅延回路４０４の出力と、後述する保持回路４１１の出力の値とを加算する。出力値は画像データ信号Ｄmodとなる。
【００９４】
さて、４０６は減算を行う演算回路であり、基準画像データ信号Ｄintから画像データ信号Ｄmodを引く。４０７は加算器であり、演算回路４０６の出力値を累積加算する。後で詳細説明する。４０８は乗算を行う演算回路であり、加算器４０７の出力値に所定の係数a3を掛けた値を出力する。本実施形態では、これを、読み出し専用メモリ等を用いた参照表等で構成してある。４０９は加算を行う演算回路で、演算回路４０３の出力と演算回路４０８の出力の値を加算する。そして、４１０は加算を行う演算回路であり、演算回路４０９の出力と、後述する演算回路４１３の出力の値とを加算する。
【００９５】
つぎに、４１１と４１２とは、それぞれデータを保持する保持回路で、それぞれ演算回路４１０の出力と保持回路４１１の出力とを保持する。本実施形態では、この回路をラッチ回路で構成してある。４１３は、乗算を行う演算回路であり、保持回路４１２の出力値に所定の係数a4を掛けた値を出力する。本実施形態では、これを、読み出し専用メモリ等を用いた参照表等で構成してある。
【００９６】
ここで、図１のタイミング回路２００から、データ補正回路３１０Ａに制御信号として、クロック信号CLKとラッチパルス信号LPとが与えられる。クロック信号CLKは、加算器４０２、４０８及び遅延回路４０４のクロック信号として用いられ、ラッチパルス信号LPは保持回路４１１、４１２のクロック信号として、また、加算器４０２、４０８の制御信号として用いられる。なお、基準画像データＤintは、クロック信号CLKの立ち上がりに同期して変化し、データ補正回路３１０Ａに入力するものとする。また、図中のp1〜p4は内部信号線の名称で、それぞれ加算器４０２、４０８、保持回路４１１、４１２の出力信号を示す。
【００９７】
図３は加算器４０２または４０８の一構成例を示す図である。図において、５０１は加算を行う演算回路、５０２はデータセレクタ回路、５０３は保持回路である。演算回路５０１は保持回路の出力値Ｄoutと入力値Ｄinとを加算する。データセレクタ回路５０２は、入力値Ｄinまたは加算回路５０１の出力値のいずれかを選択し、出力する。これはラッチパルス信号LPによって制御され、信号LPが能動の時に入力値Ｄinを、非能動の時に加算回路５０１の出力値を、それぞれ選択する。保持回路５０３は、クロック信号CLKの立ち下がりに同期してデータセレクタ回路５０２の出力値を取り込み、保持する。
【００９８】
従って、信号LPが能動な時に信号CLKが立ち下がると、保持回路５０３には入力値Ｄinが取り込まれ、その後、信号LPが非能動となり、再び信号CLKが立ち下がると、今度は保持回路５０３の値に入力値Ｄinを加算した値が、保持回路５０３に取り込まれる。その後、信号LPが非能動な期間中、信号CLKが立ち下がる度に、保持回路５０３の値に入力値Dinを加算した値が、保持回路５０３に取り込まれることになり、累積加算することになる。
【００９９】
図１及び図２のデータ補正回路３１０Ａの構成は以上のようになっている。
【０１００】
次に、動作を説明する。図４は、データ補正回路３１０Ａの動作を示すタイミング図である。図において、上からタイミング回路２００が出力するクロック信号CLK、ラッチパルス信号LP、基準画像データ信号Ｄint、内部信号p1〜p4、遅延基準画像データ信号Ｄdly、画像データ信号Ｄmodを示す。横軸は時間である。クロック信号CLKの１周期の時間をtcとすると、ラッチパルス信号LPの周期はそのｈ(=6)倍になり、その周期をtbとする。ここで、信号LPが能動（図中、上のレベル）となる期間は1・tcである。また、ラッチパルス信号LPの立ち上がりから次の立ち上がりまでを１ブロック期間とする。そして、液晶表示パネル１００のｉ番目のブロックＢiに対応する基準画像データ信号Ｖi,jが外部機器から供給されている期間を、第ｉブロック期間とし、続くブロック期間を第i+1ブロック期間とする。
【０１０１】
ここで、記号αi,j（i=1,2,…,q、j=1,2,…,6）は、液晶表示パネル１００のｉ番目のブロックＢiの中のｊ番目のデータ線と、現在選択されている走査線行とが交差する場所の画素に対応する基準画像データ信号Ｄintの内容を示す。同様に、記号βi,j（i=1,2,…,q、j=1,2,…,6）は、液晶表示パネル１００のｉ番目のブロックＢiの中のｊ番目のデータ線と、現在選択されている走査線行とが交差する部分に対応する画像データ信号Ｄmodの内容を示す。また、記号γi,1は、基準画像データ信号αi,1から所定の定数ａ1を引いた値を示す。これに続く記号Σγ1〜2は、γi,1に基準画像データ信号αi,2からa1を引いた値を加えた値を示し、記号Σγ1〜3は、Σγ1〜2に基準画像データ信号αi,3からa1を引いた値を加えた値を示し、以下同様に累積加算値を示す。次に、記号δi,1は、基準画像データ信号αi,1から画像データ信号βi-1,1を引いた値を示す。これに続く記号Σδ1〜2は、δi,1に基準画像データ信号αi,2から画像データ信号βi-1,2を引いた値を加えた値を示し、記号Σδ1〜3は、Σδ1〜2に基準画像データ信号αi,3から画像データ信号βi-1,3を引いた値を加えた値を示し、以下同様に累積加算値を示す。また、記号Ｄcmpiは、ブロックＢiに対応する基準画像データ信号Ｄintに付け加える補正電圧データの値を示す。
【０１０２】
まず、クロック信号CLKの立ち上がりに同期して、第iブロック期間の始めから、外部から供給される基準画素データ信号Ｄintは、ブロックＢiに対応する値であるαi,1、αi,2、…、αi,6をとり、続く、第i+1ブロック期間では、ブロックＢi+1に対応する値であるαi+1,1、αi+1,2、…、αi+1,6となり、以下順次繰り返される。
【０１０３】
ここで、演算回路４０１は、基準画像データ信号αi,1から定数a1を引き、値γi,1を得る。この時、信号LPは能動であるから、信号CLKの立ち下がりに同期して、加算器４０２に取り込まれ、保持される。次に、演算回路４０１は、基準画像データ信号αi,2から定数a1を引き、値γi,2を得る。この時、信号LPは非能動であるから、信号CLKの立ち下がりに同期して、加算器４０２に保持されていた値γi,1と値γi,2とを加算した値Σγ1〜2を保持する。以下、ブロック期間まで同様に累積加算される。これを信号p1として図示する。
【０１０４】
次に、演算回路４０６は、基準画像データ信号αi,1から画像データ信号βi-1,1を引き、値δi,1を得る。この時、信号LPは能動であるから、信号CLKの立ち下がりに同期して、加算器４０７に取り込まれ、保持される。次に演算回路４０６は基準画像データ信号αi,2から画像データ信号βi-1,2を引き、値δi,2を得る。この時、信号LPは非能動であるから、信号CLKの立ち下がりに同期して、加算器４０７に保持されていた値δi,1と値δi,2とを加算した値Σδ1〜2を保持する。以下、ブロック期間まで同様に累積加算される。これを信号p2として図示する。
【０１０５】
すると、ブロック期間の終わりにおいて、加算器４０２には、ブロックＢiのそれぞれの基準画像データ信号αi,jから定数a1を引いた値の総和Σγ1〜6が保持される一方、加算器４０７には、ブロックＢiのそれぞれの基準画像データ信号αi,2からブロックＢi-1の対応する画像データ信号βi-1,jを引いた値の総和Σδ1〜6が保持される。これらの値はそれぞれ乗算器４０３、４０８で定数a2、a3倍され、更に演算回路４０９で、両方の値が加算される。
【０１０６】
そして、この演算回路４０９の値と乗算器４１３の出力値とを演算回路４１０で加算する。この値が補正電圧データＤcmpiとなり、信号LPの立ち上がりに同期して保持回路４１１に取り込まれ保持される。これを信号p3として図示する。
【０１０７】
次に、遅延回路４０４は、外部から入力される基準画素データ信号Ｄintを信号CLKの立ち上がりに同期して取り込み、１ブロック期間(tb)だけ遅らせた遅延基準画素データ信号を出力する。この信号Ｄdlyとして図示する。
【０１０８】
そして、演算回路４０５は、遅延基準画素データ信号の値に保持回路４１１の値、即ち補正電圧データＤcmpiを加えて、画素データ信号Ｄmodとして出力する。即ち、ブロックＢiに対応する画像データ信号Ｄmodは、第i+1ブロック期間に出力される。
【０１０９】
最後に、保持回路４１２は、保持回路４１１の値を信号LPの立ち上がりに同期して取り込み保持する。即ち、１ブロック期間だけ前に用いた補正電圧データＤcmpi-1、言い換えれば誤差電圧データを取り込み、保持する。これを信号p4として図示する。従って、乗算器４１３の出力は誤差電圧データに定数a4を掛けたものとなる。
【０１１０】
以上の動作をするので、保持回路４１１には、ブロックＢiの基準画像データ信号Ｄintのそれぞれの値から定数a1を引いた値の総和Σγ1〜6に定数a2を乗じた値と、ブロックＢiの基準画像データ信号ＤintのそれぞれからブロックＢi-1の対応する画像データ信号Ｄmodのそれぞれを引いた値の総和Σδ1〜6に定数a3を乗じた値と、１ブロック期間だけ前の誤差電圧データに定数a4を乗じた値との和の値が保持され、この値が電圧補正データＤcmpとして用いられる。この値は、(8)式の値に他ならない。よって、これを基準画素データ信号Ｄintに加算して、画像データ信号Ｄmodを作って液晶表示パネル１００を駆動することにより、ゴーストが解消される。
【０１１１】
＜第２の実施形態＞
他の実施形態について、図を用いて説明する。図５は、液晶表示装置の全体構成を示すブロック図である。図において、３００Ｂは画像信号処理回路であり、さらに、画像信号処理回路３００Ｂを構成する３１０Ｂはデータ補正回路である。なお、このデータ補正回路３１０Ｂ以外の構成及び動作は、図１の液晶表示装置と同じであるので、同一符号を付して、説明の重複を避けることとする。
【０１１２】
図６は、データ補正回路３１０Ｂの一構成例を示す図である。図において、演算回路４０６に入力するデータ信号が、基準画像データ信号Ｄintと遅延回路４０４の出力する遅延基準画像データ信号とであることを除くと、図２のデータ補正回路３１０Ａと同じであるので、同一符号を付して、説明の重複を避ける。
【０１１３】
以上の構成となっている。ここで、図２のデータ補正回路３１０Ａとの違いは、演算回路４０６に入力するデータ信号として、データ補正回路３１０Ａでは画像データＤmodを用いているのに対し、図６のデータ補正回路３１０Ｂでは遅延回路４０４の出力する遅延基準画像データ信号Ｄdlyを用いている点だけである。ここで、画像データ信号Ｄmodは、遅延基準画像データ信号Ｄdlyに補正電圧データＤcmpを付け加えたものである。そして、補正電圧データＤcmpの絶対値はそれほど大きくはないので、画像データ信号Ｄmodと遅延基準画像データ信号Ｄdlyとの差は小さい。
【０１１４】
よって、画像データ信号Ｄmodの代わりに遅延基準画像データ信号Ｄdlyを用いて、補正電圧データＤcmpを求めて、これに基づいて基準画像データ信号Ｄintに補正を加えても、第１の実施形態と同様にゴーストを解消することが出来る。また、遅延基準画像データ信号Ｄdlyを直接、演算回路４０６へ入力出来るので、データ補正回路３１０Ｂを実際に作る際に、回路素子の動作速度を必要以上に速くすることが無く、製造が容易になる。
【０１１５】
＜第３の実施形態＞
他の実施形態について、図を用いて説明する。図７は、液晶表示装置の全体構成を示すブロック図である。図において、３００Ｃは画像信号処理回路であり、さらに、画像信号処理回路３００Ｃを構成する３１０Ｃはデータ補正回路である。なお、このデータ補正回路３１０Ｃ以外の構成及び動作は、図１の液晶表示装置と同じであるので、同一符号を付して、説明の重複を避ける。
【０１１６】
図８は、データ補正回路３１０Ｃの一構成例を示す図である。図において、保持回路４１１に入力する信号が演算回路４０９であり、演算回路４１０、保持回路４１２、乗算器４１３が省略されていることを除くと、図２のデータ補正回路３１０Ａと同じであるので、同一符号を付して、説明の重複を避ける。
【０１１７】
以上の構成となっている。ここで、図２のデータ補正回路３１０Ａとの違いは、演算回路４０９の出力信号が、補正電圧データを保持する保持回路４１１に入力している点である。即ち、本実施形態にあっては、補正電圧データの計算に、図２のデータ補正回路３１０Ａでは用いていた、データ誤差電圧データに定数a4を掛けた値を用いず省略している。ここで、データ誤差電圧データに定数a4を掛けた値は、小さい場合が多いので、これの有無によって補正電圧データが大きく影響することは少ない。よって、このような構成で補正電圧データを求めて、これに基づいて基準画像データ信号に補正を加えても、第１の実施形態と同様にゴーストを解消することが出来る。また、回路構成が簡素化され、製造が容易になる。
【０１１８】
＜第４の実施形態＞
他の実施形態について、図を用いて説明する。図９は、液晶表示装置の全体構成を示すブロック図である。図において、３００Ｄは画像信号処理回路であり、さらに、画像信号処理回路３００Ｄを構成する３１０Ｄはデータ補正回路である。なお、このデータ補正回路３１０Ｄ以外の構成及び動作は、図７の液晶表示装置と同じであるので、同一符号を付して、説明の重複を避ける。
【０１１９】
図１０は、データ補正回路３１０Ｄの一構成例を示す図である。図において、演算回路４０６に入力するデータ信号が、基準画像データ信号Ｄintと遅延回路４０４の出力する遅延基準画像データ信号Ｄdlyとであることを除くと、図８のデータ補正回路３１０Ｃと同じであるので、同一符号を付して、説明の重複を避ける。
【０１２０】
以上の構成となっている。ここで、図２のデータ補正回路３１０Ｃとの違いは、演算回路４０６に入力するデータ信号として、データ補正回路３１０Ｃでは画像データＤmodを用いているのに対し、図１０のデータ補正回路３１０Ｄでは遅延回路４０４の出力する遅延基準画像データ信号Ｄdlyを用いている点だけである。ここで、画像データ信号Ｄmodは、遅延基準画像データ信号Ｄdlyに補正電圧データＤcmpを付け加えたものである。そして、補正電圧データＤcmpの絶対値はそれほど大きくはないので、画像データ信号Ｄmodと遅延基準画像データ信号Ｄdlyとの差は小さい。
【０１２１】
よって、画像データ信号Ｄmodの代わりに遅延基準画像データ信号Ｄdlyを用いて、補正電圧データＤcmpを求め、これに基づいて基準画像データ信号Ｄintに補正を加えても、第１の実施形態と同様にゴーストを解消することが出来る。また、遅延基準画像データ信号Ｄdlyを直接、演算回路４０６へ入力出来るのでデータ補正回路３１０Ｂを実際に作る際に、素子の動作速度を必要以上に速くすることが無く、製造が容易になる。
【０１２２】
＜第５の実施形態＞
他の実施形態について、図を用いて説明する。図１１は、液晶表示装置の全体構成を示すブロック図である。図において、３００Ｅは画像信号処理回路であり、さらに、画像信号処理回路３００Ｅを構成する３１０Ｅはデータ補正回路である。なお、このデータ補正回路３１０Ｅ以外の構成及び動作は、図１の液晶表示装置と同じであるので、同一符号を付して、説明の重複を避ける。
【０１２３】
図１２は、データ補正回路３１０Ｅの一構成例を示す図である。図において、演算回路４０６と４０１とが省略され、基準画像データ信号Ｄint、画像データ信号Ｄmodが直接、それぞれ加算器４０２、４０７に入力する点と、演算回路４０９と４１０との間に加算演算を行う演算回路４１４が新たに設けられた点とを除くと、図２のデータ補正回路３１０Ａと同じ構成となっている。
【０１２４】
但し、乗算器４０３、４０８はそれぞれ、所定の定数a5、a6倍の乗算演算を行い、また、演算回路４１４は、演算回路４０９の値に所定の値a7を加算する構成となっている。
【０１２５】
以上の構成となっているので、各ブロック期間の終わりでは、加算器４０２には画像データ信号の総和の値が保持される一方、加算器４０７には画像データ信号の総和の値が保持される。そして、乗算器４０３、４０８でそれぞれの値が、それぞれa5、a6倍にされた後、演算回路４０９で両者の和を得る。更に、この和に、演算回路４１４で定数a7が加算され、更に、乗算器４１３の出力値が加算される。この値が、保持回路４１１に保持され、補正電圧データとして用いられる。この値は、(9)式の値に他ならない。よって、これを基準画素データ信号に加算することにより、ゴーストが解消される。
【０１２６】
＜第６の実施形態＞
次に、本発明の第６の実施形態に係る液晶表示装置について説明する。この液晶表示装置は、画像信号処理回路内の構成要素であるデータ補正回路を、次のような構成に変更したものである。すなわち、この第６の実施形態では、第５の実施形態で用いたデータ補正回路３１０Ｅ（図１２参照）において、加算器４０７に入力するデータ信号を、画像データ信号の代わりに遅延画像データ信号に置き換えた構成としたものである。これにより、第２の実施形態の説明で説明したのと同様効果が得られる。
【０１２７】
＜第７の実施形態＞
続いて、本発明の第７の実施形態に係る液晶表示装置について説明する。この液晶表示装置は、画像信号処理回路内の構成要素であるデータ補正回路を、次のような構成に変更したものである。すなわち、この第７の実施形態では、第５の実施形態で用いたデータ補正回路３１０Ｅにおいて、乗算器４１３の出力する値を補正電圧データの計算に用いない構成としたものである。これにより、第３の実施形態の説明で説明したのと同様効果が得られる。
【０１２８】
＜第８の実施形態＞
さらに、本発明の第８の実施形態に係る液晶表示装置について説明する。この液晶表示装置は、画像信号処理回路内の構成要素であるデータ補正回路を、次のような構成に変更したものである。すなわち、この第８の実施形態では、第５のの実施形態で用いたデータ補正回路３１０Ｅにおいて、乗算器４１３の出力する値を補正電圧データの計算に用いない構成とするとともに、加算器４０７に入力するデータ信号を、画像データ信号の代わりに遅延画像データ信号に置き換えた構成としたものである。これにより、第４の実施形態の説明で説明したのと同様効果が得られる。
【０１２９】
＜他の実施形態＞
以上、(8)式、(9)式に基づいて、演算回路構成を説明してきたが、本発明は、これに限定するものではなく、(8)式、(9)式と同じ演算結果が得られれば、他の回路構成にしても構わない。例えば、図２のデータ補正回路３１０Ａでは、加算器４０２、４０７のそれぞれの後に、乗算器４０３、４０８で乗算演算を行っているが、これらの乗算器４０３、４０８を加算器４０２、４０７の前に持ってきて、先に乗算演算を行った後に加算演算を行っても、第１の実施形態と同様の効果が得られる。
【０１３０】
また、上述した各実施形態に係る液晶表示装置は、画像データ処理回路３００Ａ〜３００Ｅ等から出力された画像データ信号を、Ｄ／Ａ変換回路３０１でアナログ信号に変換し、液晶表示パネル１００のブロックを構成する画像信号線の数に応じて時間軸伸張するとともに並列化して、液晶表示パネル１００へ供給して、いわゆるアナログ相展開を行う構成となっている。本発明は、これに限られず、これをデジタル相展開で行っても良い。これによっても同様の効果が得られることになる。
【０１３１】
＜電子機器＞
次に、上述した各実施形態で説明した液晶表示装置を電子機器に用いた例の幾つかについて説明する。
【０１３２】
＜その１：プロジェクタ＞
まず、この液晶表示装置をライトバルブとして用いたプロジェクタについて説明する。図１３はプロジェクタの一構成例を示す平面図である。
【０１３３】
１３００はプロジェクタであり、１３０１はハロゲンランプ等の白色光源からなるランプユニット、１３０２はライトガイド、１３０３はミラー、１３０４はダイクロイック・ミラー、１３０５Ｒ、１３０５Ｇ、１３０５Ｂはそれぞれ液晶パネル、１３０６はダイクロイック・プリズム、１３０７は投射レンズである。
【０１３４】
ここで、ランプユニット１３０１から射出された投射光は、ライトガイド１３０２内に配置されている４枚のミラー１３０３及び２枚のダイクロイック・ミラー１３０４によって赤、青、緑の３原色に分離され、各原色に対応するライトバルブとしての液晶パネル１３０５Ｒ、１３０５Ｇ、１３０５Ｂに入射される。
【０１３５】
液晶パネル１３０５Ｒ、１３０５Ｇ、１３０５Ｂの構成は、上述した液晶表示パネル１００と同等であり、図示しない画像信号処理回路から供給される赤、青、緑の各原色の画像データ信号でそれぞれ駆動される。そして、これらの液晶パネルによって変調された光は、ダイクロイック・プリズム１３０６に３方向から入射される。このうち、ダイクロイック・プリズム１３０６に入射した赤及び青の光は直角に反射し、緑の光は直進する。従って、各色の画像が合成される結果、投射レンズ１３０７を介して、スクリーン等にカラー画像が投射されることになる。
【０１３６】
上述したように、本発明の液晶表示装置は、基準画像データ信号に補正電圧データを付け加えたものを各液晶パネル１３０５Ｒ、１３０５Ｇ、１３０５Ｂの画像データ信号として供給するので、ゴーストの発生を抑えることが出来、表示画像の品質を大幅に改善することが出来る。
【０１３７】
＜その２：モバイル型コンピュータ＞
次に、本発明の液晶表示装置をモバイル型コンピュータに適用した例について説明する。図１４はコンピュータの構成を示す斜視図である。１４００はコンピュータであり、１４０１は本体、１４０２はキーボード、１４０３は表示部、１４０４は液晶表示装置である。本体１４０１にはキーボード１４０２等を備え、表示部１４０３には、液晶表示装置１４０４が備わっている。ここで用いられている液晶表示装置１４０４には、先に述べた液晶表示パネル１００の背面に、バックライトや反射板等が付け加えられている。これについても、ゴーストの発生を抑えることが出来、表示画像の品質を大幅に改善することが出来る。
【０１３８】
＜その３：携帯電話＞
更に、本発明の液晶表示装置を携帯電話に適用した例について説明する。図１５は携帯電話の構成を示す斜視図である。１５００は携帯電話であり、１５０１は操作釦、１５０２は液晶表示装置である。携帯電話１５００は、操作釦１５０１と液晶表示装置１５０２とを備えている。ここで、液晶表示装置１５０２の液晶表示パネルの背面には反射板が設けてあり、また前面には必要に応じてフロントライトが設けられている。これについても表示画像の品質を大幅に改善することが出来る。
【０１３９】
以上、図１３〜図１５を参照して説明した電子機器の他にも、液晶テレビやビューファインッダ型やモニタ直視型のビデオテープレコーダ、カーナビゲーション装置、ページャー、電子手帳、電卓、ワードプロセッサ、ワークステーション、テレビ電話、ＰＯＳ端末、タッチパネルを備えた装置等々が挙げられる。そして、これらの各種電子機器に適用可能なのは言うまでもない。
【０１４０】
【発明の効果】
以上説明したように本発明によれば、データ線を一乃至複数の本毎にまとめた各ブロックに対応する各サンプリング信号に基づいて、ブロック毎に各データ線に対応する画像信号を同時に供給し、これを各ブロックについて順次実行する場合に、表示画像に表れるゴーストを予め予測し、これを補償するように画像データ信号を補正するので、表示画像の品質を大幅に向上させることが出来る。
【図面の簡単な説明】
【図１】 本発明の第１の実施形態に係る液晶表示装置の全体構成を示すブロック図である。
【図２】 データ補正回路３１０Ａの一構成例を示す図である。
【図３】 加算器４０２と４０８の一構成例を示す図である。
【図４】 データ補正回路３１０Ａの動作を示すタイミング図である。
【図５】 本発明の第２の実施形態の液晶表示装置の全体構成を示すブロック図である。
【図６】 データ補正回路３１０Ｂの一構成例を示す図である。
【図７】 本発明の第３の実施形態の液晶表示装置の全体構成を示すブロック図である。
【図８】 データ補正回路３１０Ｃの一構成例を示す図である。
【図９】 本発明の第４の実施形態の液晶表示装置の全体構成を示すブロック図である。
【図１０】 データ補正回路３１０Ｄの一構成例を示す図である。
【図１１】 本発明の第５の実施形態の液晶表示装置の全体構成を示すブロック図である。
【図１２】 データ補正回路３１０Ｅの一構成例を示す図である。
【図１３】 液晶表示装置を適用した電子機器の一例たるプロジェクタの一構成例を示す平面図である。
【図１４】 液晶表示装置を適用した電子機器の一例たるコンピュータの構成を示す斜視図である。
【図１５】 液晶表示装置を適用した電子機器の一例たる携帯電話の構成を示す斜視図である。
【図１６】 従来の液晶表示装置の構成を示す図である。
【図１７】 従来の相展開回路３０２の一構成例を示す図である。
【図１８】 従来の他の相展開の方法を示す図である。
【図１９】 従来の液晶表示パネル１００の構成を示す図である。
【図２０】 従来の液晶表示パネルの表示内容及びゴーストの一部を示す図である。
【図２１】 液晶表示パネルのゴーストの発生機構を説明する電気等価回路を示す図である。
【符号の説明】
１００……液晶表示パネル
２００……タイミング回路
３００Ａ…画像信号処理回路
３０１……Ｄ／Ａ変換回路
３０２……相展開回路
３０３……増幅・反転回路
VID1〜6 …画像信号（アナログ信号）
Ｄint ……基準画像データ信号
Ｄdly ……遅延基準画像データ信号
Ｄmod ……画像データ信号
p1〜p4……内部信号名
４０１……減算を行う演算回路
４０２……累積加算を行う回路
４０３……乗算を行う乗算器
４０４……遅延回路
４０５……加算を行う演算回路
４０６……減算を行う演算回路
４０７……累積加算を行う回路
４０８……乗算を行う乗算器
４０９……加算を行う演算回路
４１０……加算を行う演算回路
４１１……保持回路
４１２……保持回路
４１３……乗算を行う乗算器[0001]
BACKGROUND OF THE INVENTION
The present invention simultaneously supplies image signals corresponding to each data line for each block based on each sampling signal corresponding to each block in which one or more data lines are grouped together, and sequentially selects these for each block. The present invention relates to an image data processing method and an image data processing circuit suitable for use in an electro-optical device to be executed, an electro-optical device using the same, and an electronic apparatus.
[0002]
[Prior art]
A conventional electro-optical device, for example, an active matrix liquid crystal device will be described with reference to FIGS.
[0003]
FIG. 16 is a block diagram showing a configuration of a conventional liquid crystal display device. In the figure, 100 is a liquid crystal display panel, 200 is a timing circuit, and 300 is an image signal processing circuit, and these constitute a liquid crystal display device. Dint is a digital image data signal supplied from an external device (not shown), and is an image information signal to be displayed on the liquid crystal display panel 100. And it usually has multiple bits. The timing circuit 200 outputs a timing signal (described later if necessary) used in each unit.
[0004]
Reference numeral 301 denotes a D / A conversion circuit, 302 denotes a phase expansion circuit, and 303 denotes an amplification / inversion circuit, which constitute an image signal processing circuit 300.
[0005]
Here, the D / A conversion circuit 301 converts the digital image data signal Dint supplied from an external device into an analog signal and outputs the analog signal as an image signal VID. Further, when a series (serial) image signal VID is input, the phase expansion circuit (serial-parallel conversion circuit) 302 expands (parallel converts) the image signal to an h-phase (h = 6 in the figure) image and outputs it. Is. Here, the reason for developing to the h phase is that in the image signal supply circuit described later, the application time of the image signal supplied to the TFT is lengthened, and the sampling time and charge / discharge of the image signal of the liquid crystal display panel 100 are sufficiently performed. This is to ensure. A detailed description of phase expansion will be given later.
[0006]
Then, the inverting / amplifying circuit 303 inverts the polarity of the image signal phase-expanded in the h phase according to a predetermined rule, or as it is, amplifies the image signal as appropriate after amplifying the liquid crystal as the image signals VID1 to VID6. This is supplied to the display panel 100. Here, the polarity inversion means that the voltage of the image signal is inverted with reference to a certain reference potential (generally the potential of the counter electrode).
[0007]
Next, the phase expansion circuit 302 will be described. FIG. 17 is a diagram illustrating a configuration example of the phase expansion circuit 302. In the figure, reference numerals 1701 to 1706 denote single-pole single-throw switches, and reference numeral 1730 denotes a six-unit single-throw switch. Reference numerals 1721 to 1726 and 1741 to 1746 denote capacitors, and reference numerals 1721 to 1726 and 1751 to 1756 denote buffer circuits. Here, one end of each of the switch circuits 1701 to 1706 serves as one terminal Vin, and the other end is connected to the inputs of the buffer circuits 1721 to 1726, respectively. The outputs of the buffer circuits 1721 to 1726 are connected to the inputs of the buffer circuits 1721 to 1726 through corresponding portions of the switch 1730, respectively.
[0008]
Capacitors 1721 to 1726 and 1741 to 1746 are connected to inputs of the buffer circuits 1721 to 1726 and 1751 to 1756, respectively, and the other ends of these capacitors 1721 to 1726 and 1741 to 1746 are connected to a certain potential. There is. Vin and Vout1 to Vout6 are terminals to which the output of the D / A conversion circuit 301 in FIG.
[0009]
In the above configuration, for example, the values of the image data signal Dint are sequentially set to αi, 1, αi, 2,..., Αi, 6, αi + 1,1, αi + 1,1,. When given as αi + 1,6, αi + 2,1,..., the D / A conversion circuit 301 outputs the corresponding voltages, Vi, 1, Vi, 2,..., Vi, 6, Vi + 1,1. , Vi + 1,1,..., Vi, 6, Vi + 2,1,. Correspondingly, when the voltage Vi, 1 is output, only the switch 1701 is turned on, the capacitor 1711 is charged to the voltage Vi, 1, and the buffer circuit 1721 holds this voltage. When the voltage Vi, 2 is output, only the switch 1702 is turned on. Similarly, the buffer circuit 1722 holds the voltage Vi, 2 and is repeated in the same manner. When the voltage Vi, 6 is output, the switch 1706 is turned on. Turns on and the buffer circuit holds the voltage Vi, 6. Only at this time, the switch 1730 is turned on. Then, capacitors 1741 to 1746 are charged with voltages Vi, 1 to Vi, 6 held in buffer circuits 1721 to 1726, respectively, and buffer circuits 1751 to 1756 hold voltages Vi, 1 to Vi, 6, respectively. Then, the signal is output to the amplifying / inverting circuit 303 in FIG. Then, the switch 1730 is turned off, and this voltage is maintained. Thereafter, when the D / A conversion circuit 301 outputs the voltage Vi + 1,1, only the switch 1701 is turned on, and the buffer circuit 1721 holds this voltage Vi + 1,1. Then, when the D / A conversion circuit 301 outputs the voltage Vi + 1,2, only the switch 1702 is turned on. Similarly, the buffer circuit 1722 holds the voltage Vi + 1,2, and thereafter, the voltage Vi is repeated. When +1,6 is output, the switch 1726 is turned on, and when the buffer circuit 1726 holds the voltage Vi + 1,6, the switch 1730 is turned on again, and the buffer circuits 1751 to 1756 have the voltages Vi + 1,1 to Holds Vi + 1,6. Thereafter, this operation is repeated. From the above operation, the voltage output from the D / A conversion circuit 301 changes sequentially every clock period, while the voltages of the buffer circuits 1751 to 1756 are updated by extending the time axis in 6 clock periods. Will be.
[0010]
The configuration of the image signal processing circuit 300 described here is a configuration in which the signal converted into the analog signal by the D / A conversion circuit 301 is phase-expanded, but the image data Dint is phase-expanded as a digital signal. However, there may be a case where each of them is converted into an analog signal by a plurality of D / A conversion circuits. FIG. 18 is a diagram showing a phase development method in this case. In the figure, 1810 is a 6-bit shift register circuit, 1820 is a latch circuit, and 1831 to 1836 are D / A conversion circuits. Din is a terminal for inputting an externally supplied image data signal Dint, and Vout1 to Vout6 are terminals for outputting to the input of the amplifying / inverting circuit 303 in FIG.
[0011]
In such a configuration, the values of the image data signal Dint are in sequence αi, 1, αi, 2,..., Αi, 6, αi + 1,1, αi + 1,1,. , 6,..., The shift register circuit 1810 takes in the image data signal Dint in synchronization with the clock signal and shifts it from bottom to top in the figure. When the contents of the shift register 1810 become αi, 1, αi, 2,..., Αi, 6 in order from the top, the contents of the shift register 1810 are taken into the latch circuit 1820 at the rising edge of the signal LP. Then, D / A conversion circuits 1831 to 1836 output voltages Vi, 1, Vi, 2,... This state is maintained until the next time signal LP rises. In the meantime, the values of the image data, αi + 1,1, αi + 1,1,... Αi, 6 are sequentially taken into the shift register 1810, and the contents of the shift register 1810 are sequentially changed from the top to αi. When +1,1, αi + 1,1,... Αi, 6, the signal LP is raised and the contents of the shift register SR are taken into the latch circuit 1820. Thereafter, the same operation is repeated.
[0012]
As shown in FIG. 16 and FIG. 17, the method of performing phase expansion after converting to an analog signal is called analog phase expansion, and the method of performing phase expansion with a digital signal and then converting to an analog signal is digital phase expansion. I will call it.
[0013]
Next, the liquid crystal display panel 100 will be described. The liquid crystal display panel 100 has a configuration in which an element substrate and a counter substrate face each other with a gap, and liquid crystal is sealed in the gap.
[0014]
FIG. 19 is a diagram showing a configuration of the liquid crystal display panel 100 of FIG. In FIG. 19, reference numeral 111 denotes a plurality of scanning lines, which are arranged in parallel along the X direction. Reference numerals 112a to 112f denote a plurality of data lines arranged in parallel along the Y direction. Here, each data line 112 is divided into blocks in units of h (here, h = 6), and these are defined as blocks B1 to Bq (q is a positive integer). For the convenience of the following description, when a general data line is pointed out, its code is 112, but when a specific data line is specified, the code is indicated as 112a to 112f.
[0015]
Reference numeral 113 denotes a switch element such as a thin film transistor (hereinafter referred to as “TFT”), which is provided at each intersection of the scanning line 111 and the data line 112, and the source electrode is connected to the data line 112. The gate electrode is connected to the scanning line 111.
[0016]
Reference numeral 114 denotes a pixel electrode, which is connected to the drain electrode of each TFT 113. Each pixel includes a pixel electrode 114, a counter electrode (common electrode) (not shown) formed on the counter substrate, and a liquid crystal sandwiched between the two electrodes, and includes a scanning electrode 111 and a data line 112. Each crossing portion is arranged in a matrix. In addition, a storage capacitor (not shown) may be formed in a state of being connected to each pixel electrode 114.
[0017]
A scanning line driving circuit 120 sequentially outputs a pulsed scanning signal to each scanning line 111 based on the clock signal CLY output from the timing circuit 200 of FIG. is there. Specifically, the scanning line driving circuit 120 sequentially shifts the transfer start signal DY supplied at the beginning of the Y-direction scanning period in accordance with the clock signal CLY and outputs it as a scanning signal, thereby sequentially selecting each scanning line 111. To do. In addition to the clock signal CLY, the inverted clock signal CLYINV (not shown) may be used together.
[0018]
A data line driving circuit 130 sequentially outputs sampling signals S1 to Sq based on the clock signal CLX output from the timing circuit 200 in FIG. 16, the transfer start signal DX, and the like. Specifically, the shift register circuit 130 in FIG. 19 sequentially shifts the transfer start signal DX supplied at the beginning of the X-direction scanning period according to the clock signal CLX and sequentially outputs it as sampling signals S1 to Sq. In addition to the clock signal CLX, the inverted clock signal CLXINV (not shown) may be used in combination.
[0019]
Reference numeral 140 denotes an image signal supply circuit having the following configuration. Reference numeral 141 denotes an image signal line, which supplies image signals DIV1 to DIV6, respectively. Reference numeral 142 denotes a sampling switch element, which comprises TFTs and is provided corresponding to all the data lines 112. Each source electrode has an image signal DIV1 on the image signal line 141 in units of six. .About.DIV6 are input, and the drain electrodes are connected in order so that one ends of the data lines 112a to 112f correspond to each other. The gate electrodes of the six TFTs 142 connected to the data lines 112a to 112f of the block B1 are connected to the signal line of the sampling signal S1, and the gates of the six TFTs 131 connected to the data lines 112a to 112f of the block B2. The electrodes are connected to the signal line of the sampling signal S2, and similarly, the gate electrodes of the six TFTs 142 connected to the data lines 112a to 112f of the block Bq are connected to the signal line of the sampling signal Sq.
[0020]
Reference numeral 150 denotes a precharge circuit having the following configuration. Reference numeral 151 denotes a precharge switch element, which is composed of TFTs and is provided corresponding to all the data lines 112. The precharge voltage VPRE supplied from the outside is input to all the source electrodes. The drain electrode is connected to each data line 112, and the gate electrode is supplied with the precharge gate signal PREG output from the timing circuit 200 of FIG. In some cases, the precharge voltage VPRE supplied from the outside has a plurality of systems. For example, the precharge voltage VPRE1 may be supplied to the odd-numbered data lines 112a, 112c, and 112e, and the precharge voltage VPRE2 may be supplied to the even-numbered data lines 112b, 112d, and 112f.
[0021]
The liquid crystal display panel 100 of FIGS. 16 and 19 has the above configuration. Here, the operation will be described.
[0022]
First, when a certain scanning line 111 is selected, first, the precharge gate signal PREG becomes active. Then, the precharge voltage VPRE is applied to all the data lines 112, and the voltage VPRE is written to all the pixels on the selected row. Here, in general, the voltage VPRE is often selected near the center voltage of the pixel signal amplitude. In this operation, an average pixel voltage (= voltage VPRE) is given to each pixel in advance to facilitate the subsequent writing operation to each pixel. In other words, the time required for writing is shortened. To do. Then, the precharge gate signal PREG is deactivated.
[0023]
Thereafter, when the sampling signal S1 is output, the image signals DIV1 to DIV6 are supplied to the six data lines 112a to 112f belonging to the block B1, respectively, and the selected scanning line 111 and the block B1 intersect. Writing is performed by the TFT 116 to the six pixels in the portion. Thereafter, when the sampling signal S2 is output, the image signals DIV1 to DIV6 are supplied to the six data lines 112a to 112f belonging to the block B2, respectively, and the selected scanning line 111 and the block B2 are connected. Writing is performed by the TFT 113 on the six pixels in the intersecting portion.
[0024]
Similarly, when the sampling signals S3, S4,..., Sq are sequentially output, the image signals VID1 to VID6 are selected for the six data lines 112a to 112f belonging to the blocks B3, B4,. The data is written to the six pixels at the intersection of the scanning line 111 and the block. Thereafter, the next scanning line 111 is selected, and the same operation is repeatedly performed.
[0025]
As described above, in this driving method, the number of stages of the data line driving circuit 130 for driving and controlling the switch 142 in the image signal supply circuit 140 is reduced to 1/6 as compared with the method of driving each data line 112 in a dot sequential manner. Further, since the frequency of the clock signal CLX and the like to be supplied to the data line driving circuit 130 is only 1/6, the number of stages is reduced and the power consumption is reduced.
[0026]
[Problems to be solved by the invention]
However, in the method of driving the data lines 112 in blocks, there is blur-like display unevenness (hereinafter, this phenomenon is referred to as ghost) in the left and right portions (X direction) adjacent to the image to be originally displayed. There is a problem that occurs.
[0027]
Here, the occurrence state of a ghost will be described in detail. This ghost can be clearly seen when a black square window is displayed on a halftone background. FIG. 20 is a diagram showing a part of the display contents of the liquid crystal display panel 100, and the whole figure is a part of the display part. In the figure, vertical lines (broken lines) indicate one pixel column, and six lines are shown. The solid line of the unit indicates the partition of each block. And, the background is a halftone, and the ghost occurrence state is shown when displaying several black windows of the same shape shown by cross hatching. And the horizontal line hatched part on the left side of the window, the right-handed diagonal hatching part on the right side of the quadrangle, and the diagonally hatched part on the right-hand side are ghosts, which are referred to as front ghost, rear ghost, and next ghost, respectively. To. The characteristic point of these ghosts is that they are generated in units of blocks, and the degree thereof does not depend on the height and width of the window but depends on the width of the window portion in the block.
[0028]
Among these, the front ghost is inconspicuous when the window width in the block is narrow, and becomes brighter and noticeable display unevenness as the window width increases. Next, the rear ghost is a display unevenness that becomes dark and conspicuous when the window width in the block is narrow, and is once inconspicuous as the window width widens, but it becomes bright and noticeable display unevenness when the window frame further expands. Then, the next ghost is inconspicuous when the window width of the block on the left side of the block is narrow, and becomes dark as the window width widens, and is noticeable display unevenness.
[0029]
These ghosts are the result of the author's diligence, research and investigation, and it was found that they were caused by the following generation mechanism. FIG. 21 is a diagram showing an electrical equivalent circuit for explaining a ghost generation mechanism of the liquid crystal display panel 100. In the figure, reference numeral 211 denotes a resistance of the counter electrode, which indicates that it is grounded to the potential indicated by the reverse Δ mark in the figure. Reference numerals 212a to 212f denote parasitic capacitances having liquid crystal as a dielectric between the image signal line 141 that supplies the image signals DIV1 to DIV6 to the TFT 142 of each switch and the counter electrode, respectively.
[0030]
Reference numerals 142a to 142f denote switches 142 of a certain block Bi (i is any one of 1 to q). Reference numerals 213a to 213f denote parasitic capacitances generated between the data line 112 corresponding to these switches 142 and the counter electrode. And the pixel capacity. Note that the voltage of the parasitic capacitance and the pixel capacitance before the selection of the block Bi is a precharge voltage.
[0031]
Since the equivalent circuit is as described above, the differential circuit is constituted by the parasitic capacitors 212a to 212f and the resistor 211. As a result, the differential of the wave height according to the voltage change amount of the image signals DIV1 to DIV6 on the counter electrode. Voltage distortion on the waveform occurs. This is factor 1.
[0032]
Further, when the sampling signal Si (i is any one of 1 to q) is output, the switch 142 of the block Bi is turned on. Then, the parasitic capacitances on the corresponding data lines 112a to 112f and the pixel capacitors 213a to 213f are charged / discharged from the precharge voltage to the corresponding voltages of the image signals DIV1 to DIV6. The voltage distortion of the differential wave shape of the wave height according to the magnitude | size of charging / discharging generate | occur | produces on an opposing electrode with an electric current. This is factor 2.
[0033]
Although the voltage distortion of the differential wave shape caused by the factor 1 and the factor 2 is attenuated with time, if it does not become zero before the sampling signal Si is output, an error voltage is generated in the pixel, resulting in display unevenness. For example, assuming that the voltage of the image signal is V0 and the error voltage remaining on the counter electrode when the sampling signal Si has been output is Ve, the voltage between the data line (voltage V0) and the counter electrode (voltage Ve) is V0-Ve. However, since this voltage becomes a voltage of the parasitic capacitance and the pixel capacitances 213a to 213f, when the switch 142 is turned off in this state, the voltage is maintained and display unevenness occurs.
[0034]
In general, this will be explained in detail. A block Bi (i = 1, 2,..., Q) is selected, and Vi, j, j = 1, 2,. Consider the case of supply.
[0035]
Here, first, the error voltage remaining on the counter electrode immediately before the block Bi is selected is set to Vε0. Then, consider immediately after the block Bi is selected. Then, the error voltage generated in the counter electrode due to factor 1 is expressed by the following equation (1).
[0036]
[Expression 1]

In equation (1), ζ is a constant, and Vi-1, j is a voltage supplied to the corresponding data line when the block Bi-1 is selected.
[0037]
Similarly, the error voltage generated in the counter electrode due to factor 2 is expressed by the following equation (2).
[0038]
[Expression 2]

In Equation (2), ξ is a constant, and Vpre is a precharge voltage. Therefore, the total error voltage generated in the counter electrode is expressed by the following equation (3).
[0039]
[Equation 3]

Here, immediately before the end of the selection of the block Bi, it can be expressed by a function (hereinafter referred to as an error function ferr) using the image signal as a variable by multiplying by a constant attenuation coefficient k and as in the following equation.
[0040]
[Expression 4]

Now, the previous ghost shown in FIG. 20 will be described using this error function ferr. Since the pixels on the left of the previous ghost block are all halftone, when the voltage Vi-1, j is considered to be, for example, the voltage Vpre, the voltage Vi, j is equal to or higher than the voltage Vpre for the block, and the second term, Both third terms are non-negative. When the number of pixels satisfying Vi, j> Vpre increases, that is, when the width of the black window applied to the block increases, both the second and third terms of the equation increase, and the positive error increases, resulting in bright unevenness. I understand that
[0041]
The rear ghost also becomes brighter as the width of the black window on the block increases. However, although the second term is non-negative, the third term takes a negative value when the black window becomes narrower. Therefore, when the width of the black window covering the block is narrowed, the third term becomes dominant, resulting in dark display.
[0042]
In the next ghost, the second term is 0 and the third term is not positive. Therefore, dark unevenness occurs.
[0043]
As described above, the front ghost, the rear ghost, and the next ghost are generated. When h is 1, in other words, even in the case of so-called dot sequential scanning driving, a ghost is generated as can be seen from equation (4).
[0044]
After all, there is a problem that such a ghost occurs and the quality of the display image deteriorates.
[0045]
The present invention has been made in view of such problems, and an object of the present invention is to use an image data processing method, an image data processing circuit, and an image data processing circuit that enable high-quality image display by removing ghosts. To provide an electro-optical device and an electronic apparatus.
[0046]
[Means for Solving the Problems]
To achieve the above object, the data line comprises a plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. The image is used in an electro-optical device in which a voltage based on an image data signal is simultaneously supplied to each data line included in the block, based on each sampling signal corresponding to each block in which a plurality of blocks are collected. An image data signal processing method for generating a data signal, which is obtained by adding correction voltage data to a signal obtained by delaying a reference image data signal corresponding to one block by one block period, and corresponding to the one block Output as the image data signal, the one block as a target block, and a block selected before the target block as a reference block The correction voltage data is generated by calculation for each block using at least the standard image data signal corresponding to the target block and the image data signal corresponding to the reference block, and the target block The display ghost is corrected based on a voltage change of the image data signal with the reference block.
[0047]
Since the error in the voltage written to the pixel is roughly determined by the image data corresponding to the target block and the reference block, the voltage error can be predicted, and is predicted to the reference image data signal corresponding to the pixel voltage to be originally written. By adding correction voltage data that cancels out the influence of the error voltage, the error in the write voltage can be eliminated, and the ghost is eliminated.
[0048]
More specifically, when the image signal Vi, j + Vcmp to which the correction voltage Vcmp is added is used instead of the reference image signal Vi, j (j = 1, 2,..., H) to be originally written, the selected scanning line is used. The j-th pixel voltage Vpi, j of the reference block Bi on the row is expressed by the following equation (5).
[0049]
[Equation 5]

Here, the pixel voltage Vpi, j may be equal to the reference pixel signal Vi, j. That is, the following equation (6) should be satisfied.
[0050]
[Formula 6]

When this is solved for the correction voltage Vcmp, the following equation (7) is established.
[0051]
[Expression 7]

Since the correction voltage Vcmp matches the error voltage Vε1 remaining on the counter electrode immediately after the selection of the reference block Bi, adding this correction voltage Vcmp to the standard image signal Vi, j should eliminate the ghost. is there. Accordingly, it is possible to eliminate the ghost by supplying the image data signal Dmod obtained by adding the correction voltage data Dcmp corresponding to the correction voltage Vcmp to the reference image data signal Dint in advance.
[0052]
As a predetermined calculation method in the image data processing method of the present case, a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block is multiplied by a second predetermined value. A sum of a value and a value obtained by subtracting each value of the image data signal of the corresponding reference block from each of the reference image data signal of the target block, and a value obtained by multiplying the reference by the third predetermined value It is desirable to add a value obtained by multiplying the correction voltage data used in the image data signal of the block by a fourth predetermined value.
[0053]
When the constant part of the equation for obtaining the correction voltage Vcmp is expressed by ax and (x is a subscript), the following equation (8) is obtained.
[0054]
[Equation 8]

In this method, the correction voltage Vcmp is obtained based on the equation (8), and the ghost is eliminated by supplying the image data signal Dmod obtained by adding the correction voltage data Dcmp corresponding thereto to the reference image data signal Dint. Is possible.
[0055]
Further, as a predetermined calculation method in the image data processing method of the present case, a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block is multiplied by a second predetermined value. A sum of a value and a value obtained by subtracting each value of the reference image data signal of the corresponding reference block from each of the reference image data signal of the target block, and a value obtained by multiplying the third predetermined value, It is desirable to add a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value.
[0056]
In this method, the calculation is performed using the standard image data signal instead of the image data signal of the reference block used in the previous method. Here, the difference between the image data signal and the reference image data signal is a correction voltage, and since this difference is generally small, the same effect can be obtained.
[0057]
On the other hand, as a predetermined calculation method in the image data processing method of the present case, a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block is multiplied by a second predetermined value. A value and a sum of values obtained by subtracting the respective values of the image data signal of the corresponding reference block from the reference image data signals of the target block and a value obtained by multiplying the sum by a third predetermined value It is desirable that
[0058]
In this method, the calculation is performed without using a value obtained by multiplying the correction voltage data by the fourth predetermined value. Here, since the value obtained by multiplying the correction voltage data by the fourth predetermined value is generally small, the same effect can be obtained and the calculation can be simplified.
[0059]
As a predetermined calculation method in the image data processing method of the present case, a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block is multiplied by a second predetermined value. And a sum of a value obtained by subtracting each value of the reference image data signal of the corresponding reference block from each of the reference image data signals of the target block is multiplied by a third predetermined value. It is desirable to be a method.
[0060]
In this method, the calculation is performed without using a value obtained by multiplying the correction voltage data by the fourth predetermined value. Here, since the value obtained by multiplying the correction voltage data by the fourth predetermined value is generally small, the same effect can be obtained and the calculation can be simplified.
[0061]
The predetermined calculation method in the image data processing method of the present case includes a value obtained by multiplying the sum of the values of the reference image data signal of the target block by a fifth predetermined value, and the image data of the reference block. A sum of respective values of the signals multiplied by a sixth predetermined value, a seventh predetermined value, and a fourth predetermined value for the correction voltage data used in the image data signal of the reference block It is desirable that the calculation method add the value multiplied by.
[0062]
The equation for obtaining the correction voltage Vcmp is transformed so that Vi, j and Vi-1, j are in the form of independent sums, and the constant part is expressed by ax and (x is a subscript). It becomes an expression.
[0063]
[Equation 9]

In this method, a ghost is eliminated by obtaining a correction voltage Vcmp based on the equation (9) and supplying an image data signal Dmod obtained by adding the corresponding correction voltage data Dcmp to the reference image data signal Dint. Is possible.
[0064]
On the other hand, as a predetermined calculation method in the image data processing method of the present invention, a value obtained by multiplying the sum of the values of the reference image data signals of the target block by a fifth predetermined value, and the reference image of the reference block A sum of respective values of the data signal is multiplied by a sixth predetermined value, a seventh predetermined value, and a fourth predetermined value is added to the correction voltage data used in the reference image data signal of the reference block. It is desirable to add the value multiplied by the value of.
[0065]
In this method, the calculation is performed using the standard image data signal instead of the image data signal of the reference block. Here, the difference between the image data signal and the reference image data signal is a correction voltage, and since this difference is generally small, the same effect can be obtained.
[0066]
The predetermined calculation method in the image data processing method of the present case includes a value obtained by multiplying the sum of the values of the reference image data signal of the target block by a fifth predetermined value, and the image data of the reference block. It is desirable to add a value obtained by multiplying the sum of the respective values of the signal by the sixth predetermined value and a seventh predetermined value.
[0067]
In this method, the calculation is performed without using a value obtained by multiplying the correction voltage data by the fourth predetermined value. Here, since the value obtained by multiplying the correction voltage data by the fourth predetermined value is generally small, the same effect can be obtained and the calculation can be simplified.
[0068]
Further, as a predetermined calculation method in the image data processing method of the present case, a value obtained by multiplying a sum of values of the reference image data signals of the target block by a fifth predetermined value, and the reference image of the reference block It is desirable to add a value obtained by multiplying the sum of the respective values of the data signal by the sixth predetermined value and a seventh predetermined value.
[0069]
In this method, the calculation is performed without using a value obtained by multiplying the correction voltage data by the fourth predetermined value. Here, since the value obtained by multiplying the correction voltage data by the fourth predetermined value is generally small, the same effect can be obtained and the calculation can be simplified.
[0070]
After all, as the predetermined calculation method in the image data processing method of the present invention, any calculation method that produces the same calculation result as any one of the calculation methods according to claims 2 to 9 may be used. That is, the calculation method is not limited to the various methods described above, and ghosts can be eliminated if the same calculation result is obtained.
[0071]
Next, in order to achieve the above object, the present invention includes a plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. And an electro-optic in which a voltage based on an image data signal is simultaneously supplied to each data line included in the block based on each sampling signal corresponding to each block in which the data lines are grouped into a plurality of blocks. An image data signal processing circuit for generating the image data signal used in the apparatus, wherein a reference image data signal corresponding to one block is delayed by one block period and the correction voltage data is added Output as the image data signal corresponding to one block, the one block as a target block, and a block selected before the target block When a reference block is used, the target block and the reference block generated by calculation for each block using at least a standard image data signal corresponding to the target block and the image data signal corresponding to the reference block, And an arithmetic processing circuit for obtaining the correction voltage data for correcting a display ghost based on a voltage change of the image data signal.
The present invention is a circuit that embodies the above-described image data processing method, and can obtain the same effects as described above for the image data processing method.
[0072]
Now, as an arithmetic processing circuit in the image data processing circuit of the present case, a value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block is multiplied by a second predetermined value. A sum of values obtained by subtracting each value of the image data signal of the corresponding reference block from each of the reference image data signal of the target block, and a value obtained by multiplying the reference block by a third predetermined value The circuit is preferably a circuit that performs an operation of adding a value obtained by multiplying the correction voltage data used in the image data signal by a fourth predetermined value. This configuration is a circuit that embodies the above-described image data processing method, and according to this configuration, the same effect as described above for the image data processing method can be obtained.
[0073]
Further, as the arithmetic processing circuit in the image data processing circuit of the present case, a value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block is multiplied by a second predetermined value. A sum of values obtained by subtracting the respective values of the reference image data signals of the corresponding reference blocks from the respective reference image data signals of the target block, and a value obtained by multiplying the reference value by the third predetermined value. It is desirable that the circuit is a circuit that performs an operation of adding a value obtained by multiplying the correction voltage data used in the image data signal of the block by a fourth predetermined value. This configuration is a circuit that embodies the above-described image data processing method, and according to this configuration, the same effect as described above for the image data processing method can be obtained.
[0074]
On the other hand, as an arithmetic processing circuit in the image data processing circuit of the present case, a value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block is multiplied by a second predetermined value. And a sum of values obtained by subtracting the values of the corresponding image data signals of the reference block from the respective reference image data signals of the target block and a value obtained by multiplying the value by a third predetermined value are performed. A configuration that is a circuit is desirable. This configuration is a circuit that embodies the above-described image data processing method, and according to this configuration, the same effect as described above for the image data processing method can be obtained.
[0075]
Now, as an arithmetic processing circuit in the image data processing circuit of the present case, a value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block is multiplied by a second predetermined value. And a sum of values obtained by subtracting each value of the reference image data signal of the reference block corresponding to each of the reference image data signals of the target block and a value obtained by multiplying the value by a third predetermined value A configuration that is a circuit for performing the above is desirable. This configuration is a circuit that embodies the above-described image data processing method, and according to this configuration, the same effect as described above for the image data processing method can be obtained.
[0076]
Further, the arithmetic processing circuit in the image data processing circuit of the present case includes a value obtained by multiplying the sum of the values of the reference image data signal of the target block by a fifth predetermined value, and the image data signal of the reference block. A sum of the respective values of the first value multiplied by a sixth predetermined value, a seventh predetermined value, and a fourth predetermined value for the correction voltage data used in the image data signal of the reference block. A configuration that is a circuit that performs an operation of adding the multiplied value is desirable. This configuration is a circuit that embodies the above-described image data processing method, and according to this configuration, the same effect as described above for the image data processing method can be obtained.
[0077]
On the other hand, the arithmetic processing circuit in the image data processing circuit of the present case includes a value obtained by multiplying the sum of the values of the reference image data signal of the target block by a fifth predetermined value, and the image data signal of the reference block. A sum of the respective values of the first value multiplied by a sixth predetermined value, a seventh predetermined value, and a fourth predetermined value for the correction voltage data used in the reference image data signal of the reference block A configuration that is a circuit that performs an operation of adding a value multiplied by is desirable. This configuration is a circuit that embodies the above-described image data processing method, and according to this configuration, the same effect as described above for the image data processing method can be obtained.
[0078]
Further, the arithmetic processing circuit in the image data processing circuit of the present case includes a value obtained by multiplying the sum of the values of the reference image data signal of the target block by a fifth predetermined value, and the image data signal of the reference block. It is desirable that the circuit be a circuit that performs an operation of adding a value obtained by multiplying the sum of the respective values by a sixth predetermined value and a seventh predetermined value. This configuration is a circuit that embodies the above-described image data processing method, and according to this configuration, the same effect as described above for the image data processing method can be obtained.
[0079]
The arithmetic processing circuit in the image data processing circuit of the present invention includes a value obtained by multiplying the sum of the values of the reference image data signal of the target block by a fifth predetermined value, and the reference image data of the reference block. It is desirable that the circuit be a circuit that performs an operation of adding a value obtained by multiplying the sum of the respective values of the signal by a sixth predetermined value and a seventh predetermined value. This configuration is a circuit that embodies the above-described image data processing method, and according to this configuration, the same effect as described above for the image data processing method can be obtained.
[0080]
After all, the arithmetic processing circuit in the image data processing circuit of the present invention may have a circuit configuration that provides the same arithmetic result as any one of claims 12 to 19. That is, the configuration of the arithmetic processing circuit is not limited to the above-described various configurations, and ghosts can be eliminated if the same calculation result is obtained.
[0081]
Next, in order to achieve the above object, an electro-optical device according to the present invention converts an image data processing circuit according to claims 11 to 20 and an image data signal that is a digital signal output from the image data processing circuit into an analog signal. A D / A conversion circuit for conversion, a parallelization circuit for extending and parallelizing an image signal output from the D / A conversion circuit according to the number of image signal lines constituting the block, and the scanning A scanning line driving circuit for sequentially selecting lines; a data line driving circuit for generating each sampling signal for sequentially selecting a block in which the plurality of image signal lines are grouped together; and the parallelized image signal based on each sampling signal Is provided with an image signal supply circuit that supplies the data line to each of the data lines belonging to the selected block.
[0082]
According to this electro-optical device, the quality of the display image can be greatly improved, and an image signal can be supplied to the data lines in units of blocks, so that the configuration of the data line driving circuit can be simplified. And power consumption can be reduced.
[0083]
Similarly, in order to achieve the above object, another electro-optical device according to the present invention constitutes the image data processing circuit according to claim 11 and an image data signal output from the image data processing circuit in the block. A parallel circuit that extends and parallelizes the time axis according to the number of image signal lines, a D / A conversion circuit that converts an image data signal output from the parallel circuit into an analog signal, and the scanning lines are sequentially selected. A scanning line driving circuit, a data line driving circuit for generating each sampling signal for sequentially selecting a block in which the plurality of image signal lines are grouped together, and the parallelized image signal is selected based on each sampling signal And an image signal supply circuit for supplying each of the data lines belonging to the block.
[0084]
According to this electro-optical device, the quality of the display image can be greatly improved, and an image signal can be supplied to the data lines in units of blocks, so that the configuration of the data line driving circuit can be simplified. And power consumption can be reduced.
[0085]
Furthermore, in order to achieve the above object, an electronic apparatus according to the present invention includes the electro-optical device according to claim 21 or 22. Examples of such an electronic device include a video projector, a notebook personal computer, a mobile phone, and the like.
[0086]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0087]
<First Embodiment>
First, an active matrix liquid crystal display device according to a first embodiment of the present invention will be described as an example of an electro-optical device.
[0088]
FIG. 1 is a block diagram showing the overall configuration of the liquid crystal display device of the present invention. In the figure, 100 is a liquid crystal display panel, 200 is a timing circuit, and 300A is an image signal processing circuit, and these constitute a liquid crystal display device. Among these, the timing circuit 200 outputs a timing signal (described later if necessary) used in each unit.
[0089]
In addition, 301 is a D / A conversion circuit, 302 is a phase expansion circuit, 303 is an amplification / inversion circuit, 310A is a data correction circuit, and these constitute an image signal processing circuit 300A. The liquid crystal display device according to this embodiment is the same as the conventional liquid crystal display device shown in FIG. 16 except that the data correction circuit 310A is provided in the preceding stage of the D / A conversion circuit 301 in the image signal processing circuit 300A. Since they are configured, common parts are given the same reference numerals to avoid duplication of explanation. Note that Dint is a reference image data signal supplied from an external device (not shown), and Dmod is an image data signal output from the data correction circuit 310A. Here, in the description of the prior art, Dint is called an image data signal. However, the name is changed in this way. The reference image data signal Dint is usually composed of a plurality of bits.
[0090]
The D / A conversion circuit 301 converts the image data Dmod into an analog signal and outputs it as an image signal VID. Further, when a series of image signals VID are inputted, the phase development circuit 302 develops and outputs them into h-phase image signals. In the present embodiment, the case where h is 6 will be described. However, the present invention is not limited to this, and may be an arbitrary number of one or more integers.
[0091]
The inverting / amplifying circuit 303 inverts the polarity of the image signal in accordance with a predetermined rule, or amplifies the image signal as it is, and supplies it to the liquid crystal display panel 100 as phase-developed image signals VID1 to VID6. .
[0092]
FIG. 2 is a diagram illustrating a configuration example of the data correction circuit 310A. In this figure, 401 is an arithmetic circuit that performs subtraction, and subtracts a predetermined numerical value a1 from the reference image data signal. Reference numeral 402 denotes an adder that cumulatively adds the output values of the arithmetic circuit 401. Details will be described later. An arithmetic circuit 403 performs multiplication, and outputs a value obtained by multiplying the output value of the adder 402 by a predetermined coefficient a2. In the present embodiment, this is configured by a look-up table using a read-only memory or the like. That is, the output value of the adder 402 is used as the memory address, and the data at the address is set to the value obtained by multiplying the address value by the coefficient a2.
[0093]
On the other hand, reference numeral 404 denotes a delay circuit which takes in the reference image data Dint, outputs it with a delay. In this embodiment, it consists of a six-stage shift register circuit. The data signal output with a delay is referred to as a delayed reference data signal and is represented by the symbol Ddly. Reference numeral 405 denotes an arithmetic circuit that performs addition, and adds the output of the delay circuit 404 and the output value of the holding circuit 411 described later. The output value is the image data signal Dmod.
[0094]
Reference numeral 406 denotes an arithmetic circuit that performs subtraction, and subtracts the image data signal Dmod from the reference image data signal Dint. Reference numeral 407 denotes an adder that cumulatively adds the output values of the arithmetic circuit 406. Details will be described later. An arithmetic circuit 408 performs multiplication, and outputs a value obtained by multiplying the output value of the adder 407 by a predetermined coefficient a3. In the present embodiment, this is configured by a look-up table using a read-only memory or the like. Reference numeral 409 denotes an arithmetic circuit that performs addition, and adds the output value of the arithmetic circuit 403 and the output value of the arithmetic circuit 408. Reference numeral 410 denotes an arithmetic circuit that performs addition, and adds an output of the arithmetic circuit 409 and an output value of an arithmetic circuit 413 described later.
[0095]
Next, 411 and 412 are holding circuits that hold data, respectively, and hold the output of the arithmetic circuit 410 and the output of the holding circuit 411, respectively. In this embodiment, this circuit is configured by a latch circuit. Reference numeral 413 denotes an arithmetic circuit that performs multiplication, and outputs a value obtained by multiplying the output value of the holding circuit 412 by a predetermined coefficient a4. In the present embodiment, this is configured by a look-up table using a read-only memory or the like.
[0096]
Here, the clock signal CLK and the latch pulse signal LP are supplied as control signals from the timing circuit 200 of FIG. 1 to the data correction circuit 310A. The clock signal CLK is used as a clock signal for the adders 402 and 408 and the delay circuit 404, and the latch pulse signal LP is used as a clock signal for the holding circuits 411 and 412 and a control signal for the adders 402 and 408. The reference image data Dint changes in synchronization with the rising edge of the clock signal CLK and is input to the data correction circuit 310A. Also, p1 to p4 in the figure are names of internal signal lines, which indicate output signals of the adders 402 and 408 and the holding circuits 411 and 412, respectively.
[0097]
FIG. 3 is a diagram illustrating a configuration example of the adder 402 or 408. In the figure, reference numeral 501 denotes an arithmetic circuit for performing addition, 502 a data selector circuit, and 503 a holding circuit. The arithmetic circuit 501 adds the output value Dout and the input value Din of the holding circuit. The data selector circuit 502 selects and outputs either the input value Din or the output value of the adder circuit 501. This is controlled by the latch pulse signal LP, and the input value Din is selected when the signal LP is active, and the output value of the adder circuit 501 is selected when the signal LP is inactive. The holding circuit 503 captures and holds the output value of the data selector circuit 502 in synchronization with the falling edge of the clock signal CLK.
[0098]
Therefore, when the signal CLK falls while the signal LP is active, the input value Din is taken into the holding circuit 503, and then the signal LP becomes inactive, and when the signal CLK falls again, this time, the holding circuit 503 A value obtained by adding the input value Din to the value is taken into the holding circuit 503. Thereafter, each time the signal CLK falls during a period in which the signal LP is inactive, a value obtained by adding the input value Din to the value of the holding circuit 503 is taken into the holding circuit 503 and cumulatively added. .
[0099]
The configuration of the data correction circuit 310A in FIGS. 1 and 2 is as described above.
[0100]
Next, the operation will be described. FIG. 4 is a timing chart showing the operation of the data correction circuit 310A. In the figure, a clock signal CLK, a latch pulse signal LP, a reference image data signal Dint, internal signals p1 to p4, a delayed reference image data signal Ddly, and an image data signal Dmod output from the timing circuit 200 are shown. The horizontal axis is time. If the time of one period of the clock signal CLK is tc, the period of the latch pulse signal LP is h (= 6) times, and the period is tb. Here, the period during which the signal LP is active (the upper level in the figure) is 1 · tc. The period from the rising edge of the latch pulse signal LP to the next rising edge is defined as one block period. A period during which the reference image data signal Vi, j corresponding to the i-th block Bi of the liquid crystal display panel 100 is supplied from an external device is defined as an i-th block period, and a subsequent block period is defined as an i + 1-th block period. To do.
[0101]
Here, the symbols α i, j (i = 1, 2,..., Q, j = 1, 2,..., 6) denote the j th data line in the i th block Bi of the liquid crystal display panel 100, The contents of the reference image data signal Dint corresponding to the pixel at the location where the currently selected scanning line row intersects are shown. Similarly, the symbols βi, j (i = 1, 2,..., Q, j = 1, 2,..., 6) are the j-th data lines in the i-th block Bi of the liquid crystal display panel 100, and The contents of the image data signal Dmod corresponding to the portion where the currently selected scanning line row intersects are shown. A symbol γi, 1 indicates a value obtained by subtracting a predetermined constant a1 from the reference image data signal αi, 1. Subsequent symbols Σγ1 to γ2 indicate a value obtained by adding a value obtained by subtracting a1 from the reference image data signal αi, 2 to γi, 1, and symbols Σγ1 to 3 indicate the reference image data signal αi, 3 to Σγ1 to 2. The value obtained by subtracting a1 from the value is added, and the cumulative addition value is similarly shown below. Next, symbol Δi, 1 indicates a value obtained by subtracting the image data signal βi-1,1 from the reference image data signal αi, 1. Subsequent symbols Σδ1-2 indicate values obtained by adding image data signals βi-1,2 to reference image data signals αi, 2 to δi, 1, and symbols Σδ1-3 indicate Σδ1-2 A value obtained by adding a value obtained by subtracting the image data signals βi-1,3 from the reference image data signal αi, 3 is shown, and the cumulative addition value is similarly shown below. Symbol Dcmpi indicates the value of the correction voltage data added to the reference image data signal Dint corresponding to the block Bi.
[0102]
First, in synchronization with the rising edge of the clock signal CLK, the reference pixel data signal Dint supplied from the outside from the beginning of the i-th block period is a value corresponding to the block Bi, αi, 1, αi, 2,. In the following (i + 1) -th block period, αi, 6 is taken to become αi + 1,1, αi + 1,2,..., αi + 1,6 corresponding to the block Bi + 1, and so on. It is.
[0103]
Here, the arithmetic circuit 401 subtracts a constant a1 from the reference image data signal αi, 1 to obtain a value γi, 1. At this time, since the signal LP is active, it is taken into the adder 402 and held in synchronization with the falling edge of the signal CLK. Next, the arithmetic circuit 401 subtracts a constant a1 from the reference image data signal αi, 2 to obtain a value γi, 2. At this time, since the signal LP is inactive, the values Σγ1 to Σ2 are added by adding the values γi, 1 and γi, 2 held in the adder 402 in synchronization with the falling of the signal CLK. . Thereafter, the cumulative addition is similarly performed until the block period. This is illustrated as signal p1.
[0104]
Next, the arithmetic circuit 406 subtracts the image data signal βi−1,1 from the reference image data signal αi, 1 to obtain a value Δi, 1. At this time, since the signal LP is active, the signal LP is captured and held in the adder 407 in synchronization with the falling of the signal CLK. Next, the arithmetic circuit 406 subtracts the image data signal βi-1,2 from the reference image data signal αi, 2 to obtain a value Δi, 2. At this time, since the signal LP is inactive, the value Σδ1 to 2 obtained by adding the value δi, 1 held in the adder 407 and the value δi, 2 is held in synchronization with the falling of the signal CLK. . Thereafter, the cumulative addition is similarly performed until the block period. This is illustrated as signal p2.
[0105]
Then, at the end of the block period, the adder 402 holds the sum Σγ1 to 6 of the values obtained by subtracting the constant a1 from the respective reference image data signals αi, j of the block Bi, while the adder 407 The sums Σδ1 to 6 of values obtained by subtracting the corresponding image data signals βi-1, j of the block Bi-1 from the respective reference image data signals αi, 2 of the block Bi are held. These values are multiplied by constants a2 and a3 by multipliers 403 and 408, respectively, and both values are added by an arithmetic circuit 409.
[0106]
Then, the value of the arithmetic circuit 409 and the output value of the multiplier 413 are added by the arithmetic circuit 410. This value becomes the correction voltage data Dcmpi, and is taken in and held in the holding circuit 411 in synchronization with the rise of the signal LP. This is illustrated as signal p3.
[0107]
Next, the delay circuit 404 takes in the reference pixel data signal Dint input from the outside in synchronization with the rising edge of the signal CLK, and outputs a delayed reference pixel data signal delayed by one block period (tb). This is shown as this signal Ddly.
[0108]
The arithmetic circuit 405 adds the value of the holding circuit 411, that is, the correction voltage data Dcmpi to the value of the delayed reference pixel data signal, and outputs the result as the pixel data signal Dmod. That is, the image data signal Dmod corresponding to the block Bi is output during the (i + 1) th block period.
[0109]
Finally, the holding circuit 412 captures and holds the value of the holding circuit 411 in synchronization with the rising edge of the signal LP. That is, the correction voltage data Dcmpi-1 used only one block before, in other words, the error voltage data is captured and held. This is illustrated as signal p4. Therefore, the output of the multiplier 413 is obtained by multiplying the error voltage data by a constant a4.
[0110]
Since the above operation is performed, the holding circuit 411 includes a value obtained by multiplying the sum of the values obtained by subtracting the constant a1 from the respective values of the reference image data signal Dint of the block Bi and the constant a2 and the reference of the block Bi. A sum of values obtained by subtracting each of the corresponding image data signals Dmod of the block Bi-1 from each of the image data signals Dint is multiplied by a constant a3, and a constant a4 is added to the error voltage data one block period before. Is stored, and this value is used as the voltage correction data Dcmp. This value is nothing but the value of equation (8). Therefore, this is added to the reference pixel data signal Dint to generate the image data signal Dmod and drive the liquid crystal display panel 100, thereby eliminating the ghost.
[0111]
<Second Embodiment>
Other embodiments will be described with reference to the drawings. FIG. 5 is a block diagram showing the overall configuration of the liquid crystal display device. In the figure, reference numeral 300B denotes an image signal processing circuit, and reference numeral 310B constituting the image signal processing circuit 300B denotes a data correction circuit. Since the configuration and operation other than the data correction circuit 310B are the same as those of the liquid crystal display device of FIG. 1, the same reference numerals are given to avoid redundant description.
[0112]
FIG. 6 is a diagram illustrating a configuration example of the data correction circuit 310B. In the figure, the data signal input to the arithmetic circuit 406 is the same as the data correction circuit 310A of FIG. 2 except that the reference image data signal Dint and the delayed reference image data signal output from the delay circuit 404 are the same. The same reference numerals are attached to avoid redundant description.
[0113]
It has the above configuration. 2 is different from the data correction circuit 310A in FIG. 2 in that the data correction circuit 310A uses image data Dmod as a data signal input to the arithmetic circuit 406, whereas the data correction circuit 310B in FIG. Only the delay reference image data signal Ddly output from the circuit 404 is used. Here, the image data signal Dmod is obtained by adding the correction voltage data Dcmp to the delay reference image data signal Ddly. Since the absolute value of the correction voltage data Dcmp is not so large, the difference between the image data signal Dmod and the delayed reference image data signal Ddly is small.
[0114]
Therefore, even if the corrected voltage data Dcmp is obtained using the delayed reference image data signal Ddly instead of the image data signal Dmod and the reference image data signal Dint is corrected based on this, the same as in the first embodiment. The ghost can be eliminated. In addition, since the delay reference image data signal Ddly can be directly input to the arithmetic circuit 406, when the data correction circuit 310B is actually made, the operation speed of the circuit elements is not increased more than necessary, and the manufacture becomes easy. .
[0115]
<Third Embodiment>
Other embodiments will be described with reference to the drawings. FIG. 7 is a block diagram showing the overall configuration of the liquid crystal display device. In the figure, 300C is an image signal processing circuit, and 310C constituting the image signal processing circuit 300C is a data correction circuit. Since the configuration and operation other than the data correction circuit 310C are the same as those of the liquid crystal display device of FIG. 1, the same reference numerals are given to avoid redundant description.
[0116]
FIG. 8 is a diagram illustrating a configuration example of the data correction circuit 310C. In the figure, the signal input to the holding circuit 411 is the arithmetic circuit 409, and is the same as the data correction circuit 310A in FIG. 2 except that the arithmetic circuit 410, the holding circuit 412, and the multiplier 413 are omitted. The same reference numerals are attached to avoid redundant description.
[0117]
It has the above configuration. Here, the difference from the data correction circuit 310A of FIG. 2 is that the output signal of the arithmetic circuit 409 is input to the holding circuit 411 that holds the correction voltage data. That is, in this embodiment, the calculation of the correction voltage data is omitted without using the value obtained by multiplying the data error voltage data by the constant a4, which was used in the data correction circuit 310A of FIG. Here, since the value obtained by multiplying the data error voltage data by the constant a4 is often small, the presence or absence of the correction voltage data hardly affects the value. Therefore, even if the correction voltage data is obtained with such a configuration, and the reference image data signal is corrected based on the correction voltage data, the ghost can be eliminated as in the first embodiment. In addition, the circuit configuration is simplified and manufacturing is facilitated.
[0118]
<Fourth Embodiment>
Other embodiments will be described with reference to the drawings. FIG. 9 is a block diagram showing the overall configuration of the liquid crystal display device. In the figure, reference numeral 300D denotes an image signal processing circuit, and reference numeral 310D constituting the image signal processing circuit 300D denotes a data correction circuit. The configuration and operation other than the data correction circuit 310D are the same as those of the liquid crystal display device of FIG.
[0119]
FIG. 10 is a diagram illustrating a configuration example of the data correction circuit 310D. In the figure, the data signal input to the arithmetic circuit 406 is the same as the data correction circuit 310C of FIG. 8 except that the reference image data signal Dint and the delayed reference image data signal Ddly output from the delay circuit 404 are the same. Therefore, the same reference numerals are attached to avoid duplication of explanation.
[0120]
It has the above configuration. 2 is different from the data correction circuit 310C in FIG. 2 in that the data correction circuit 310C uses image data Dmod as a data signal input to the arithmetic circuit 406, whereas the data correction circuit 310D in FIG. Only the delay reference image data signal Ddly output from the circuit 404 is used. Here, the image data signal Dmod is obtained by adding the correction voltage data Dcmp to the delay reference image data signal Ddly. Since the absolute value of the correction voltage data Dcmp is not so large, the difference between the image data signal Dmod and the delayed reference image data signal Ddly is small.
[0121]
Therefore, even if the corrected voltage data Dcmp is obtained by using the delayed reference image data signal Ddly instead of the image data signal Dmod, and the reference image data signal Dint is corrected based on this, the same as in the first embodiment. Ghost can be eliminated. In addition, since the delay reference image data signal Ddly can be directly input to the arithmetic circuit 406, when the data correction circuit 310B is actually made, the operation speed of the element is not increased more than necessary, and the manufacture becomes easy.
[0122]
<Fifth Embodiment>
Other embodiments will be described with reference to the drawings. FIG. 11 is a block diagram showing the overall configuration of the liquid crystal display device. In the figure, reference numeral 300E denotes an image signal processing circuit, and reference numeral 310E constituting the image signal processing circuit 300E denotes a data correction circuit. Since the configuration and operation other than the data correction circuit 310E are the same as those of the liquid crystal display device of FIG. 1, the same reference numerals are given to avoid redundant description.
[0123]
FIG. 12 is a diagram illustrating a configuration example of the data correction circuit 310E. In the figure, the arithmetic circuits 406 and 401 are omitted, and the addition operation is performed between the arithmetic circuits 409 and 410 and the reference image data signal Dint and the image data signal Dmod input directly to the adders 402 and 407, respectively. Except for the point that the arithmetic circuit 414 to be newly provided is provided, the configuration is the same as that of the data correction circuit 310A of FIG.
[0124]
However, the multipliers 403 and 408 respectively perform multiplication operations of predetermined constants a5 and a6, and the arithmetic circuit 414 is configured to add a predetermined value a7 to the value of the arithmetic circuit 409.
[0125]
With the above configuration, at the end of each block period, the adder 402 holds the total value of the image data signals, while the adder 407 holds the total value of the image data signals. . Then, after the multipliers 403 and 408 respectively multiply the respective values by a5 and a6, the arithmetic circuit 409 obtains the sum of both. Further, a constant a7 is added to this sum by the arithmetic circuit 414, and further, the output value of the multiplier 413 is added. This value is held in the holding circuit 411 and used as correction voltage data. This value is nothing but the value of equation (9). Therefore, the ghost is eliminated by adding this to the reference pixel data signal.
[0126]
<Sixth Embodiment>
Next, a liquid crystal display device according to a sixth embodiment of the present invention is described. In this liquid crystal display device, the data correction circuit, which is a component in the image signal processing circuit, is changed to the following configuration. That is, in the sixth embodiment, in the data correction circuit 310E (see FIG. 12) used in the fifth embodiment, the data signal input to the adder 407 is converted into a delayed image data signal instead of the image data signal. This is a replacement configuration. Thereby, the same effect as described in the description of the second embodiment can be obtained.
[0127]
<Seventh Embodiment>
Subsequently, a liquid crystal display device according to a seventh embodiment of the present invention will be described. In this liquid crystal display device, the data correction circuit, which is a component in the image signal processing circuit, is changed to the following configuration. That is, in the seventh embodiment, the data correction circuit 310E used in the fifth embodiment is configured such that the value output from the multiplier 413 is not used for calculation of correction voltage data. Thereby, the same effect as described in the description of the third embodiment can be obtained.
[0128]
<Eighth Embodiment>
Furthermore, a liquid crystal display device according to an eighth embodiment of the present invention will be described. In this liquid crystal display device, the data correction circuit, which is a component in the image signal processing circuit, is changed to the following configuration. That is, in the eighth embodiment, in the data correction circuit 310E used in the fifth embodiment, the value output from the multiplier 413 is not used for calculation of the correction voltage data, and the adder 407 includes The input data signal is replaced with a delayed image data signal instead of the image data signal. Thereby, the same effect as described in the description of the fourth embodiment can be obtained.
[0129]
<Other embodiments>
As described above, the arithmetic circuit configuration has been described based on the formulas (8) and (9), but the present invention is not limited to this, and the same calculation results as the formulas (8) and (9) are obtained. If it is obtained, other circuit configurations may be used. For example, in the data correction circuit 310A of FIG. 2, the multiplication operations are performed by the multipliers 403 and 408 after the adders 402 and 407, respectively, but these multipliers 403 and 408 are placed before the adders 402 and 407, respectively. Even if the addition operation is performed after the multiplication operation is performed first, the same effect as in the first embodiment can be obtained.
[0130]
In the liquid crystal display device according to each of the above-described embodiments, the image data signal output from the image data processing circuits 300A to 300E is converted into an analog signal by the D / A conversion circuit 301, and the block of the liquid crystal display panel 100 is converted. The time axis is expanded and paralleled according to the number of image signal lines constituting the signal line, and supplied to the liquid crystal display panel 100 to perform so-called analog phase expansion. The present invention is not limited to this, and this may be performed by digital phase development. This also achieves the same effect.
[0131]
<Electronic equipment>
Next, some examples in which the liquid crystal display device described in each embodiment described above is used in an electronic device will be described.
[0132]
<Part 1: Projector>
First, a projector using this liquid crystal display device as a light valve will be described. FIG. 13 is a plan view showing a configuration example of the projector.
[0133]
1300 is a projector, 1301 is a lamp unit made of a white light source such as a halogen lamp, 1302 is a light guide, 1303 is a mirror, 1304 is a dichroic mirror, 1305R, 1305G, and 1305B are liquid crystal panels, and 1306 is a dichroic prism, Reference numeral 1307 denotes a projection lens.
[0134]
Here, the projection light emitted from the lamp unit 1301 is separated into three primary colors of red, blue, and green by four mirrors 1303 and two dichroic mirrors 1304 disposed in the light guide 1302. The light enters the liquid crystal panels 1305R, 1305G, and 1305B as light valves corresponding to the primary colors.
[0135]
The configurations of the liquid crystal panels 1305R, 1305G, and 1305B are the same as those of the liquid crystal display panel 100 described above, and are driven by image data signals of primary colors of red, blue, and green supplied from an image signal processing circuit (not shown). The light modulated by these liquid crystal panels is incident on the dichroic prism 1306 from three directions. Of these, red and blue light incident on the dichroic prism 1306 are reflected at right angles, and green light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1307.
[0136]
As described above, the liquid crystal display device of the present invention supplies the reference image data signal plus the correction voltage data as the image data signal of each of the liquid crystal panels 1305R, 1305G, and 1305B. The quality of the displayed image can be greatly improved.
[0137]
<Part 2: Mobile computer>
Next, an example in which the liquid crystal display device of the present invention is applied to a mobile computer will be described. FIG. 14 is a perspective view showing the configuration of the computer. Reference numeral 1400 denotes a computer, 1401 a main body, 1402 a keyboard, 1403 a display unit, and 1404 a liquid crystal display device. The main body 1401 includes a keyboard 1402 and the like, and the display portion 1403 includes a liquid crystal display device 1404. In the liquid crystal display device 1404 used here, a backlight, a reflector, and the like are added to the back surface of the liquid crystal display panel 100 described above. With respect to this as well, the occurrence of ghost can be suppressed, and the quality of the displayed image can be greatly improved.
[0138]
<Part 3: Mobile phone>
Further, an example in which the liquid crystal display device of the present invention is applied to a mobile phone will be described. FIG. 15 is a perspective view showing a configuration of a mobile phone. Reference numeral 1500 denotes a mobile phone, 1501 denotes an operation button, and 1502 denotes a liquid crystal display device. A cellular phone 1500 includes an operation button 1501 and a liquid crystal display device 1502. Here, a reflection plate is provided on the back surface of the liquid crystal display panel of the liquid crystal display device 1502, and a front light is provided on the front surface as necessary. In this respect, the quality of the display image can be greatly improved.
[0139]
As described above, in addition to the electronic devices described with reference to FIGS. 13 to 15, liquid crystal televisions, viewfinder type and monitor direct-view type video tape recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, Examples include workstations, videophones, POS terminals, and devices with touch panels. Needless to say, the present invention can be applied to these various electronic devices.
[0140]
【The invention's effect】
As described above, according to the present invention, an image signal corresponding to each data line is simultaneously supplied for each block based on each sampling signal corresponding to each block in which data lines are grouped into one or more books. When this is sequentially executed for each block, a ghost appearing in the display image is predicted in advance, and the image data signal is corrected so as to compensate for it, so that the quality of the display image can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration example of a data correction circuit 310A.
FIG. 3 is a diagram illustrating a configuration example of adders 402 and 408;
FIG. 4 is a timing chart showing the operation of the data correction circuit 310A.
FIG. 5 is a block diagram showing an overall configuration of a liquid crystal display device according to a second embodiment of the present invention.
FIG. 6 is a diagram illustrating a configuration example of a data correction circuit 310B.
FIG. 7 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a third embodiment of the present invention.
FIG. 8 is a diagram illustrating a configuration example of a data correction circuit 310C.
FIG. 9 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a fourth embodiment of the present invention.
FIG. 10 is a diagram illustrating a configuration example of a data correction circuit 310D.
FIG. 11 is a block diagram showing an overall configuration of a liquid crystal display device according to a fifth embodiment of the present invention.
FIG. 12 is a diagram illustrating a configuration example of a data correction circuit 310E.
FIG. 13 is a plan view illustrating a configuration example of a projector as an example of an electronic apparatus to which a liquid crystal display device is applied.
FIG. 14 is a perspective view illustrating a configuration of a computer as an example of an electronic apparatus to which a liquid crystal display device is applied.
FIG. 15 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which a liquid crystal display device is applied.
FIG. 16 is a diagram showing a configuration of a conventional liquid crystal display device.
17 is a diagram showing a configuration example of a conventional phase expansion circuit 302. FIG.
FIG. 18 is a diagram showing another conventional phase development method.
FIG. 19 is a diagram showing a configuration of a conventional liquid crystal display panel 100. FIG.
FIG. 20 is a diagram illustrating a display content of a conventional liquid crystal display panel and a part of a ghost.
FIG. 21 is a diagram showing an electrical equivalent circuit for explaining a ghost generation mechanism of a liquid crystal display panel.
[Explanation of symbols]
100 …… LCD panel
200 …… Timing circuit
300A ... Image signal processing circuit
301 …… D / A conversion circuit
302 …… Phase expansion circuit
303 …… Amplification / inversion circuit
VID1 ~ 6 ... Image signal (analog signal)
Dint: Reference image data signal
Ddly ...... Delay reference image data signal
Dmod: Image data signal
p1 to p4 …… Internal signal name
401... Arithmetic circuit for performing subtraction
402... Circuit for cumulative addition
403 ... Multiplier that performs multiplication
404 …… Delay circuit
405... Arithmetic circuit for performing addition
406... Arithmetic circuit for performing subtraction
407 ... Circuit for cumulative addition
408... Multiplier that performs multiplication
409... Arithmetic circuit for performing addition
410... Arithmetic circuit for performing addition
411. Holding circuit
412 .. Holding circuit
413... Multiplier that performs multiplication

Claims (21)

A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersecting portions of the scanning lines and the data lines. An image for generating the image data signal used in an electro-optical device in which a voltage based on an image data signal is simultaneously supplied to each data line included in the block based on each sampling signal corresponding to the block A data signal processing method comprising:
A reference image data signal corresponding to one block is delayed by one block period and the correction voltage data is added as the image data signal corresponding to the one block;
When the one block is a target block and a block selected before the target block is a reference block, the correction voltage data includes at least the reference image data signal corresponding to the target block and the reference block. It is generated by calculation for each block using the corresponding image data signal, and corrects a display ghost based on a voltage change of the image data signal between the target block and the reference block. A featured image data processing method. A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. An image data signal processing method for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image signal data,
When a certain block is a target block and a block selected before the target block is a reference block, the reference image data signal corresponding to the target block corresponds to at least the reference image data signal and the reference block. An image data signal or a reference image data signal, and the addition of the correction voltage data obtained by performing a predetermined calculation using the image data signal or the reference image data signal as an image data signal corresponding to the target block,
The predetermined calculation method includes a value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block and a second predetermined value, and the reference of the target block. The sum of values obtained by subtracting the respective values of the image data signal of the corresponding reference block from the corresponding image data signals is multiplied by a third predetermined value and used in the image data signal of the reference block. An image data processing method, which is a calculation method of adding a value obtained by multiplying the correction voltage data by a fourth predetermined value. A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. An image data signal processing method for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image signal data,
When a certain block is a target block and a block selected before the target block is a reference block, the reference image data signal corresponding to the target block corresponds to at least the reference image data signal and the reference block. An image data signal or a reference image data signal, and the addition of the correction voltage data obtained by performing a predetermined calculation using the image data signal or the reference image data signal as an image data signal corresponding to the target block,
The predetermined calculation method includes a value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block and a second predetermined value, and the reference of the target block. The sum of values obtained by subtracting the respective values of the reference image data signals of the corresponding reference blocks from the corresponding image data signals is multiplied by a third predetermined value, and the image data signals of the reference blocks are used. An image data processing method, characterized by being a calculation method of adding a value obtained by multiplying the corrected voltage data by a fourth predetermined value. A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. An image data signal processing method for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image signal data,
When a certain block is a target block and a block selected before the target block is a reference block, the reference image data signal corresponding to the target block corresponds to at least the reference image data signal and the reference block. An image data signal or a reference image data signal, and the addition of the correction voltage data obtained by performing a predetermined calculation using the image data signal or the reference image data signal as an image data signal corresponding to the target block,
The predetermined calculation method includes a value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block and a second predetermined value, and the reference of the target block. An image processing method comprising: adding a value obtained by multiplying a value obtained by subtracting each value of the image data signal of the reference block corresponding to each of the image data signal to a value obtained by multiplying a third predetermined value. Data processing method. A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. An image data signal processing method for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image signal data,
When a certain block is a target block and a block selected before the target block is a reference block, the reference image data signal corresponding to the target block corresponds to at least the reference image data signal and the reference block. An image data signal or a reference image data signal, and the addition of the correction voltage data obtained by performing a predetermined calculation using the image data signal or the reference image data signal as an image data signal corresponding to the target block,
The predetermined calculation method includes a value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block and a second predetermined value, and the reference of the target block. A calculation method of adding a value obtained by multiplying a value obtained by subtracting each value of the reference image data signal of the reference block corresponding to each of the image data signals to a value obtained by multiplying a third predetermined value. Image data processing method. A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. An image data signal processing method for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image signal data,
When a certain block is a target block and a block selected before the target block is a reference block, the reference image data signal corresponding to the target block corresponds to at least the reference image data signal and the reference block. An image data signal or a reference image data signal, and the addition of the correction voltage data obtained by performing a predetermined calculation using the image data signal or the reference image data signal as an image data signal corresponding to the target block,
The predetermined calculation method includes calculating a value obtained by multiplying a sum of values of the reference image data signals of the target block by a first predetermined value and a sum of values of the image data signals of the reference block. 2. A calculation method of adding a value obtained by multiplying a predetermined value of 2, a third predetermined value, and a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. An image data processing method characterized by that. A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. An image data signal processing method for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image signal data,
When a certain block is a target block and a block selected before the target block is a reference block, the reference image data signal corresponding to the target block corresponds to at least the reference image data signal and the reference block. An image data signal or a reference image data signal, and the addition of the correction voltage data obtained by performing a predetermined calculation using the image data signal or the reference image data signal as an image data signal corresponding to the target block,
In the predetermined calculation method, a sum of respective values of the reference image data signal of the target block is multiplied by a first predetermined value, and a sum of values of the reference image data signal of the reference block is calculated. An operation of adding a value obtained by multiplying the second predetermined value, a third predetermined value, and a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. A method for processing image data, characterized by being a method. A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. An image data signal processing method for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image signal data,
When a certain block is a target block and a block selected before the target block is a reference block, the reference image data signal corresponding to the target block corresponds to at least the reference image data signal and the reference block. An image data signal or a reference image data signal, and the addition of the correction voltage data obtained by performing a predetermined calculation using the image data signal or the reference image data signal as an image data signal corresponding to the target block,
The predetermined calculation method includes calculating a value obtained by multiplying a sum of values of the reference image data signals of the target block by a first predetermined value and a sum of values of the image data signals of the reference block. An image data processing method, which is a calculation method of adding a value obtained by multiplying a predetermined value of 2 and a third predetermined value. A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. An image data signal processing method for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image signal data,
When a certain block is a target block and a block selected before the target block is a reference block, the reference image data signal corresponding to the target block corresponds to at least the reference image data signal and the reference block. An image data signal or a reference image data signal, and the addition of the correction voltage data obtained by performing a predetermined calculation using the image data signal or the reference image data signal as an image data signal corresponding to the target block,
In the predetermined calculation method, a sum of respective values of the reference image data signal of the target block is multiplied by a first predetermined value, and a sum of values of the reference image data signal of the reference block is calculated. An image data processing method, which is an arithmetic method for adding a value obtained by multiplying a second predetermined value and a third predetermined value. A plurality of scanning lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines. An image data signal for generating the image data signal used in an electro-optical device in which a voltage based on the image data signal is simultaneously supplied to each data line included in the block based on each sampling signal corresponding to the block A processing circuit,
A reference image data signal corresponding to one block is delayed by one block period and the correction voltage data is added as the image data signal corresponding to the one block;
When the one block is a target block and a block selected before the target block is a reference block, at least a standard image data signal corresponding to the target block and the image data signal corresponding to the reference block An arithmetic processing circuit for obtaining the correction voltage data for correcting a display ghost based on a voltage change of the image data signal between the target block and the reference block, which is generated by calculation for each block. An image data processing circuit comprising: A plurality of scan lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scan lines and the data lines. An image data signal processing circuit for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image data signal,
When a block is a target block and a block selected before the target block is a reference block, a standard image data signal corresponding to the target block and an image data signal or a standard image data signal corresponding to the reference block A calculation processing circuit that adds a calculation result to the reference image data signal corresponding to the target block as the correction voltage data, and outputs the result as an image data signal.
A value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block, a second predetermined value, and the reference image of the target block; The sum of values obtained by subtracting the respective values of the image data signals of the corresponding reference blocks from the corresponding data signals is multiplied by a third predetermined value, and the image data signal used in the image data signals of the reference blocks. An image data processing circuit which is a circuit for performing an operation of adding a value obtained by multiplying correction voltage data by a fourth predetermined value. A plurality of scan lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scan lines and the data lines. An image data signal processing circuit for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image data signal,
When a block is a target block and a block selected before the target block is a reference block, a standard image data signal corresponding to the target block and an image data signal or a standard image data signal corresponding to the reference block A calculation processing circuit that adds a calculation result to the reference image data signal corresponding to the target block as the correction voltage data, and outputs the result as an image data signal.
A value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block, and a reference image of the target block; A sum of values obtained by subtracting each value of the reference image data signal of the corresponding reference block from each of the data signals is multiplied by a third predetermined value and used in the image data signal of the reference block. An image data processing circuit, which is a circuit for performing an operation of adding a value obtained by multiplying the correction voltage data by a fourth predetermined value. A plurality of scan lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scan lines and the data lines. An image data signal processing circuit for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image data signal,
When a block is a target block and a block selected before the target block is a reference block, a standard image data signal corresponding to the target block and an image data signal or a standard image data signal corresponding to the reference block A calculation processing circuit that adds a calculation result to the reference image data signal corresponding to the target block as the correction voltage data, and outputs the result as an image data signal.
A value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block, and a reference image of the target block; A circuit for performing an operation of adding a value obtained by multiplying a value obtained by subtracting each value of the corresponding image data signal of the reference block from a value of each data signal to a third predetermined value. Image data processing circuit. A plurality of scan lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scan lines and the data lines. An image data signal processing circuit for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image data signal,
When a block is a target block and a block selected before the target block is a reference block, a standard image data signal corresponding to the target block and an image data signal or a standard image data signal corresponding to the reference block A calculation processing circuit that adds a calculation result to the reference image data signal corresponding to the target block as the correction voltage data, and outputs the result as an image data signal.
A value obtained by multiplying a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block, and a reference image of the target block; A circuit for performing an operation of adding a value obtained by multiplying a value obtained by subtracting each value of the reference image data signal of the reference block corresponding to each of the data signals to a value obtained by multiplying a third predetermined value. An image data processing circuit. A plurality of scan lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scan lines and the data lines. An image data signal processing circuit for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image data signal,
When a block is a target block and a block selected before the target block is a reference block, a standard image data signal corresponding to the target block and an image data signal or a standard image data signal corresponding to the reference block A calculation processing circuit that adds a calculation result to the reference image data signal corresponding to the target block as the correction voltage data, and outputs the result as an image data signal.
The arithmetic processing circuit outputs a value obtained by multiplying a sum of values of the reference image data signals of the target block by a first predetermined value and a sum of values of the image data signals of the reference block. An operation is performed to add a value obtained by multiplying the predetermined value, a third predetermined value, and a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. An image data processing circuit which is a circuit. A plurality of scan lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scan lines and the data lines. An image data signal processing circuit for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image data signal,
When a block is a target block and a block selected before the target block is a reference block, a standard image data signal corresponding to the target block and an image data signal or a standard image data signal corresponding to the reference block A calculation processing circuit that adds a calculation result to the reference image data signal corresponding to the target block as the correction voltage data, and outputs the result as an image data signal.
The arithmetic processing circuit adds a value obtained by multiplying a sum of values of the reference image data signal of the target block by a first predetermined value and a sum of values of the reference image data signal of the reference block. An operation of adding a value obtained by multiplying a predetermined value of 2, a third predetermined value, and a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. An image data processing circuit characterized by being a circuit to perform. A plurality of scan lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scan lines and the data lines. An image data signal processing circuit for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image data signal,
When a block is a target block and a block selected before the target block is a reference block, a standard image data signal corresponding to the target block and an image data signal or a standard image data signal corresponding to the reference block A calculation processing circuit that adds a calculation result to the reference image data signal corresponding to the target block as the correction voltage data, and outputs the result as an image data signal.
The arithmetic processing circuit outputs a value obtained by multiplying a sum of values of the reference image data signals of the target block by a first predetermined value and a sum of values of the image data signals of the reference block. An image data processing circuit characterized by being a circuit for performing an operation of adding a value obtained by multiplying a predetermined value by a third predetermined value. A plurality of scan lines, a plurality of data lines, and transistors and pixel electrodes provided corresponding to the intersections of the scan lines and the data lines. An image data signal processing circuit for generating image signal data used in an electro-optical device that simultaneously selects the data lines included in the block based on each sampling signal corresponding to each block,
When outputting the reference image data signal plus correction voltage data as the image data signal,
When a block is a target block and a block selected before the target block is a reference block, a standard image data signal corresponding to the target block and an image data signal or a standard image data signal corresponding to the reference block A calculation processing circuit that adds a calculation result to the reference image data signal corresponding to the target block as the correction voltage data, and outputs the result as an image data signal.
The arithmetic processing circuit adds a value obtained by multiplying a sum of values of the reference image data signal of the target block by a first predetermined value and a sum of values of the reference image data signal of the reference block. An image data processing circuit, which is a circuit for performing an operation of adding a value obtained by multiplying a predetermined value of 2 and a third predetermined value. An image data processing circuit according to any one of claims 10 to 18,
A D / A conversion circuit for converting an image data signal which is a digital signal output from the image data processing circuit into an analog signal;
A parallel circuit for extending the time axis and parallelizing the image signal output from the D / A converter circuit according to the number of image signal lines constituting the block;
A scanning line driving circuit for sequentially selecting the scanning lines;
A data line driving circuit for generating each sampling signal for sequentially selecting a block in which a plurality of image signal lines are grouped together;
An electro-optical device, comprising: an image signal supply circuit that supplies the parallel image signal to each of the data lines belonging to the selected block based on each sampling signal. An image data processing circuit according to any one of claims 10 to 18,
A parallelizing circuit for extending and parallelizing the image data signal output from the image data processing circuit in accordance with the number of image signal lines constituting the block;
A D / A conversion circuit for converting an image data signal output from the parallel circuit into an analog signal;
A scanning line driving circuit for sequentially selecting the scanning lines;
A data line driving circuit for generating each sampling signal for sequentially selecting a block in which a plurality of image signal lines are grouped together;
An electro-optical device, comprising: an image signal supply circuit that supplies the parallel image signal to each of the data lines belonging to the selected block based on each sampling signal.   An electronic apparatus comprising the electro-optical device according to claim 19.

Images