JP2001324953A - Method and circuit for processing picture data, electro- optical device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a ghost occurring at the time of sequentially selecting and displaying one or plural data lines collected in blocks. SOLUTION: A value obtained by performing a prescribed arithmetic operation using the picture data of the current block and that of the preceding block is added to the picture data of the current data as a correction data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of simultaneously supplying an image signal corresponding to each data line for each block based on a sampling signal corresponding to each block in which one or a plurality of data lines are grouped. The present invention relates to an image data processing method and an image data processing circuit suitable for use in an electro-optical device for sequentially selecting and executing each block for each block, an electro-optical device using the same, and an electronic apparatus.

[0002]

2. Description of the Related Art FIGS. 16 to 19 show a conventional electro-optical device, for example, an active matrix type liquid crystal device.
This will be described with reference to FIG.

FIG. 16 is a block diagram showing a configuration of a conventional liquid crystal display device. In the figure, 100 is a liquid crystal display panel, 200 is a timing circuit, and 300 is an image signal processing circuit, and these constitute a liquid crystal display device.
Dint is a digital image data signal supplied from an external device (not shown).
Is an image information signal to be displayed. It usually has a multiple bit width. The timing circuit 200 outputs a timing signal (to be described later as necessary) used in each unit.

Further, reference numeral 301 denotes a D / A conversion circuit, 302 denotes a phase expansion circuit, and 303 denotes an amplifying / inverting circuit, and these constitute an image signal processing circuit 300.

Here, the D / A conversion circuit 301 converts the digital image data signal Dint supplied from an external device.
Is converted to an analog signal and output as an image signal VID. Further, a phase expansion circuit (serial-parallel conversion circuit) 3
02, when a series (serial) image signal VID is input, it is developed (parallel-converted) into an h-phase (h = 6 in the figure) image signal and output. Here, the reason for expanding to the h phase is that an image signal supply circuit described later
This is because the application time of the image signal supplied to the TFT is extended, and the sample time and charge / discharge of the image signal of the liquid crystal display panel 100 are sufficiently ensured. A detailed description of the phase development will be given later.

The inverting / amplifying circuit 303 inverts the polarity of the image signal phase-developed into the h phase in accordance with a predetermined rule, or amplifies the image signal VID1 to VID1 to VID1 to VID1 to the phase-developed image signal as appropriate. LCD panel 1 as VID6
00 is supplied. Here, the polarity inversion means inverting the voltage of the image signal with reference to a certain reference potential (generally, the potential of the counter electrode).

Next, the phase expansion circuit 302 will be described. FIG. 17 is a diagram illustrating a configuration example of the phase expansion circuit 302. In the figure, 1701 to 1706 are single pole single throw switches, and 1730 is a 6-pole single throw switch. 1721-1
726 and 1741 to 1746 are capacitors, 1721
1726 and 1751 to 1756 are buffer circuits. Here, one ends of the switch circuits 1701 to 1706 are one terminal Vin, and the other ends are connected to inputs of the buffer circuits 1721 to 1726, respectively.
The outputs of the buffer circuits 1721 to 1726 are connected to the inputs of the buffer circuits 1721 to 1726 via corresponding portions of the switch 1730, respectively.

[0008] Buffer circuits 1721 to 1726 and 175
Each of the inputs 1 to 1756 has a capacitor 17 respectively.
21 to 1726 and 1741 to 1746 are connected, and these capacitors 1721 to 1726 and 1741 are connected.
The other end of .about.1746 is connected to a certain potential. Further, Vin and Vout1 to Vout6 are D / D in FIG.
A terminal to which the output of the A conversion circuit 301 is input, and a terminal to output to the input of the amplification / inversion circuit 303.

[0009] In the above configuration, for example, the value of the image data signal Dint is sequentially changed by α in synchronization with a certain clock signal.
i, 1, αi, 2, ..., αi, 6, αi + 1,1, αi + 1,1, ... αi + 1,
6, αi + 2,1,..., The D / A conversion circuit 301 applies the corresponding voltages, Vi, 1, Vi, 2,.
1, 1, Vi + 1, 1,... Vi, 6, Vi + 2, 1,. Then, in response to this, when the voltage Vi, 1 is output, only the switch 1701 is turned on, the capacitor 1711 is charged to the voltage Vi, 1, and the buffer circuit 1721 holds this voltage. When the voltage Vi, 2 is output, only the switch 1702 is turned on, and similarly, the buffer circuit 172 is turned on.
2 retains the voltage Vi, 2, and so on. The switch 1706 is turned on when the voltage Vi, 6 is output, and the buffer circuit retains the voltage Vi, 6. And only at this time,
The switch 1730 is turned on. Then, the voltage V held in each of the buffer circuits 1721 to 1726 is output.
i, 1 to Vi, 6 and capacitors 1741 to 1746, respectively
And the buffer circuits 1751 to 1756 hold the voltages Vi, 1 to Vi, 6, respectively, and output them to the amplification / inversion circuit 303 in FIG. Then, the switch 1730 is turned off, and this voltage is maintained. afterwards,
When the D / A conversion circuit 301 outputs the voltage Vi + 1,1, only the switch 1701 is turned on, and the buffer circuit 1721
Holds this voltage Vi + 1,1. When the D / A conversion circuit 301 outputs the voltage Vi + 1,2, the switch 170
2 is turned on, and similarly, the buffer circuit 1722 changes the voltage V
When the voltage Vi + 1,6 is output, the switch 1726 is turned on and the buffer circuit 1
When 726 holds the voltage Vi + 1,6, switch 1 again
730 turns on, and the buffer circuits 1751 to 1756 hold the voltages Vi + 1,1 to Vi + 1,6, respectively. Hereinafter, this operation is repeated. From the above operation, the voltage output from the D / A conversion circuit 301 changes successively every clock period, whereas the voltage of the buffer circuits 1751 to 1756 is extended on the time axis in six clock periods and updated. It was done.

Note that the image signal processing circuit 3 described here
In the configuration of 00, the signal converted into the analog signal by the D / A conversion circuit 301 is phase-expanded. The image data Dint is phase-expanded as a digital signal, and a plurality of D / A In some cases, the conversion circuit converts the analog signal into an analog signal. FIG. 18 is a diagram illustrating a phase expansion method in this case. In the figure, 1810 is 6
A bit shift register circuit, 1820 is a latch circuit,
Reference numerals 1831 to 1836 denote D / A conversion circuits. Din is a terminal for inputting an externally supplied image data signal Dint, and Vout1 to Vout6 are terminals for outputting to the input of the amplification / inversion circuit 303 in FIG.

[0011] In such a configuration, the value of the image data signal Dint is changed in order of αi, 1,.
, αi + 1,1,... αi + 1,1,... αi, 6,..., the shift register circuit 1810 synchronizes with the clock signal to generate the image data signal Dint. And shift upward from the bottom in the figure. Then, the contents of the shift register 1810 are, in order from the top, αi, 1, αi, 2,
.., Αi, 6, the contents of the shift register 1810 are taken into the latch circuit 1820 at the rise of the signal LP. Then, voltages Vi, 1, Vi, 2,...
The D / A conversion circuits 1831 to 1836 output Vi, 6, respectively. This state is maintained until the next signal LP rises. During that time, the values of the image data, αi + 1,1, αi + 1,1,... Αi, 6, are sequentially taken into the shift register 1810, and the contents of the shift register 1810 are shifted in order from the top to αi + 1. .., Αi, 6, the signal LP rises and the contents of the shift register SR are taken into the latch circuit 1820. Hereinafter, the same operation is repeated.

As shown in FIGS. 16 and 17, a method of performing phase expansion after converting to an analog signal is referred to as analog phase expansion, and a method of performing phase expansion of a digital signal and converting it to an analog signal. This will be referred to as digital phase development.

Next, the liquid crystal display panel 100 will be described. The liquid crystal display panel 100 has a configuration in which an element substrate and a counter substrate face each other with a gap, and liquid crystal is sealed in the gap.

FIG. 19 shows the liquid crystal display panel 100 of FIG.
FIG. 3 is a diagram showing the configuration of FIG. In FIG. 19, reference numeral 111 denotes a plurality of scanning lines, which are arranged in parallel along the X direction.
112a to 112f are a plurality of data lines, which are arranged in parallel along the Y direction. Here, each data line 112
Are divided into blocks in units of h (here, h = 6), and these are referred to as blocks B1 to Bq (q is a positive integer). For convenience of the following description, when a general data line is pointed out, its code is set to 112, but when a specific data line is specified, its code is set to 112a to 112a.
f.

Reference numeral 113 denotes, for example, a thin film transistor (Thin).
A switching element such as a film transistor (hereinafter, referred to as “TFT”) is provided at each intersection of the scanning line 111 and the data line 112, a source electrode is connected to the data line 112, and a gate electrode is connected to the scanning line 111. Is connected to

Reference numeral 114 denotes a pixel electrode.
Connected to the drain electrode. Each pixel is composed of a pixel electrode 114, a counter electrode (common electrode) (not shown) formed on a counter substrate, and a liquid crystal sandwiched between these electrodes, and includes a scanning electrode 111 and a data line 112.
Will be arranged in a matrix at each intersection with.
Note that, in addition to this, a storage capacitor (not shown) is
4 in some cases.

A scanning line driving circuit 120 is a clock signal output by the timing circuit 200 shown in FIG.
A pulse-like scanning signal is sequentially output to each scanning line 111 based on the CLY, the transfer start signal DY, and the like.
Specifically, the scanning line driving circuit 120 outputs the transfer start signal DY supplied at the beginning of the Y-direction scanning period to the clock signal CLY.
, And sequentially outputs as a scanning signal, thereby sequentially selecting each scanning line 111. In addition,
In addition to the clock signal CLY, its inverted clock signal CLYINV
(Not shown) in some cases.

Reference numeral 130 denotes a data line driving circuit.
The sampling signals S1 to Sq are sequentially output based on the clock signal CLX output from the timing circuit 200 in FIG. 16, the transfer start signal DX, and the like. More specifically, the shift register circuit 130 shown in FIG. 19 sequentially shifts the transfer start signal DX supplied at the beginning of the X-direction scanning period in accordance with the clock signal CLX to sample signals S1 to S1.
These are sequentially output as q. Note that the clock signal C
The inverted clock signal CLXINV (not shown) may be used in addition to LX.

An image signal supply circuit 140 has the following configuration. An image signal line 141 supplies image signals DIV1 to DIV6, respectively. Reference numeral 142 denotes a sampling switch element which is formed of a TFT and is provided corresponding to all the data lines 112. Each source electrode has an image signal on the image signal line 141 in units of six.
DIV1 to DIV6 are input, respectively, and the drain electrodes are connected in order so that one ends of the data lines 112a to 112f correspond to each other. Then, the six TFTs 142 connected to the data lines 112a to 112f of the block B1
Are connected to the signal line of the sampling signal S1, the gate electrodes of the six TFTs 131 connected to the data lines 112a to 112f of the block B2 are connected to the signal line of the sampling signal S2, and so on.
TFs connected to the data lines 112a to 112f
The gate electrode of T142 is connected to the signal line of the sampling signal Sq.

Reference numeral 150 denotes a precharge circuit having the following configuration. Reference numeral 151 denotes a switch element for precharging, which is formed of a TFT, and is provided for all data lines 112.
The precharge voltage VPRE supplied from the outside is input to all the source electrodes, and the drain electrodes are connected to the respective data lines 112.
The precharge gate signal PREG output from the timing circuit 200 in FIG. 19 is supplied to the gate electrode. Note that the precharge voltage VPRE supplied from the outside may have a configuration of a plurality of systems. For example, the pre-charge voltage VPRE1 is applied to the odd-numbered data lines 112a, 112c, and 112e, and the even-numbered data lines 112b, 112d, and 112 are used.
f may be supplied with the precharge voltage VPRE2.

The liquid crystal display panel 100 shown in FIGS.
Has the above configuration. Here, the operation will be described.

First, when a certain scanning line 111 is selected,
First, the precharge gate signal PREG becomes active. Then, the precharge voltage VPRE is applied to all the data lines 112, and the voltage VPRE is written to all the pixels on the selected row. Here, generally, the voltage VPRE is often selected near the center voltage of the pixel signal amplitude. In this operation, an average pixel voltage (= voltage VPR) is applied to each pixel in advance.
By providing E), the subsequent writing operation to each pixel is facilitated, in other words, the time required for writing is shortened. And
Deactivate the precharge gate signal PREG.

Thereafter, when the sampling signal S1 is output, the six data lines 112a to 112a to 112c belonging to the block B1 are output.
Image signals DIV1 to DIV6 are supplied to 112f, respectively, and written to the six pixels at the intersection of the selected scanning line 111 and block B1 by the TFT 116. Thereafter, when the sampling signal S2 is output, the six data lines 112a belonging to the block B2 are output.
To 112f, image signals DIV1 to DIV6 are supplied, respectively, and written to the six pixels at the intersection of the selected scanning line 111 and block B2 by the TFT 113.

Hereinafter, similarly, the sampling signals S3, S4,
.., Sq are sequentially output, and blocks B3, B4,.
The six data lines 112a to 112f belonging to Bq
Scan line 1 in which image signals VID1 to VID6 are selected
Data is written to the six pixels at the intersection of the block 11 and the block. And after this,
The next scanning line 111 is selected, and the same operation is repeatedly performed.

As described above, in this driving method, the number of stages of the data line driving circuit 130 for driving and controlling the switch 142 in the image signal supply circuit 140 is reduced to 1/6 as compared with the method of driving each data line 112 in a dot-sequential manner. Is done. Furthermore, since the frequency of the clock signal CLX and the like to be supplied to the data line driving circuit 130 can be reduced to 1/6, the power consumption can be reduced along with the reduction in the number of stages.

[0026]

However, in the method in which the data lines 112 are driven in blocks, the image to be displayed is blurred in the left and right portions (X direction) adjacent to the image to be displayed (hereinafter referred to as "unevenness"). This phenomenon is called a ghost).

Here, the ghost occurrence will be described in detail. The ghost can be clearly seen when a black square window is displayed on a halftone background. FIG. 20 is a view showing a part of the display content of the liquid crystal display panel 100. The whole figure is a part of the display part, and the vertical lines (dashed lines) in the figure show one pixel column at a time. The solid line of the unit indicates the break of each block. The background is halftone, and the ghosting state is shown when several identically shaped black windows shown by cross hatching are displayed.
The horizontal hatching on the left side of the window, the diagonal hatching on the right side of the square, and the diagonal hatching on the right side are ghosts, respectively, and are called the front ghost, the rear ghost, and the next ghost, respectively. To The characteristic point of these ghosts is that they occur in block units, and the degree does not depend on the height and width of the window, but on the width of the window portion within the block.

Among them, the front ghost is inconspicuous when the window width in the block is small, and becomes brighter as the window width increases, resulting in conspicuous display unevenness. next,
The rear ghost is dark and conspicuous display unevenness when the window width in the block is narrow, and becomes inconspicuous once the window width is widened, but becomes bright and conspicuous when the window frame is further widened. The next ghost is inconspicuous when the window width on the block on the left side of the block is narrow, and becomes darker as the window width increases, resulting in noticeable display unevenness.

These ghosts were found by the authors and the like to be due to the following generation mechanism as a result of research and investigation. FIG. 21 is a diagram showing an electrical equivalent circuit for explaining a ghost generation mechanism of the liquid crystal display panel 100. In the figure, reference numeral 211 denotes a resistance of the counter electrode, which is grounded to a potential indicated by a reverse triangle in the figure. 212a to 212f are image signals DI
It is a parasitic capacitance using liquid crystal as a dielectric between the image signal line 141 that supplies V1 to DIV6 to the TFT 142 of each switch and the counter electrode.

The blocks 142a to 142f include a certain block Bi.
(I is any of 1 to q) switches 142, and 2
13a to 213f are a parasitic capacitance and a pixel capacitance generated between the data line 112 corresponding to the switch 142 and the counter electrode. Note that the voltages of the parasitic capacitance and the pixel capacitance before the block Bi is selected are precharge voltages.

Since the above equivalent circuit is obtained,
As a result of the differentiation circuit being formed by the parasitic capacitances 212a to 212f and the resistor 211, the image signal
Voltage distortion occurs on the differential waveform of the wave height according to the voltage change amount of DIV1 to DIV6. This is factor 1.

Further, when the sampling signal Si (i is any one of 1 to q) is output, the switch 142 of the block Bi is turned on. Then, the parasitic capacitance and the pixel capacitance 2 on the corresponding data lines 112a to 112f are
13a to 213f, charging and discharging are performed from the precharge voltage to the voltage of the corresponding image signal DIV1 to DIV6, and the current at this time causes the counter electrode to have a wave height corresponding to the magnitude of the charging and discharging. A voltage distortion having a differential wave shape occurs. This is factor 2.

The voltage distortion in the form of a differential wave caused by these factors 1 and 2 attenuates with time. However, if the voltage distortion does not become 0 before the output of the sampling signal Si, an error voltage is generated in the pixel, causing display unevenness. Become. For example, assuming that the voltage of the image signal is V0 and the error voltage remaining on the common electrode when the sampling signal Si is completely output is Ve, the voltage between the data line (voltage V0) and the common electrode (voltage Ve) is V0.
−Ve, but this voltage depends on the parasitic capacitance and the pixel capacitance 21.
Since the voltages are 3a to 213f, when the switch 142 is turned off in this state, the voltage is maintained and display unevenness occurs.

To explain this in more detail, a block Bi (i = 1, 2,..., Q) is selected, and Vi, j, j = 1, 2,. , H.

Here, the error voltage remaining on the common electrode immediately before the block Bi is selected is set to Vε0. Then, consider immediately after the block Bi is selected. Then
The error voltage generated at the counter electrode due to factor 1 is as follows (1)
It is shown by the formula.

[0036]

(Equation 1) In equation (1), ζ is a constant, and Vi-1, j is the voltage supplied to the corresponding data line when the block Bi-1 is selected.

Similarly, the error voltage generated at the counter electrode due to factor 2 is expressed by the following equation (2).

[0038]

(Equation 2) However, in the equation (2), ξ is a constant, and Vpre is a precharge voltage. Therefore, the total error voltage generated in the counter electrode is expressed by the following equation (3).

[0039]

(Equation 3) Here, immediately before the end of the selection of the block Bi, it can be expressed by a function using the image signal as a variable (hereinafter, referred to as an error function ferr) by multiplying by a constant attenuation coefficient k as shown in the following equation.

[0040]

(Equation 4) Now, the pre-ghost shown in FIG. 20 will be described with the error function ferr. Since all the pixels on the left of the block of the previous ghost are halftone, if the voltage Vi-1, j is considered to be, for example, the voltage Vpre, the voltage Vi, j is also equal to or higher than the voltage Vpre for the block, and the second term, The third term is non-negative. When the number of pixels satisfying Vi, j> Vpre increases, that is, when the width of the black window over the block increases, both the second and third terms of the equation increase, the positive error increases, and bright unevenness increases. It turns out to be.

Regarding the rear ghost, bright unevenness occurs when the width of the black window over the block increases. But the second
Although the term is non-negative, the third term takes a negative value as the black window becomes narrower. Therefore, when the width of the black window over the block is reduced, the third term becomes dominant and a dark display is obtained.

In the next ghost, the second term becomes 0 and the third term becomes
The term is not positive. Therefore, dark unevenness occurs.

As described above, a front ghost, a rear ghost, and a next ghost occur. In addition, when h is 1, in other words, even in the case of the so-called point-sequential scanning drive, a ghost occurs as understood from the equation (4).

In any case, there is a problem that such a ghost is generated and the quality of a displayed image is deteriorated.

The present invention has been made in view of the above problems, and has as its object to provide an image data processing method and an image data processing circuit capable of removing a ghost and displaying a high quality image. An object of the present invention is to provide an electro-optical device and an electronic device using the same.

[0046]

In order to achieve the above object, in the image data signal processing method of the present invention, a plurality of scanning lines and a plurality of data lines, and an intersection of each of the scanning lines and each of the data lines are provided. A transistor and a pixel electrode provided corresponding to a portion of the data line, and based on a sampling signal corresponding to each block in which the data lines are grouped into one or more lines, the data lines are connected to the respective data lines for each block. A corresponding image signal is supplied simultaneously, which is used for an electro-optical device which is sequentially selected and executed for each block,
An image data signal processing method for generating the image signal, wherein a certain block is set as a target block, and the block selected before the target block is set as a reference block and supplied from outside corresponding to the target block. Correction voltage data obtained by performing a predetermined operation on a reference image data signal using at least the reference image data signal and an image data signal or a reference image data signal corresponding to the image signal supplied to the reference block. Is used as an image data signal corresponding to the target block.

The error of the voltage written to the pixel is substantially determined by the image data corresponding to the target block and the reference block, so that the error of the voltage can be predicted, and the reference image data signal corresponding to the pixel voltage to be originally written is By adding correction voltage data that cancels out the effect of the predicted error voltage, an error in the write voltage can be eliminated, and ghost is eliminated.

More specifically, instead of the reference image signal Vi, j (j = 1, 2,..., H) to be written, the correction voltage Vc
Using the image signal Vi, j + Vcmp to which mp is added, the j-th pixel voltage Vpi, j of the reference block Bi on the selected scanning line row is expressed by the following equation (5).

[0049]

(Equation 5) Here, the pixel voltage Vpi, j only needs to be equal to the reference pixel signal Vi, j. That is, the following equation (6) should be satisfied.

[0050]

(Equation 6) When this is solved for the correction voltage Vcmp, the following equation (7) is established.

[0051]

(Equation 7) Since the correction voltage Vcmp coincides with the error voltage Vε1 remaining on the counter electrode immediately after the selection of the reference block Bi, the ghost should be eliminated by adding the correction voltage Vcmp to the reference image signal Vi, j. is there. Therefore, the ghost can be eliminated by supplying the image data signal Dmod in which the correction voltage data Dcmp corresponding to the correction voltage Vcmp is added to the reference image data signal Dint in advance.

As a predetermined calculation method in the image data processing method of the present invention, a second predetermined value is added to a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. And a value obtained by multiplying a sum of values obtained by subtracting respective values of the image data signal of the corresponding reference block from each of the reference image data signals of the target block by a third predetermined value. And a method of adding a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value.

When the constant part of the above equation for determining the correction voltage Vcmp is represented by ax and (x is a subscript), the following equation (8) is obtained.

[0054]

(Equation 8) In this method, a correction voltage Vcmp is obtained based on the equation (8), and a ghost is eliminated by supplying an image data signal Dmod obtained by adding the corresponding correction voltage data Dcmp to a reference image data signal Dint. Is made possible.

Further, the predetermined calculation method in the image data processing method of the present invention includes a second predetermined value obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. And a third predetermined value multiplied by a sum of values obtained by subtracting respective values of the reference image data signal of the corresponding reference block from each of the reference image data signals of the target block. When,
It is preferable that the correction voltage data used for the image data signal of the reference block be added to a value obtained by multiplying the correction voltage data by a fourth predetermined value.

In this method, the calculation is performed using the reference image data signal instead of the image data signal of the reference block used in the previous method. Here, the difference between the image data signal and the reference image data signal is equivalent to the correction voltage, and since the difference is generally small, the same effect can be obtained.

On the other hand, as a predetermined calculation method in the image data processing method of the present invention, a second predetermined value is obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. And a value obtained by multiplying a sum of values obtained by subtracting respective values of the image data signal of the corresponding reference block from each of the reference image data signals of the target block by a third predetermined value. Is desirable.

In this method, the calculation is performed without using a value obtained by multiplying the correction voltage data by a fourth predetermined value. Here, the value obtained by multiplying the correction voltage data by the fourth predetermined value is generally small, so that the same effect can be obtained and the calculation can be simplified.

As a predetermined calculation method in the image data processing method of the present invention, a second predetermined value is added to a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. And a third predetermined value multiplied by a sum of values obtained by subtracting respective values of the reference image data signal of the corresponding reference block from each of the reference image data signals of the target block. It is desirable to use a method of adding

In this method, the calculation is performed without using a value obtained by multiplying the correction voltage data by a fourth predetermined value. Here, the value obtained by multiplying the correction voltage data by the fourth predetermined value is generally small, so that the same effect can be obtained and the calculation can be simplified.

The predetermined calculation method in the image data processing method of the present invention includes a value obtained by multiplying a sum of respective values of the reference image data signal of the target block by a fifth predetermined value, and a value of the reference block. A value obtained by multiplying a sum of the respective values of the image data signal by a sixth predetermined value, a seventh predetermined value, and the correction voltage data used in the image data signal of the reference block have a fourth value. It is desirable that the calculation method be a method of adding a value multiplied by a predetermined value.

The equations for determining the correction voltage Vcmp are represented by Vi, j and Vi−
When the constants are represented by ax and (x is a suffix), the following equation (9) is obtained.

[0063]

(Equation 9) This method is to solve the ghost by obtaining a correction voltage Vcmp based on the equation (9) and supplying an image data signal Dmod obtained by adding the corresponding correction voltage data Dcmp to the reference image data signal Dint. Is made possible.

On the other hand, as a predetermined calculation method in the image data processing method of the present invention, a value obtained by multiplying a sum of respective values of the reference image data signal of the target block by a fifth predetermined value and a value of the reference block are obtained. A value obtained by multiplying a sum of the respective values of the reference image data signal by a sixth predetermined value, a seventh predetermined value, and the correction voltage data used in the reference image data signal of the reference block are described as follows. It is desirable to use a method of adding a value multiplied by a predetermined value of 4.

In this method, the calculation is performed using the reference image data signal instead of the image data signal of the reference block. Here, the difference between the image data signal and the reference image data signal is equivalent to the correction voltage, and since the difference is generally small, the same effect can be obtained.

The predetermined calculation method in the image data processing method of the present invention includes a value obtained by multiplying a sum of respective values of the reference image data signal of the target block by a fifth predetermined value, and a value of the reference block. It is preferable that a method of adding a value obtained by multiplying a sum of the respective values of the image data signal by a sixth predetermined value and a seventh predetermined value is used.

In this method, the calculation is performed without using a value obtained by multiplying the correction voltage data by a fourth predetermined value. Here, the value obtained by multiplying the correction voltage data by the fourth predetermined value is generally small, so that the same effect can be obtained and the calculation can be simplified.

The predetermined calculation method in the image data processing method of the present invention includes a value obtained by multiplying a sum of respective values of the reference image data signal of the target block by a fifth predetermined value, and a value of the reference block. It is preferable that a method of adding a value obtained by multiplying a sum of the respective values of the reference image data signal by a sixth predetermined value and a seventh predetermined value is used.

In this method, the calculation is performed without using a value obtained by multiplying the correction voltage data by a fourth predetermined value. Here, the value obtained by multiplying the correction voltage data by the fourth predetermined value is generally small, so that the same effect can be obtained and the calculation can be simplified.

As a result, the predetermined calculation method in the image data processing method of the present invention may be any calculation method that provides the same calculation result as any one of the second to ninth calculation methods. That is, the calculation method is not limited to the various methods described above, and ghosts can be eliminated if the same calculation result is obtained.

Next, in order to achieve the above object, in the image data signal circuit of the present invention, a plurality of scanning lines and a plurality of data lines, and a portion where each of the scanning lines intersects with each of the data lines are provided. An image signal corresponding to each data line for each block based on a sampling signal corresponding to each block in which the data lines are grouped into one or more data lines. And an image data signal processing circuit for generating the image signal, which is used in an electro-optical device that is sequentially selected and executed for each block. The reference image data signal supplied from outside corresponding to the target block and the reference block are referred to as the reference block. A predetermined operation is performed using an image data signal or a reference image data signal corresponding to the image signal supplied to the block, and the calculation result is added to the reference image data signal corresponding to the target block as correction voltage data. And an arithmetic processing circuit for outputting an image data signal. The present invention is a circuit which embodies the above-described image data processing method, and has the same effects as described above for the image data processing method.

The arithmetic processing circuit in the image data processing circuit according to the present invention is configured such that a second predetermined value is added to a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A value obtained by multiplying a sum of values obtained by subtracting respective values of the image data signal of the corresponding reference block from each of the reference image data signals of the target block by a third predetermined value, It is preferable that the circuit be a circuit that performs an operation of adding a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. This configuration is a circuit that embodies the image data processing method, and according to this configuration, the same effects as described above for the image data processing method can be obtained.

The arithmetic processing circuit in the image data processing circuit of the present invention may be configured such that a second predetermined value is added to a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A value obtained by multiplying a sum of values obtained by subtracting respective values of the reference image data signal of the corresponding reference block from each of the reference image data signals of the target block by a third predetermined value; And a circuit for performing an operation of adding a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. This configuration is a circuit that embodies the image data processing method, and according to this configuration, the same effects as described above for the image data processing method can be obtained.

On the other hand, as an arithmetic processing circuit in the image data processing circuit of the present invention, a second predetermined value is added to a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A value obtained by multiplying a sum of values obtained by subtracting respective values of the image data signal of the corresponding reference block from each of the reference image data signals of the target block by a third predetermined value is added. A configuration that is a circuit that performs an operation is desirable. This configuration is a circuit that embodies the image data processing method, and according to this configuration, the same effects as described above for the image data processing method can be obtained.

The arithmetic processing circuit in the image data processing circuit according to the present invention is configured such that a second predetermined value is added to a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A value obtained by multiplying a sum of values obtained by subtracting respective values of the reference image data signal of the corresponding reference block from each of the reference image data signals of the target block by a third predetermined value; Is desirably a circuit that performs an operation of adding This configuration is a circuit that embodies the image data processing method, and according to this configuration, the same effects as described above for the image data processing method can be obtained.

The arithmetic processing circuit in the image data processing circuit of the present invention includes a value obtained by multiplying a sum of the respective values of the reference image data signal of the target block by a fifth predetermined value, and a value of the reference block. A value obtained by multiplying the sum of the respective values of the image data signal by a sixth predetermined value;
And a circuit for performing an operation of adding a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. This configuration is a circuit that embodies the image data processing method, and according to this configuration, the same effects as described above for the image data processing method can be obtained.

On the other hand, the arithmetic processing circuit in the image data processing circuit of the present invention includes a value obtained by multiplying the sum of the respective values of the reference image data signals of the target block by a fifth predetermined value and the value of the reference block. A value obtained by multiplying the sum of the respective values of the image data signal by a sixth predetermined value;
And a circuit for performing an operation of adding a value obtained by multiplying the correction voltage data used in the reference image data signal of the reference block by a fourth predetermined value. This configuration is a circuit that embodies the image data processing method, and according to this configuration, the same effects as described above for the image data processing method can be obtained.

The arithmetic processing circuit in the image data processing circuit of the present invention includes a value obtained by multiplying a sum of the respective values of the reference image data signal of the target block by a fifth predetermined value, and a value of the reference block. A value obtained by multiplying the sum of the respective values of the image data signal by a sixth predetermined value;
It is desirable that the circuit is a circuit that performs an operation of adding the predetermined value. This configuration is a circuit that embodies the image data processing method, and according to this configuration, the same effects as described above for the image data processing method can be obtained.

The arithmetic processing circuit in the image data processing circuit according to the present invention includes a value obtained by multiplying a sum of respective values of the reference image data signals of the target block by a fifth predetermined value, and a value of the reference block. A value obtained by multiplying a sum of respective values of the reference image data signal by a sixth predetermined value;
It is desirable that the circuit be a circuit that performs an operation of adding a seventh predetermined value. This configuration is a circuit that embodies the image data processing method, and according to this configuration, the same effects as described above for the image data processing method can be obtained.

After all, the arithmetic processing circuit in the image data processing circuit of the present case may have any circuit configuration that can provide the same operation result as any one of the twelfth to nineteenth aspects. That is, the configuration of the arithmetic processing circuit is not limited to the various configurations described above, and ghosts can be eliminated if the same arithmetic result is obtained.

Next, in order to achieve the above object, an electro-optical device according to the present invention includes an image data processing circuit according to claim 11 and an image data signal which is a digital signal output from the image data processing circuit. D to convert to analog signal
A / A conversion circuit, a parallelization circuit for extending the image signal output from the D / A conversion circuit on a time axis according to the number of image signal lines constituting the block and parallelizing the image signal, and sequentially connecting the scanning lines. A scanning line driving circuit for selecting, a data line driving circuit for generating each sampling signal for sequentially selecting a block in which the image signal lines are grouped into a plurality of lines, and selecting the parallelized image signal based on each sampling signal. And an image signal supply circuit for supplying each of the data lines belonging to the selected block.

According to this electro-optical device, the quality of the displayed image can be greatly improved, and the image signal can be supplied to the data lines in block units, so that the configuration of the data line driving circuit can be simplified. Can be
And the power consumption can be reduced.

Similarly, in order to achieve the above-mentioned object, another electro-optical device according to the present invention comprises an image data processing circuit according to claim 11 and an image data signal output from the image data processing circuit, and And a D / A conversion circuit for converting an image data signal output from the parallelization circuit into an analog signal, and a scan line. A scanning line driving circuit for sequentially selecting the image signal lines, a data line driving circuit for generating each sampling signal for sequentially selecting a block in which a plurality of the image signal lines are grouped, and the parallelized image signal based on each sampling signal. And an image signal supply circuit for supplying each of the data lines belonging to the selected block.

According to this electro-optical device, the quality of the displayed image can be greatly improved, and the image signal can be supplied to the data lines in block units, so that the configuration of the data line driving circuit can be simplified. Can be
And the power consumption can be reduced.

Further, in order to achieve the above object, an electronic apparatus according to the present invention is provided with an electro-optical device according to claim 21 or 22. Such electronic devices include, for example, video projectors, notebook personal computers, mobile phones, and the like.

[0086]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment First, an active matrix liquid crystal display device according to a first embodiment of the present invention will be described as an example of an electro-optical device.

FIG. 1 is a block diagram showing the overall configuration of the liquid crystal display device of the present invention. In the figure, 100 is a liquid crystal display panel, 200 is a timing circuit, 300A is an image signal processing circuit, and these constitute a liquid crystal display device. Among these, the timing circuit 200 outputs a timing signal (to be described later as necessary) used in each unit.

Reference numeral 301 denotes a D / A conversion circuit, 302 denotes a phase expansion circuit, 303 denotes an amplification / inversion circuit, and 310A denotes a data correction circuit, and these constitute an image signal processing circuit 300A. The liquid crystal display device according to this embodiment includes a data correction circuit 310 in the image signal processing circuit 300A.
Except that A is provided before the D / A conversion circuit 301,
Since the configuration is the same as that of the conventional liquid crystal display device shown in FIG. 16, common portions are denoted by the same reference numerals to avoid duplication of description. Dint is a reference image data signal supplied from an external device or the like (not shown), and Dmod is an image data signal output from the data correction circuit 310A.
Here, in the description of the related art, Dint is referred to as an image data signal, but the name will be changed in the following manner. In addition, the reference image data signal Dint usually includes a plurality of bits.

Then, the D / A conversion circuit 301 converts the image data Dmod into an analog signal and outputs it as an image signal VID. Further, the phase expansion circuit 302 outputs a series of image signals.
When a VID is input, it is developed into an h-phase image signal and output. In the present embodiment, the case where h is 6 will be described, but is not limited to this, and may be any number of one or more integers.

The inverting / amplifying circuit 303 inverts the polarity of the image signal in accordance with a predetermined rule, or amplifies the image signal as it is, and appropriately amplifies the image signal to expand the image signals VID1 to VID6.
To the liquid crystal display panel 100.

FIG. 2 is a diagram showing a configuration example of the data correction circuit 310A. In this figure, reference numeral 401 denotes an arithmetic circuit for performing subtraction, and a predetermined numerical value a1 is calculated from a reference image data signal.
pull. Reference numeral 402 denotes an adder, which cumulatively adds the output values of the arithmetic circuit 401. Details will be described later. An arithmetic circuit 403 performs multiplication, and outputs a value obtained by multiplying the output value of the adder 402 by a predetermined coefficient a2. In the present embodiment, this is
It is composed of a look-up table using a read-only memory or the like. That is, the output value of the adder 402 is used as the address of the memory, and the data on the address is a value obtained by multiplying the address value by the coefficient a2.

On the other hand, a delay circuit 404 takes in the reference image data Dint, delays it and outputs it. In the present embodiment, the shift register circuit includes six stages of shift register circuits. The data signal output with delay is referred to as a delayed reference data signal,
It will be represented by the symbol Ddly. An arithmetic circuit 405 performs addition, and adds an output of the delay circuit 404 and a value of an output of a holding circuit 411 described later. The output value becomes the image data signal Dmod.

Reference numeral 406 denotes an arithmetic circuit for performing a subtraction operation.
pull. Reference numeral 407 denotes an adder, which cumulatively adds the output values of the arithmetic circuit 406. Details will be described later. An arithmetic circuit 408 performs multiplication, and outputs a value obtained by multiplying the output value of the adder 407 by a predetermined coefficient a3. In the present embodiment, this is
It is composed of a look-up table using a read-only memory or the like. An arithmetic circuit 409 performs addition, and adds the output of the arithmetic circuit 403 and the output value of the arithmetic circuit 408. And
An arithmetic circuit 410 performs addition, and adds the output of the arithmetic circuit 409 and the output value of the arithmetic circuit 413 described later.

Next, reference numerals 411 and 412 denote holding circuits for holding data, respectively, which hold the output of the arithmetic circuit 410 and the output of the holding circuit 411, respectively. In this embodiment, this circuit is constituted by a latch circuit. 413
Is an arithmetic circuit that performs multiplication, and outputs a value obtained by multiplying the output value of the holding circuit 412 by a predetermined coefficient a4. In the present embodiment, this is constituted by a reference table or the like using a read-only memory or the like.

Here, the clock signal CLK and the latch pulse signal LP are given as control signals from the timing circuit 200 of FIG. 1 to the data correction circuit 310A. The clock signal CLK is supplied to the adders 402 and 408 and the delay circuit 4
04 used as a clock signal and a latch pulse signal
LP is used as a clock signal for the holding circuits 411 and 412 and as a control signal for the adders 402 and 408. Note that the reference image data Dint changes in synchronization with the rise of the clock signal CLK, and the data correction circuit 310A
Shall be entered. In the drawing, p1 to p4 are names of internal signal lines, and indicate output signals of the adders 402 and 408 and the holding circuits 411 and 412, respectively.

FIG. 3 is a diagram showing a configuration example of the adder 402 or 408. In the figure, 501 is an arithmetic circuit for performing addition, 502 is a data selector circuit, and 503 is a holding circuit. The arithmetic circuit 501 adds the output value Dout of the holding circuit and the input value Din. Data selector circuit 502
Selects either the input value Din or the output value of the adding circuit 501 and outputs the selected value. This is controlled by the latch pulse signal LP, and selects the input value Din when the signal LP is active and the output value of the adder 501 when the signal LP is inactive. The holding circuit 503 fetches and holds the output value of the data selector circuit 502 in synchronization with the falling of the clock signal CLK.

Therefore, when the signal CLK falls while the signal LP is active, the input value Din is taken into the holding circuit 503, and thereafter, the signal LP becomes inactive, and when the signal CLK falls again, the holding value is held. The value obtained by adding the input value Din to the value of the circuit 503 is taken into the holding circuit 503. Thereafter, during the period in which the signal LP is inactive, each time the signal CLK falls, the value obtained by adding the input value Din to the value of the holding circuit 503 becomes
The data is taken into the holding circuit 503 and cumulatively added.

The configuration of the data correction circuit 310A shown in FIGS. 1 and 2 is as described above.

Next, the operation will be described. FIG. 4 is a timing chart showing the operation of the data correction circuit 310A. In the figure, a clock signal CLK, a latch pulse signal LP, a reference image data signal Dint, internal signals p1 to p4, and a delay reference image data signal Ddl output from the timing circuit 200 from above.
y indicates an image data signal Dmod. The horizontal axis is time. Assuming that the time of one cycle of the clock signal CLK is tc, the cycle of the latch pulse signal LP is h (= 6) times that, and the cycle is tb.
And Here, the period during which the signal LP is active (upper level in the figure) is 1 · tc. A period from the rising of the latch pulse signal LP to the next rising is defined as one block period. A period in which the reference image data signal Vi, j corresponding to the i-th block Bi of the liquid crystal display panel 100 is supplied from an external device is defined as an i-th block period, and a subsequent block period is defined as an (i + 1) -th block period. I do.

Here, the symbol αi, j (i = 1,2,..., Q, j = 1,2,
.., 6) are the i-th block B of the liquid crystal display panel 100.
The content of the reference image data signal Dint corresponding to the pixel at the position where the j-th data line in i and the currently selected scanning line row intersect is shown. Similarly, the symbol βi, j (i = 1,2,
.., Q, j = 1, 2,..., 6) correspond to the portion where the j-th data line in the i-th block Bi of the liquid crystal display panel 100 intersects with the currently selected scanning line row. The content of the corresponding image data signal Dmod is shown. The symbol γi, 1 indicates a value obtained by subtracting a predetermined constant a1 from the reference image data signal αi, 1. Subsequent symbols Σγ1-2 represent values obtained by adding a value obtained by subtracting a1 from the reference image data signal αi, 2 to γi, 1, and symbols Σγ1-3 represent reference image data signals αi, 3 to Σγ1-2. From a
Indicates a value obtained by adding a value obtained by subtracting 1, and similarly indicates a cumulative addition value. Next, the symbol δi, 1 is the reference image data signal αi, 1
Is a value obtained by subtracting the image data signal βi-1,1 from. Subsequent symbols Σδ1 to Σ2 are the reference image data signals αi, 2
From the image data signal βi-1,2 is subtracted from the reference image data signal α.
A value obtained by adding a value obtained by subtracting the image data signal βi-1,3 from i, 3 is shown, and similarly, a cumulative addition value is shown below. The symbol Dcmpi
Indicates the value of the correction voltage data added to the reference image data signal Dint corresponding to the block Bi.

First, in synchronization with the rise of the clock signal CLK, from the beginning of the i-th block period, the externally supplied reference pixel data signal Dint has values αi, 1, αi, 2 corresponding to the block Bi. ,…, Take αi, 6 and follow, i-th
In the +1 block period, the values corresponding to the block Bi + 1 are αi + 1,1, αi + 1,2,..., Αi + 1,6, and are sequentially repeated.

Here, the arithmetic circuit 401 subtracts a constant a1 from the reference image data signal αi, 1 to obtain a value γi, 1. At this time, since the signal LP is active, it is taken into the adder 402 and held in synchronization with the fall of the signal CLK. Next, the arithmetic circuit 401 subtracts the constant a1 from the reference image data signal αi, 2 to obtain a value γi, 2. At this time, since the signal LP is inactive, a value Σγ1-2 obtained by adding the value γi, 1 and the value γi, 2 held in the adder 402 is held in synchronization with the fall of the signal CLK. . Hereinafter, the cumulative addition is similarly performed until the block period. This is shown as a signal p1.

Next, the arithmetic circuit 406 subtracts the image data signal βi-1,1 from the reference image data signal αi, 1 to obtain a value δi, 1
Get. At this time, since the signal LP is active, it is taken into the adder 407 and held in synchronization with the fall of the signal CLK. Next, the arithmetic circuit 406 outputs the reference image data signal α
The image data signal βi-1,2 is subtracted from i, 2 to obtain a value δi, 2. At this time, since the signal LP is inactive, the value Σδ1〜2 obtained by adding the value δi, 1 and the value δi, 2 held in the adder 407 is held in synchronization with the fall of the signal CLK. . Hereinafter, the cumulative addition is similarly performed until the block period. This is shown as a signal p2.

Then, at the end of the block period,
The adder 402 has a total sum of values obtained by subtracting a constant a1 from the respective reference image data signals αi, j of the block BiΣγ1Σ6.
Is stored in the adder 407 from the reference image data signal αi, 2 of each block Bi to the block Bi−1
Sum of values obtained by subtracting the corresponding image data signals βi-1, j
δ1 to 6 are retained. These values are respectively assigned to multipliers 40
Are multiplied by the constants a2 and a3 by 3 and 408, and furthermore by the arithmetic circuit 409
And both values are added.

Then, the value of the arithmetic circuit 409 and the output value of the multiplier 413 are added by the arithmetic circuit 410. This value becomes the correction voltage data Dcmpi, and is taken in and held by the holding circuit 411 in synchronization with the rise of the signal LP. This is shown as a signal p3.

Next, the delay circuit 404 takes in the reference pixel data signal Dint input from the outside in synchronization with the rise of the signal CLK, and outputs a delayed reference pixel data signal delayed by one block period (tb). This signal is shown as Ddly.

Then, the arithmetic circuit 405 adds the value of the holding circuit 411, that is, the correction voltage data Dcmpi to the value of the delay reference pixel data signal, and outputs the result as a pixel data signal Dmod. That is, the image data signal Dm corresponding to the block Bi
od is output during the (i + 1) th block period.

Lastly, the holding circuit 412
The value of 1 is captured and held in synchronization with the rise of the signal LP. That is, the correction voltage data Dcmpi-1 used one block period ago, in other words, the error voltage data is taken in,
Hold. This is shown as a signal p4. Therefore, the output of the multiplier 413 is obtained by multiplying the error voltage data by the constant a4.

Since the above operation is performed, a value obtained by multiplying the sum of values obtained by subtracting the constant a1 from each value of the reference image data signal Dint of the block Bi by the constant a2 and the value From each of the Bi reference image data signals Dint, the corresponding image data signal Dm of the block Bi-1
Sum of values obtained by subtracting each of od Σ δ1 ~ 6 multiplied by a constant a3 and error voltage data one block period earlier by a constant
The value of the sum with the value multiplied by a4 is held, and this value is used as the voltage correction data Dcmp. This value is nothing but the value of equation (8). Therefore, this is referred to as the reference pixel data signal Dint
By generating an image data signal Dmod and driving the liquid crystal display panel 100, the ghost is eliminated.

<Second Embodiment> Another embodiment will be described with reference to the drawings. FIG. 5 is a block diagram illustrating the overall configuration of the liquid crystal display device. In the figure, reference numeral 300B denotes an image signal processing circuit.
Reference numeral 310B which constitutes 00B is a data correction circuit. Since the configuration and operation other than the data correction circuit 310B are the same as those of the liquid crystal display device of FIG. 1, the same reference numerals are given and the description will not be repeated.

FIG. 6 is a diagram showing a configuration example of the data correction circuit 310B. In the figure, since the data signal input to the arithmetic circuit 406 is the same as the data correction circuit 310A in FIG. 2 except that the reference image data signal Dint and the delayed reference image data signal output from the delay circuit 404 are used. , Are denoted by the same reference numerals to avoid duplication of description.

The configuration is as described above. Here, the difference from the data correction circuit 310A in FIG. 2 is that the data correction circuit 310A uses the image data Dmod as the data signal to be input to the arithmetic circuit 406, whereas the data correction circuit 310B in FIG. The only difference is that the delay reference image data signal Ddly output from the circuit 404 is used.
Here, the image data signal Dmod is obtained by adding the correction voltage data Dcmp to the delay reference image data signal Ddly. Since the absolute value of the correction voltage data Dcmp is not so large, the difference between the image data signal Dmod and the delay reference image data signal Ddly is small.

Therefore, even if the correction voltage data Dcmp is obtained by using the delayed reference image data signal Ddly instead of the image data signal Dmod, and the reference image data signal Dint is corrected based on this, the first embodiment Ghosts can be eliminated similarly to the form. In addition, since the delay reference image data signal Ddly can be directly input to the arithmetic circuit 406, when the data correction circuit 310B is actually manufactured, the operation speed of the circuit element does not need to be increased more than necessary, and manufacturing becomes easy. .

<Third Embodiment> Another embodiment will be described with reference to the drawings. FIG. 7 is a block diagram illustrating the overall configuration of the liquid crystal display device. In the figure, reference numeral 300C denotes an image signal processing circuit.
310C which constitutes 00C is a data correction circuit. Since the configuration and operation other than the data correction circuit 310C are the same as those of the liquid crystal display device of FIG. 1, they are denoted by the same reference numerals and the description thereof will not be repeated.

FIG. 8 is a diagram showing a configuration example of the data correction circuit 310C. In the figure, the signal input to the holding circuit 411 is the arithmetic circuit 409, and is the same as the data correction circuit 310A in FIG. 2 except that the arithmetic circuit 410, the holding circuit 412, and the multiplier 413 are omitted. , Are denoted by the same reference numerals to avoid duplication of description.

The configuration is as described above. Here, the difference from the data correction circuit 310A of FIG. 2 is that the output signal of the arithmetic circuit 409 is a holding circuit 411 that holds correction voltage data.
It is the point that is input to. That is, in the present embodiment, the data correction circuit 3 shown in FIG.
The constant a4 is used for the data error voltage data used in 10A.
Is omitted without using the value multiplied by. Here, since the value obtained by multiplying the data error voltage data by the constant a4 is often small, the presence or absence of the value does not greatly affect the correction voltage data. Therefore, even when the correction voltage data is obtained in such a configuration and the reference image data signal is corrected based on the correction voltage data, the ghost can be eliminated as in the first embodiment. Further, the circuit configuration is simplified, and the manufacture is facilitated.

<Fourth Embodiment> Another embodiment will be described with reference to the drawings. FIG. 9 is a block diagram illustrating the overall configuration of the liquid crystal display device. In the figure, reference numeral 300D denotes an image signal processing circuit, and further, an image signal processing circuit 3
310D which constitutes 00D is a data correction circuit. Since the configuration and operation other than the data correction circuit 310D are the same as those of the liquid crystal display device of FIG. 7, the same reference numerals are given to avoid duplication of the description.

FIG. 10 is a diagram showing a configuration example of the data correction circuit 310D. In the figure, the data correction circuit 310C is the same as the data correction circuit 310C in FIG. 8 except that the data signals input to the arithmetic circuit 406 are the reference image data signal Dint and the delay reference image data signal Ddly output from the delay circuit 404. Therefore, the same reference numerals are given to avoid duplicate description.

The configuration is as described above. Here, the difference from the data correction circuit 310C of FIG. 2 is that the data correction circuit 310C uses the image data Dmod as the data signal to be input to the arithmetic circuit 406, whereas the data correction circuit 310D of FIG. The only difference is that the delay reference image data signal Ddly output from the circuit 404 is used. Here, the image data signal Dmod is obtained by adding the correction voltage data Dcmp to the delay reference image data signal Ddly. Since the absolute value of the correction voltage data Dcmp is not so large, the difference between the image data signal Dmod and the delay reference image data signal Ddly is small.

Therefore, the correction voltage data Dcmp is obtained by using the delay reference image data signal Ddly instead of the image data signal Dmod, and based on this, the reference image data signal Di is obtained.
Even if a correction is made to nt, the ghost can be eliminated as in the first embodiment. In addition, since the delay reference image data signal Ddly can be directly input to the arithmetic circuit 406, when the data correction circuit 310B is actually produced, the operation speed of the element is not increased more than necessary, and the manufacturing becomes easy.

<Fifth Embodiment> Another embodiment will be described with reference to the drawings. FIG. 11 is a block diagram illustrating the overall configuration of the liquid crystal display device. In the figure, 300E
Is an image signal processing circuit, and 310E constituting the image signal processing circuit 300E is a data correction circuit.
Since the configuration and operation other than the data correction circuit 310E are the same as those of the liquid crystal display device of FIG. 1, the same reference numerals are given to avoid duplication of the description.

FIG. 12 is a diagram showing a configuration example of the data correction circuit 310E. In the figure, arithmetic circuits 406 and 4
01 is omitted, and the reference image data signal Dint and the image data signal Dmod are directly added to the adders 402 and 407, respectively.
2 except for the point that the data correction circuit 310A is input and the addition of an arithmetic circuit 414 that performs an addition operation between the arithmetic circuits 409 and 410.

However, the multipliers 403 and 408 are respectively
The arithmetic circuit 414 performs a multiplication operation by a predetermined constant a5 or a6 times, and the arithmetic circuit 414 adds a predetermined value a7 to the value of the arithmetic circuit 409.

With the above configuration, at the end of each block period, the adder 402 holds the sum of the image data signals, while the adder 407 holds the sum of the image data signals. Will be retained. And the multiplier 40
After the respective values are multiplied by a5 and a6 in 3 and 408, respectively, the arithmetic circuit 409 obtains the sum of the two. Further, the arithmetic circuit 414 adds a constant a7 to the sum, and further adds an output value of the multiplier 413. This value is stored in the holding circuit 41
1 and used as correction voltage data. This value is nothing but the value of equation (9). Therefore, a ghost is eliminated by adding this to the reference pixel data signal.

<Sixth Embodiment> Next, a liquid crystal display device according to a sixth embodiment of the present invention will be described. In this liquid crystal display device, a data correction circuit, which is a component in the image signal processing circuit, is changed to the following configuration. That is, in the sixth embodiment, the data correction circuit 310E (see FIG. 12) used in the fifth embodiment converts the data signal input to the adder 407 into a delayed image data signal instead of an image data signal. The configuration is replaced. Thereby, the same effect as that described in the description of the second embodiment can be obtained.

<Seventh Embodiment> Subsequently, a seventh embodiment of the present invention will be described.
The liquid crystal display device according to the embodiment will be described. In this liquid crystal display device, a data correction circuit, which is a component in the image signal processing circuit, is changed to the following configuration. That is, in the seventh embodiment, in the data correction circuit 310E used in the fifth embodiment, the multiplier 4
13 is not used for calculating the correction voltage data. Thereby, the same effects as described in the description of the third embodiment can be obtained.

<Eighth Embodiment> An eighth embodiment of the present invention will be described.
The liquid crystal display device according to the embodiment will be described. In this liquid crystal display device, a data correction circuit, which is a component in the image signal processing circuit, is changed to the following configuration. That is, in the eighth embodiment, in the data correction circuit 310E used in the fifth embodiment, the value output from the multiplier 413 is not used for calculating the correction voltage data, and the adder 407 The input data signal is replaced with a delayed image data signal instead of the image data signal. Thereby, the same effects as described in the description of the fourth embodiment can be obtained.

<Other Embodiments> The configuration of the arithmetic circuit has been described based on the expressions (8) and (9). However, the present invention is not limited to this. Other circuit configurations may be used as long as the same operation result as the expression (9) is obtained. For example, in the data correction circuit 310A of FIG.
After each of the multipliers 403 and 407, the multipliers 403 and 408 perform a multiplication operation.
The same effect as in the first embodiment can be obtained by bringing 8 before the adders 402 and 407, performing the multiplication operation first, and then performing the addition operation.

In the liquid crystal display device according to each of the above-described embodiments, the D / A conversion circuit 301 converts the image data signals output from the image data processing circuits 300A to 300E into analog signals, The time axis is extended and parallelized according to the number of image signal lines constituting 100 blocks, and supplied to the liquid crystal display panel 100.
It is configured to perform so-called analog phase expansion. The present invention is not limited to this, and this may be performed by digital phase expansion. With this, the same effect can be obtained.

<Electronic Equipment> Next, some examples in which the liquid crystal display device described in each of the above embodiments is used for electronic equipment will be described.

<Part 1: Projector> First, a projector using this liquid crystal display device as a light valve will be described. FIG. 13 is a plan view showing one configuration example of the projector.

Reference numeral 1300 denotes a projector;
Is a lamp unit including a white light source such as a halogen lamp, 1302 is a light guide, 1303 is a mirror, 13
04 is a dichroic mirror, 1305R, 1305
G and 1305B are liquid crystal panels, 1306 is a dichroic prism, and 1307 is a projection lens.

Here, the projection light emitted from the lamp unit 1301 is divided into four mirrors 1303 and two dichroic mirrors arranged in the light guide 1302.
The light is separated into three primary colors of red, blue, and green by a mirror 1304 and is incident on liquid crystal panels 1305R, 1305G, and 1305B as light valves corresponding to the respective primary colors.

Liquid crystal panels 1305R, 1305G, 13
The configuration of 05B is equivalent to that of the above-described liquid crystal display panel 100, and is driven by image data signals of respective primary colors of red, blue and green supplied from an image signal processing circuit (not shown). Light modulated by these liquid crystal panels is incident on the dichroic prism 1306 from three directions. Among them, dichroic prism 13
The red and blue light incident on 06 is reflected at right angles, and the green light goes straight. Therefore, as a result of combining the images of the respective colors, a color image is projected on a screen or the like via the projection lens 1307.

As described above, the liquid crystal display device of the present invention uses the reference image data signal with the correction voltage data added thereto for each of the liquid crystal panels 1305R, 1305G, and 1305.
Since the image data is supplied as the B image data signal, the occurrence of ghost can be suppressed, and the quality of the displayed image can be greatly improved.

<Part 2: Mobile Computer> Next, an example in which the liquid crystal display device of the present invention is applied to a mobile computer will be described. FIG. 14 is a perspective view showing the configuration of a computer. 1400 is a computer, 1401 is a main body, 1402 is a keyboard, 1403
Denotes a display unit, and 1404 denotes a liquid crystal display device. Body 140
1 includes a keyboard 1402 and the like, and a display portion 1403 includes a liquid crystal display device 1404. In the liquid crystal display device 1404 used here, a backlight, a reflector, and the like are added to the back surface of the liquid crystal display panel 100 described above. Also in this case, occurrence of ghost can be suppressed, and the quality of the displayed image can be greatly improved.

<Part 3: Mobile phone> An example in which the liquid crystal display device of the present invention is applied to a mobile phone will be described. FIG. 15 is a perspective view showing a configuration of a mobile phone. 1500 is a mobile phone, 1501 is an operation button, and 1502 is a liquid crystal display device. The mobile phone 1500 includes an operation button 1501 and a liquid crystal display device 1502. Here, a reflection plate is provided on the back surface of the liquid crystal display panel of the liquid crystal display device 1502, and a front light is provided on the front surface as needed. Also in this case, the quality of the display image can be greatly improved.

In addition to the electronic devices described with reference to FIGS. 13 to 15, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic organizer, and a calculator , A word processor, a workstation, a videophone, a POS terminal, a device having a touch panel, and the like. It goes without saying that the present invention can be applied to these various electronic devices.

[0140]

As described above, according to the present invention, an image corresponding to each data line is provided for each block based on a sampling signal corresponding to each block in which one or more data lines are combined. When signals are simultaneously supplied and sequentially executed for each block, a ghost appearing in a display image is predicted in advance, and the image data signal is corrected so as to compensate for the ghost, thereby greatly improving the quality of the display image. I can do it.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a data correction circuit 310A.

FIG. 3 is a diagram illustrating a configuration example of adders 402 and 408.

FIG. 4 is a timing chart showing an operation of the data correction circuit 310A.

FIG. 5 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration example of a data correction circuit 310B.

FIG. 7 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration example of a data correction circuit 310C.

FIG. 9 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration example of a data correction circuit 310D.

FIG. 11 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 12 is a diagram illustrating a configuration example of a data correction circuit 310E.

FIG. 13 is a plan view illustrating a configuration example of a projector as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 14 is a perspective view illustrating a configuration of a computer as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 15 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 16 is a diagram illustrating a configuration of a conventional liquid crystal display device.

FIG. 17 is a diagram illustrating a configuration example of a conventional phase expansion circuit 302.

FIG. 18 is a diagram showing another conventional phase expansion method.

FIG. 19 is a diagram showing a configuration of a conventional liquid crystal display panel 100.

FIG. 20 is a diagram illustrating a display content of a conventional liquid crystal display panel and a part of a ghost.

FIG. 21 is a diagram showing an electric equivalent circuit for explaining a ghost generation mechanism of the liquid crystal display panel.

[Explanation of symbols]

 100: liquid crystal display panel 200: timing circuit 300A: image signal processing circuit 301: D / A conversion circuit 302: phase expansion circuit 303: amplification / inversion circuit VID1-6 VID1-6: image signal (analog signal) Dint: ... Reference image data signal Ddly... Delayed reference image data signal Dmod... Image data signals p1 to p4... Internal signal name 401... Subtraction arithmetic circuit 402. Unit 404 delay circuit 405 addition arithmetic circuit 406 subtraction arithmetic circuit 407 cumulative addition circuit 408 multiplier multiplication 409 addition arithmetic circuit 410 addition ... Holding circuit 412... Holding circuit 413.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Katsutoshi Ueno 3-3-5 Yamato, Suwa-shi, Nagano F-term in Seiko Epson Corporation 2H093 NA31 NA41 NA42 NC21 NC22 NC26 ND41 5C006 AA01 AA02 AA22 AC02 AC21 AF46 AF64 BB16 BC03 BC06 BC13 BF07 BF11 BF25 BF27 BF28 BF34 EC02 EC05 EC09 EC13 FA26 FA31 5C080 AA10 BB05 CC03 DD12 EE32 FF09 KK02 KK04 KK07 KK20 KK43

Claims (23)

[Claims] A plurality of scanning lines and a plurality of data lines; a transistor and a pixel electrode provided corresponding to an intersection of each of the scanning lines and each of the data lines; An image signal corresponding to each data line is simultaneously supplied for each block based on each sampling signal corresponding to each block compiled for each of a plurality of blocks, and the image signal is sequentially selected and executed for each block. An image data signal processing method for generating the image signal that is used, wherein a certain block is set as a target block, and the block selected before the target block is set as a reference block, from the outside corresponding to the target block. The supplied reference image data signal includes at least the reference image data signal and the image signal supplied to the reference block. Image data processing, wherein an image data signal corresponding to the target block is obtained by adding correction voltage data obtained by performing a predetermined operation using a corresponding image data signal or a reference image data signal. Method. 2. The image data processing method according to claim 1, wherein the predetermined calculation method calculates a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A third predetermined value is added to a sum of a value obtained by multiplying a second predetermined value and a value obtained by subtracting each value of the image data signal of the corresponding reference block from each of the reference image data signals of the target block. Multiplied by the value
An image data processing method, which is a calculation method for adding a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. 3. The image data processing method according to claim 1, wherein the predetermined calculation method calculates a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A third predetermined value is added to a sum of a value obtained by multiplying a second predetermined value and a value obtained by subtracting each value of the reference image data signal of the corresponding reference block from each of the reference image data signals of the target block. A multiplied value and a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. . 4. The image data processing method according to claim 1, wherein the predetermined calculation method calculates a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A third predetermined value is added to a sum of a value obtained by multiplying a second predetermined value and a value obtained by subtracting each value of the image data signal of the corresponding reference block from each of the reference image data signals of the target block. An image data processing method, which is an arithmetic method for adding a value multiplied by a value. 5. The image data processing method according to claim 1, wherein the predetermined calculation method calculates a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A third predetermined value is added to a sum of a value obtained by multiplying a second predetermined value and a value obtained by subtracting each value of the reference image data signal of the corresponding reference block from each of the reference image data signals of the target block. An image data processing method which is a calculation method of adding a value multiplied by the value of 6. The image data processing method according to claim 1, wherein said predetermined calculation method multiplies a sum of respective values of said reference image data signal of said target block by a fifth predetermined value. A value obtained by multiplying a sum of respective values of the image data signals of the reference block by a sixth predetermined value, a seventh predetermined value, and the correction used in the image data signal of the reference block. An image data processing method, which is an arithmetic method for adding a value obtained by multiplying voltage data by a fourth predetermined value. 7. The image data processing method according to claim 1, wherein the predetermined calculation method multiplies a sum of respective values of the reference image data signal of the target block by a fifth predetermined value. And a value obtained by multiplying a sum of respective values of the image data signals of the reference block by a sixth predetermined value, a seventh predetermined value, and the value used in the reference image data signal of the reference block. An image data processing method, which is a calculation method for adding a value obtained by multiplying correction voltage data by a fourth predetermined value. 8. The image data processing method according to claim 1, wherein the predetermined calculation method multiplies a sum of respective values of the reference image data signal of the target block by a fifth predetermined value. And an arithmetic method for adding a value obtained by multiplying a sum of respective values of the image data signals of the reference block by a sixth predetermined value and a seventh predetermined value. Method. 9. The image data processing method according to claim 1, wherein the predetermined calculation method multiplies a sum of respective values of the reference image data signal of the target block by a fifth predetermined value. And a seventh predetermined value which is obtained by multiplying a sum of respective values of the reference image data signal of the reference block by a sixth predetermined value and a seventh predetermined value. Processing method. 10. The image data processing method according to claim 1, wherein said predetermined operation method is an operation method having the same operation result as any one of the operation methods according to any one of claims 2 to 9. Image data processing method. 11. A semiconductor device comprising: a plurality of scanning lines and a plurality of data lines; a transistor and a pixel electrode provided corresponding to a portion where each of the scanning lines intersects with each of the data lines; Based on each sampling signal corresponding to each block grouped into a plurality of lines, simultaneously supply an image signal corresponding to each data line for each block,
This is used in an electro-optical device that is sequentially selected and executed for each block, and is an image data signal processing circuit that generates the image signal, wherein a certain block is set as a target block, and the block selected before the target block is selected. A block is used as a reference block, and a predetermined image data signal or a reference image data signal corresponding to the image signal supplied to the reference block and an externally supplied reference image data signal corresponding to the target block is used. An image data processing circuit comprising: an arithmetic processing circuit that performs an operation, adds the operation result as correction voltage data to a reference image data signal corresponding to the target block, and outputs the result as an image data signal. 12. The image data processing circuit according to claim 11, wherein the arithmetic processing circuit calculates a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A third predetermined value to a sum of a value obtained by multiplying a predetermined value of 2 and a value obtained by subtracting each value of the image data signal of the corresponding reference block from each of the reference image data signals of the target block. And a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. . 13. The image data processing circuit according to claim 11, wherein the arithmetic processing circuit calculates a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A third predetermined sum to a sum of a value multiplied by a predetermined value of 2 and a value obtained by subtracting each value of the reference image data signal of the corresponding reference block from each of the reference image data signals of the target block. A circuit for performing an operation of adding a value multiplied by a value and a value obtained by multiplying the correction voltage data used in the image data signal of the reference block by a fourth predetermined value. circuit. 14. The image data processing circuit according to claim 11, wherein the arithmetic processing circuit calculates a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A third predetermined value to a sum of a value obtained by multiplying a predetermined value of 2 and a value obtained by subtracting each value of the image data signal of the corresponding reference block from each of the reference image data signals of the target block. An image data processing circuit, which is a circuit for performing an operation of adding a value obtained by multiplying by. 15. The image data processing circuit according to claim 11, wherein the arithmetic processing circuit calculates a sum of values obtained by subtracting a first predetermined value from each of the reference image data signals of the target block. A third predetermined sum to a sum of a value multiplied by a predetermined value of 2 and a value obtained by subtracting each value of the reference image data signal of the corresponding reference block from each of the reference image data signals of the target block. An image data processing circuit, which is a circuit for performing an operation of adding a value multiplied by a value. 16. The image data processing circuit according to claim 11, wherein the arithmetic processing circuit multiplies a sum of respective values of the reference image data signal of the target block by a fifth predetermined value. A value obtained by multiplying a sum of respective values of the image data signals of the reference block by a sixth predetermined value, a seventh predetermined value, and the correction voltage used in the image data signal of the reference block. An image data processing circuit, which is a circuit for performing an operation of adding data multiplied by a fourth predetermined value. 17. The image data processing circuit according to claim 11, wherein the arithmetic processing circuit multiplies a sum of respective values of the reference image data signal of the target block by a fifth predetermined value. A value obtained by multiplying a sum of respective values of the image data signals of the reference block by a sixth predetermined value, a seventh predetermined value, and the correction used in the reference image data signal of the reference block. An image data processing circuit, which is a circuit for performing an operation of adding a value obtained by multiplying voltage data by a fourth predetermined value. 18. The image data processing circuit according to claim 11, wherein the arithmetic processing circuit multiplies a sum of respective values of the reference image data signal of the target block by a fifth predetermined value. A circuit for performing an operation of adding a value obtained by multiplying a sum of respective values of the image data signals of the reference block by a sixth predetermined value and a seventh predetermined value. Processing circuit. 19. The image data processing circuit according to claim 11, wherein the arithmetic processing circuit multiplies a sum of respective values of the reference image data signal of the target block by a fifth predetermined value. A circuit for performing an operation of adding a value obtained by multiplying a sum of respective values of the reference image data signal of the reference block by a sixth predetermined value and a seventh predetermined value. Data processing circuit. 20. An image data processing circuit according to claim 11, wherein said arithmetic processing circuit is a circuit for performing an operation having the same result as any one of claims 12 to 19. Processing circuit. 21. An image data processing circuit according to claim 11, wherein: a D / A conversion circuit for converting an image data signal, which is a digital signal output from the image data processing circuit, into an analog signal; A parallelization circuit that expands the time axis of the image signal output from the conversion circuit according to the number of image signal lines constituting the block and parallelizes the image signal; a scanning line driving circuit that sequentially selects the scanning line; A data line driving circuit for generating each sampling signal for sequentially selecting a block in which a plurality of signal lines are grouped, and the parallelized image signal based on each sampling signal;
An image signal supply circuit for supplying each of the data lines belonging to the selected block to the data line. 22. The image data processing circuit according to claim 11, wherein an image data signal output from the image data processing circuit is time-axis-expanded and parallelized according to the number of image signal lines constituting the block. A D / A conversion circuit for converting an image data signal output from the parallelization circuit into an analog signal; a scanning line driving circuit for sequentially selecting the scanning lines; and a plurality of the image signal lines. A data line drive circuit for generating each sampling signal for sequentially selecting the blocks combined into: the parallelized image signal based on each sampling signal;
An image signal supply circuit for supplying each of the data lines belonging to the selected block to the data line. 23. An electronic apparatus comprising the electro-optical device according to claim 21.