JP3882443B2 - Electro-optical panel, driving method thereof, scanning line driving circuit and data line driving circuit, electro-optical device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical panel, a driving method thereof, a scanning line driving circuit and a data line driving circuit, an electro-optical device, and an electronic apparatus.
[0002]
[Prior art]
In general, an image display unit of a liquid crystal display device includes an element substrate, a counter substrate, and liquid crystal sealed in a gap between the substrates. In the element substrate, a plurality of scanning lines, a plurality of data lines, a plurality of transistors and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines are formed. On the other hand, a common electrode is formed on the counter substrate. A thin film transistor (hereinafter referred to as “TFT”) is used as the transistor.
[0003]
The gate of the TFT is connected to one scanning line, the source is connected to one data line, and the drain is connected to the pixel electrode.
[0004]
As a driving method of the image display unit, by selecting a scanning line at a predetermined timing, a plurality of TFTs connected to the scanning line are simultaneously turned on, and the voltages of the data lines are simultaneously applied to the pixel electrodes. The method is common. In this case, a voltage corresponding to the image data is supplied to each data line, and the transmittance of the liquid crystal is controlled according to the voltage applied between the pixel electrode and the common electrode. Thereby, gradation display according to the value of the image data becomes possible.
[0005]
By the way, the relationship between the voltage applied to the liquid crystal and the transmittance of the liquid crystal is not a linear relationship but a non-linear relationship. For this reason, it is necessary to perform a process for equalizing the amount of change in transmittance of the liquid crystal for each gradation of the image data. In the present application, this processing is called γ correction.
[0006]
FIG. 15 is a block diagram showing a data line driving circuit for driving one data line and its peripheral circuits. In this figure, the data line driving circuit includes a first latch circuit 921, a second latch circuit 922, and a DA converter 93. Further, a controller 6 and a γ correction circuit 91 are provided in the previous stage of the data line driving circuit.
[0007]
The controller 6 generates 6-bit image data DA. The γ correction circuit 91 performs γ correction on the image data DA to generate 8-bit image data DB (Dγ1, Dγ2,..., Dγ8). Here, the γ correction circuit 91 is composed of a RAM or a ROM, and stores a table for performing γ correction. The contents of this table are determined based on the input / output characteristics of the DA converter 93 and the liquid crystal transmittance characteristics with respect to the applied voltage.
[0008]
The DA converter 93 is a capacity division type DA converter using a switch and a capacitor. The DA converter 93 has eight capacitive elements 941 to 948 arranged in parallel. If the capacitance value of the capacitive element 941 is C, the capacitance values of the capacitive elements 942, 943,..., 948 are selected to be 2C, 4C,.
[0009]
Further, the data line 99 is parasitic on the data line 99. In FIG. 15, this parasitic capacitance value is indicated by Cs. The voltage Vcom at the other end of the data line capacitor 940 is a voltage applied to the common electrode arranged on the counter substrate.
[0010]
Two reference voltages Va and Vb are supplied to the DA converter 93. One terminal of each of the capacitive elements 941 to 948 is connected to the supply terminal Ta of the reference voltage Va. On the other hand, the other terminals of the capacitive elements 941 to 948 are connected to the supply terminal Ta via reset switches 951 to 958, respectively. When the switches 951 to 958 are turned on, both terminals of the capacitive elements 941 to 948 are short-circuited, and the respective charged charges are discharged. Further, a reset switch 910 is connected between the other reference voltage Vb supply terminal Tb and the data line 99. When the switch 910 is turned on, the potential of the data line 99 is reset to the voltage Vb.
[0011]
In addition, switches 961 to 968 that are turned on and off according to the values of the image data Dγ1 to Dγ8 are provided between the data line 99 and the capacitive elements 941 to 948. By selectively turning on each of the switches 961 to 968, the capacitive elements connected to the switches that are turned on are connected in parallel to each other. As a result, a voltage corresponding to the image data DB is applied to the data line 99.
[0012]
FIG. 16A is a graph showing the relationship between the decimal value of the image data DA and the output voltage Vc of the DA converter 93, and FIG. 16B shows the transmittance SLP of the liquid crystal and the data line. It is a graph which shows the relationship of the voltage VLP applied to a pixel electrode.
[0013]
With reference to FIGS. 16A and 16B, the operation principle of the drive circuit will be briefly described. First, when 6-bit image data DA is input from the controller 6 to the γ correction circuit 91, the γ correction circuit 91 converts the image data DA into 8-bit image data DB. Here, the above-described table is created as follows. First, 64 pieces of 8-bit data capable of uniformly engraving gradation are selected from 256 pieces of 8-bit data in accordance with the transmittance characteristics of the liquid crystal pixels. Then, the selected 64 pieces of 8-bit data are stored in the table as image data DB in association with 6-bit image data DA.
[0014]
As a result, when 6-bit image data DA is input to the γ correction circuit 91, the γ correction circuit 91 reads data corresponding to the value of the image data DA from the table and outputs it as an image data DB. That is, the image data DB is configured with 8 bits so that the change amount ΔSLP of the liquid crystal transmittance is equal for each gradation of the image data DA.
[0015]
[Problems to be solved by the invention]
Incidentally, since the drive circuit shown in FIG. 15 performs the γ correction as described above, the γ correction circuit 91 is required. Furthermore, liquid crystal panels tend to be larger and higher in definition, but as the panel scale increases and the number of pixels increases, the length of the data line 99 increases. For this reason, the liquid crystal panel tends to have a large parasitic capacitance value Cs with an increase in size and definition. On the other hand, the DA converter 93 applies a desired voltage to the data line 99 by moving charges between the parasitic capacitance 940 and the capacitive elements 941 to 948. Therefore, when the parasitic capacitance value Cs increases, it is necessary to increase the capacitance values of the capacitive elements 941 to 948. In general, a capacitive element occupies a large area in an integrated circuit. For this reason, it becomes an obstacle to miniaturization of the drive circuit.
[0016]
In addition, when the parasitic capacitance of the data line increases, it is conceivable to increase the voltage supplied to each of the capacitive elements 941 to 948 instead of increasing the size of the capacitive elements 941 to 948 constituting the DA converter 93. However, when a TFT is used as an element constituting the drive circuit, the power supply voltage cannot be increased so much due to the breakdown voltage or the like, and the limit is 20 V at most.
[0017]
On the other hand, it is conceivable that a data line driving circuit is configured by using an amplifier without using the DA converter 93 and has a γ correction function. However, since the amplifier consumes a large amount of power, it is not suitable for a driving circuit of a liquid crystal display device that is inherently characterized by low power consumption. In addition, when an operational amplifier made of TFT is formed on a glass substrate, the operational characteristics of the operational amplifier tend to vary.
[0018]
SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical panel that has a small circuit area and can be driven with low power consumption, and a driving method thereof. Another object of the present invention is to provide a device with little variation in output characteristics of the drive circuit and high reliability even when the data line drive circuit and the scanning line drive circuit are formed on the electro-optical panel. is there. Another object of the present invention is to provide a drive circuit for an electro-optical panel that can be driven at a low voltage. Another object of the present invention is to provide an electro-optical device and an electronic apparatus using such an electro-optical panel.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, a driving method of an electro-optical panel according to the present invention includes a pixel electrode, an internal capacitor, and a pixel electrode and a counter electrode between each of a plurality of pixels arranged in a matrix. An electro-optical panel driving method including an electro-optical capacitor formed by sandwiching an electro-optical material, the first state in which the internal capacitor and the pixel electrode are electrically connected, the internal capacitor and the pixel It is possible to set the second state in which the electrode is electrically disconnected, and after setting the first state, charging the reset voltage to the electro-optic capacitor and the internal capacitor, and setting the second state, Charging the internal capacitor with a set voltage to be in the first state, thereby transferring charge between the internal capacitor and the electro-optic capacitor, and charging the set voltage to the internal capacitor; and Engineering to move charge And wherein the repeating number of times corresponding to the value of the image data.
[0020]
According to the present invention, first, the reset voltage can be charged to the electro-optical capacitor. If a voltage corresponding to the black level or the white level is selected as the reset voltage, the electro-optical capacitance can be rapidly charged to a voltage corresponding to the black level or the white level. Next, the charging voltage of the electro-optical capacitor can be adjusted by charging the internal capacitor with the reset voltage and moving the charge between the internal capacitor and the electro-optical capacitor. Since the number of times of charge and charge transfer is performed according to the value of the image data, gradation display according to the value of the image data is possible.
[0021]
In the electro-optical panel driving method according to the present invention, an electro-optical material is narrowed between each of a plurality of pixels arranged in a matrix, a pixel electrode, an internal capacitor, and the pixel electrode and the counter electrode. And a first reset voltage corresponding to the black side level or a first level corresponding to the white side level according to the digit of the most significant bit of the image data. And selecting either one of the two reset voltages, supplying the selected voltage to the electro-optic capacitance, and depending on the digit of the most significant bit, the first set voltage or white side level corresponding to the black side level And selecting one of the second set voltages corresponding to, supplying the selected voltage to the internal capacitor, performing charge transfer between the electro-optic capacitor and the internal capacitor, and The feeding step and the charge transfer process, and repeating for the number of times the corresponding to the lower bit value except the most significant bit of the image data.
[0022]
When the electro-optic material used in the electro-optic device is, for example, liquid crystal, the transmittance characteristic curve representing the transmittance of the liquid crystal with respect to the applied voltage has a gradient of the characteristic curve that increases as the applied voltage increases. In the region where the voltage is large and the transmittance is low, the slope of the characteristic curve increases as the applied voltage decreases. The change in the slope of the transmittance characteristic curve is reversed between the high transmittance region and the low transmittance region. That is, the transmittance characteristic curve is substantially point symmetric with respect to a point where the transmittance is 50%. Therefore, the γ correction characteristic also needs to be point-symmetric before and after the center value of the image data value. For this purpose, it is necessary to determine whether the image data value is larger or smaller than the center value, and to reverse the magnitude relationship between the reset voltage and the set voltage according to the determination result. According to the present invention, the reset voltage and the set voltage are selected according to the most significant bit of the image data, and the charge movement is executed a number of times according to the lower bit value, so that the image data is subjected to γ correction. DA conversion can be performed.
[0023]
Here, if the electro-optical material is a liquid crystal and the image data indicates a dark gradation as the data value increases, the first liquid crystal is used when the liquid crystal operates in a normally white mode. It is preferable that the first difference voltage between the reset voltage and the first set voltage is set to be larger than the second difference voltage between the second reset voltage and the second set voltage.
[0024]
In addition, if the electro-optic material is liquid crystal and the image data indicates a bright gradation as the data value increases, the first reset is performed when the liquid crystal operates in a normally black mode. It is preferable that the first difference voltage between the voltage and the first set voltage is set to be smaller than the second difference voltage between the second reset voltage and the second set voltage.
[0025]
The dielectric constant of liquid crystal (particularly TN liquid crystal) has the property that it increases as the applied voltage increases. For this reason, the electro-optical capacitance value increases as the applied voltage increases. According to the two methods described above, this change in capacitance value can be compensated.
[0026]
Next, in the electro-optical panel according to the present invention, the first scanning line for supplying the clock signal, the second scanning line for supplying the inverted clock signal, the first reset voltage value or the first set voltage for the black side level. A third scanning line that supplies a black level voltage that is one of the voltage values, and a white level voltage that is one of the second reset voltage value or the second set voltage value for the white side level. A plurality of scanning line sets including a fourth scanning line, a first data line supplying a black level selection signal, and a plurality of data line sets including a second data line supplying a white level selection signal And each pixel arranged in a matrix corresponding to the intersection of the scanning line set and the data line set, the pixel sandwiching an electro-optic material between the pixel electrode and the counter electrode Electricity A first switching element provided between the pixel capacitor and the internal capacitor and controlled to be turned on / off based on the inverted clock signal; and the internal capacitor and one terminal connected to the clock signal. A second switch element that is controlled to be turned on / off based on the second switch element; one terminal connected to the other terminal of the second switch element; the other terminal connected to the third scanning line; and the black level selection A third switch element that is controlled to be turned on / off based on a signal; one terminal connected to the other terminal of the second switch element; the other terminal connected to the fourth scanning line; And a fourth switch element that is controlled to be turned on / off based on a level selection signal.
[0027]
According to the present invention, first, either the black level voltage or the white level voltage is selected by the third and fourth switch elements. Second, the selected voltage is applied to the internal capacitor and the electro-optic capacitor by the second switch element and the first switch element. For this reason, the charge transfer between the internal capacitor and the electro-optic capacitor can be controlled by the clock signal and the inverted clock signal that control the on / off of the third and fourth switch elements. In addition, the voltage supplied to the internal capacitor can be limited by the black level selection signal and the white level selection signal that control ON / OFF of the first and second switch elements. Therefore, gradation can be displayed if the pulse widths of the black level selection signal and the white level selection signal are set in accordance with the data value of the image data.
[0028]
Next, the scanning line driving circuit of the present invention is used in the above-described electro-optical panel, and drives a plurality of scanning line sets. The scanning line sets are sequentially shifted by transferring transfer pulses in a vertical scanning period. A shift register that sequentially outputs a plurality of scanning line group selection signals to be selected, and provided for each of the scanning line groups, and based on each of the scanning line group selection signals, the clock signal, And a plurality of selection circuits for supplying the inverted clock signal, the black level voltage, and the white level voltage.
[0029]
Since each scanning line is accompanied by parasitic capacitance, the load in the high frequency region is particularly heavy. The power consumption and circuit scale of the drive circuit that drives these signals are determined according to the load. According to the present invention, the clock signal, the inverted clock signal, the black level voltage, and the white level voltage are selectively supplied to the scanning line groups, so that each signal is supplied to all the scanning line groups. The current consumption of the drive circuit can be greatly reduced, and the circuit scale can be further reduced.
[0030]
Next, the data line driving circuit of the present invention is used in the above-described electro-optical panel and drives a plurality of data line sets. The transfer pulse of the horizontal scanning cycle is sequentially shifted to sequentially select each selection signal. A shift register for outputting, a first latch for latching image data based on each selection signal and outputting a plurality of dot sequential image data, and a plurality of latches for latching each dot sequential image data at a horizontal scanning period. A second latch unit for outputting line sequential image data; and a control unit having a plurality of control units provided respectively corresponding to the data line sets, wherein one control unit includes the line sequential image data A pulse width modulation signal generator for generating a pulse width modulated signal that is pulse width modulated according to the data value of the lower bits excluding the most significant bit, and the most significant bit of the line sequential image data A selection unit that selects whether to supply the pulse width modulation signal as the black level selection signal to the first data line or as the white level selection signal to the second data line according to a digit; It is characterized by that.
[0031]
According to the present invention, a black level selection signal or a white level selection signal corresponding to the lower bit value of image data can be supplied to each data line. Therefore, gradation display according to the data value of the image data can be displayed on the electro-optical panel described above.
[0032]
Here, the pulse width modulation signal generation unit resets the count value in a horizontal scanning cycle, and count data obtained by counting the master clock signal and lower-order bit data excluding the most significant bit from the line-sequential image data It is desirable to provide a comparison circuit that generates the pulse width modulation signal based on the comparison result.
[0033]
Next, the electro-optical device according to the present invention includes the above-described electro-optical panel, the above-described scanning line driving circuit, the above-described data line driving circuit, the clock signal, the inverted clock signal, the black level voltage, And a timing signal generation circuit that generates the white level voltage and supplies the white level voltage to the scanning line driving circuit.
[0034]
Here, the timing generation circuit sets the value of the black level voltage as the first reset voltage value in a predetermined reset period at the beginning of the horizontal scanning period, and sets the value of the black level voltage in the other period as the first reset voltage value. A black level voltage generating unit that generates the black level voltage so as to have one set voltage value, and the white level voltage value as the second reset voltage value in the reset period, while the white level voltage in the other period. And a white level voltage generation unit that generates the white level voltage so that the value of the second value is a second set voltage value.
[0035]
According to the present invention, the voltage that becomes the first reset voltage value or the second reset voltage value is supplied to the pixel in the reset period, so that the electro-optic capacitance can be charged to the reset voltage at the beginning of the vertical scanning period. . In other periods, a voltage having the first set voltage value or the second set voltage value is supplied to the pixel, so that the set voltage can be charged in the internal capacitor. In addition, since the first and second switch elements operate based on the clock signal and the inverted clock signal, the charge is transferred between the internal capacitor and the electro-optic capacitor. This makes it possible to display an image according to the data value of the image data while performing γ correction.
[0036]
Here, if the electro-optical material is a liquid crystal and the image data indicates a dark gradation as the data value increases, the first liquid crystal is used when the liquid crystal operates in a normally white mode. It is preferable that the first difference voltage between the reset voltage and the first set voltage is set to be larger than the second difference voltage between the second reset voltage and the second set voltage.
[0037]
In addition, if the electro-optic material is liquid crystal and the image data indicates a bright gradation as the data value increases, the first reset is performed when the liquid crystal operates in a normally black mode. It is preferable that the first difference voltage between the voltage and the first set voltage is set to be smaller than the second difference voltage between the second reset voltage and the second set voltage.
[0038]
Since the dielectric constant of liquid crystal (particularly TN liquid crystal) has a property of increasing as the applied voltage increases, the electro-optic capacitance value increases as the applied voltage increases. According to the two methods described above, it is possible to compensate for the change in the capacitance value and perform good γ correction.
[0039]
In the electro-optical device according to the aspect of the invention, it is preferable that the scanning line driving circuit and the data line driving circuit are built in an electro-optical panel, and an active element constituting the electro-optical panel is a thin film transistor. In this case, each pixel, the scanning line driving circuit, and the data line driving circuit can be formed by the same process. In general, the operational characteristics of thin film transistors vary. However, each pixel can apply a desired voltage to the electro-optic capacitor by moving the charge between the internal capacitor and the electro-optic capacitor. Even if configured, DA conversion can be performed accurately.
[0040]
Next, an electronic apparatus according to an aspect of the invention includes the above-described electro-optical device, and displays an image on the electro-optical panel. Thereby, it is possible to provide a low-power consumption and compact electronic device with a display device. Examples of the electronic device include an engineering workstation, a pager, a mobile phone, a television, a viewfinder type or a monitor direct-view type video camera, a car navigation device, and the like.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0042]
<1. Configuration of liquid crystal display device>
<1-1. Overall configuration of liquid crystal display device>
First, a liquid crystal display device using liquid crystal as an electro-optical material will be described as an example of the electro-optical device according to the present invention. The main part of the liquid crystal display device is composed of a liquid crystal panel AA in which an element substrate and a counter substrate are attached to each other with their electrode formation surfaces facing each other and with a certain gap therebetween, and liquid crystal is sandwiched between the gaps. ing. Here, TFTs are formed on the element substrate as switching elements. In this example, a glass substrate is used as the element substrate, but it is needless to say that a semiconductor substrate or a plastic substrate may be used.
[0043]
FIG. 1 is a block diagram showing the overall configuration of the liquid crystal display device according to the present embodiment. This liquid crystal display device includes a liquid crystal panel AA and an external processing circuit. An image display area A, a scanning line driving circuit 100, and a data line driving circuit 200 are formed on the element substrate of the liquid crystal panel AA. Among these, the data line driving circuit 200 generates a black level selection signal CMPBK and a white level selection signal CMPBK whose pulse width is modulated according to the data value of the image data D. Note that active elements constituting each circuit on the element substrate are constituted by TFTs.
[0044]
In addition, the liquid crystal display device includes a timing generation circuit 300, a power supply circuit 400, and an image data conversion circuit 500 as external processing circuits.
[0045]
The input image data Din supplied to the liquid crystal display device is in a parallel format, for example, and the number of bits is arbitrary. Of course, the serial format may be used, but in this example, the input image data Din will be described as a 4-bit or 6-bit parallel format. In order to simplify the following description, the input image data Din is described as corresponding to one color. However, the present invention is not limited to this, and the input image data Din may correspond to three primary colors of RGB. Of course it is good.
[0046]
First, the image data conversion circuit 500 controls whether or not to invert other lower bits excluding the most significant bit based on the most significant bit digit of the input image data Din. Specifically, when the most significant bit digit is “1”, the other lower bits are inverted and output as image data D, while when the most significant bit digit is “0”, the input image data Din is directly used as an image. Output as data D. The image data conversion circuit 500 provides an exclusive ethical sum circuit corresponding to the other lower bits excluding the most significant bit, and the exclusive logic of each bit corresponding to the most significant bit in each exclusive OR circuit. What is necessary is just to calculate the sum. Therefore, if the number of bits of the input image data Din is 4 bits, the image data conversion circuit 500 can be configured with three exclusive OR circuits. The image data conversion circuit 500 converts the input image data Din, as will be described later, in the pixel DAC 7 by switching the reset voltage Vr and the set voltage Va in accordance with the most significant bit digit and performing DA correction while performing γ correction. This is for conversion.
[0047]
Next, the timing generation circuit 300 generates a Y clock YCK, an X clock XCK, a Y transfer start signal DY, an X transfer start signal DX, a latch pulse TRS, etc. in synchronization with the input image data D. The timing generation circuit 300 supplies these signals to the scanning line driving circuit 100 and the data line driving circuit 200, respectively.
[0048]
The power supply circuit 400 is composed of a constant voltage circuit, and generates a black level voltage VBK and a white level voltage VWT in addition to generating a power supply voltage of each circuit formed on the element substrate of the liquid crystal panel AA. As will be described later, the black level voltage VBK is one of the two values of the black side reset voltage value Vr1 and the black side set voltage value Va1. The white level voltage VWT is one of the two values of the white side reset voltage value Vr2 and the white side set voltage value Va2.
[0049]
<1-2. Image display area>
In the image display area A, as shown in FIG. 1, a set of four scanning lines 3a1 to 3a4 is formed and arranged in parallel along the X direction. In addition, there are two data lines 6a1 and 6a2 formed as a set, which are arranged in parallel along the Y direction. Here, the scanning line 3a1 supplies the clock signal CLK, the scanning line 3a2 supplies the inverted clock signal CLKB obtained by inverting the clock signal CLK, the scanning line 3a3 supplies the black level voltage VBK, and the scanning line 3a4 supplies the white level voltage VWT. . The data line 6a1 supplies a black level selection signal CMPBK, and the data line 6a2 supplies a white level selection signal CMPBK. Although these signals will be described later, both are used for DA conversion.
[0050]
Next, in the vicinity of the intersection between the scanning lines 3a1 to 3a4 and the data lines 6a1 and 6a2, a pixel DAC 7 and a pixel electrode 9a connected thereto are provided.
[0051]
Each pixel includes a pixel DAC 7 and a pixel electrode 9a, a counter electrode formed on the counter substrate, and a liquid crystal sandwiched between the two electrodes. As a result, the pixels are arranged in a matrix corresponding to the intersections of the scanning lines 3a1 to 3a4 and the data lines 6a1 and 6a2.
[0052]
Here, since the orientation and order of the liquid crystal molecules change according to the voltage level applied to the pixel electrode 9a, gradation display by light modulation becomes possible. For example, the amount of light passing through the liquid crystal is limited as the applied voltage increases in the normally white mode, while it is reduced as the applied voltage increases in the normally black mode. Therefore, in the entire liquid crystal display device, light having a contrast corresponding to the image signal is emitted for each pixel, and predetermined display is possible. Note that the image display area A in this example is configured to operate in a normally white mode.
[0053]
<1-3. Pixel DAC>
The pixel DAC 7 converts these signals from a digital signal to an analog signal while performing γ correction on the black level selection signal CMPBK and the white level selection signal CMPBK whose pulse widths are modulated according to the data value of the image data D. It has a function.
[0054]
FIG. 2 is a circuit diagram showing the pixel DAC and its peripheral configuration. As shown in this figure, the pixel DAC 7 includes switch elements 71 to 74 and a DAC capacitor CD. Each of the switch elements 71 to 74 is constituted by a TFT, and is turned on when a signal supplied to each control input terminal is at a high level (active), and turned off when the signal is at a low level. One terminal of the DAC capacitor CD is connected to a connection point between the switch element 73 and the switch element 74, and the other terminal is connected to a fixed potential. In addition, the pixel electrode 9 a is connected to the output terminal of the switch element 74. In this example, a capacitance generated when the pixel electrode 9a and the counter electrode face each other with a liquid crystal interposed therebetween is referred to as a liquid crystal capacitor CX, and the capacitance value is represented by Cx. Note that a storage capacitor may be provided in parallel with the liquid crystal capacitor CX between the liquid crystal capacitor CX and the switch element 74 in order to prevent the held image signal from leaking. In this case, the retention characteristic is improved by the storage capacitor, so that a high contrast ratio in the liquid crystal display device can be realized.
[0055]
FIG. 3 is a conceptual diagram for explaining the principle of DA conversion. In the DA conversion in the pixel DAC 7, first, the switch element 74 is turned on to charge the DAC capacitor CD and the liquid crystal capacitor CX with the reset voltage Vr (first step). This reset voltage Vr is used to initialize the voltage of the liquid crystal capacitor CX.
[0056]
Next, the switch element 74 is changed from the on state to the off state, and the DAC capacitor CD is charged with the set voltage Va (second step).
[0057]
Here, the voltage value of the black level voltage VBK supplied via the scanning line 3a3 is similarly switched from the black side reset voltage value Vr1 to the black side set voltage value Va1 at a predetermined timing. Similarly, the voltage value of the white level voltage VWT supplied via the scanning line 3a4 is switched from the white side reset voltage value Vr2 to the white side set voltage value Va2 at a predetermined timing. In addition, in the first step and the second step, one of the white level voltage VWT and the black level voltage VBK is selected by the switch elements 71 and 72, and the selected voltage is applied via the switch element 73. It has become. Therefore, the value of the reset voltage Vr in the first process described above is Vr1 or Vr2, and the value of the set voltage Va in the second process is Va1 or Va2. The reason for switching the reset voltage Vr and the set voltage Va is to execute γ correction while performing DA conversion. This point will be described later.
[0058]
Next, the switch element 73 is turned off, while the switch element 74 is turned on (third step). Then, charges move between the DAC capacitor CD and the liquid crystal capacitor CX. In the example shown in the figure, charge flows from the DAC capacitor CD to the liquid crystal capacitor CX, and finally the voltage value of the DAC capacitor CD becomes equal to the voltage value of the liquid crystal capacitor CX. Next, the switch element 74 is turned off, while the switch element 73 is turned on, and the DAC capacitor CD is charged again with the set voltage Va (fourth step). Thereafter, the voltage value of the liquid crystal capacitor CX can be set to a desired value by repeating the third step and the fourth step.
[0059]
Here, assuming that the charge voltage of the liquid crystal capacitor CX when the switch element 74 is turned on N times is Vc (N), Vc (N) is as follows.
[0060]
When N = 0, that is, when charging the liquid crystal capacitor CX is completed only in the first step, Vc (N) = Vr.
[0061]
When N is 1 or more, Vc (N) is given by the following equation.
[0062]
N = 1: Vc (1) = {Cd / (Cd + Cx)} (Va−Vr) + Vr
N = 2: Vc (2) = {Cd / (Cd + Cx)} (Va-Vc (1)) + Vc (1)
...
N = n: Vc (n) = {Cd / (Cd + Cx)} (Va−Vc (n−1)) + Vc (n−1)
Here, if the capacitance ratio of the DAC capacitance value Cd to the liquid crystal capacitance value Cx is α (= Cd / Cx), Vc (N) is given by the following equation (1).
[0063]
Vc (n) = {1 / (1 + 1 / α)} (Va−Vc (n−1)) + Vc (n−1) (1)
From equation (1), Vc (N) is determined by Va, Vr, and α. In particular, when α increases, the rate of change of the charging voltage Vc (N) increases.
[0064]
FIG. 4 shows a graph in which the vertical axis represents Vc (N) and the horizontal axis represents the number N of charge / discharge cycles. As can be seen from this figure, the charging voltage Vc (N) of the liquid crystal capacitor CX starts from the reset voltage Vr and increases monotonously as the charging / discharging number N increases, and then gradually approaches the set voltage Va. In the example shown in FIG. 4, Va> Vr. Conversely, when Vr> Va, the relationship between the charging voltage Vc (N) and the number N of charge / discharge is as shown in FIG. In this case, the charging voltage Vc (N) starts from the reset voltage Vr and decreases monotonously as the charging / discharging number N increases, and then gradually approaches the set voltage Va. Further, as α increases from the equation (1), the charging voltage Vc (N) gradually approaches the set voltage Va with a small number of charge / discharge cycles. Therefore, the curve shapes shown in FIGS. 4 and 5 can be changed by adjusting Va, Vr, and α.
[0065]
FIG. 6B is a graph showing the transmissivity of the liquid crystal on the horizontal axis and the applied voltage VLP of the liquid crystal on the vertical axis, where the number of bits of the input image data Din is 6 bits. As shown in this figure, the transmittance characteristic curve Y has an S-shape. On the other hand, FIG. 6A shows the relationship between the input image data Din necessary for obtaining the transmittance characteristic curve Y and the applied voltage VLP of the liquid crystal. That is, in order to display the gradation corresponding to the image data value using the liquid crystal having the transmittance characteristic shown in FIG. 6B, the image data value is supported according to the output characteristic curve shown in FIG. It is necessary to apply a voltage to the liquid crystal. If this is possible, ideal γ correction can be performed.
[0066]
In order to obtain the output characteristic curve shown in FIG. 6A, the curve shown in FIG. 4 may be connected to the curve shown in FIG. In order to connect the curve shown in FIG. 5 and the curve shown in FIG. 6, the following conditions are required. First, it is necessary to switch Vr and Va between the range A1 and the range A2 shown in FIG. A set of the set voltage Va and the reset voltage Vr corresponding to the range A1 is Va2 and Vr2, and a set of the set voltage Va and the reset voltage Vr corresponding to the range A2 is Va1 and Vr1. Second, in the range A1, the image data value is matched with the charge / discharge count N, while in the range A2, the image data value is converted as shown in FIG. There is a need. Whether the value of the inputted input image data Din is in the range A1 or the range A2 can be distinguished by the digit of the most significant bit MSB of the input image data Din.
[0067]
The image data conversion circuit 500 described above generates the image data D by inverting the lower bit when the most significant bit MSB digit is “1”, while the input image when the most significant bit MSB is “0”. Data Din is output as image data D. Therefore, the value of the lower-order bit data excluding the most significant bit in the image data D matches the number N of times of charging / discharging. In the present embodiment, the data line driving circuit 200 described later generates a pulse-width-modulated signal according to the lower bit data value, and the switch elements 73 and 74 are turned on / off using this signal. So that a desired number of times of charging / discharging N can be obtained.
[0068]
By the way, the liquid crystal has a property that the dielectric constant increases as the applied voltage VLP increases. That is, as the applied voltage VLP of the liquid crystal increases, the liquid crystal capacitance value Cx increases. On the other hand, the DAC capacitance value Cd is constant. Therefore, the higher the applied voltage VLP of the liquid crystal, the smaller the capacitance ratio α (= Cd / Cx). This means that in the range A1 and the range A2 shown in FIG. 6A, the capacity ratio α is smaller in the range A2. As described above, when the capacity ratio α decreases, the rate of change of the charging voltage Vc (N) decreases, so the rate of change of the charging voltage Vc (N) decreases in the range A2.
[0069]
In the present embodiment, Va1, Vr1 and Va2, Vr2 are determined so as to compensate for the change in the capacitance ratio α. This point will be specifically described with reference to FIG. FIG. 7 is a graph showing the relationship between Va1, Vr1 and Va2, Vr2. In the figure, the vertical axis represents the voltage of the pixel electrode, and the horizontal axis represents the data value (gradation) of the image data D.
[0070]
As shown in this figure, when the difference voltage value between the black side set voltage value Va1 and the black side reset voltage value Vr1 is V1, and the difference voltage value between the white side reset voltage value Vr2 and the white side set voltage value Va2 is V2. , A set of Va1, Vr1 and a set of Vr2, Va2 are set so that V1> V2. Thereby, even if the change rate of the charging voltage Vc (N) is smaller in the range A2 on the black level side, a change range of transmittance equivalent to the range A1 can be obtained.
[0071]
<1-4. Scan Line Drive Circuit>
Next, the configuration of the scanning line driving circuit 100 will be described. FIG. 8 is a circuit diagram showing a detailed configuration of the scanning line driving circuit 100. As shown in this figure, the scanning line driving circuit 100 supplies a Y shift register 110, a clock signal supply line CLKL that supplies a clock signal CLK, an inverted clock signal supply line CLKBL that supplies an inverted clock signal CLKB, and a black level voltage VBK. The black level voltage supply line VBKL that supplies the white level voltage VWT, the white level voltage supply line VWTL that supplies the white level voltage VWT, and the selection circuits SWG1 to SWGm.
[0072]
First, the Y shift register 110 sequentially shifts the Y transfer start signal DY indicating the start of the vertical scanning period in the Y direction by using the Y clock YCK that is inverted every horizontal scanning period, so that the scanning signals Y1, Y2,. Output as Ym. For this reason, the scanning signals Y1, Y2,..., Ym are configured such that the active signals are sequentially switched every horizontal scanning period.
[0073]
Next, each of the selection circuits SWG1 to SWGm includes four switches SW1 to SW4. The input / output terminal of the switch SW1 is connected to the clock signal supply line CLKL and the scanning line 3a1, the input / output terminal of the switch SW2 is connected to the inverted clock signal supply line CLKBL and the scanning line 3a2, and the input / output terminal of the switch SW3 is The black level voltage supply line VBKL is connected to the scanning line 3a3, and the input / output terminal of the switch SW4 is connected to the white level voltage supply line VWTL and the scanning line 3a4. In addition, the switches SW1 to SW4 are turned on when the scanning signals Y1, Y2,..., Ym supplied to the selection circuits SWG1 to SWGm are active, and are turned off when they are inactive. It is configured. Accordingly, the clock signal CLK, the inverted clock signal CLKB, the black level voltage VBK, and the white level voltage VWT are supplied to each pixel in one row in a certain horizontal scanning period, and are supplied to each pixel in the next row in the next horizontal scanning period. Supplied.
[0074]
Here, these signals are always supplied to all the pixels, and each pixel is provided with a switch element that is controlled to be turned on / off by the scanning signals Y1, Y2,..., Ym. Is possible. However, in this embodiment, these signals are not always supplied to all the pixels, but are supplied to the pixels for each row selected for each horizontal scanning period. The reason for this is as follows.
[0075]
First, the scanning lines 3a1 to 3a4 are formed on the element substrate along the X direction. Each of the scanning lines 3a1 to 3a4 is accompanied by parasitic capacitance due to the intersection with the data lines 6a1 and 6a2 and facing the counter electrode through the liquid crystal. If the clock signal CLK or the like is supplied to all the pixels using m scanning lines 3a1 to 3a4, a large parasitic capacitance acts as a load. Will become bigger. On the other hand, the voltage applied to the liquid crystal in each pixel may be updated for each row. In other words, it is not always necessary to supply the clock signal CLK or the like to all the pixels, and it is sufficient to supply them for each row. Therefore, in the present embodiment, the clock signal CLK and the like are sequentially supplied to the pixels in each row using the selection circuits SW1 to SWm. As a result, the power consumption of the supply circuit can be reduced to about 1 / m compared to the case where the clock signal CLK or the like is supplied to all the pixels.
[0076]
<1-5. Data line drive circuit>
Next, the data line driving circuit 200 will be described. FIG. 9 is a block diagram showing a configuration of the data line driving circuit 200. As shown in the figure, the data line driving circuit 200 includes an X shift register 210, image data supply lines Ld0 to Ld3 to which image data D0 to D3 are supplied, switches SW10 to SWn3, a first latch unit 220, and a second latch unit 230. , And a PWM signal generator 240.
[0077]
Data D0 to D3 indicating the bit values of the image data D are supplied to the image data supply lines Ld0 to Ld3.
[0078]
The X shift register 210 is configured by connecting latch circuits in multiple stages. The X shift register 210 sequentially generates the sampling pulses SR1, SR2,..., SRn by sequentially shifting the X transfer start signal DX according to the X clock XCK.
[0079]
Next, the switches SW10 to SWn3 are constituted by TFTs. The switches SW10 to SWn3 have a set of four switches SW10 to SW13, SW20 to SW23,..., SWn0 to SWn3. A set of switches is called a switch group. The number of switch groups corresponds to the number of pixel columns in the image display area A, and there are “n”. Each switch constituting each switch group is connected to the image data supply lines Ld0 to Ld3. In addition, n sampling pulses SR1, SR2,..., SRn are supplied to each switch group. Therefore, the image data D0 to D3 are taken into the first latch unit 220 in synchronization with the sampling pulses SR1, SR2,.
[0080]
Next, the first latch unit 220 includes n latch units UA1 to UAn. Each latch unit UA1 to UAn latches image data D0 to D3 supplied from each switch group. Thereby, image data D scanned in a dot sequential manner is obtained. The second latch unit 230 includes n latch units UB1 to UBn. Each of the latch units UB1 to UBn is configured to latch the output data of the first latch unit 220 in synchronization with the latch pulse TRS. The latch pulse TRS is a signal that becomes active every horizontal scanning period. Therefore, the second latch unit 230 converts the data of the first latch unit 220 output in the dot sequential manner into the line sequential data. In other words, the image data D0 to D3 are converted into line-sequential data by using the switches SW10 to SWn3, the first latch unit 220, and the second latch unit 230.
[0081]
Next, the PWM signal generation unit 240 includes a counter 241 and n PWM signal generation units UC1 to UCn corresponding to 2n data lines 6a. FIG. 10 is a block diagram showing the configuration of the PWM signal generator and its peripheral circuits. The clock signal generation unit 310 is built in the timing generation circuit 300, and the white / black level voltage generation unit 410 is built in the power supply circuit 400. These will be described together with the PWM signal generation unit 240. To do.
[0082]
First, the counter 241 is a 3-bit counter, and counts the master clock signal CLKM to generate count data CNT0 to CNT2. The count data CNT0 to CNT2 are each bit data from the first bit to the third bit indicating the count result. Further, the counter 241 is configured to reset the count value when the reset signal RST becomes active. The reset signal RST is a signal that makes the vertical scanning period one cycle, and is supplied from the timing generation circuit 300.
[0083]
Next, each PWM signal generation unit UC1 to UCn includes a comparator CMP, an inverter 242, and AND circuits 243 and 244, all having the same configuration. Here, the PWM signal generation unit UC1 will be described.
[0084]
First, the comparator CMP of the PWM signal generation unit UC1 compares the count data CNT0 to CNT2 and the lower 3 bits of the data D0 to D2 of the output data of the latch unit UB1, and the former value exceeds the latter value. The comparison result signal CMPout which becomes active (low level) is generated.
[0085]
Next, the AND circuit 243 of the PWM signal generation unit UC1 calculates a logical product of the comparison result signal CMPout and the data D3 of the most significant bit MSB out of the output data of the latch unit UB1, and uses the calculated result as the black level selection signal. Output as CMPBK. For this reason, the black level selection signal CMPBK becomes high level (active) when the data D3 of the most significant bit MSB is “1” and the values of the count data CNT0 to CNT2 are less than or equal to the values of the data D0 to D2. .
[0086]
On the other hand, the AND circuit 244 calculates the logical product of the comparison result signal CMPout and the inverted data D3 via the inverter 242, and outputs the calculation result as the white level selection signal CMPWT. Therefore, the white level selection signal CMPWT becomes a high level (active) when the data D3 of the most significant bit MSB is “0” and the values of the count data CNT0 to CNT2 are equal to or less than the values of the data D0 to D2. . Therefore, the pulse widths of the white level selection signal CMPWT and the black level selection signal CMPBK are determined according to the lower 3 bits of the image data D.
[0087]
Next, the clock signal generation unit 310 includes an inverter 311 and NAND circuits 312 and 313. The NAND circuit 312 outputs the inverted clock signal CLKB that is obtained by inverting the logical product of the reset signal RST and the master clock signal CLKM. On the other hand, the NAND circuit 313 calculates a logical product of the inverted version of the master clock signal CLKM obtained through the inverter 311 and the reset signal RST, and further inverts this to output it as the clock signal CLK.
[0088]
Next, the white / black level voltage generator 410 includes a constant voltage circuit 411 and switches SWa and SWb. The constant voltage circuit 411 generates voltages whose voltage values are a black side reset voltage value Vr1, a black side set voltage value Va1, a white side reset voltage value Vr2, and a white side set voltage value Va2. Both switches SWa and SWb are controlled by a reset signal RST. Here, the switch SWa is configured to select Vr1 when the reset signal RST is active while selecting Va1 when the reset signal RST is inactive. The switch SWb is configured to select Vr2 when the reset signal RST is active, and select Va2 when the reset signal RST is inactive.
[0089]
<2. Operation of liquid crystal display device>
Next, the operation of the liquid crystal display device will be described. FIG. 11 is a timing chart showing the operation of the liquid crystal display device.
[0090]
First, the operation of the data line driving circuit 200 will be described. When the image data D is supplied to the data line driving circuit 200, the input image data D is converted into point-sequential data by the first latch unit 220, and the point-sequential data is converted into point-sequential data by the second latch unit 230. Is converted to In the example shown in the figure, the data value is (0101) in the first field from the latch unit UC1 of the second latch unit 230. ₂ Image data D is output, and the data value is (1010) in the second field. ₂ The image data D is output.
[0091]
Thereafter, the PWM signal generation unit 240 generates a pulse level-modulated black level selection signal CMPBK and a white level selection signal CMPBK based on the pre-sequential image data D supplied from the second latch unit 230. First, when the reset signal RST becomes a low level during the period from time t1 to time t2, the counter 241 (see FIG. 10) of the PWM signal generation unit 240 is reset. Therefore, the count data CNT0 to CNT2 are all “0” during the same period. Similarly, during the period from the time t4 to the time t5 in the second field, the reset signal RST is at a low level, and the count data CNT0 to CNT2 are all “0”. Hereinafter, these periods are referred to as a reset period Trst.
[0092]
Thereafter, when the master clock signal CLKM is supplied to the counter 241, the counter 241 counts rising edges of the master clock signal CLKM and outputs counter data CNT0 to CNT2. The count data CNT0 to CNT2 are converted into lower bits (data value (101)) of the image data D of the first field by the comparator CMP of the PWM signal generation unit UC1. ₂ ). As described above, the comparator CMP sets the logic level of the comparison result signal CMPout to a low level when the value of the count data CNT0 to CNT2 exceeds the lower 3 bits of the image data D. Therefore, the comparison result signal CMPout is at a high level during the period from the start of the field until the value of the count data CNT0 to CNT2 matches the lower 3 bit value of the image data D.
[0093]
In this example, since the lower 3 bits of the image data D in the first field are “5” in decimal, the values of the count data CNT0 to CNT2 are changed from “0” (time t1) to “5” (time). It becomes a high level during the period up to t3). On the other hand, in the second field, since the lower 3 bits of the image data D are “3” in decimal, the value of the count data CNT0 to CNT2 is “3” from time t1 when the value is “0” in decimal. It becomes high level in the period up to time t3.
[0094]
In this example, the bit data D3 of the most significant bit of the image data D in the first field is “1”, and “0” in the second field. Therefore, the black level selection signal CMPBK is active (high level) in the first field, while the white level selection signal CMPBK is active in the second field.
[0095]
Next, the operation of the pixel DAC 7 in the first row and the first column among the pixel DACs 7 provided in the pixel display area A will be described. The voltage value of the black level voltage VBK (shown by a solid line) supplied to the pixel DAC 7 via the scanning line 3a3 becomes the black side reset voltage value Vr1 in the reset period Trst of each field as shown in FIG. In the period, the black side set voltage value Va1 is obtained. On the other hand, the voltage value of the white level voltage VWT (shown by a dotted line) supplied to the pixel DAC 7 via the scanning line 3a4 becomes the white side reset voltage value Vr2 in the reset period Trst, and in the other periods, the white side voltage VWT2 The set voltage value Va2. In the drawing, Vr1 and Va2 are close to each other for convenience of drawing, and Vr2 and Va1 are close to each other, but they are actually separated from each other.
[0096]
In this example, in the reset period Trst of the first field, the black level selection signal CMPBK becomes high level, while the white level selection signal CMPWT becomes low level, so that the switch element 71 of the pixel DAC 7 is turned off. The switch element 72 is turned on. In addition, since the clock signal CLK and the inverted clock signal CLKB are at a high level during this period, the switch element 73 and the switch element 74 are simultaneously turned on. As a result, the black-side reset voltage Vr1 is charged in the DAC capacitor CD and the liquid crystal capacitor CX.
[0097]
Thereafter, the switch elements 73 and 74 are complementarily turned on and off based on the clock signal CLK and the inverted clock signal CLKB. At this time, since the voltage value of the black level voltage VBK is the black side set voltage value Va1, the voltage Vc applied to the pixel electrode 9a gradually decreases toward the black side set voltage value Va1. At time t3, the black level selection signal CMPBK changes from the high level to the low level, and the switch element 72 is turned off. Accordingly, during the period from time t3 to time t4, even if the switch element 73 is turned on, the black-side set voltage Va1 is not supplied to the DAC capacitor CD. For this reason, the voltage Vc applied to the pixel electrode 9a does not change during the period from time t3 to time t4. Here, when comparing the period from time t1 to time t3 and the period from time t3 to time t4, the latter period is much longer than the former period. Therefore, the average value of the voltage Vc applied to the pixel electrode 9a in the first field substantially matches the value of the voltage Vc in the latter period. As a result, the voltage applied to the liquid crystal corresponds to the gradation value of the image data D.
[0098]
In the second field, in the reset period Trst, the black level selection signal CMPBK becomes low level, while the white level selection signal CMPWT becomes high level. Therefore, the DAC capacitor CD and the liquid crystal capacitor CX have white The side reset voltage Vr2 is charged. Thereafter, the switch elements 73 and 74 are repeatedly turned on and off in the same manner as in the first field. At this time, since the voltage value of the white level voltage VWT is the white side set voltage value Va2, the voltage Vc applied to the pixel electrode 9a gradually increases toward the white side set voltage value Va2. At time t5, the white level selection signal CMPWT transits from the high level to the low level, and the switch element 72 is turned off. Since the voltage Vc applied to the pixel electrode 9a does not change during the period from time t5 to time t6, the average value of the voltage Vc applied to the pixel electrode 9a in the second field is almost equal to the value of the voltage Vc at time t5. Match. Thereby, a voltage corresponding to the gradation value of the image data D can be applied to the liquid crystal.
[0099]
As described above, in the present embodiment, the DA conversion is performed by providing the DAC capacitor CD for each pixel and transferring the charge between the DAC capacitor CD and the liquid crystal capacitor CX. The value of the DAC capacity CD can be greatly reduced as compared with a capacity distribution type DA conversion circuit that performs DA conversion using individual internal capacitors.
[0100]
By the way, one DAC capacitor CD is provided for each row of pixels, and the charge is transferred to and from the parasitic capacitance of the data line, thereby charging the parasitic capacitance with the voltage to be applied to the liquid crystal capacitance. It is also conceivable that this voltage is taken into the liquid crystal capacitor at a predetermined timing. However, the parasitic capacitance value of the data line is much larger than the liquid crystal capacitance value Cx. For this reason, in order to obtain a desired γ characteristic, the value of the DAC capacitance CD must be increased.
[0101]
However, in this embodiment, since the DAC capacitor CD is provided for each pixel, it is only necessary to perform charge transfer with the liquid crystal capacitor CX having a small capacitance value. For this reason, the DAC capacitance value Cx can be reduced. As a result, the area of the liquid crystal panel AA can be reduced, and downsizing and cost reduction can be achieved.
[0102]
Further, by performing a charge / discharge operation between the DAC capacitor CD and the liquid crystal capacitor CX, the applied voltage of the liquid crystal capacitor CX can be increased or decreased exponentially. The reset voltage Vr is selected according to the data D3 of the most significant bit MSB of the image data, and the charge / discharge number N is determined according to other bit values. Therefore, DA conversion can be performed while performing γ correction according to the transmittance characteristics of the liquid crystal. Therefore, it is not necessary to separately provide a γ correction circuit before the data line driving circuit, so that the circuit configuration of the entire liquid crystal display device can be greatly reduced. As a result, the area occupied by the data line driving circuit can be greatly reduced as compared with a data line driving circuit using a conventional capacitance distribution type DA conversion circuit or a DA conversion circuit using an operational amplifier.
[0103]
<3. Modification of Embodiment>
<3-1: Change of reset voltages Vr1 and Vr2>
If the black side reset voltage value Vr1 and the white side reset voltage value Vr2 in the above-described embodiment are shifted to the positive side by the same value, the luminance (transmittance) of the pixel can be shifted to the higher side. . On the other hand, if the pixel is shifted to the negative side, the luminance in the pixel can be shifted to the lower side. If the voltage difference of Vr1-Vr2 is set large in advance, the contrast ratio can be increased, and if it is decreased, the contrast ratio can be decreased. Therefore, it is desirable to provide a variable voltage generation circuit inside the power supply circuit 400 so that the reset voltages Vr1 and Vr2 can be adjusted.
[0104]
<3-2: AC drive>
In the embodiment described above, when the black-side reset voltage value Vr1 and the white-side reset voltage value Vr2 and the black-side set voltage value Va1 and the white-side set voltage value Va2 are set to the reference voltage as the reference voltage, the positive polarity is obtained. However, in an actual liquid crystal panel, the liquid crystal of the pixel is AC driven in order to prevent the deterioration of the liquid crystal. Therefore, the black level voltage VBK and the white level voltage VWT need to output a negative voltage with reference to the voltage of the counter electrode, and apply a negative voltage to the pixel liquid crystal. For this reason, the white level / black level voltage generator 410 needs to generate a black level voltage VBK and a white level voltage VWT by switching between a positive voltage and a negative voltage according to the AC drive cycle. .
[0105]
Therefore, the power supply circuit 400 exchanges each output voltage of the positive polarity power supply circuit that generates each voltage for positive polarity, the negative polarity power supply circuit that generates each voltage for negative polarity, the positive polarity power supply circuit, and the negative polarity power supply circuit. It is desirable to provide a selection circuit that selects according to the driving cycle.
[0106]
Examples of the switching cycle of the set voltages Va1 and Va2 and the reset voltages Vr1 and Vr2 include the following modes. In the first aspect, the polarity of the applied voltage is switched every vertical scanning period. This is a driving method in which the polarity of the liquid crystal applied voltage is inverted every vertical scanning period (one field or one frame). In the second aspect, the polarity of the applied voltage is switched every horizontal scanning period. Further, as a third aspect, there is a case where the polarity of the liquid crystal applied voltage is inverted for each column line (so-called source line inversion), or the polarity of the liquid crystal applied voltage is inverted for each pixel (so-called dot inversion driving). .
[0107]
In these cases, the polarities of the voltages given as Va1, Va2, Vr1, and Vr2 need to be alternately different between adjacent DA units. For this reason, the power supply circuit 400 includes a negative polarity power supply circuit and a positive polarity power supply circuit, and supplies their output voltages to the scanning line driving circuit 100.
[0108]
<3-3: Relationship between image data and white / black level>
In the embodiment described above, the input image data Din is described as “1111” being a black level and “0000” being a white level. Conversely, even if “1111” is a white level and “0000” is a black level. Good. In the embodiment, the orientation of the liquid crystal molecules and the setting of the polarization axis are changed (as a normally black mode), and the transmittance is low when the output voltage of the DA converter is low, and the transmittance is high when the output voltage is high. Even in this case, the same applies.
[0109]
<4. Application example>
Next, application examples of the liquid crystal display device described in the above-described embodiments and modifications will be described.
[0110]
<4-1: Projector>
First, a projector using this liquid crystal display device as a light valve will be described. FIG. 12 is a plan view showing a configuration example of the projector.
[0111]
As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.
[0112]
The configuration of the liquid crystal panels 1110R, 1110B, and 1110G is the same as that of the above-described liquid crystal panel AA, and is driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.
[0113]
Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.
[0114]
Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.
[0115]
<4-2: Mobile computer>
Next, an example in which the liquid crystal panel AA is applied to a mobile personal computer will be described. FIG. 13 is a perspective view showing the configuration of the personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal panel 1005 described above.
[0116]
<4-3: Mobile phone>
Further, an example in which the liquid crystal panel AA is applied to a mobile phone will be described. FIG. 14 is a perspective view showing the configuration of this mobile phone. In the figure, a cellular phone 1300 includes a reflective liquid crystal panel 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal panel 100, a front light is provided on the front surface thereof as necessary.
[0117]
In addition to the electronic devices described with reference to FIGS. 12 to 14, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Stations, videophones, POS terminals, devices with touch panels, etc. Needless to say, the present invention can be applied to these various electronic devices.
[0118]
【The invention's effect】
As described above, according to the present invention, the reset voltage and the set voltage are selected according to the most significant bit of the image data and the charge movement is executed a number of times according to the lower bit value. The DA conversion can be performed while performing γ correction on the image data with low power consumption and low power consumption.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a pixel DAC used in the embodiment and a peripheral configuration thereof.
FIG. 3 is a conceptual diagram for explaining the principle of DA conversion of the present invention.
FIG. 4 is a graph showing the relationship between the charge voltage value and the number of charge / discharge cycles when Va> Vr.
FIG. 5 is a graph showing the relationship between the charge voltage value and the number of charge / discharge cycles when Vr> Va.
6A is a graph showing a relationship between image data D necessary for obtaining a transmittance characteristic curve Y and an applied voltage VLP of a liquid crystal, and FIG. 6B is a graph showing that the number of bits of image data is 6 bits. The horizontal axis represents the transmittance of the liquid crystal, and the vertical axis represents the applied voltage VLP of the liquid crystal.
FIG. 7 is a graph showing the relationship between Va1, Vr1 and Va2, Vr2.
FIG. 8 is a circuit diagram showing a detailed configuration of a scanning line driving circuit used in the embodiment.
FIG. 9 is a block diagram showing a configuration of a data line driving circuit used in the embodiment.
FIG. 10 is a block diagram showing a configuration of a PWM signal generator and its peripheral circuits used in the same embodiment.
FIG. 11 is a timing chart showing the operation of the liquid crystal display device of the embodiment.
FIG. 12 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which a liquid crystal display device is applied.
FIG. 13 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which a liquid crystal display device is applied.
FIG. 14 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal display device is applied.
FIG. 15 is a block diagram showing a data line driving circuit for driving one data line and its peripheral circuit.
16A is a graph showing the relationship between the decimal value of image data DA and the output voltage Vc of the DA converter 93. FIG. (B) is a graph showing the relationship between the liquid crystal transmittance SLP and the voltage VLP applied to the pixel electrode via the signal line.
[Explanation of symbols]
AA …… Electro-optical panel
CX: Liquid crystal capacity (electro-optic capacity)
CD …… DAC capacity (internal capacity)
D, D0 to D3 …… Image data
9a: Pixel electrode
3a1 to 3a4... Scanning lines (first to fourth scanning lines)
6a1, 6a2... Data lines (first data line, second data line)
71-74 ...... Switch elements (fourth to first switch elements)
100: Scan line driving circuit
110 …… Y shift register
CMPBK, CNPWT …… Black level selection signal, white level selection signal
CLK, CLKB: Clock signal, inverted clock signal
SW1 to SWm ... selection circuit
Y1-Ym: Scanning signal (scanning line set selection signal)
200: Data line driving circuit
210 ... X shift register
220 …… First latch section
230 …… Second latch part
UC1 to UCn: PWM signal generation unit (control unit)
CMPout …… Comparison result signal
CMP …… Comparator (Comparator)
300 ... Timing signal generation circuit
410... White / black level voltage generator (black level voltage generator, white level voltage generator)

Claims (14)

An electro-optical panel having a pixel electrode, an internal capacitor, and an electro-optical capacitor formed by sandwiching an electro-optical material between the pixel electrode and a counter electrode in each of a plurality of pixels arranged in a matrix. A driving method comprising:
A first state in which the internal capacitor and the pixel electrode are electrically connected; and a second state in which the internal capacitor and the pixel electrode are electrically disconnected.
After setting the first state, the electro-optic capacitor and the internal capacitor are charged with a reset voltage,
After the second state, the internal capacitor is charged with a set voltage,
By setting the first state, the charge is transferred between the internal capacitor and the electro-optic capacitor,
The method of driving an electro-optical panel, wherein the step of charging the internal capacitor with a set voltage and the step of moving the charge are repeated a number of times according to the value of image data. An electro-optical panel having a pixel electrode, an internal capacitor, and an electro-optical capacitor formed by sandwiching an electro-optical material between the pixel electrode and a counter electrode in each of a plurality of pixels arranged in a matrix. A driving method comprising:
In accordance with the digit of the most significant bit of the image data, either the first reset voltage corresponding to the black side level or the second reset voltage corresponding to the white side level is selected, and the selected voltage is selected as the electric voltage. Power the optical capacity,
Depending on the digit of the most significant bit, either the first set voltage corresponding to the black side level or the second set voltage corresponding to the white side level is selected, and the selected voltage is applied to the internal capacitor. Power
Performing charge transfer between the electro-optic capacitance and the internal capacitance;
The method of driving an electro-optical panel, wherein the power feeding step to the internal capacitor and the charge transfer step are repeated a number of times according to a lower bit value excluding the most significant bit in the image data. The electro-optical material is a liquid crystal, and the image data indicates a dark gradation as the data value increases,
When the liquid crystal operates in a normally white mode, a first difference voltage between the first reset voltage and the first set voltage is set between the second reset voltage and the second set voltage. The method of driving an electro-optical panel according to claim 2, wherein the driving voltage is set to be larger than the second differential voltage. The electro-optic material is a liquid crystal, and the image data indicates a brighter gradation as the data value increases,
When the liquid crystal operates in a normally black mode, a first difference voltage between the first reset voltage and the first set voltage is set between the second reset voltage and the second set voltage. 3. The method for driving an electro-optical panel according to claim 2, wherein the driving method is set to be smaller than the second differential voltage. A first scanning line that supplies a clock signal, a second scanning line that supplies an inverted clock signal, and a black level voltage that is one of the first reset voltage value and the first set voltage value for the black side level. A plurality of sets of a third scanning line to be supplied and a fourth scanning line to supply a white level voltage that is one of the second reset voltage value or the second set voltage value with respect to the white level. A scan line set;
A plurality of data line sets each including a first data line for supplying a black level selection signal and a second data line for supplying a white level selection signal;
Each pixel arranged in a matrix corresponding to the intersection of the scanning line set and the data line set,
The pixel is
An electro-optic capacitance formed by sandwiching an electro-optic material between the pixel electrode and the counter electrode;
A first switch element provided between the pixel electrode and an internal capacitor and controlled to be turned on / off based on the inverted clock signal;
A second switch element connected to the internal capacitor and one terminal and controlled to be turned on / off based on the clock signal;
A third switch element having one terminal connected to the other terminal of the second switch element, the other terminal connected to the third scanning line, and an ON / OFF control based on the black level selection signal When,
A fourth switch element having one terminal connected to the other terminal of the second switch element, the other terminal connected to the fourth scanning line, and controlled to be turned on / off based on the white level selection signal; And an electro-optical panel. A scanning line driving circuit that is used in the electro-optical panel according to claim 5 and drives a plurality of scanning line sets,
A shift register that sequentially outputs a plurality of scanning line set selection signals for sequentially selecting transfer line sets by sequentially shifting transfer pulses of a vertical scanning period;
Provided for each scanning line group, and supply the clock signal, the inverted clock signal, the black level voltage, and the white level voltage to each corresponding scanning line group based on each scanning line group selection signal A scanning line driving circuit comprising: a plurality of selection circuits. A data line driving circuit used for the electro-optical panel according to claim 5 for driving a plurality of data line sets,
A shift register that sequentially shifts transfer pulses of a horizontal scanning period and sequentially outputs each selection signal;
A first latch unit that latches image data based on each selection signal and outputs a plurality of dot sequential image data;
A second latch unit that latches each point sequential image data in a horizontal scanning period and outputs a plurality of line sequential image data;
A control unit having a plurality of control units provided corresponding to each data line set,
One control unit is
A pulse width modulation signal generating unit that generates a pulse width modulation signal that is pulse width modulated according to a data value of a lower bit excluding the most significant bit in the line sequential image data;
The pulse width modulation signal is supplied to the first data line as the black level selection signal or the second data line as the white level selection signal according to the most significant bit digit of the line sequential image data. A data line driving circuit comprising: a selection unit that selects whether to supply. The pulse width modulation signal generator is
The count value is reset in the horizontal scanning cycle, and the count data obtained by counting the master clock signal is compared with the lower-order bit data excluding the most significant bit in the line-sequential image data. The data line driving circuit according to claim 7, further comprising a comparison circuit that generates a pulse width modulation signal. An electro-optical panel according to claim 5;
A scanning line driving circuit according to claim 6;
A data line driving circuit according to claim 7,
An electro-optical device comprising: a timing signal generation circuit that generates the clock signal, the inverted clock signal, the black level voltage, and the white level voltage and supplies the generated voltage to the scanning line driving circuit. The timing generation circuit includes:
In the predetermined reset period at the beginning of the horizontal scanning period, the black level voltage value is set as the first reset voltage value, and the black level voltage value is set as the first set voltage value in the other periods. A black level voltage generator for generating a black level voltage;
A white level voltage that generates the white level voltage so that the value of the white level voltage is the second reset voltage value in the reset period and the value of the white level voltage is the second set voltage value in the other period. The electro-optical device according to claim 9, further comprising: a generation unit. The electro-optical material is a liquid crystal, and the image data indicates a dark gradation as the data value increases,
When the liquid crystal operates in a normally white mode, a first difference voltage between the first reset voltage and the first set voltage is set between the second reset voltage and the second set voltage. The electro-optical device according to claim 9, wherein the electro-optical device is set to be larger than the second differential voltage. The electro-optic material is a liquid crystal, and the image data indicates a brighter gradation as the data value increases,
When the liquid crystal operates in a normally black mode, a first difference voltage between the first reset voltage and the first set voltage is set between the second reset voltage and the second set voltage. The electro-optical device according to claim 9, wherein the electro-optical device is set to be smaller than the second differential voltage. The electro-optical device according to claim 9,
The electro-optical device, wherein the scanning line driving circuit and the data line driving circuit are built in an electro-optical panel, and an active element constituting the electro-optical panel is a thin film transistor.   An electronic apparatus comprising the electro-optical device according to claim 9, wherein an image is displayed on the electro-optical panel.

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