JP2002140292A - Arbitration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To terminate an access permitting period when a bus access request is released. SOLUTION: This arbitration circuit is provided with an input part 1 constructed of a plurality of D flip-flops 11 and 12, an output part 2 constructed of a plurality of pairs of D flip-flops 211 and 221 and selectors 212 and 222, an order determination control circuit 3 executing processing for priority order determination and internal control, and a correction circuit 4 correcting an access permitting period ending time shown by an output level change of the D flip-flop in the output part 2 to a bus access request ending time obtained from a bus access request signal according to bus access request signals IS1 and IS2 and access permitting signals OS1 and OS2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration circuit for outputting a plurality of access permission signals indicating whether or not access is permitted in response to a plurality of bus access request signals indicating the presence or absence of a bus access request.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing one configuration example of a conventional arbitration circuit. The arbitration circuit shown in this figure includes a plurality (two or more, and for simplicity, two) of bus access request signals IS
1 and IS2 to D terminals, respectively, and an input unit 1 composed of a plurality of D flip-flops 11 and 12 and access permission signals OS1 and OS2 corresponding to a plurality of bus access request signals IS1 and IS2 are output terminals ( An output section 2a composed of a plurality of JK flip-flops 21a and 22a (which may be D flip-flops) that output from an inverted Q terminal which is low in a set state, and a rank determination control circuit 3a Have.

The order determination control circuit 3a performs priority order determination and internal control processing. The inputs are the Q terminals of a plurality of D flip-flops 11 and 12, and the outputs of a plurality of JK flip-flops 21a and 22a. While the terminals are connected, the outputs are connected to the J and K terminals of the plurality of JK flip-flops 21a and 22a. Here, a specific example of the above processing will be described. The Q level of the plurality of D flip-flops 11 and 12 is monitored while monitoring the output levels of the output terminals of the plurality of JK flip-flops 21a and 22a.
According to the output level of the terminal, a plurality of control signals CS11 / CS12, CS21 / CS22 are output according to a predetermined priority rule (including a case where there is no conflict), and a plurality of JK flip-flops 21a, 22a are output. A plurality of access permission signals OS1, OS1
2 is output. For example, if two or more of the plural (here, two or more) bus access request signals compete, an access permission signal corresponding to the bus access request signal having the highest priority is output in accordance with the above-mentioned priority rule. Is output. Further, in order to prevent the output monopoly of the access permission signal due to the bus access request signal having the higher priority, the output levels of the output terminals of the plurality of JK flip-flops 21a and 22a are considered (Japanese Patent Laid-Open No. 63-247857, etc.). See).

Japanese Unexamined Patent Publication No. 3-1263 discloses an arbitration for a high-order contention access request generated in an execution cycle at a timing delayed by a predetermined time from a system clock, thereby determining an asynchronous device with one system clock. An arbitration circuit that can arbitrate an access request from an arbitrator is disclosed.

[0005]

FIG. 4 is a timing chart showing an operation example of the arbitration circuit of FIG. When the output level of each control signal of the order determination control circuit 3a is Low, the input level of the D terminal of the D flip-flop 11 changes from High to Low, and the bus access request signal IS1 changes to a signal for requesting a bus access. When (t
1) At the rising time t2 of the system clock CLK, D
The output level of the Q terminal of the flip-flop 11 is High
From Low to Low, and the level of the control signal CS11 output from the rank determination control circuit 3a is changed to Low in response to this.
Switching from w to High. The High level of the control signal CS11 is held until the next rising time t3 of the system clock CLK. Thus, the control signal CS1
When 1 is switched to High level (t2), the input levels of the J and K terminals of the JK flip-flop 21a become High and Low, respectively.
At the rising time point t3 of K, as shown in the lower part of FIG.
The output level of the output terminal of the K flip-flop 21a is H
Switching from high to low. As a result, the access permission signal OS1 indicating access permission is output, and the access permission period occupied by the device (not shown) that has output the bus access request signal IS1 for making a bus access request starts at time t3.

After that, the input level of the D terminal of the D flip-flop 11 changes from Low to High (the bus access request is released), and the bus access request signal IS1
Becomes a signal not requesting a bus access (t4), at the rising time t5 of the system clock CLK, the output level of the Q terminal of the D flip-flop 11 changes from low to high.
h, and the level of the control signal CS12 output from the rank determination control circuit 3a is changed from Low to H in response to this.
It switches to the high level. The High level of the control signal CS12 is held until the next rising time t6 of the system clock CLK. Thus, the control signal CS1
2 is switched to the high level (t5), the input levels of the J and K terminals of the JK flip-flop 21a become low and high, respectively.
At the rising time t6 of K, as shown at the bottom of FIG.
The output level of the output terminal of the K flip-flop 21a is L
Switching from ow to High. Thus, the access permission period occupied by the device of the bus access request signal IS1 ends at the time point t6.

Here, the device of the bus access request signal IS1 starts accessing the bus from the point in time t3 when the access permission signal OS1 is output, and thereafter, at the point in time t4 when the access to the bus becomes unnecessary. Since the access request is released, the period between the time point t3 and the time point t4 is necessary and sufficient for the device as the bus access permission period.

However, in the circuit configuration shown in FIG. 3, the actual access permission period given to the device is shifted until time t6, and one of the plurality of devices has the access permission period (t3-t).
6) Due to the role of the arbitration circuit which cannot permit access to other devices while occupied, time t
However, there is a problem that the access cannot be permitted, although the access can be permitted to another device from the device No. 4. As can be seen from FIG. 4, the arbitration circuit of FIG. 3 is delayed by at least one clock cycle and at the most less than two clock cycles.

The present invention has been made in view of the above circumstances, and has as its object to provide an arbitration circuit capable of terminating an access permission period when a bus access request is released.

[0010]

According to a first aspect of the present invention, there is provided an output register for synchronizing with a clock, wherein a plurality of access registers are provided in response to a plurality of bus access request signals. An arbitration circuit having at least a function of outputting a signal from each of the plurality of output registers, wherein the arbitration circuit indicates an access permission period by a change in an output level of the output register. A correction means is provided which is initialized in response to a permission signal and corrects the end point of the access permission period by the output register to the end point of the bus access request indicated by the corresponding bus access request signal.

[0011]

FIG. 1 is a block diagram of an arbitration circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart showing an operation example of the arbitration circuit of FIG. This embodiment will be described.

The arbitration circuit shown in FIG. 1 has an input unit 1 in the same manner as the conventional arbitration circuit shown in FIG. 3, and is different from the conventional arbitration circuit in that an output unit 2 and a rank determination control circuit are provided. 3 and a correction circuit 4.

The output unit 2 provides access permission signals OS1, OS2 corresponding to a plurality of bus access request signals IS1, IS2.
2 from the Q terminal, and a plurality of D flip-flops 211 and 221 respectively, and a plurality of control signals CS1 and CS2
, And a plurality of selectors 212 and 222 for inputting the respective values.

Each of the plurality of selectors is connected to a select terminal S for inputting a corresponding control signal from the rank determination control circuit 3, a grounded first terminal, and a Q terminal of a pair of D flip-flops. And a pair of D terminals
An output terminal connected to the D terminal of the flip-flop, and switching the output terminal to either the first terminal or the second terminal according to a control signal input to the select terminal S. In the example of FIG. 1, the plurality of selectors 212 and 22
When the control signal input to its own select terminal S is High (1), each of its 2
When the control signal is Low (0) while switching to the terminal, the output terminal of the terminal is switched to the second terminal of the terminal.

The order determination control circuit 3 executes processing for priority order determination and internal control. The inputs include the Q terminals of a plurality of D flip-flops 11 and 12 and the Q terminals of a plurality of D flip-flops 211 and 221. While a terminal is connected, a plurality of D flip-flops 211 and 22 are connected to the output via a plurality of selectors 212 and 222, respectively.
1 D terminal is connected. Here, a specific example of the above processing will be described.
While monitoring the output level of the Q terminal 21, a plurality of control signals CS 1 and CS 2 are output in accordance with a predetermined priority rule according to the output levels of the Q terminals of the plurality of D flip-flops 11 and 12. Thus, a process of outputting a plurality of access permission signals OS1 and OS2 from the Q terminals of the plurality of D flip-flops 211 and 221 is executed. Further, as in the conventional case, in order to prevent output monopolization of the access permission signal due to the bus access request signal having the higher priority, the Q flip-flops 211,
The output level of the terminal is taken into account.

The correction circuit 4 responds to the input levels of the D terminals of the plurality of D flip-flops 11 and 12 and the output levels of the Q terminals of the plurality of D flip-flops 211 and 221 respectively. To correct the end point of the access permission period to the end point of the bus access request obtained from the input levels of the D terminals of the plurality of D flip-flops 11 and 12. In the example of FIG. 1, the correction circuit 4 has a plurality of two-input AND gates each having one input terminal being active low,
One input terminals of the plurality of AND gates 41 and 42 are connected to a plurality of D flip-flops 211 and 221 respectively.
And the other input terminal is connected to the D terminal of each of the plurality of D flip-flops 11 and 12,
The output terminals of the plurality of AND gates 41 and 42 are
Each of the plurality of D flip-flops 211 and 221 is connected to a set terminal S for initialization.

Next, the operation of the arbitration circuit having the above configuration will be described. The output level of each control signal of the rank determination control circuit 3 is L
When the signal is low, the input level of the D terminal of the D flip-flop 11 changes from High to Low, and when the bus access request signal IS1 becomes a signal for requesting a bus access (t11), the rising edge time t of the system clock CLK is reached.
At 12, the output level of the Q terminal of the D flip-flop 11 switches from High to Low, and in response, the level of the control signal CS1 output from the rank determination control circuit 3 switches from Low to High. This control signal CS
The High level of 1 is held until the next rising time t13 of the system clock CLK. As described above, when the control signal CS1 switches to the high level (t12), the output terminal of the selector 212 is switched and connected to the first terminal, and
Since the D terminal of the D flip-flop 211 becomes Low level, the output level of the Q terminal of the D flip-flop 211 becomes Hi at the rising time t13 of the system clock CLK.
It switches from gh to Low. At this time, the selector 21
2, the level of the control signal CS1 input to the select terminal S is switched from High to Low, and the level of the selector 212 is changed.
Is connected to the second terminal by switching, and the selector 212
The output level (Low level) of the Q terminal is applied to the D terminal of the D flip-flop 211 via the switch. As a result, the output level of the Q terminal of the D flip-flop 211 is kept Low even after time t13.

Thereafter, when the input level of the D terminal of the D flip-flop 11 changes from Low to High and the bus access request signal IS1 becomes a signal not requesting a bus access (t14), the level of one input terminal is changed. Low
Since the high-level bus access request signal IS1 is input to the other input terminal of the AND gate 41, the level of the output terminal of the AND gate 41 becomes High, and the D flip-flop 211 is initialized. As a result, the output level of the Q terminal of the D flip-flop 211 switches from low to high at time t14, and the output level of the Q terminal of the D flip-flop 211 is input to the D terminal.
The output level of the Q terminal is kept High even after time t14.

At time t14, the input level of the D terminal of the D flip-flop 11 changes to High, so that at the rising time t16 of the system clock CLK,
The output level of the Q terminal of the D flip-flop 11 is Low
From High to High, but in the example of FIG.
At the time point t15 before the time point t16, the input level of the D terminal of the D flip-flop 12 changes from High to Low, and the bus access request signal IS2 becomes a signal for requesting a bus access. Thereby, the system clock C
At the rise time t16 of LK, the output level of the Q terminal of the D flip-flop 12 switches from High to Low, and in response thereto, the level of the control signal CS2 output from the rank determination control circuit 3 switches from Low to High. The High level of the control signal CS2 is held until the next rising time t17 of the system clock CLK. Thereafter, the operation is the same as that of the bus access request signal IS1, and the D flip-flop 221 is initialized and the level of the Q terminal is switched to High according to the bus access request signal IS2 that does not make a bus access request at time t18. , Rising time t19 of system clock CLK
And the output level of the Q terminal of the D flip-flop 12 is L
Switching from ow to High.

As described above, according to the present embodiment, as shown in FIG. 2, the times t14 and t1 when the bus access request is released.
8, access permission periods t13 to t14, t17 to t18
Can be terminated. Thus, since the bus access request can be immediately responded to after the bus access request is released, the processing speed of the entire system can be increased. More specifically, in the example of FIG. 4, a time point t4 at which the bus access request is released and a time point t6 at which the bus access request can be satisfied after this time point
Is at least a little more than one clock cycle and at most a little less than two clock cycles, in the example of FIG. 2, it responds to the time t14 when the bus access request is canceled and the bus access request after this time. The time interval from the time point t16, which can be performed, is about 0 at the minimum and less than 1 clock cycle at the maximum.

In this embodiment, the output unit 2 and the order determination control circuit 3 are provided. However, the correcting means of the present invention comprises the output unit 2 and the order determination control circuit 3.
Not only the specific configuration (specific circuit, specific function) but also a plurality of output registers for synchronization with the system clock CLK, such as the configuration of FIG. 3, and a plurality of access permission signals are transmitted in response to a plurality of bus access request signals. It has at least a function of outputting from each of a plurality of output registers, and is applicable to a configuration in which an access permission period is indicated (defined) by a change in an output level of the output register.

[0022]

As is apparent from the above description, the invention according to claim 1 includes a plurality of output registers for synchronizing with a clock, and outputs a plurality of access permission signals in response to a plurality of bus access request signals. An arbitration circuit having at least a function of outputting from each of the plurality of output registers and indicating an access permission period by a change in an output level of the output register, wherein the arbitration circuit outputs a corresponding bus access request signal and access permission signal And the correction means for correcting the end point of the access permission period by the output register to the end point of the bus access request indicated by the corresponding bus access request signal. Since it is modified at the end of the bus access request indicated by the corresponding bus access request signal, After the time that Seth request is canceled, it can be immediately responsive to the bus access request, this result, it is possible to the processing speed of the entire system at a high speed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an arbitration circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation example of the arbitration circuit of FIG. 1;

FIG. 3 is a diagram illustrating a configuration example of a conventional arbitration circuit.

FIG. 4 is a timing chart illustrating an operation example of the arbitration circuit of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input part 11,12 D flip-flop 2 Output part 211,221 D flip-flop 212,222 Selector 3 Order determination control circuit 4 Correction circuit 41,42 AND gate

Claims (1)

[Claims] A plurality of output registers for synchronizing with a clock; a plurality of output registers for outputting a plurality of access permission signals from the plurality of output registers in response to a plurality of bus access request signals; An arbitration circuit that indicates an access permission period by a change in an output level of a register, wherein the output register is initialized according to a corresponding bus access request signal and an access permission signal, and the end point of the access permission period by the output register Arbitration circuit, which corrects the time at the end of the bus access request indicated by the corresponding bus access request signal.