JP2002134736A - Field effect type compound semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably and accurately obtain an expected threshold Vth, without increasing the amount of gate recess in a field effect type compound semiconductor device, and to provide a manufacturing method of the field effect type compound semiconductor device. SOLUTION: A gate electrode 8, formed on a semiconductor layer 4, is composed by a lamination structure where a reaction layer 5 of a semiconductor layer 4 and a metal film, a metal oxide film 6, and a metal layer 7 are successively laminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect compound semiconductor device and a method of manufacturing the same, and
A plurality of HEMT having different threshold voltages V _th (high electron mobility transistor) or MESFET (Metal
-Semiconductor FET) field-effect compound semiconductor device and a manufacturing method thereof is characterized by the arrangement for accurately controlling the threshold V _th of field effect type compound semiconductor device obtained by integrating a field effect type compound semiconductor elements such as It is about.

[0002]

2. Description of the Related Art Conventionally, an electronic device using a compound semiconductor such as GaAs or InP constituting a high-frequency amplifying element or an ultra-high-speed integrated circuit device has a problem of an interface state. A type compound semiconductor device is used.

In an integrated circuit device using such a field-effect type compound semiconductor element, elements having different V _th may be separately formed on the same substrate. For example, an enhancement mode (E mode) and a depletion mode (D mode) may be used.
Mode), a circuit may be constituted by two types of elements, and here, with reference to FIG. 10, a conventional E-DHE
MT will be described.

FIG. 10 is a schematic sectional view of a conventional E-DHEMT.
First, an i-type AlGaAs buffer layer 52, an i-type InGaAs channel layer 53, an n-type AlGaAs electron supply layer 54, an n-type GaAs are formed on a semi-insulating GaAs substrate 51 by MOVPE (metal organic chemical vapor deposition). Cap layer 55, n-type AlGaAs etching stopper layer 56, n
-Type GaAs cap layer 57, n-type AlGaAs etching stopper layer 58, and n-type GaAs cap layer 59
Are sequentially grown.

Next, an element isolation region 60 reaching the i-type AlGaAs buffer layer 52 is formed by selectively implanting oxygen ions, and then ohmic source / drain electrodes are formed so as to extend over the element isolation region 60. 61 is formed.

Next, on the E-mode element side, a deep gate recess region 62 reaching the n-type GaAs cap layer 55 is formed, and on the D-mode element side,
After forming a shallow gate recess region 63 reaching the n-type GaAs cap layer 57, gate electrodes 64 and 65 are formed.

In such an E-DHHEMT, V _th is controlled by the distance between the contact surfaces of the gate electrodes 64 and 65 and the i-type InGaAs channel layer 53, and the depth of the gate recess regions 62 and 63 is controlled. By doing so, V _th is made different.

Therefore, when an E-mode element is formed, the number of selective etching steps is increased by one. However, the anisotropy of etching in such a selective etching step is not sufficient, and is often isotropic. When the depth of the gate recess region 62 is increased, the amount of side etching also increases.

As described above, when the depth of the gate recess region 62 is increased, the source resistance R _s is increased. However, when the side etching amount is increased, the source resistance R _s is further increased. since depth and amount of side etching region 62 are both large, the source resistance R _s increases significantly, resulting in degradation transconductance g _m, there is a problem that high speed is inhibited. Note that the amount of etching when forming the gate recess region 62 cannot be reduced to determine the threshold value V _th .

On the other hand, an InGaAs / InAlAs HE
In MT, since there is no good etching stopper layer such as AlGaAs for GaAs, it has been proposed to control V _th by using a reaction layer with a gate electrode. −47
No. 800 publication), so here, with reference to FIG.
A conventional improved E-DHEMT will be described.

FIG. 11 is a schematic sectional view of a conventional improved E-DHEMT. First, an MBE is placed on a semi-insulating InP substrate 71.
(Molecular beam epitaxial growth) method, i-type In
_0.52 Al _0.48 As buffer layer 72, i-type In _0.53 Ga
_0.47 As active layer 73 and n-type In _0.52 Al _0.48 As
After sequentially growing the electron supply layer 74, mesa etching is performed.

Next, AuGe /
After forming a drain electrode 75, a source / drain electrode 76, and a source electrode 77 made of Au, a gate electrode 78 made of Al is formed on the D mode element side, and a Pt layer 81 is formed on the E mode element side. Ti layer 82, Pt
A layer 83 and an Au layer 84 are sequentially deposited.

Then, at 300 to 450 ° C., for example, at 35
By annealing at 0 ° C. for 10 minutes, Pt
Part of layer 81 and n-type In _0.52 Al _0.48 As electron supply layer 7
PTAS ₂ layer 80 is formed by reacting a 4, PTAS ₂ layer 80 / Pt layer 81 / Ti layer 82 / P
Buried gate electrode 79 composed of t layer 83 / Au layer 84
Is formed.

In the improved E-DHHEMT, by using a reaction layer, that is, a PtAs ₂ layer 80,
Since the distance between the gate electrode and the i-type In _0.53 Ga _0.47 As active layer 73 is changed, the gate electrode only needs to be formed on the same plane, and the mutual conductance g _m may be deteriorated due to the amount of side etching. Absent.

[0015] Therefore, such technical matters are referred to as GaAs.
/ AlGaAs-based HEMT, the gate recess region on the E-mode device side may be the same depth as the gate recess region on the D-mode device side, so that only one etching stopper layer is required, and therefore the side etching amount Can be suppressed from increasing.

[0016]

However, as described above,
Using the reaction layer formed by annealing, the threshold V
_thThe temperature required to form a reaction layer
300-450 ° C., this temperature is
Demand for heat resistance of gate electrode in fabrication process
The reaction temperature is about 350 ° C.
Reaction progresses further due to thermal environment in post-process
Then, the depth of the reaction layer changes and the threshold V_thFluctuates
There is a problem.

A Ti layer 82 is inserted in the gate electrode 79 in the E-mode element shown in FIG. 11, and Ti reacts with InAlAs or AlGaAs similarly to Pt to form a T layer.
Since it is known to form iAs, this Ti layer 82 does not function as a reaction stopper layer, and therefore, when placed in a long thermal environment after the formation of the reaction layer, T
The reaction reaches the i-layer 82, and the depth of the reaction layer further increases, so that the threshold value _Vth fluctuates. Therefore, there is a problem that the desired _Vth characteristic cannot be stably obtained.

Accordingly, it is an object of the present invention to stably and accurately obtain a desired threshold value _Vth without increasing the amount of gate recess.

[0019]

Here, means for solving the problem in the present invention will be described with reference to FIG. 1 and FIG. FIG. 1 is a schematic sectional view of a field-effect compound semiconductor device according to the present invention. In this case, a channel layer 2, a carrier supply layer 3, and a semiconductor layer 4 are sequentially stacked on a semiconductor substrate 1. Reference numeral 10 denotes a source / drain electrode. Also, FIG.
FIG. 4 is an explanatory diagram of the dependence of the threshold value V _{th on} the thickness of the reaction layer in the field-effect compound semiconductor device of the present invention.

Referring to FIG. 1, in order to solve the above-mentioned problem, the present invention relates to a field effect type compound semiconductor device, in which a gate electrode 8 formed on a semiconductor layer 4 is formed by a reaction layer 5 between the semiconductor layer 4 and a metal film. , A metal oxide film 6 and a metal layer 7 are sequentially stacked.

Referring to FIG. 2, as is apparent from FIG. 2, the threshold value V _th varies substantially linearly with the thickness of the reaction layer 5, that is, the thickness of the buried portion. The threshold V _th can be controlled arbitrarily by controlling, and an _ED field-effect compound semiconductor device can be configured by integrating elements having different thicknesses of the reaction layer 5. When the thickness of the reaction layer 5 is 0, the gate electrode 9 composed of the metal oxide film 6 and the metal layer 7 becomes a D-mode element.

In the present invention, the metal oxide film 6 serves as a reaction stopper layer when the reaction layer 5 is formed.
Therefore, the thickness of the reaction layer 5 does not change due to the thermal environment after the formation, and thus the desired threshold value V _th can be stably and accurately realized.

In this case, the metal elements constituting the metal oxide film 6 include Ti, Co, Ta, Ni, Pd, Pr, H
A metal having a large generation energy of an oxide such as f or Zr is preferable, and the interface state at the gate interface can be reduced.

The present invention also relates to a method of manufacturing a field-effect compound semiconductor device, comprising the steps of: forming a gate electrode 8 comprising a metal film / metal oxide film 6 / metal layer 7 on a semiconductor layer 4; And a step of forming a reaction layer 5 by reacting the semiconductor layer 4 and the metal film by performing a heat treatment.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process according to a first embodiment of the present invention will now be described with reference to FIGS. First, an i-type AlGaAs having a thickness of, for example, 200 nm is formed on a semi-insulating GaAs substrate 11 by MOVPE.
s buffer layer 12, i-type I having a thickness of, for example, 25 nm
The nGaAs channel layer 13 has a thickness of, for example, 25 nm.
Then, the n-type impurity concentration is, for example, 2 × 10 ¹⁸ cm ⁻³ n
Type AlGaAs electron supply layer 14 having a thickness of, for example, 50
nm, the n-type impurity concentration is, for example, 2 × 10 ¹⁸ cm ^−3.
N-type GaAs layer 15 having a thickness of, for example, 5 nm
N-type Al having a type impurity concentration of, for example, 2 × 10 ¹⁸ cm ⁻³
GaAs etching stopper layer 16 and a thickness of, for example, 50 nm, and an n-type impurity concentration of, for example, 2 × 1
An n-type GaAs cap layer 17 of 0 ¹⁸ cm ^-3 is sequentially deposited.

Next, the size corresponding to the element formation region is
Using the resist pattern 18 having
19 at an acceleration energy of 150 keV.¹²
cm ^-2Ion implantation at a dose of
The element isolation region 20 reaching the lGaAs buffer layer 12 is
Form.

Next, after removing the resist pattern 18, a new resist pattern (not shown) is provided, and a lift-off method using the resist pattern is used to form an AuGe layer having a thickness of, for example, 30 nm. A source / drain electrode 21 made of a layer and a 300 nm Au layer is formed.

Then, after removing the resist pattern, RTA (Rapid Thermal Anneal) for 5 minutes at 350 ° C. in an N ₂ gas atmosphere, for example.
By performing l), the source / drain electrodes 21 are alloyed to form ohmic electrodes.

Next, as shown in FIG. 3C, a new resist pattern 22 is provided, and the resist pattern 22 is used as a mask to perform selective dry etching using a mixed gas of SiCl ₄ + SF ₆ to expose n. The GaAs cap layer 17 is removed, and then the exposed n-type AlGaAs etching stopper layer 16 is selectively removed by ammonia-based wet etching, thereby simultaneously forming the gate recess regions 23 corresponding to the E-mode element and the D-mode element. Form.

Next, after the resist pattern 22 is removed, a new resist is applied, and a predetermined exposure and development are performed, whereby a downward convex opening is formed only in the E-mode element forming region. Are formed. Although three resist layers are actually provided, two resist layers are used here for the sake of simplicity.

Next, a Ti film having a thickness of, for example, 5 nm is deposited by using a vapor deposition method.
The surface of the film is oxidized by exposing the surface of the film to O ₂ plasma to form a Ti oxide film 27.
m.

Referring to FIG. 4E, the thickness is again reduced to, for example, 10
A T-shaped gate electrode 28 is formed by sequentially depositing a Pt layer of nm and a Au layer of 400 nm. In the case where the lift-off method is used, the illustration of a deposited film or the like deposited on a portion to be removed together with the resist pattern is omitted.

Next, after removing the resist patterns 24 and 25 to remove the deposited film and the like deposited on the undesired portions, a new resist is applied again, and predetermined exposure and development are performed. Is performed, resist patterns 29 and 30 having downwardly convex openings only in the D-mode element formation region are formed.

Then, again, by using the vapor deposition method,
For example, after depositing a 2 nm Ti film, the Ti film is completely oxidized by exposure to an O ₂ plasma atmosphere to form a Ti oxide film 31.

Referring to FIG. 5 (g), the thickness is again reduced to, for example, 10
A T-shaped gate electrode 32 is formed by sequentially depositing a Pt layer of nm and a Au layer of 400 nm.

Next, after removing the resist patterns 29 and 30 to remove the deposited film and the like deposited on the undesired portions, the resist patterns 29 and 30 are removed in an N ₂ gas atmosphere at 150 to 450 ° C., preferably at 150 to 450 ° C. , 250-
A heat treatment is performed at 350 ° C., for example, 300 ° C. for 5 to 60 minutes, for example, 30 minutes, so that the Ti film 26 and the n-type GaAs layer 15 in the E-mode element are
By forming a reaction layer 33 by causing a reaction so that 6 completely disappears, the basic structure of the E-DHEMT is completed.

In this case, in the E-mode element, since the reaction layer 33 effectively becomes the tip of the gate electrode 28, the distance between the gate electrode 28 and the i-type InGaAs channel layer 13 is shorter than that in the D-mode element. As a result, an E-mode element having a positive V _th is obtained as shown in FIG.

As described above, in the first embodiment of the present invention, since V _th is controlled by using the reaction layer 33, the depth of the gate recess region 23 between the E mode element and the D mode element is reduced. Therefore, it is not necessary to make the gate recess region 23 of the E-mode element deep, so that the gate recess region 23 does not expand by side etching and the source resistance R _s does not increase.

In the first embodiment,
The Ti oxide films 27 and 31 are used as reaction stopper layers.
Therefore, as in the conventional example shown in FIG.
Undesirable reactions do not occur due to the thermal environment.
And V on the E-mode element side _thWith high accuracy as set
And the gate electrode 32 on the D-mode element side.
The Pt layer and the n-type GaAs layer 15 constituting
I will not respond.

Next, the manufacturing process of the second embodiment of the present invention will be described with reference to FIGS. 6 and 7. This second embodiment uses a common gate electrode forming process. Things. Referring to FIG. 6 (a), first, as in the first embodiment, FIG.
3C, the gate recess regions 23 corresponding to the E mode element and the D mode element are simultaneously formed.

Next, after the resist pattern 22 is removed, a new resist is applied, and predetermined exposure and development are performed to thereby form a resist pattern 34 having an opening only in the E-mode element formation region. Is formed, and then a Ti film 35 having a thickness of, for example, 3 nm is deposited by using an evaporation method.

Next, after removing the resist pattern 34 to remove the Ti film deposited on an undesired portion, a new resist is applied again, and predetermined exposure and development are performed. By
Resist patterns 36 and 37 having downward convex openings corresponding to the gate electrode formation regions of the E mode element and the D mode element are formed.

Then, again, by using the vapor deposition method,
For example, after depositing a 2 nm Ti film, the Ti film is completely oxidized by exposing it to an O ₂ plasma atmosphere to form a Ti oxide film 38 in the gate electrode formation regions of the E mode element and the D mode element. .

Next, referring to FIG. 7D, the thickness is again reduced to, for example, 10
T-shaped gate electrodes 39 and 40 are formed by sequentially depositing a Pt layer of nm and an Au layer of 400 nm.

Next, after removing the resist patterns 36 and 37 to remove the deposited film and the like deposited on the undesired portions, the resist patterns 36 and 37 are removed in an N ₂ gas atmosphere at 150 to 450 ° C., preferably at 450 to 450 ° C. , 250-
By performing a heat treatment at 350 ° C., for example, 300 ° C. for 5 to 60 minutes, for example, 30 minutes, the Ti film 35 and the n-type GaAs layer 15 in the E-mode element are
By forming a reaction layer 41 by causing a reaction such that 6 completely disappears, a basic structure of the E-DHEMT is completed.

Also in this case, in the E-mode element, since the reaction layer 41 effectively becomes the tip of the gate electrode 28,
The distance between the gate electrode 28 and the i-type InGaAs channel layer 13 is shorter than that of the D-mode element, and an E-mode element having a positive _Vth is obtained as shown in FIG.

As described above, in the second embodiment of the present invention, the steps of forming the gate electrodes 39 and 40 are shared, so that the number of steps can be reduced, and
It is possible to improve the throughput and reduce the cost. However,
In the process from FIG. 6B to FIG. 6C, the opening of the resist pattern 36 needs to be accurately aligned with the Ti film 35.

Next, the manufacturing process of the third embodiment of the present invention will be described with reference to FIGS. 8 and 9. This third embodiment is based on the thickness of the reaction layer, V _th is varied depending on the depth of the reaction layer, and only the reaction layer is formed on the D-mode element side in the first embodiment. Other basic manufacturing steps are the same as those in the first embodiment. Same as the form.

Referring to FIG. 8A, first, just as in the first embodiment, FIG.
3C, the gate recess regions 23 corresponding to the high V _th E mode element and the low V _th E mode element are simultaneously formed.

Next, after the resist pattern 22 is removed, a new resist is applied, and predetermined exposure and development are performed, so that a downward convex shape is formed only in the high V _th E mode element formation region. The resist patterns 24 and 25 having the openings are formed. In this case, three resist layers are actually provided, but here, two resist layers are used for the sake of simplicity.

Next, a Ti film having a thickness of, for example, 8 nm is deposited by using a vapor deposition method.
By exposing the surface of the film to O ₂ plasma, the surface is oxidized to form a Ti oxide film 27, and the Ti film 26 is formed of, for example, 6n.
m.

Next, referring to FIG. 8C, the thickness is again reduced to, for example, 10
A T-shaped gate electrode 28 is formed by sequentially depositing a Pt layer of nm and a Au layer of 400 nm.

Next, after removing the resist patterns 24 and 25 to remove the deposited film and the like deposited on the undesired portions, a new resist is applied again, and a predetermined exposure / development is performed. Is performed, resist patterns 29 and 30 having downwardly convex openings are formed only in the low V _th E mode element formation region.

Next, again by using the vapor deposition method,
For example, after depositing a 5 nm Ti film, the surface of the Ti film is exposed to O ₂ plasma to oxidize
The i-oxide film 43 is left, for example, with the Ti film 42 remaining at 3 nm.

Referring to FIG. 9E, the thickness is again reduced to, for example, 10
A T-shaped gate electrode 44 is formed by sequentially depositing a Pt layer of nm and a Au layer of 400 nm.

Next, after removing the resist patterns 29 and 30 to remove the deposited film and the like deposited on an undesired portion, the resist patterns are removed in an N ₂ gas atmosphere at 150 to 450 ° C., preferably at 150 to 450 ° C. , 250-
350 ° C., for example, at 300 ° C., 5 to 60 minutes, for example, by heat treatment for 30 minutes, the Ti film 42 and the n-type GaAs layer 15 in the Ti film 26 and a low V _th E mode element in the high V _th E mode element And the Ti film 26
And by the Ti film 42 to form a reaction layer 33 and the reaction layer 45 was reacted as completely eliminated, the basic structure of the E-EHEMT is completed consisting E mode elements having different V _th each other.

In this case, as is apparent from FIG. 2, V _th of each element depends on the depth of the reaction layer, so that V _{th of the} left element on which the deep reaction layer 33 is formed is V _th of the right element. higher than _th .

As described above, in the third embodiment of the present invention, by controlling the thickness of the reaction layer, devices having different V _th can be formed, and the basic manufacturing process is not changed. It is possible to integrate HEMTs having different types of V _th required in terms of circuit design on the same substrate.

The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations and conditions described in the embodiments, and various changes can be made. For example, in each of the above embodiments, when the Ti oxide film is formed, the Ti film is formed by exposing the Ti film to an O ₂ plasma atmosphere to oxidize the Ti film. 150 ° C in atmosphere or air
Oxidation may be performed at the above temperature.

In each of the above embodiments, Ti is used as the metal element constituting the metal oxide film serving as the reaction stopper layer. However, the present invention is not limited to Ti.
Like i, Co, Ta, Ni, Pd, Pr, Hf, and Zr, which are metals having a large oxide generation energy, may be used.

In the above embodiments, Ti is used as the metal forming the reaction layer.
Pt, which easily reacts with the GaAs layer like Ti, may be used.

In the description of each of the above embodiments, the gate electrode is made of a Pt / Au film.
A film may be used.

In each of the above embodiments, 2
E-DHEMT or EE with two different V _th
Although described as the HEMT, the present invention is not limited to such a configuration, and a D-mode element having no reaction layer and a plurality of E-mode elements having different reaction layer depths are integrated on the same substrate. It is a good thing.

In the third embodiment, both devices are described as E-mode devices.
Since it depends on the layer thickness of the n-type GaAs layer 15, if the depth of the reaction layer is shallow, it is possible to use a D-mode element even with the reaction layer, so that a different V _th is required. It becomes possible to integrate a D-mode device having the same.

In each of the above embodiments, an n-channel GaAs HEMT has been described. However, the present invention is not limited to an n-channel GaAs HEMT, but is also applicable to a p-channel GaAs HEMT. The InP-based H shown in FIG.
The present invention is also applied to other field effect type compound semiconductor devices such as EMT and MESFET.

Here, the detailed features of the present invention will be described with reference to FIG. 1 again. See FIG. 1 (Supplementary Note 1) The gate electrode 8 formed on the semiconductor layer 4 is
A reaction layer 5 between the semiconductor layer 4 and the metal film, a metal oxide film 6,
And a field effect compound semiconductor device having a stacked structure in which the metal layers 7 are sequentially stacked. (Supplementary Note 2) On the same semiconductor substrate 1, a gate electrode 8 composed of a reaction layer 5 of a semiconductor layer 4 and a metal film / a metal oxide film 6 / a metal layer 7, and a gate electrode 9 composed of a metal oxide film 6 / a metal layer 7 And a field-effect compound semiconductor device provided with at least: (Supplementary Note 3) A plurality of gate electrodes 8 including a reaction layer 5 of a semiconductor layer 4 and a metal film / a metal oxide film 6 / a metal layer 7 are provided on the same semiconductor substrate 1, and at least one reaction layer in the gate electrode 8 is provided. A field-effect compound semiconductor device, characterized in that the thickness of the gate electrode is different from the thickness of the reaction layer of the other gate electrode. (Supplementary Note 4) The metal constituting the metal oxide film 6 is T
4. The field-effect compound semiconductor device according to any one of supplementary notes 1 to 3, wherein the field-effect compound semiconductor device is any one of i, Co, Ni, Pd, Ta, Pr, Hf, and Zr. (Supplementary Note 5) When the metal film to be reacted with the semiconductor layer 4 is T
5. The field-effect compound semiconductor device according to any one of supplementary notes 1 to 4, wherein the field-effect compound semiconductor device is made of any one of i and Pt. (Supplementary Note 6) The field-effect compound semiconductor device is a high electron mobility transistor having a stacked structure in which a channel layer 2, a carrier supply layer 3, and a semiconductor layer 4 are sequentially stacked on a semiconductor substrate 1. 6. The field-effect compound semiconductor device according to any one of supplementary notes 1 to 5, characterized in that: (Supplementary Note 7) A step of providing a gate electrode 8 composed of a metal film / metal oxide film 6 / metal layer 7 on the semiconductor layer 4 and a gate electrode 9 composed of the metal oxide film 6 / metal layer, A method for manufacturing a field effect compound semiconductor device, comprising a step of forming a reaction layer 5 by reacting a layer 4 with a metal film. (Supplementary Note 8) The field-effect compound according to supplementary note 7, wherein the metal oxide film 6 functions as a reaction stopper layer in a step of reacting the semiconductor layer 4 and the metal film to form the reaction layer 5. A method for manufacturing a semiconductor device.

[0067]

According to the present invention, since the threshold value _Vth is controlled by the depth of the reaction layer, the characteristics of the E-mode element are not deteriorated. Since the metal oxide film functioning as a reaction stopper is interposed between the metal layer constituting the gate electrode and the reaction layer, the depth of the reaction layer does not change due to the thermal environment in the post-processing step. _Thereby , the threshold value _{Vth of} each element can be controlled with high precision as designed, and this greatly contributes to the enhancement of the performance and reliability of the field-effect compound semiconductor device.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a dependency of a threshold voltage on a reaction layer thickness.

FIG. 3 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention up to the middle of FIG.

FIG. 5 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention after FIG. 4;

FIG. 6 is an explanatory diagram of a manufacturing process partway through a second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a manufacturing process of the second embodiment of the present invention after FIG. 6;

FIG. 8 is an explanatory diagram of a manufacturing process partway through a third embodiment of the present invention.

FIG. 9 is an explanatory diagram of a manufacturing process of the third embodiment of the present invention after FIG. 8;

FIG. 10 is a schematic sectional view of a conventional E-DHEMT.

FIG. 11 is a schematic sectional view of a conventional improved E-DHHEMT.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 channel layer 3 carrier supply layer 4 semiconductor layer 5 reaction layer 6 metal oxide film 7 metal layer 8 gate electrode 9 gate electrode 10 source / drain electrode 11 semi-insulating GaAs substrate 12 i-type AlGaAs buffer layer 13 i-type InGaAs Channel layer 14 n-type AlGaAs electron supply layer 15 n-type GaAs layer 16 n-type AlGaAs etching stopper layer 17 n-type GaAs cap layer 18 resist pattern 19 oxygen ion 20 element isolation region 21 source / drain electrode 22 resist pattern 23 gate recess region 24 resist Pattern 25 resist pattern 26 Ti film 27 Ti oxide film 28 gate electrode 29 resist pattern 30 resist pattern 31 Ti oxide film 32 gate electrode 33 reaction layer 34 resist pattern 35 T Film 36 resist pattern 37 resist pattern 38 Ti oxide film 39 gate electrode 40 gate electrode 41 reaction layer 42 Ti film 43 Ti oxide film 44 gate electrode 45 reaction layer 51 semi-insulating GaAs substrate 52 i-type AlGaAs buffer layer 53 i-type InGaAs channel Layer 54 n-type AlGaAs electron supply layer 55 n-type GaAs cap layer 56 n-type AlGaAs etching stopper layer 57 n-type GaAs cap layer 58 n-type AlGaAs etching stopper layer 59 n-type GaAs cap layer 60 element isolation region 61 source / drain electrode 62 gate recess region 63 recessed gate region 64 a gate electrode 65 gate electrode 71 semi-insulating InP substrate 72 i-type In _0.52 Al _0.48 As buffer layer 73 i-type In _0.53 Ga _0.47 As active layer 74 n-type I _0.52 Al _0.48 As electron supply layer 75 drain electrode 76 source and drain electrodes 77 source electrode 78 gate electrode 79 gate electrode 80 PTAS ₂ layer 81 Pt layer 82 Ti layer 83 Pt layer 84 Au layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA05 BB10 BB36 CC01 CC03 DD26 DD34 DD68 DD79 DD80 DD81 DD83 DD88 FF07 FF13 GG12 HH20 5F102 FA03 GA02 GB01 GC01 GD01 GD10 GJ05 GJ06 GK04 GK06 GL04 GM04 GM04 GM04 GM04 GM04 GM04 GS02 GS04 GT03 GT04 GT10 HC01 HC17 HC21 HC24

Claims (5)

[Claims] 1. An electric field, wherein a gate electrode formed on a semiconductor layer has a stacked structure in which a reaction layer of the semiconductor layer and a metal film, a metal oxide film, and a metal layer are sequentially stacked. Effect type compound semiconductor device. 2. A gate electrode comprising a reaction layer of a semiconductor layer and a metal film / a metal oxide film / a metal layer on the same semiconductor substrate;
A field-effect compound semiconductor device comprising at least a gate electrode comprising a metal oxide film / metal layer. 3. A plurality of gate electrodes comprising a reaction layer of a semiconductor layer and a metal film / a metal oxide film / a metal layer are provided on the same semiconductor substrate, and at least one of the gate electrodes has a thickness of another reaction layer. A field-effect compound semiconductor device, wherein the thickness of the reaction layer is different from that of the gate electrode. 4. The method according to claim 1, wherein the metal constituting the metal oxide film is T
4. The field-effect compound semiconductor device according to claim 1, wherein the device is any one of i, Co, Ni, Pd, Ta, Pr, Hf, and Zr. 5. 5. A step of providing a metal film / metal oxide film / metal layer gate electrode on a semiconductor layer and a metal oxide film / metal layer gate electrode, and performing heat treatment on the semiconductor layer and the metal film. A step of forming a reaction layer by reacting the same with each other.