JP2002134656A - Semiconductor device and its inspection method - Google Patents
Semiconductor device and its inspection methodInfo
- Publication number
- JP2002134656A JP2002134656A JP2000324153A JP2000324153A JP2002134656A JP 2002134656 A JP2002134656 A JP 2002134656A JP 2000324153 A JP2000324153 A JP 2000324153A JP 2000324153 A JP2000324153 A JP 2000324153A JP 2002134656 A JP2002134656 A JP 2002134656A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- package substrate
- back surface
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/302—Contactless testing
- G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
- G01R31/311—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子回路が高密度
で集積されている半導体チップ（以下、「ＩＣチップ」
と記す）の不良部分をフォトエミッション解析方法によ
り解析し易くした半導体装置、特に複数個の電極バンプ
がボールグリッドアレイ（ＢＧＡ）形式で形成され、パ
ッケージされている表面実装型半導体装置に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip on which electronic circuits are integrated at a high density (hereinafter referred to as "IC chip").
The present invention relates to a semiconductor device in which a defective portion is easily analyzed by a photoemission analysis method, and more particularly to a surface-mounted semiconductor device in which a plurality of electrode bumps are formed in a ball grid array (BGA) format and packaged. .
【０００２】[0002]
【従来の技術】先ず、図を参照しながら、一般的なＢＧ
Ａパッケージ形式の半導体装置の構造を概念的に説明す
る。2. Description of the Related Art First, a general BG will be described with reference to the drawings.
The structure of an A-package type semiconductor device will be conceptually described.
【０００３】図２はサーマルエンハンスッドＢＧＡパッ
ケージ型半導体装置の断面側面図であり、図３はプラス
チックモールド成形のＢＧＡパッケージ型半導体装置の
断面側面図である。FIG. 2 is a cross-sectional side view of a thermally enhanced BGA package type semiconductor device, and FIG. 3 is a cross-sectional side view of a plastic molded BGA package type semiconductor device.
【０００４】図２に示したサーマルエンハンスッドＢＧ
Ａパッケージ（以下、「Ｅ−ＢＧＡ」と記す）型の半導
体装置（以下、単に「ＩＣ」と記す）２０は、金属基板
２２に貼り合わされたパッケージ基板２３の中央部に開
けられた開口部２４内で前記金属基板２２の裏面に、電
源、接地配線など及び複数の電極（不図示）などが形成
されている面を下向きにして（以下、「フェイスダウ
ン」と記す）ＩＣチップ２１が固定され、前記各電極を
パッケージ基板２３に形成されている電極ランド（不図
示）にワイヤー２７を用いて接続し、封止材２５で封止
された構造のものである。パッケージ基板２３は単層基
板であってもよいが、通常は、多層の積層基板構造のも
ので、その最下層の裏面には半田製ボール状の複数個の
電極バンプ２６が所定のグリッド状配列で形成されてい
る。[0004] The thermal enhanced BG shown in FIG.
An A package (hereinafter, referred to as “E-BGA”) type semiconductor device (hereinafter, simply referred to as “IC”) 20 includes an opening 24 formed in the center of a package substrate 23 bonded to a metal substrate 22. An IC chip 21 is fixed on the back surface of the metal substrate 22 with the surface on which a power supply, a ground wiring, and the like and a plurality of electrodes (not shown) are formed facing downward (hereinafter referred to as “face-down”). Each of the electrodes is connected to an electrode land (not shown) formed on the package substrate 23 using a wire 27 and sealed with a sealing material 25. The package substrate 23 may be a single-layer substrate, but usually has a multi-layer laminated substrate structure, and a plurality of solder ball-shaped electrode bumps 26 are arranged in a predetermined grid pattern on the back surface of the lowermost layer. It is formed with.
【０００５】また、図３に示したプラスチックモールド
成形のＢＧＡパッケージ（以下、「Ｐ−ＢＧＡ」と記
す）型ＩＣ３０は、電極ランド（不図示）などの配線が
施されたパッケージ基板３２上に、電源、接地配線など
及び複数の電極（不図示）などが形成されている面を上
向きにして（以下、「フェイスアップ」と記す）ＩＣチ
ップ３１が固定され、前記各電極をパッケージ基板３２
の各電極ランド（不図示）にワイヤー３３を用いて接続
し、その状態のＩＣチップ３１及びパッケージ基板３２
の電極ランドを含む表面を封止樹脂３４で封止された構
造のものである。パッケージ基板３２もパッケージ基板
２３の構造と同一であって、パッケージ基板３２の最下
層の裏面には複数個の電極バンプ３５が所定のグリッド
状配列で形成されている。A plastic molded BGA package (hereinafter referred to as “P-BGA”) type IC 30 shown in FIG. 3 is provided on a package substrate 32 provided with wiring such as electrode lands (not shown). An IC chip 31 is fixed with a surface on which a power supply, a ground wiring and the like and a plurality of electrodes (not shown) are formed facing upward (hereinafter referred to as “face-up”).
Are connected to the respective electrode lands (not shown) using wires 33, and the IC chip 31 and the package substrate 32 in that state are connected.
The surface including the electrode lands is sealed with a sealing resin. The package substrate 32 has the same structure as that of the package substrate 23. A plurality of electrode bumps 35 are formed in a predetermined grid pattern on the lower surface of the lowermost layer of the package substrate 32.
【０００６】これらＥ−ＢＧＡパッケージ型ＩＣ２０
(以下、単に「ＩＣ２０」と略記する)及びＰ−ＢＧＡパッ
ケージ型ＩＣ３０(以下、単に「ＩＣ３０」と略記する)は
工場で最終的に品質検査されてアセンブルメーカなどの
ユーザーに販売される。そしてユーザーはＩＣ２０或い
はＩＣ３０を基板やテーピングを利用してユーザー側の
電子回路基板に表面実装されるものである。These E-BGA package type ICs 20
(Hereinafter simply abbreviated as “IC20”) and P-BGA package type IC30 (hereinafter simply abbreviated as “IC30”) are finally subjected to quality inspection at a factory and sold to a user such as an assembly maker. The user mounts the IC 20 or IC 30 on the user's electronic circuit board by using a board or taping.
【０００７】ＩＣ２０は、図２に示したように、放熱性
を向上させるために金属基板２２が上でＩＣチップ２１
が下方に向いた姿勢（フェイスダウン）の状態でユーザ
ーの電子回路基板に表面実装され、ＩＣ３０は、図３に
示したように、ＩＣチップ３１がパッケージ基板３２の
上側に存在する姿勢（フェイスアップ）の状態でユーザ
ーの電子回路基板に表面実装される。As shown in FIG. 2, the IC 20 has an IC chip 21 on which a metal substrate 22 is placed to improve heat dissipation.
3 is mounted on the user's electronic circuit board in a posture (face-down) facing downward, and the IC 30 is in a posture (face-up) in which the IC chip 31 exists above the package substrate 32, as shown in FIG. ) Is surface mounted on the user's electronic circuit board in the state of).
【０００８】しかし、これらＩＣ２０或いはＩＣ３０が
実装されてから、中には実装時に実装不良が生じたり、
ＩＣ２０或いはＩＣ３０そのものに潜在していた欠陥が
実装により表面化し、それら不良のＩＣ２０或いはＩＣ
３０は販売した半導体メーカ側に返品されてくる。半導
体メーカ側では、不良の原因を探るために、返品されて
きたＩＣ２０或いはＩＣ３０の不良の原因の解析を行
う。その解析は、通常、フォトエミッション解析方法で
行われる。However, after the IC 20 or the IC 30 is mounted, some of the IC 20 or IC 30 may have a mounting defect during mounting,
Defects latent in the IC 20 or the IC 30 themselves are surfaced by mounting, and these defective ICs 20 or ICs 30
30 is returned to the selling semiconductor manufacturer. The semiconductor manufacturer analyzes the cause of the defect of the returned IC 20 or IC 30 in order to find the cause of the defect. The analysis is usually performed by a photo emission analysis method.
【０００９】フォトエミッション解析方法とは、ＩＣの
不良のモードがラッチアップやジャンクション崩れなど
のＤＣ特性不良の場合にＩＣチップ上での位置を特定す
るための方法であって、ＭＯＳ型ＩＣの場合、正常なト
ランジスタのＰＮジャンクションには電流は殆ど流れな
いが、前記の不良モードになると、このジャンクション
電流が多く流れ、この過剰電流により遠赤外線が発生
し、その遠赤外線を特殊検出器で捕捉して、その不良位
置を特定する方法である。なお、配線部分での金属系の
ショートによる発熱の場合も遠赤外線が放射されるが、
波長の帯域が異なるので解析する場合には、これらの波
長の感度を切り替えて観測する。The photoemission analysis method is a method for specifying a position on an IC chip when an IC failure mode is a DC characteristic failure such as latch-up or junction collapse. Although almost no current flows through the PN junction of a normal transistor, in the above-described failure mode, a large amount of this junction current flows, and this excess current generates far-infrared rays, which are captured by a special detector. This is a method of specifying the defective position. In addition, far-infrared rays are radiated also in the case of heat generation due to a metal short circuit in the wiring part,
When analyzing because the wavelength bands are different, the sensitivities of these wavelengths are switched and observed.
【００１０】前記のように、このフォトエミッション解
析方法は、トランジスタのＰＮジャンクション部分から
の遠赤外線を捉えなければならないため、そのＰＮジャ
ンクション部分の上方に構成されているアルミ配線層が
多層になるほど配線が網目状に複雑に交差しているた
め、ＩＣチップの表面側から観測する場合には、最下層
からの遠赤外線の放射が遮られる。従って、ＩＣチップ
が多層配線構造で形成されていると、ＩＣチップの表面
側からの観測は不可能となる。As described above, in this photoemission analysis method, since far infrared rays from the PN junction of the transistor must be captured, the wiring becomes larger as the number of aluminum wiring layers formed above the PN junction increases. Are complicatedly intersected in a mesh pattern, so that when observing from the surface side of the IC chip, the radiation of far-infrared rays from the lowermost layer is blocked. Therefore, if the IC chip is formed in a multilayer wiring structure, observation from the surface side of the IC chip becomes impossible.
【００１１】しかし、この遠赤外線はバルクのシリコン
を通過することができるので、配線層側とは反対側のＩ
Ｃチップ裏面から遠赤外線を観測することになる。However, since this far infrared ray can pass through the bulk silicon, the far infrared ray is located on the side opposite to the wiring layer side.
Far infrared rays will be observed from the back of the C chip.
【００１２】不良ＩＣを解析する時には、通常のＩＣチ
ップの動作モードになるように電源を印加し、特定し易
いタイミングにホールドした状態にして解析する。When analyzing a defective IC, power is applied so as to be in a normal operation mode of the IC chip, and analysis is performed in a state where the IC is held at a timing that is easy to specify.
【００１３】従って、ＩＣ２０の場合は、金属基板２２
をカットしても放熱性に若干影響はあるが、ＩＣチップ
２１の動作は無関係であることから、ＩＣチップ２１が
存在する部分の金属基板２２を機械的にカットすること
によって遠赤外線の放射を観測することができる。Therefore, in the case of the IC 20, the metal substrate 22
Although the heat radiation property is slightly affected even if the IC chip 21 is cut off, the radiation of the far-infrared ray can be reduced by mechanically cutting the metal substrate 22 where the IC chip 21 exists. Can be observed.
【００１４】なお、通常のクワッドフラットパッケージ
（ＱＦＰ）型ＩＣはＩＣチップがフェイスアップボンデ
ィングで構成されているが、裏面からモールドを削り、
最後にリードフレームを削ってＩＣチップの裏面を露出
させる（このリードフレームには通常は有効となる信号
配線はない）。Incidentally, a normal quad flat package (QFP) type IC has an IC chip formed by face-up bonding.
Finally, the lead frame is shaved to expose the back surface of the IC chip (this lead frame has no signal wiring which is normally effective).
【００１５】[0015]
【発明が解決しようとする課題】しかし、ＩＣ３０の場
合は、ＩＣチップ３１の上方の封止樹脂３４を削り、Ｉ
Ｃチップ３１を露出させることは可能であるが、電源層
がＩＣチップ３１の表面に施されていることから特殊な
薬品で電源配線部分を削除しなければならず、これを行
うと電源配線部分のインピーダンスが増大したり、必要
な部分を削除してしまうなどの問題が生じ、実際に動作
しなくなる場合がある。また、前記のように、封止樹脂
３４側からの遠赤外線の観測は、ＩＣチップ３１のＰＮ
ジャンクションの上方部分にアルミ配線が各層で形成さ
れ、封止樹脂３４側から見た場合に全体として網目状に
複雑に交差して見えることから遠赤外線は遮断されてし
まい、フォトエミッションによる解析は不可能となる。However, in the case of the IC 30, the sealing resin 34 above the IC chip 31 is cut off,
Although it is possible to expose the C chip 31, since the power supply layer is provided on the surface of the IC chip 31, the power supply wiring must be removed with a special chemical. In some cases, problems such as an increase in the impedance of the device or deletion of a necessary portion may occur, and the device may not actually operate. As described above, the observation of the far-infrared ray from the sealing resin 34 side is based on the PN of the IC chip 31.
Aluminum wiring is formed in each layer above the junction, and when viewed from the side of the sealing resin 34, it looks as if it crosses in a complex network as a whole, so far infrared rays are blocked, and analysis by photoemission is not possible. It becomes possible.
【００１６】一方、封止樹脂３４の裏側（下側）から遠
赤外線の観測を行おうとすると、ＩＣチップ３１はその
全面がパッケージ基板３２に覆われているため、そのＩ
Ｃチップが実装されているであろうパッケージ基板３２
の中央部分を切り取らねばならない。パッケージ基板３
２には当然のことながら配線パターンが無数に走つてお
り、簡単にカットにより削除することはできない。削除
しても動作が可能となるように、ＩＣチップ３１の下方
部分に予め配線パターンを施さないように配線を施すよ
うにしておいてもよいが、この部分をパターン配線に使
用できないので無駄が多くなる。配線パターンを出来る
だけ有効利用できるように配線設計した場合に、パッケ
ージ基板３２の削除する面積を最小限に抑え、正確にＩ
Ｃチップ３１の全面が露出するように削除しなければな
らないが、通常では内部実装されたＩＣチップの位置を
外から把握するのは困難である。On the other hand, when observing far-infrared rays from the back side (lower side) of the sealing resin 34, the IC chip 31 is covered with the package substrate 32 over its entire surface.
Package substrate 32 on which C chip will be mounted
The central part of must be cut off. Package substrate 3
Naturally, the wiring pattern 2 runs innumerably and cannot be easily deleted by cutting. Wiring may be performed beforehand on the lower part of the IC chip 31 so that the wiring pattern is not formed so that the operation can be performed even if the wiring is deleted. However, since this part cannot be used for pattern wiring, there is no waste. More. When the wiring pattern is designed so that the wiring pattern can be used as effectively as possible, the area to be removed from the package substrate 32 is minimized and the I
The C chip 31 must be removed so that the entire surface is exposed, but it is usually difficult to grasp the position of the internally mounted IC chip from outside.
【００１７】従って、本発明はこのような課題を解決し
ようとするものであって、ＩＣチップの上層配線部分な
どを加工することなくフォトエミッション解析を行うこ
とができる半導体装置及びその検査方法を得ることを目
的とするものである。Accordingly, the present invention is to solve such a problem, and provides a semiconductor device capable of performing photoemission analysis without processing an upper wiring portion of an IC chip and a method of inspecting the semiconductor device. The purpose is to do so.
【００１８】[0018]
【課題を解決するための手段】それ故、請求項１に記載
の発明では、表面には複数本の電極ランド、配線などの
配線パターンが、裏面には前記配線パターンに対応して
複数個の電極バンプが形成されているパッケージ基板の
前記表面にフェイスアップで電子回路が集積されている
半導体チップを搭載、固定し、該半導体チップを封止部
材で封止した構造で構成されている半導体装置におい
て、前記パッケージ基板の前記裏面に、前記半導体チッ
プの位置を示す表示を付して、前記課題を解決してい
る。Therefore, according to the first aspect of the present invention, a plurality of wiring patterns such as electrode lands and wirings are provided on the front surface, and a plurality of wiring patterns corresponding to the wiring patterns are provided on the back surface. A semiconductor device having a structure in which a semiconductor chip in which electronic circuits are integrated face-up is mounted and fixed on the surface of a package substrate on which electrode bumps are formed, and the semiconductor chip is sealed with a sealing member. In order to solve the above-mentioned problem, the back surface of the package substrate is provided with a display indicating a position of the semiconductor chip.
【００１９】そして請求項２に記載の発明では、請求項
１に記載の半導体装置における前記表示が、その半導体
装置をフォトエミッション解析方法により不良原因の解
析を行う場合に、前記パッケージ基板の裏面を除去して
開口を開けるための目印であることを特徴とする。ま
た、請求項３に記載の発明では、請求項１に記載の半導
体装置における前記表示が、前記パッケージ基板の前記
配線パターンを形成するエッチング工程でエッチングに
より形成されることを特徴とする。According to the second aspect of the present invention, the display in the semiconductor device according to the first aspect is such that when the semiconductor device is analyzed for a cause of failure by a photoemission analysis method, the back surface of the package substrate is analyzed. It is a mark for removing and opening an opening. According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the display is formed by etching in an etching step of forming the wiring pattern on the package substrate.
【００２０】更に、請求項４に記載の発明では、表面に
は複数本の電極ランド、配線などの配線パターンが、裏
面には前記配線パターンに対応して複数個の電極バンプ
が形成されているパッケージ基板の前記表面にフェイス
アップで電子回路が集積されている半導体チップを搭
載、固定し、該半導体チップを封止部材で封止し、前記
パッケージ基板の前記裏面に、前記半導体チップの位置
を示す表示が付されている半導体装置の前記表示で囲ま
れた面積部分のパッケージ基板を除去して、前記半導体
チップの裏面を開口、露出させ、該半導体チップの裏面
が露出された半導体装置を検査回路基板に装着して該半
導体チップに通電し、該通電により前記半導体チップの
不良部分で発光する遠赤外線を前記開口から放出させ、
該放出された遠赤外線を遠赤外線検出装置で検出してフ
ォトエミッション解析方法により前記不良部分を解析す
る方法を採って、前記課題を解決している。Further, according to the present invention, a plurality of wiring patterns such as a plurality of electrode lands and wirings are formed on the front surface, and a plurality of electrode bumps are formed on the back surface corresponding to the wiring patterns. A semiconductor chip in which electronic circuits are integrated face-up on the surface of the package substrate is mounted and fixed, the semiconductor chip is sealed with a sealing member, and the position of the semiconductor chip is located on the back surface of the package substrate. The package substrate in the area surrounded by the display of the semiconductor device to which the display shown is attached is removed, the back surface of the semiconductor chip is opened and exposed, and the semiconductor device in which the back surface of the semiconductor chip is exposed is inspected. The semiconductor chip is energized by being mounted on a circuit board, and far-infrared rays emitted at a defective portion of the semiconductor chip are emitted from the opening by the energization,
The above problem is solved by adopting a method of detecting the emitted far-infrared ray with a far-infrared ray detecting device and analyzing the defective portion by a photo emission analysis method.
【００２１】それ故、本発明によれば、コストを掛ける
ことなく、除去すべきパッケージ基板の半導体チップが
存在する領域を容易に把握でき、半導体チップの機能を
損なうことなく除去して開口部を開けることができ、フ
ォトエミッション解析方法により容易に不良個所の検査
及び解析を行うことができる。Therefore, according to the present invention, the region where the semiconductor chip is present on the package substrate to be removed can be easily grasped without increasing the cost, and the opening can be removed without impairing the function of the semiconductor chip. It can be opened, and the inspection and analysis of the defective portion can be easily performed by the photo emission analysis method.
【００２２】[0022]
【発明の実施の形態】以下、図１を用いて、本発明の一
実施形態の半導体装置及びその検査方法を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention and an inspection method thereof will be described below with reference to FIG.
【００２３】図１は本発明の一実施形態の半導体装置を
概念的に示していて、同図Ａはその裏面から見た平面図
であり、同図Ｂは同図ＡのＡ―Ａ線上における断面側面
図である。FIG. 1 conceptually shows a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view as viewed from the back surface, and FIG. 1B is a sectional view taken on line AA of FIG. It is sectional side view.
【００２４】なお、本発明においても、従来の半導体装
置（Ｐ−ＢＧＡ型ＩＣ３０）、その構造を流用し、その
半導体装置とフォトエミッション解析に用いた用語を用
いて説明する。In the present invention, the conventional semiconductor device (P-BGA type IC 30), the structure of which is diverted, will be described using the semiconductor device and terms used in photoemission analysis.
【００２５】図１において、符号１０は全体として本発
明の半導体装置であるＰ−ＢＧＡ型パッケージＩＣ(以
下、単に「ＩＣ」と略記する)を指す。このＩＣ１０の構造
も、ＩＣ３０の構造と同様に、電極ランド（不図示）な
どの配線が施されたパッケージ基板１２上に、電源、接
地配線など及び複数の電極（不図示）などが形成されて
いる面を上向きにして（以下、「フェイスアップ」と記
す）ＩＣチップ１１が固定され、前記各電極をパッケー
ジ基板１２の各電極ランド（不図示）にワイヤー１３を
用いて接続し、その状態のＩＣチップ１１及びパッケー
ジ基板１２の電極ランドを含む表面を封止樹脂１４で封
止された構造のものである。パッケージ基板１２の最下
層の裏面には半田製ボール状の複数個の電極バンプ１５
が所定のグリッド状配列で形成されている。In FIG. 1, reference numeral 10 indicates a P-BGA type package IC (hereinafter simply abbreviated as “IC”) which is a semiconductor device of the present invention as a whole. Similarly to the structure of the IC 30, the structure of the IC 10 is such that a power supply, a ground wiring, and a plurality of electrodes (not shown) are formed on a package substrate 12 on which wiring such as electrode lands (not shown) is provided. The IC chip 11 is fixed with its surface facing upward (hereinafter referred to as “face-up”), and the respective electrodes are connected to respective electrode lands (not shown) of the package substrate 12 using wires 13. It has a structure in which the surfaces including the electrode lands of the IC chip 11 and the package substrate 12 are sealed with a sealing resin 14. A plurality of solder ball-shaped electrode bumps 15 are formed on the back surface of the lowermost layer of the package substrate 12.
Are formed in a predetermined grid-like arrangement.
【００２６】本ＩＣ１０には、図１Ａに示したように、
そのパッケージ基板１２の裏面１２Ａに、ＩＣチップ１
１の四隅の位置を示す表示１６を付した。この表示１６
は裏面１２Ａから中に封止されているＩＣチップ１１の
全面積が判り、切削などで除去する必要のあるパッケー
ジ基板１２の面積がどの範囲かを明示する。図示の実施
例では、表示１６は四隅に施したが、表示する範囲の全
周を実線、破線などで囲うようにして表示してもよい。This IC 10 has, as shown in FIG.
The IC chip 1 is provided on the back surface 12A of the package substrate 12.
Indications 16 indicating the positions of the four corners 1 are attached. This display 16
Indicates the entire area of the IC chip 11 sealed therein from the back surface 12A, and specifies the range of the area of the package substrate 12 that needs to be removed by cutting or the like. In the illustrated embodiment, the display 16 is provided at the four corners. However, the display 16 may be displayed such that the entire periphery of the display range is surrounded by a solid line, a broken line, or the like.
【００２７】そしてこの表示１６はシルク印刷等で付し
てもよいが、パッケージ基板１２の配線パターンを形成
するエッチング工程で同時に直接エッチングして付すこ
とにより工程を削減でき、コストを掛けず製作すること
ができる。The display 16 may be provided by silk printing or the like. However, since the display 16 is directly etched simultaneously with the etching step for forming the wiring pattern of the package substrate 12, the number of steps can be reduced, and the display 16 can be manufactured without cost. be able to.
【００２８】本発明のＩＣ１０のパッケージ基板１２を
設計する場合に、ＩＣチップ１１の実装部分とその周辺
部分以外で基本のパターン配線を行い、ＩＣチップ１１
の実装部直下には、放熱用のランド、電源強化用のパタ
ーン配線、及びＩＣテスト用の実動作に無関係の信号線
の一部を配線するに止める。When designing the package substrate 12 of the IC 10 of the present invention, basic pattern wiring is performed except for the mounting portion of the IC chip 11 and its peripheral portion, and
Immediately below the mounting portion, only lands for heat radiation, pattern wiring for power supply reinforcement, and a part of signal lines irrelevant to actual operation for IC test are arranged.
【００２９】ＩＣチップ１１位置は、パッケージ基板１
２が、例えば、４層基板であれば、４層基板のパターン
重ね合わせの精度で最上層に実装するＩＣの位置と最下
層の表示１６の位置を印すことが可能である。The position of the IC chip 11 is
If 2 is a four-layer board, for example, it is possible to mark the position of the IC mounted on the uppermost layer and the position of the display 16 on the lowermost layer with the accuracy of pattern superposition of the four-layer board.
【００３０】前記のような表示１６を付すことにより、
作業者はパッケージ基板１２の四隅の表示１６を繋ぎ合
わせた領域部分（四隅の表示１６で囲んだ斜線を施した
面積部分１６Ａ）を除去し、その裏面１２Ａから内部の
ＩＣチップ１１の場所を全て露出させるための確認を容
易にでき、基板パターンの削除過多による誤作動等の問
題を生じさせることなく、その必要最低限の面積部分を
除去することが可能となる。次に、ＩＣ１０の不良部分
を前記のフォトエミッション解析により検査する場合に
は、前記の要領でパッケージ基板１２に開口（図１Ａの
斜線部分１６Ａ）を開け、開口が開けられたＩＣ１０を
テスト基板（不図示）に装着し、通常のＩＣ１０の動作
モードになるように電源を印加し、テストパターンを流
し、特定し易いタイミングにホールドした状態にする。
この電源の印加及びテストパターンの入力により、前記
のように不良部分で遠赤外線が放射され、これを検出し
てフォトエミッション解析を行うことにより不良の種類
を特定することができる。By attaching the display 16 as described above,
The operator removes the area (the hatched area 16A surrounded by the four corners 16) of the package board 12 and connects the four corners 16 to the entire area of the IC chip 11 from the rear surface 12A. Confirmation for exposure can be easily performed, and a necessary minimum area can be removed without causing a problem such as malfunction due to excessive deletion of the substrate pattern. Next, when inspecting the defective portion of the IC 10 by the above-described photoemission analysis, an opening (the hatched portion 16A in FIG. 1A) is opened in the package substrate 12 in the manner described above, and the IC 10 having the opening is connected to the test substrate ( (Not shown), power is applied so as to be in the normal operation mode of the IC 10, a test pattern is flown, and the state is held at a timing that is easy to specify.
By the application of the power supply and the input of the test pattern, far-infrared rays are radiated at the defective portion as described above, and the type of the defect can be specified by detecting this and performing photoemission analysis.
【００３１】[0031]
【発明の効果】以上説明したように、本発明によれば、 １．検査するＩＣのパッケージ基板の削除すべき領域を
簡単に把握でき、加工が容易 ２．パッケージ基板を削除しても、基本動作を行わすこ
とが可能 ３．以上の事柄からフォトエミッション解析が容易 ４．パッケージ基板の除去半導体ウェーハ部分を示す表
示を付す場合に、パターン配線のエッチングと同時に行
えば、製作コストの追加は不要 ５．ＩＣチップの最上層配線等を加工することなく実現
可能 など、数々の優れた効果が得られる。As described above, according to the present invention, there are provided: 1. The area to be deleted of the package substrate of the IC to be inspected can be easily grasped and processing is easy. 2. Basic operation can be performed even if the package substrate is deleted. 3. From the above, photo emission analysis is easy. 4. When a mark indicating the semiconductor wafer portion removed from the package substrate is added, if the pattern wiring is etched simultaneously, no additional manufacturing cost is required. Numerous excellent effects can be obtained, such as realization without processing the top layer wiring of the IC chip.
【図面の簡単な説明】[Brief description of the drawings]
【図１】 本発明の一実施形態の半導体装置を概念的に
示していて、同図Ａはその裏面から見た平面図であり、
同図Ｂは同図ＡのＡ―Ａ線上における断面側面図であ
る。FIG. 1 conceptually shows a semiconductor device according to an embodiment of the present invention, and FIG. 1A is a plan view seen from the back surface thereof;
FIG. B is a cross-sectional side view taken along line AA of FIG.
【図２】 サーマルエンハンスッドＢＧＡパッケージ型
半導体装置の断面側面図である。FIG. 2 is a cross-sectional side view of a thermal enhanced BGA package type semiconductor device.
【図３】 プラスチックモールド成形のＢＧＡパッケー
ジ型半導体装置の断面側面図である。FIG. 3 is a sectional side view of a plastic molded BGA package type semiconductor device.
１０…本発明の一実施形態のＰ−ＢＧＡ型ＩＣ、１１…
ＩＣチップ、１２…パッケージ基板、１２ａ…パッケー
ジ基板１２の裏面、１３…ワイヤー、１４…封止樹脂、
１５…電極バンプ、１６…表示、１６Ａ…除去部分10 ... P-BGA type IC of one embodiment of the present invention, 11 ...
IC chip, 12: package substrate, 12a: back surface of package substrate 12, 13: wire, 14: sealing resin,
15 ... electrode bump, 16 ... display, 16A ... removed part
Claims (4)
の配線パターンが、裏面には前記配線パターンに対応し
て複数個の電極バンプが形成されているパッケージ基板
の前記表面にフェイスアップで電子回路が集積されてい
る半導体チップを搭載、固定し、該半導体チップを封止
部材で封止した構造で構成されている半導体装置におい
て、 前記パッケージ基板の前記裏面に、前記半導体チップの
位置を示す表示が付されていることを特徴とする半導体
装置。1. A surface of a package substrate on which a plurality of electrode lands and a wiring pattern such as wiring are formed on a front surface, and a plurality of electrode bumps corresponding to the wiring pattern are formed on a back surface in a face-up manner. In a semiconductor device having a structure in which a semiconductor chip on which an electronic circuit is integrated is mounted and fixed, and the semiconductor chip is sealed with a sealing member, the position of the semiconductor chip is located on the back surface of the package substrate. A semiconductor device, characterized by being provided with an indication shown.
ミッション解析方法により不良原因の解析を行う場合
に、前記パッケージ基板の裏面を除去して開口を開ける
場合の目印であることを特徴とする請求項１に記載の半
導体装置。2. The display device according to claim 1, wherein when the semiconductor device is analyzed for a cause of a defect by a photoemission analysis method, an opening is formed by removing a back surface of the package substrate. Item 2. The semiconductor device according to item 1.
線パターンを形成するエッチング工程でエッチングによ
り形成されることを特徴とする請求項１に記載の半導体
装置。3. The semiconductor device according to claim 1, wherein the display is formed by etching in an etching step of forming the wiring pattern on the package substrate.
の配線パターンが、裏面には前記配線パターンに対応し
て複数個の電極バンプが形成されているパッケージ基板
の前記表面にフェイスアップで電子回路が集積されてい
る半導体チップを搭載、固定し、該半導体チップを封止
部材で封止し、前記パッケージ基板の前記裏面に、前記
半導体チップの位置を示す表示が付されている半導体装
置の前記表示で囲まれた面積部分のパッケージ基板を除
去して、前記半導体チップの裏面を開口、露出させ、該
半導体チップの裏面が露出された半導体装置を検査回路
基板に装着して該半導体チップに通電し、該通電により
前記半導体チップの不良部分で発光する遠赤外線を前記
開口から放出させ、該放出された遠赤外線を遠赤外線検
出装置で検出してフォトエミッション解析方法により前
記不良部分を解析することを特徴とする半導体装置の検
査方法。4. A wiring pattern such as a plurality of electrode lands and wirings is formed on a front surface, and a plurality of electrode bumps are formed on a back surface of the package substrate having a plurality of electrode bumps corresponding to the wiring pattern. A semiconductor device in which a semiconductor chip on which an electronic circuit is integrated is mounted and fixed, the semiconductor chip is sealed with a sealing member, and a display indicating the position of the semiconductor chip is provided on the back surface of the package substrate. Removing the package substrate in the area surrounded by the display, opening and exposing the back surface of the semiconductor chip, and mounting the semiconductor device having the exposed back surface of the semiconductor chip on an inspection circuit board; Through the opening, and emits far-infrared rays emitted from the defective portion of the semiconductor chip through the opening. A method for inspecting a semiconductor device, wherein the defective portion is analyzed by a photo emission analysis method.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000324153A JP4407785B2 (en) | 2000-10-24 | 2000-10-24 | Semiconductor device and inspection method thereof |
| US09/983,253 US6818986B2 (en) | 2000-10-24 | 2001-10-23 | Semiconductor device and method of inspecting the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000324153A JP4407785B2 (en) | 2000-10-24 | 2000-10-24 | Semiconductor device and inspection method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002134656A true JP2002134656A (en) | 2002-05-10 |
| JP4407785B2 JP4407785B2 (en) | 2010-02-03 |
Family
ID=18801729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000324153A Expired - Fee Related JP4407785B2 (en) | 2000-10-24 | 2000-10-24 | Semiconductor device and inspection method thereof |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6818986B2 (en) |
| JP (1) | JP4407785B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100407878C (en) * | 2003-05-21 | 2008-07-30 | 华为技术有限公司 | Method and apparatus for examining uniformity |
| CN100446638C (en) * | 2006-08-25 | 2008-12-24 | 华为技术有限公司 | Method and system for creating B side and T side detailed list of veneer |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100546698B1 (en) * | 2003-07-04 | 2006-01-26 | 앰코 테크놀로지 코리아 주식회사 | Substrate for semiconductor package |
| GB2432967A (en) * | 2005-11-30 | 2007-06-06 | Unity Opto Technology Co Ltd | White light LED with fluorescent powder containing wavelength converting plate |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6233434A (en) * | 1985-08-07 | 1987-02-13 | Nec Corp | Integrated circuit |
| EP0312217A1 (en) * | 1987-09-30 | 1989-04-19 | AT&T Corp. | Integrated circuit chip assembly |
| US4893163A (en) * | 1988-03-28 | 1990-01-09 | International Business Machines Corporation | Alignment mark system for electron beam/optical mixed lithography |
| US4949148A (en) * | 1989-01-11 | 1990-08-14 | Bartelink Dirk J | Self-aligning integrated circuit assembly |
| US5834799A (en) * | 1989-08-28 | 1998-11-10 | Lsi Logic | Optically transmissive preformed planar structures |
| EP0630058A3 (en) * | 1993-05-19 | 1995-03-15 | Siemens Ag | Process for forming an arrangement of pyrodetectors by electrochemically etching a silicon substrate. |
| FR2715002B1 (en) * | 1994-01-07 | 1996-02-16 | Commissariat Energie Atomique | Electromagnetic radiation detector and its manufacturing process. |
| JP3634505B2 (en) * | 1996-05-29 | 2005-03-30 | 株式会社ルネサステクノロジ | Alignment mark placement method |
| US6246098B1 (en) * | 1996-12-31 | 2001-06-12 | Intel Corporation | Apparatus for reducing reflections off the surface of a semiconductor surface |
| KR100223826B1 (en) * | 1997-06-04 | 1999-10-15 | 구본준 | Method of manufacturing ccd |
| US5972725A (en) * | 1997-12-11 | 1999-10-26 | Advanced Micro Devices, Inc. | Device analysis for face down chip |
| JPH11233684A (en) * | 1998-02-17 | 1999-08-27 | Seiko Epson Corp | Semiconductor device, substrate therefor, manufacture thereof and electronic device |
| JP3597392B2 (en) * | 1998-08-07 | 2004-12-08 | シャープ株式会社 | 2D image detector |
| US6329212B1 (en) * | 1999-01-08 | 2001-12-11 | Advanced Micro Devices, Inc. | Process for exposing for analysis the back side of a semiconductor die mounted in a package |
| US6096568A (en) * | 1999-01-08 | 2000-08-01 | Advanced Micro Devices | Process for preparing a semiconductor device package for analysis of a die |
-
2000
- 2000-10-24 JP JP2000324153A patent/JP4407785B2/en not_active Expired - Fee Related
-
2001
- 2001-10-23 US US09/983,253 patent/US6818986B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100407878C (en) * | 2003-05-21 | 2008-07-30 | 华为技术有限公司 | Method and apparatus for examining uniformity |
| CN100446638C (en) * | 2006-08-25 | 2008-12-24 | 华为技术有限公司 | Method and system for creating B side and T side detailed list of veneer |
Also Published As
| Publication number | Publication date |
|---|---|
| US20020063250A1 (en) | 2002-05-30 |
| JP4407785B2 (en) | 2010-02-03 |
| US6818986B2 (en) | 2004-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5160498B2 (en) | Semiconductor device | |
| US20030143777A1 (en) | Super thin/super thermal ball grid array package | |
| US20010015009A1 (en) | Method of fabricating semiconductor package | |
| KR19980047801A (en) | Wafer level chip scale package and its manufacturing method | |
| JPS61111561A (en) | Semiconductor device | |
| JP3512169B2 (en) | Multi-chip semiconductor module and manufacturing method thereof | |
| JPH05129366A (en) | Tab mounting structure for integrated circuit use | |
| JP2004056135A (en) | Folded tape area array package having one metal layer | |
| JP4407785B2 (en) | Semiconductor device and inspection method thereof | |
| JP2004289156A (en) | Recessed bonded semiconductor package substrate | |
| JPH1012809A (en) | Multichip module | |
| WO2017088286A1 (en) | Flip chip package structure of flip chip, and flip chip | |
| JP5732493B2 (en) | Semiconductor device | |
| JP2003229533A (en) | Semiconductor device and method for manufacturing same | |
| WO2003039974A2 (en) | Package enclosing multiple packaged chips | |
| JP5885332B2 (en) | Manufacturing method of semiconductor device | |
| KR20080000879A (en) | Ball grid array semiconductor chip package and testing method of the same | |
| JPS6220707B2 (en) | ||
| KR102443830B1 (en) | Method of routing electrical wiring and its structure | |
| TWI250655B (en) | Wafer level package structure of image sensor and method for making the same | |
| TW455978B (en) | Method for testing wafers | |
| US20040128830A1 (en) | Mapable tape apply for LOC and BOC packages | |
| JP2004296464A (en) | Semiconductor device | |
| JPH01155637A (en) | Multichip module | |
| JP5331934B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061229 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080811 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090729 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090925 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20091021 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091103 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121120 Year of fee payment: 3 |
|
| LAPS | Cancellation because of no payment of annual fees |