JP2002131396A - Method and device for testing semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and device for testing semiconductor capable of reducing the test pattern storage media cost and the communication cost in the transmission of a test pattern and shortening the time of a test pattern. SOLUTION: This method comprises forming only the change portion from the previous pattern vector into a file, paying attention to a test pattern used for a semiconductor test every pattern vector, to compress the test pattern file. This device is provided with a compression means for forming only the change portion from the previous pattern, while paying attention to a test pattern file used for a semiconductor test every pattern vector, to compress the test pattern file, and a memory means for storing the test pattern file compressed by the compression means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test method and apparatus, and more particularly, to a method of compressing a test pattern used for testing a semiconductor and a semiconductor test apparatus using the method.

[0002]

2. Description of the Related Art Generally, a semiconductor test apparatus (hereinafter, referred to as a test apparatus) generates an input / output pattern when testing a semiconductor. A test pattern file serving as original data for generating this pattern is loaded into a test pattern memory of a test apparatus before a test. Conventionally, this test pattern file has a format depending on the H / W configuration of the test pattern memory of the test apparatus, and its capacity is determined by the number of run bits (number of vectors) of the pattern.
And it depends on the number of pins.

[0003]

In the conventional semiconductor test apparatus, the load time of the test pattern file on the test apparatus increases due to the increase in the capacity of the test pattern file due to the complexity of the semiconductor and the increase in the number of pins. In addition, there has been a problem that the amount of media used for storing a test pattern file such as an HDD increases, and that the transmission communication load of the test pattern file increases.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and is intended to convert only a change in a pattern into data without depending on the number of vectors and pins of the pattern. To provide a semiconductor test method and a semiconductor test apparatus which realizes compression of a test pattern file and minimizes the overhead of data expansion at the time of loading, in which an H / W configuration is also an element for optimizing compression. With the goal.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor test method which focuses on a test pattern file used for a semiconductor test for each pattern vector, and converts only a change from the previous pattern vector into a file. To compress the test pattern file.

According to a second aspect of the present invention, there is provided a semiconductor testing method comprising:
In the invention of claim 1, when the test pattern file is compressed, a block size of data included in the test pattern file is changed, and the changed block size is compared with a test pattern file before compression to change the block size. Number, extract the compressed test pattern file size including the changed block number, select the block size that has become the minimum test pattern file size after compression, and select the minimum test pattern file size after compression and the above The size of the test pattern file before compression is compared, and the quality of the selected block size is determined based on the comparison result.

According to a third aspect of the present invention, there is provided a semiconductor test method comprising:
According to the first aspect of the present invention, a block size of data included in the test pattern file when the test pattern file is compressed is optimized in consideration of a configuration of a semiconductor test apparatus.

According to a fourth aspect of the present invention, there is provided a semiconductor testing method comprising:
In the invention according to claim 3, when compressing the test pattern file, a candidate of a block size of data included in the test pattern file is designated, the candidate block size is changed, and the changed block size is compressed. The number of changed blocks is extracted by comparing with the previous test pattern file, the size of the compressed test pattern file including the number of changed blocks is calculated, and the block size that is the minimum test pattern file size after compression is selected,
The minimum test pattern file size after compression is compared with the size of the test pattern file before compression, and the quality of the selected block size is determined based on the comparison result.

According to a fifth aspect of the present invention, there is provided a semiconductor test method comprising:
In the invention according to claim 2 or 4, the determination of the pass / fail of the block size based on the comparison result is performed when the minimum test pattern file size after compression is smaller than the size of the test pattern file before compression. The block size is determined as the optimum block size, and if it is large, the compression is not suitable.

A semiconductor test method according to a sixth aspect of the present invention is
In the invention according to claim 4, the candidate block size is selected in consideration of a bus width to a storage unit in which the test pattern file is stored.

A semiconductor test method according to a seventh aspect of the present invention is
The invention according to any one of claims 1 to 6, wherein the test pattern of the compressed test pattern file is transferred to another location via a communication medium.

[0012] The semiconductor test method according to the invention of claim 8 is as follows.
The invention according to any one of claims 1 to 7, wherein a disk cache is used for data transfer of the test pattern file.

According to a ninth aspect of the present invention, there is provided a semiconductor test apparatus comprising:
A compression means for focusing on a test pattern file used for semiconductor testing for each pattern vector, compressing only the change from the previous pattern vector and compressing the test pattern file, and a test compressed by the compression means. Storage means for storing a pattern file, wherein a test of the semiconductor device to be measured is performed using the compressed test pattern file.

A semiconductor test apparatus according to a tenth aspect of the present invention is the semiconductor test apparatus according to the ninth aspect, further comprising an HDD functioning as a disk cache for performing high-speed data transfer of the test pattern file.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described.
This will be described with reference to the drawings. Embodiment 1 FIG. FIG. 1 is a configuration diagram showing Embodiment 1 of the present invention. In the figure, 1 is a host engineering workstation (hereinafter, referred to as a host EWS), 2 is a disk drive device (hereinafter, referred to as an HDD) of the host EWS 1, and 3 is a host EWS via a LAN.
The test equipment control EWS 4 connected to the test equipment control EWS 3 is connected to the test equipment control EWS 3 and functions as a disk cache for performing high-speed data transfer. The test pattern 5 is connected to the test equipment control EWS 3. The memory 6 is a semiconductor to be measured.

Next, the operation will be described. In order to execute a test of the semiconductor 6 to be measured, a test pattern is loaded from the HDD 2 of the host EWS 1 to the test pattern memory 5 via the LAN and the test equipment control EWS 3 via the LAN. Then, under the control of the test equipment control EWS 3, an input pattern (test pattern) is generated from the test pattern memory 5 for the semiconductor 6 to be measured, and an expected output pattern is generated for the determination device (not shown). You. The measurement result from the semiconductor 6 to be measured is supplied to a determination device, and is compared and determined with an expected output pattern. Normally, the pattern loaded once is the HDD of the test equipment control EWS3.
4 and operates as a disk cache at the next loading.

FIG. 2 is a view showing binary data of a test pattern file stored in the test pattern memory 5. The capacity of one vector depends on the number of pins (horizontal direction) used for the test and is fixed. That is, the number of bits of 1-pin data depends on the test apparatus. The capacity of the entire test pattern file is the product of the capacity of one vector and the number of vectors (vertical direction). In the present embodiment, compression of the test pattern file (compression means) is realized by, for example, making only the changed data from the immediately preceding vector into a file, instead of putting all the data of one vector into a file.
Bits enclosed by squares in FIG. 2 show an example of data changed from the immediately preceding vector as an example.

FIG. 3 is a diagram showing the format of one vector of compressed data. The capacity of one vector is variable,
The configuration includes, at the beginning, the “number of changed blocks” in the vector, “changed block numbers” for the number of changed blocks, and “changed block data”. The bit size of the “number of changed blocks” and “changed block number” is the maximum block number. Is the size that can be expressed.

The maximum block number. Is the maximum number of pins of the test apparatus / block size. Therefore, since the maximum number of pins of the test apparatus is fixed, when the block size, that is, the changed block data is reduced, the maximum block No. Is larger, the “changed block data” portion is smaller, but the “number of changed blocks” and “changed block No.” are larger. Conversely, if the block size is increased, the maximum block No. Becomes smaller, the “changed block data” part becomes larger, but the “number of changed blocks” and “changed block N”
o. "becomes smaller. Efficient compression is performed by setting an optimal block size.

FIG. 4 is a diagram showing the relationship between the number of test vectors according to the number of compressed blocks in the test pattern and the test pattern file capacity. If the number of compressed blocks is large, the capacity of the test pattern file before compression becomes larger, and compression is unsuitable. If it is applied to the shaded portion in the figure, it will be compressed. That is, the hatched portion in the figure is the effective compression area.

FIG. 5 is a diagram showing the relationship between the number of pins changed from the previous vector and the compression ratio depending on the block size. When the number of changed pins is small, the smaller block size has a higher compression ratio than the larger one, but as the number of changed pins increases, the probability that the changed pin is included in the same block increases.
A larger block size has a higher compression ratio than a smaller block size. Therefore, it is necessary to optimize the block size for efficient compression.

FIG. 6 is a flowchart of the block size determination focusing on the test pattern file size after compression. Next, the optimization algorithm for compression of the test pattern file will be described with reference to FIG.
First, the block size of the data in the test pattern file is changed from 1 bit (pin 1) to MAX pin / 2 (step S1), and the changed block size is compared with the test pattern file before compression to determine the number of changed blocks. Extraction is performed (steps S2 and S3), and a compressed test pattern file size including the number of changed blocks is calculated, and the calculated value is stored in a buffer (step S4).

After the calculation is completed, that is, after confirming the completion of the block size (step S5), a block size having the minimum test pattern file size after compression is selected (step S6). Then, it is determined whether or not the minimum test pattern file size after compression is smaller than the size of the original test pattern file, that is, the size of the test pattern file before compression (step S7). Is determined as the optimal block size (step S8), and if the block size is large, the compression is not suitable (step S8).
9).

As described above, in this embodiment, the test pattern file used for the semiconductor test is focused on for each pattern vector, and only the change from the previous vector is converted into data, thereby compressing the test pattern file. As a result, the cost of the test pattern storage medium can be reduced, the communication cost for transmitting the test pattern can be reduced, and the time for the test pattern can be reduced.

Embodiment 2 FIG. 7 is a flowchart for determining a block size in consideration of the H / W configuration of the test apparatus according to Embodiment 2 of the present invention. Note that the circuit configuration may be the same as that of the first embodiment. In the first embodiment, when the compressed test pattern file is loaded into the test apparatus, the test pattern file is expanded by the test apparatus control EWS. In the present embodiment, the H / W configuration of the test apparatus is reduced in order to suppress the operation time. Is determined in consideration of the block size.

Next, the operation will be described with reference to FIG. First, candidates for the block size of the test pattern file data are specified (step S11). The candidate block size is stored in the test pattern memory 5.
It is listed based on the bus width.

For example, when the bus width is 24 bits,
Most preferably, the block size is 24 bits.
In addition, 1/2 bits of 12 bits, 1
Candidates include 8 bits of / 3, 48 bits of twice, and 32 bits... For ease of CPU control.

After the candidate block size is determined, the optimum block size is determined from a flow substantially similar to that of the first embodiment. That is, block size B
(I) is changed from 0 to the number of candidates T (step S1)
2) The changed block size is compared with the test pattern file before compression to extract the number of changed blocks in the case of B (i) (steps S13 and S14), and after the compression including the changed number of blocks, Is calculated (step S15), and the calculated value is stored in a buffer.

After the calculation is completed, that is, after confirming the completion of the block size (step S16), the block size having the minimum test pattern file size is selected (step S16).
17). Then, it is determined whether the minimum test pattern file size after compression is smaller than the size of the original test pattern file, that is, the size of the test pattern file before compression (step S18). If smaller, the selected minimum test pattern file size is determined. Is determined as the optimal block size (step S19). If the block size is large, the compression is determined to be incompatible (step S2).
0).

As described above, in the present embodiment, the compression unit, that is, the block size when compressing the test pattern file is optimized in consideration of the configuration of the test apparatus. This makes it possible to reduce the cost and reduce the cost of the test pattern storage medium.

Embodiment 3 In the first embodiment,
The test pattern file compressed in step 2 may be transferred to another location via a communication medium. in this way,
In the present embodiment, the compressed test pattern file is transferred to another location via a communication medium. For example, when a public line is used, communication costs are reduced, and
In a local network, the communication load is reduced, and the danger of data corruption when using a general compression / decompression tool can be avoided.

Embodiment 4 FIG. In the present embodiment,
The above-described compressed test pattern file is applied to the test device also having the HDD 4 functioning as a disk cache for performing the data transfer at a high speed shown in FIG. In this way, the compressed test pattern file is loaded into the test pattern memory 5 and also stored in the HDD 4 at the same time. If there is a test pattern file in the HDD 4, it is not necessary to load it via the (hit) LAN.

As described above, in the present embodiment, since the above-described compressed test pattern file is applied to the test apparatus having the disk cache, the number of pattern files that can be cached in the disk cache increases, and The hit ratio is improved, the load from the disk cache is increased, the network load is reduced, and the load from the disk cache is increased, and the average load time is reduced.

[0034]

As described above, according to the first aspect of the present invention, the test pattern file used for the semiconductor test is focused on for each pattern vector, and only the change from the previous pattern vector is filed. Since the test pattern file is compressed, it is possible to reduce the cost of the test pattern storage medium and the communication cost at the time of transmitting the test pattern, and it is possible to shorten the time for the test pattern.

According to the second aspect of the present invention, when the test pattern file is compressed, the block size of the data included in the test pattern file is changed, and the changed block size is changed to the test pattern before compression. The number of changed blocks is extracted by collating with the file, the test pattern file size after compression including the number of changed blocks is calculated, and the block size that is the minimum test pattern file size after compression is selected. Since the minimum test pattern file size is compared with the size of the test pattern file before compression and the quality of the selected block size is determined based on the comparison result, the block size can be optimized. , Test pattern storage media cost and communication cost during test pattern transmission There is an effect that can contribute to faster time and test pattern.

According to the third aspect of the present invention, the block size of the data included in the test pattern file when compressing the test pattern file is optimized in consideration of the configuration of the semiconductor test apparatus. It is possible to reduce the time required to load the test pattern into the test apparatus, and to reduce the cost of the test pattern storage medium.

According to the fourth aspect of the present invention, at the time of compressing the test pattern file, a candidate for a block size of data included in the test pattern file is designated, and the candidate block size is changed. The changed block size is compared with the test pattern file before compression to extract the number of changed blocks, calculate the size of the compressed test pattern file including the changed number of blocks, and obtain the minimum test pattern file size after compression. Block size is selected, the minimum test pattern file size after compression is compared with the test pattern file before compression, and the quality of the selected block size is determined based on the comparison result. And the load time of the test pattern on the test equipment is reduced. There is an effect that can contribute to the reduction of and test pattern storage media cost.

According to the fifth aspect of the present invention, the optimization of the block size based on the comparison result is determined when the minimum test pattern file size after compression is smaller than the size of the test pattern file before compression. The block size of the minimum test pattern file size is determined as the optimum block size, and if the block size is large, the compression is made unsuitable, so that the test pattern file can be accurately compressed.

According to the sixth aspect of the present invention, the candidate block size is selected in consideration of the bus width to the storage means for storing the test pattern file. This makes it possible to reduce the time required to load the test pattern into the test apparatus and to reduce the cost of the test pattern storage medium.

According to the seventh aspect of the present invention, the test pattern of the compressed test pattern file is transferred to another location via a communication medium, so that communication cost and communication load can be reduced. In addition, there is an effect that the danger of data destruction when using a general compression and decompression tool can be avoided.

According to the eighth aspect of the present invention, since the disk cache is used for data transfer of the test pattern file, high-speed data transfer becomes possible, and the number of pattern files that can be cached in the disk cache increases. In addition, the hit rate of the disk cache is improved, the load from the disk cache increases, the network load is reduced, and the load from the disk cache increases, and the average load time is shortened. .

According to the ninth aspect of the present invention, the test pattern file used for the semiconductor test is focused on for each pattern vector, and only the change from the previous pattern vector is filed to compress the test pattern file. And a storage unit for storing the test pattern file compressed by the compression unit, and the semiconductor device under test is tested using the compressed test pattern file. Communication costs during test pattern transmission can be reduced,
Further, there is an effect that the time for the test pattern can be reduced.

According to the tenth aspect of the present invention, since the HDD which functions as a disk cache for performing the data transfer of the test pattern file at high speed is provided, the network load can be reduced and the average load time can be reduced. This has the effect.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a symbolized binary image of a test pattern file according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of one vector in a compressed test pattern file according to the first embodiment of the present invention.

FIG. 4 is a diagram showing the relationship between the number of test vectors based on the number of compressed blocks and the test pattern file capacity according to the first embodiment of the present invention.

FIG. 5 is a diagram showing the relationship between the number of pins changed from the previous vector and the compression ratio according to the block size according to the first embodiment of the present invention.

FIG. 6 is a flowchart of block size determination focusing on a test file size after compression according to the first embodiment of the present invention.

FIG. 7 is a flowchart for determining a block size in consideration of an H / W configuration of a test apparatus according to Embodiment 2 of the present invention.

[Explanation of symbols]

1 host engineering workstation (host EWS), 3 test equipment control EWS, 4
HDD (disk cache), 5 test pattern memory, 6 semiconductor to be measured.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kenichi Sakai 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 2M032 AB01 AC04 AD05 AE07 AE08 AE09 AE10 AE12 AG02

Claims (10)

[Claims] 1. A semiconductor test wherein a test pattern file used for a semiconductor test is focused on for each pattern vector, and only a change from a previous pattern vector is filed to compress the test pattern file. Method. 2. When compressing the test pattern file, a block size of data included in the test pattern file is changed, and the changed block size is compared with a test pattern file before compression to determine the number of changed blocks. Extract, calculate the compressed test pattern file size including the number of changed blocks, select the block size that has become the minimum test pattern file size after compression,
2. The semiconductor according to claim 1, wherein the minimum test pattern file size after compression is compared with the size of the test pattern file before compression, and the quality of the selected block size is determined based on the comparison result. Test method. 3. The semiconductor according to claim 1, wherein a block size of data included in the test pattern file when compressing the test pattern file is optimized in consideration of a configuration of a semiconductor test apparatus. Test method. 4. When compressing the test pattern file, a candidate of a block size of data included in the test pattern file is designated, the candidate block size is changed, and the changed block size is set to a value before compression. Extract the number of changed blocks by comparing with the test pattern file,
Calculate the test pattern file size after compression including the number of changed blocks, select the block size that is the minimum test pattern file size after compression, and select the minimum test pattern file size after compression and the test pattern before compression. 4. The semiconductor test method according to claim 3, wherein the sizes of the files are compared, and the quality of the selected block size is determined based on the comparison result. 5. A determination as to whether the block size is good or bad based on the result of the comparison, when the minimum test pattern file size after compression is smaller than the size of the test pattern file before compression, the block size of the minimum test pattern file size is optimized. 5. The test method for a semiconductor device according to claim 2, wherein the block size is determined as an appropriate block size, and if the block size is large, the compression is determined to be incompatible. 6. The test method for a semiconductor device according to claim 4, wherein said candidate block size is selected in consideration of a bus width to a storage means for storing said test pattern file. 7. The semiconductor test method according to claim 1, wherein the test pattern of the compressed test pattern file is transferred to another location via a communication medium. 8. The semiconductor test method according to claim 1, wherein a disk cache is used for data transfer of the test pattern file. 9. A compression means for focusing on a test pattern file used for a semiconductor test for each pattern vector, compressing only the change from the previous pattern vector into a file, and compressing the test pattern file. A storage means for storing a test pattern file compressed in step (a), wherein a test of the semiconductor device to be measured is performed using the compressed test pattern file. 10. The semiconductor test apparatus according to claim 9, further comprising an HDD functioning as a disk cache for performing high-speed data transfer of the test pattern file.