JPH09246988A - Decoder and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a decoder and the method for simultaneously decoding plural variable length codes while maintaining the address length and total capacity of a decoding table small and accelerating a decoding processing. SOLUTION: In the case of decoding one code, decoding is performed by the corresponding word of a decoding RAM 4. In this case, when a code length is long, the plural words are referred to. Also, in the case of simultaneously decoding the plural codes, by indicating a word address in a second decoding RAM 7 in the corresponding word of the decoding RAM 4 and referring to the word of the second decoding RAM 7, the plural codes are simultaneously decoded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding apparatus and a method thereof, for example, a decoding apparatus and a method for decoding a variable length code.

[0002]

2. Description of the Related Art With the recent development of communication devices and information processing devices, data encoding has become an indispensable technique for more efficient data communication and more efficient data storage. A method of conversion has been proposed.

As a coding method, a variable length coding method is known in which the code is not necessarily fixed length. The simplest method of performing decoding (decoding) of this variable length code is a method of referring to a table (decoding table) in which codes and data are associated with each other. In this case, the table is referred to by associating the same bit width as the longest code length in the variable length code with the bit width of the address of the table.

Further, when a plurality of bits of a variable length code are referred to for sequential decoding, a plurality of variable length codes may be included in the plurality of bits. In such a case, by decoding only the code at the beginning or by expanding the one-word width of the table and storing a plurality of codes as the table contents, for example, from the beginning to the second One of the methods that enables two codes to be decoded at the same time has been adopted.

[0005]

However, in the above-mentioned conventional example, when the longest code length in the variable length code is long, the address length of the table becomes very long, and therefore the table capacity becomes very large. I will end up.

Further, in order to store a plurality of variable length codes in the table and simultaneously decode a plurality of codes,
It is necessary to expand the table by one word width. Therefore, the table capacity is further increased.

Since the table capacity increases in this way, it has become difficult to configure the table with a semiconductor memory. This is the LS of the decoder
It was also an obstacle to I conversion.

The present invention has been made to solve the above-mentioned problems, and enables simultaneous decoding of a plurality of variable-length codes while keeping the address length and total capacity of the decoding table small, thus enabling high-speed decoding processing. It is an object of the present invention to provide a decoding device and a method for realizing the same.

[0009]

As one means for achieving the above object, the decoding apparatus of the present invention has the following configuration.

That is, input means for inputting a variable length code,
A first decoding means for decoding one variable-length code and a second decoding means for simultaneously decoding a plurality of variable-length codes
When the variable-length code input by the input means includes a plurality of codes, the first decoding means includes information of the second decoding means for the plurality of codes. Characterized by giving.

For example, the first decoding means and the second decoding means
The decoding means of is a first decoding table and a second decoding table, respectively.

For example, the second decoding table includes a plurality of decoded values.

For example, when the variable length code input by the input means includes a plurality of codes, the first decoding table gives address information in the second decoding table to the plurality of codes. It is characterized by

For example, in the first decoding table, when the variable length code input by the input means includes a plurality of codes, the address information and the head in the second decoding table for the plurality of codes are given. It is characterized in that a decoded value of the code is given.

For example, the second table is characterized in that it includes decoded values of codes other than the first one of the plural codes.

For example, the variable length code is a Huffman code.

For example, the variable length code includes additional bits.

Further, in the decoding device for decoding a variable length code by referring to a table, the variable length code length corresponding to each word of the table is fixed, and the variable length code to be decoded is the fixed variable. If the length is longer than the long code length, the variable length code is decoded using a plurality of words in the table.

Further, as one method for achieving the above-mentioned object, the decoding method of the present invention comprises the following steps.

That is, a decoding method in a decoding device for decoding a variable length code, comprising a first decoding step of decoding one code of the variable length code by referring to a first decoding table, and a plurality of variable length codes. A second decoding step for simultaneously decoding the code with reference to the second decoding table, wherein in the first decoding step, when the input variable length code includes a plurality of codes, Information of the second decoding table corresponding to the plurality of codes is given by the first decoding table.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 is a block diagram showing the arrangement of a decoding apparatus according to this embodiment. Reference numeral 1 is a code input unit that receives a variable length code, 2 is a bit string extraction unit that extracts a bit string required for analysis for decoding, 3 is an address generation unit that generates an address of a table necessary for decoding, and 4 is decoding A decoding RAM which is a table, 7 is a second decoding RAM for decoding a plurality of codes, 5 is a word analysis section for analyzing the contents of the decoding table, 8 is a serial conversion section for sending the decoding results of a plurality of codes in order, A selector 9 selects and outputs a decoding result of one code or a decoding result of a plurality of codes. A shift control unit 6 controls the code input unit 1 and the bit string extraction unit 2 to adjust the number of input bits to the address generation unit 3. Hereinafter, detailed operations in each of these configurations will be described.

In this embodiment, a Huffman code will be described as an example of the variable length code. This Huffman code is first input to the code input unit 1. The code input unit 1 is controlled by the shift control unit 6 and performs an operation of taking in a Huffman code bit string from the outside as needed. The bit string extraction unit 2 extracts the data input to the code input unit 1 in the number of bits required for analysis for decoding. Then, at this time, as many bits as the analysis has already been completed are discarded from the extracted bit string.

In this way, a bit string having the number of bits required for analysis is sent to the address generator 3. Then, in the first analysis, the bit string is directly given as the address of the decode RAM 4 as a predetermined analysis bit length.

The word structure of the decode RAM 4 is shown in FIG. Based on the data obtained by the decode RAM 4, the word analysis unit 5 at the next stage performs a decoding process according to the content of the data. Hereinafter, the details will be described.

First, a case where decoding of one Huffman code is completed by one analysis will be described. In this case, in the corresponding word of the decode RAM 4, the first decoded value is set in the area 31 and the code length of the Huffman code corresponding to the first decoded value is set in the area 32 shown in FIG. Further, the search end flag 33 is set. Then, the word analysis unit 5 outputs the decoding result (first decoded value) to the selector 9 and includes the code length in the shift control unit 6 so that the bit string extraction unit 2 discards the bit string portion that has been decoded. Send a command.

In addition, there may occur a case where the decoding is not completed by one analysis, that is, the Huffman code to be decoded is longer than the above-mentioned predetermined analysis bit length. In this case, the corresponding word of the decode RAM4 is
A pointer indicating the word is set in the area 31 shown in FIG. 3, and a next analysis length indicating a bit length required for the next analysis is set in the area 32. Further, the search end flag is not set in the area 33.

When decoding the Huffman code, the decoding RA
When such a word is searched for in M4, the word analysis unit 5 first removes the analyzed bit from the bit string in the bit string extraction unit 2 via the shift control unit 6. Then, the Huffman code indicated by the next analysis length held in the area 32 and having the number of bits required for the next analysis is sent to the address generation unit 3. Further, the address generation unit 3 is provided with the pointer held in the area 31 by the word analysis unit 5. The address generator 3 adds the pointer and the Huffman code to determine the address of the decode RAM 4 to be accessed for the second analysis.

Then, the above operation is repeated for a plurality of words until it is detected that the search end flag of the area 33 is raised in each word of the decoded RAM 4 thus accessed. Then, when a word for which the search end flag is raised is detected, the first decoded value held in the area 31 in the word is set as the decoded value of the Huffman code.

As described above, in the present embodiment, even when the Huffman code length is long, by using a plurality of words in the decode RAM 4, it is possible to properly analyze and decode up to the end of the code.

The selector 9 selects and outputs the output from the word analysis unit 5 to output the decoding result.

Next, the case where at least two Huffman codes are included in the search bit string in one search of the decode RAM 4 will be described. In this case, the word corresponding to the decode RAM 4 has the area 34 shown in FIG.
A multiple code flag indicating multiple codes is set in. In this case, in order to decode a plurality of codes in this embodiment,
The second decoding RAM 7 is accessed. Therefore, in the word configuration in the decode RAM 4, any area other than the plural code flags in the area 34 (for example, the area 31
Etc., the pointer corresponding to the second decoding RAM 7 is stored. Then, using the pointer as an address,
The second decoding RAM 7 is accessed.
The pointer to the second decoding RAM 7 may be directly given from the decoding RAM 4 as described above, or
It may be given to the address generation unit 3 via the word analysis unit 5.

The word structure of the second decode RAM 7 is shown in FIG.
Shown in In FIG. 4, 41 is a first decoded value which is the decoding result of the head code of the analyzed bit string, and 42 is a second decoded value which is the decoding result of the second code. Also, 43
Is the analysis end code length which is the total number of bits of the first code and the second code. The first decoded value 41 and the second decoded value 42 are serially converted in time series by the serial converter 8 and selectively output from the selector 9.

In this way, when a plurality of codes are decoded by one search, the word analysis unit 5 sends the analysis end code length 43 to the shift control unit 6, and the bit extraction unit 2 outputs two codes. Is taken out. Therefore, there is an advantage that the processing time is shortened as compared with the case where the processing is performed for each code. Also, the second decoding RAM
When the output of 7 is converted to serial by the serial conversion unit 8, the following code is extracted by the bit string extraction unit 2 and the decoding RAM 4 is accessed to start the next decoding process, that is, parallel processing is performed. This enables further high-speed processing.

When decoding a plurality of codes, the analysis end code length 43 is set as the code length of the second code in the word configuration of the second decode RAM 7 shown in FIG. 4, and the leading code length is the decode RAM 4 The word may be written in the word with the pointer of the second decoding RAM 7. In this case, the code lengths of the two codes are summed in the word analysis unit 5 (or separately) and sent to the shift control unit 6, and the bit extraction unit 2 discards the unnecessary bits. good.

The analysis end code length 43 may be omitted from the word configuration of the second decoding RAM 7 shown in FIG. 4 and the code length may be configured as a part of the word of the decoding RAM 4. This is effective when the pointer to the second decoding RAM 7 does not require a large bit width, and the total capacity of the second decoding RAM 7 can be reduced.

In this embodiment, as an example of decoding a plurality of codes, the case where the first and second two codes are decoded at the same time has been described. However, of course, it is applied to three or more codes. May be.

As described above, according to the present embodiment, even if the code length of the Huffman code is long, it is possible to perform decoding using a plurality of words, so that it is possible to construct a decode table with a minimum required word width. Therefore, the total capacity of the table can be reduced.

Further, it is necessary to decode a plurality of codes by judging whether or not a plurality of codes are to be decoded from the search result of the decoding table, and when the plurality of codes are to be decoded, the second decoding table is used. It suffices to prepare the second decoding table only for the bit string.
The address width of the second decoding table can be made extremely small, and the capacity of the table can be reduced.

<Second Embodiment> The second embodiment of the present invention will be described below.
An embodiment will be described.

FIG. 2 shows a block configuration of a decoding device in the second embodiment. In FIG. 2, the same components as those in FIG. 1 described in the first embodiment described above are designated by the same reference numerals, and the description thereof will be omitted.

For example, in the JPEG standard encoding method that employs a Huffman code during encoding, there are cases where additional bits are inserted between the Huffman code and the Huffman code. The decoding device of the second embodiment is characterized in that it is possible to appropriately decode even a code in which the load bit is inserted in this way.

In the second embodiment, the decode RAM 4
When only one code is decoded in one search of, the additional bit is extracted from the bit extraction unit 2 after the first decoded value is selected and output from the selector 9.
It is selectively output from the selector 9. Decode R in this case
The word structure of AM4 may be the same as that of FIG. 3 shown in the first embodiment. In this case, since the word analysis unit 5 can detect the additional bit length based on the information in the first decoded value, the bit extraction unit 2 can be controlled via the shift control unit 6.

Next, a case where a plurality of codes are decoded by one search of the decode RAM 4 will be described. In this case, the first word in the corresponding word of the decode RAM4
Similar to the embodiment, a plural code flag indicating plural codes is set in the area 34 shown in FIG. 3, and the second decoding RAM 7 for decoding the plural codes based on the flag.
Access to. Therefore, the decoding RA shown in FIG.
In the word structure in M4, a pointer corresponding to the second decoding RAM 7 is stored in any area (for example, the area 31 etc.) other than the plural code flags of the area 34. Then, using the pointer as an address, the second decoding RAM 7 is accessed. The pointer to the second decode RAM 7 may be directly given from the decode RAM 4 as described above, or may be given to the address generation unit 3 via the word analysis unit 5.

Second decode RAM in the second embodiment
The word structure of 7 is shown in FIG. In FIG. 5, the first decoded value 51, its additional bits 52, and the second decoded value 53
And the additional bits 53, which are sequentially taken out from the selector 9 via the serial conversion unit 8. In this case, in the second decoding RAM 7, the load on the serial conversion unit 8 can be reduced by fixing the bit width of the area for storing the additional bits 52 and 54.

Second word analysis unit 1 in the second embodiment
0 is a configuration for supplementing the function of the word analysis unit 5.
In the second word analysis unit 10, for example, when the additional bit areas 52 and 54 shown in FIG. 5 are not constant length (maximum additional bit width) but variable, the additional bit length corresponding to the decoded value is detected. Then, information for separating the part is given to the serial conversion unit 8. At this time, the number of additional bits is added to the sum of the code lengths of the first code and the second code to control the shift control unit 6.

Further, a total of two code lengths and a total of two additional bit lengths may be stored in advance in the analysis end code length 55 of FIG.

The second embodiment can also be configured as follows.

Here, if only the first code and its additional bits and the second code are included in the bit string to be searched in the first search, and the additional bits of the second code are not included in the bit string. However, it is possible to decode two codes with one search. In this case, the word structure of the second decoding RAM 7 is set as shown in FIG. That is, the additional bit flag 61 is provided.
Since the other areas are the same as those in the configuration of FIG. 5, the description thereof will be omitted.

When the additional bit flag 65 is set, it indicates that the first and second decoded values and the two additional bits corresponding thereto are included in the word, while the additional bit flag 65 is set. When it is not set, it means that the word includes one additional bit corresponding to the first and second decoded values and the first decoded value. In the latter case, the additional bit corresponding to the second decoded value is instructed to the shift control unit 6 so that the second word analysis unit 10 extracts it in the bit extraction unit 2 and directly outputs it to the selector 9.

As described above, according to the second embodiment,
Even for a code such as a JPEG code in which additional bits are inserted between Huffman codes, it is possible to obtain the same effect as that of the first embodiment by appropriately setting the decoding table. it can.

<Third Embodiment> The third embodiment of the present invention will be described below.
An embodiment will be described.

The third embodiment is a modification of the above-described first embodiment.

The configuration of the decoding device in the third embodiment is as follows.
Since it is the same as FIG. 1 shown in the above-described first embodiment, description thereof will be omitted.

The word configuration of the decode RAM 4 in the third embodiment is shown in FIG. 7 (a). When decoding a plurality of codes in one search, the pointer to the second decoding RAM 7 is stored in the area 72 indicating the code length or the next analysis length in the word and the search end flag 73. Then, the plural code flag 74 is set. This state is shown in FIG.
It is shown in the lower part of (a).

That is, since the decoded value (first decoded value) of the head code is contained in the word of the decode RAM 4, as shown in (b) of FIG. The decrypted value can be omitted. Therefore, the word width in the second decoding RAM 7 can be reduced, and a plurality of codes can be decoded at high speed with a smaller table capacity.

Therefore, when a plurality of codes are decoded by one search in the third embodiment, the word decoding section 5 first selects the first decoded value from the word selector 5 as the decoded data flow.
The second decoded value is output via the serial conversion unit 8
It is output from the selector 9 via. The analysis end code length 76 shown in FIG. 7B is the total value of the first and second code lengths.

In the third embodiment, the area width of the second decoding RAM 7 pointer is the total width of the area 72 indicating the code length or the next analysis length shown in FIG. 7A and the search end flag area 73. If it slightly exceeds, the word width of the decode RAM 4 may be slightly widened so that the pointer can be accommodated.

On the contrary, even if the bit string extracted by the bit string extraction unit 2 has such a length that a plurality of codes can be decoded at one time, a code having a low appearance frequency (especially a code having a relatively long bit length) However, the decoding of a plurality of codes may not be performed. By doing so, the capacity of the second decode RAM 7 can be reduced, and therefore the address width of the pointer for the second decode RAM 7 can be reduced, and the second decode RAM in the word in the decode RAM 4
The bit area for storing the 7 pointer is also small.

That is, if it is possible to decode a plurality of codes only in the case where a code having a relatively high bit length and a relatively short bit length continues, the second decoding RA is performed.
Since the capacity of M7 can be minimized and it is not necessary to refer to a long bit string, the decode RAM
The address length of 4 is also short, and a sufficient high-speed decoding operation is possible while achieving a small capacity.

Of course, in the first decoding by the decoding RAM 4, there is no problem even if a bit string having the same length as the longest Huffman code is analyzed. However, in this case, in the word configuration of the decode RAM 4 shown in FIG. 7A, the pointer for the second decoding, the next analysis length, the search end flag of the area 73, etc. are not necessary, and the plurality of areas 74 The code flag remains.

As described above, according to the third embodiment,
By storing the first decoded value in the word of the decode RAM 4, the first decoded value for the leading code can be omitted in each word of the second decode RAM 7. Therefore, decoding of a plurality of codes can be performed at high speed with a smaller table capacity.

<Other Embodiments> Incidentally, even when the present invention is applied to a system composed of a plurality of devices (eg, host computer, interface device, reader, printer, etc.), a device composed of one device ( For example, it may be applied to a copying machine, a facsimile machine, etc.).

Another object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or apparatus.
And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

Further, by executing the program code read by the computer, not only the functions of the above-described embodiment are realized, but also the OS (operating system) running on the computer based on the instruction of the program code. It is needless to say that this also includes a case where the above) performs a part or all of the actual processing and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided on a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0069]

As described above, according to the present invention, even if the code length of the Huffman code is long, it is possible to perform decoding using a plurality of words. It becomes possible and the total capacity of the table can be reduced.

Further, it is necessary to decode a plurality of codes by judging whether or not a plurality of codes are to be decoded from the search result of the decoding table, and when the plurality of codes are to be decoded, the second decoding table is used. It suffices to prepare the second decoding table only for the bit string.
The address width of the second decoding table can be made extremely small, and the capacity of the table can be reduced.

That is, it is possible to simultaneously decode a plurality of variable length codes while keeping the address length and the total capacity of the decoding table small, and it is possible to speed up the decoding process.

[0072]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a decoding device that is an embodiment according to the present invention.

FIG. 2 is a block diagram showing a configuration of a decoding device according to a second embodiment.

FIG. 3 is a diagram showing a word configuration of a decode table in the present embodiment.

FIG. 4 is a diagram showing a word configuration of a second decode table in the present embodiment.

FIG. 5 is a diagram showing a word configuration of a second decode table in the second embodiment.

FIG. 6 is a diagram showing a word configuration of a second decode table in the second embodiment.

FIG. 7 is a diagram showing a word configuration of a decode table in the third embodiment.

[Description of Codes] 1 code input unit 2 bit string extraction unit 3 address generation unit 4 decode RAM 5 word analysis unit 6 shift control unit 7 second decode RAM 8 serial conversion unit 9 selector 10 second word analysis unit

Claims (10)

[Claims] 1. Input means for inputting a variable-length code, first decoding means for decoding one variable-length code, and second decoding means for simultaneously decoding a plurality of variable-length code. Wherein the first decoding means, when the variable-length code input by the input means includes a plurality of codes, provides the information of the second decoding means to the plurality of codes. Characterizing decoding device. 2. The decoding device according to claim 1, wherein the first decoding means and the second decoding means are a first decoding table and a second decoding table, respectively. 3. The decoding device according to claim 2, wherein the second decoding table includes a plurality of decoded values. 4. The first decoding table gives address information in the second decoding table to the plurality of codes when the variable length code input by the input means includes a plurality of codes. 2. The method according to claim 2, wherein
Or the decoding device according to 3. 5. The first decoding table, when the variable-length code input by the input means includes a plurality of codes, the address information and the head in the second decoding table for the plurality of codes. The decoding device according to claim 2 or 3, wherein a decoding value of the code is given. 6. The decoding device according to claim 5, wherein the second table includes decoded values of codes other than the first one of the plurality of codes. 7. The decoding device according to claim 1, wherein the variable length code is a Huffman code. 8. The decoding device according to claim 5, wherein the variable length code includes additional bits. 9. A decoding device for decoding a variable length code by referring to a table, wherein a variable length code length corresponding to each word of the table is fixed, and the variable length code to be decoded is the fixed variable. A decoding device, wherein when the length is longer than a long code length, the variable length code is decoded using a plurality of words in the table. 10. A decoding method in a decoding device for decoding a variable length code, comprising: a first decoding step of decoding one code of the variable length code by referring to a first decoding table; and a plurality of variable length codes. A second decoding step for simultaneously decoding the code with reference to the second decoding table, wherein in the first decoding step, when the input variable length code includes a plurality of codes, A decoding method, wherein information of the second decoding table corresponding to the plurality of codes is given by the first decoding table.