JP2002124848A - Surface acoustic wave element, electronic component and its mounting method - Google Patents

Surface acoustic wave element, electronic component and its mounting method

Info

Publication number
JP2002124848A
JP2002124848A JP2000316470A JP2000316470A JP2002124848A JP 2002124848 A JP2002124848 A JP 2002124848A JP 2000316470 A JP2000316470 A JP 2000316470A JP 2000316470 A JP2000316470 A JP 2000316470A JP 2002124848 A JP2002124848 A JP 2002124848A
Authority
JP
Japan
Prior art keywords
acoustic wave
single crystal
surface acoustic
crystal chip
wave device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000316470A
Other languages
Japanese (ja)
Inventor
Fumio Uchikoba
文男 内木場
Tomoyuki Goi
智之 五井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP2000316470A priority Critical patent/JP2002124848A/en
Publication of JP2002124848A publication Critical patent/JP2002124848A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent

Abstract

PROBLEM TO BE SOLVED: To provide an SAW element in which thermal shock resistance characteristics and reliability are enhanced by minimizing the effect of anisotropy in the coefficient of thermal expansion of a single crystal chip, and an electronic component incorporating the SAW element. SOLUTION: The surface acoustic wave element comprises an electrode 12 and terminal conductors 131-136 arranged on one side of a single crystal chip 11. The terminal conductors 131-136 are arranged on an imaginary oval line OV1 on one side of the single crystal chip 11. The oval line OV1 has a short diameter a in the direction of the single crystal chip 11 having a larger coefficient of thermal expansion.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、表面弾性波素子
(以下SAW素子と称する)、SAW素子と基板とを組
み合わせた電子部品、及び、その製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface acoustic wave device (hereinafter, referred to as a SAW device), an electronic component obtained by combining a SAW device and a substrate, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】電子機器において、その小型化は市場要
求が常にあり、使用される部品についても小型化、軽量
化が要求される。携帯電話に代表される、高周波機器に
おいてはこの傾向が著しく、使用する部品においても、
特にこの傾向が顕著に見られる。
2. Description of the Related Art In electronic equipment, there is always a demand for miniaturization in the market, and the size and weight of components used are also required. This tendency is remarkable in high-frequency devices such as mobile phones.
This tendency is particularly noticeable.

【0003】SAW素子は、単結晶チップの表面にID
T電極及び端子導体を形成した構造となっており、通
常、基板の上に搭載して用いられる。SAW素子をセラ
ミック基板に搭載する場合、従来は、表面にIDT電極
を形成したSAW素子の背面を、基板の一面に接着固定
し、Auワイヤーボンド法で表面のIDT電極を、基板
に設けられた接続導体に接続する方法が採用されてき
た。
[0003] A SAW element has an ID on the surface of a single crystal chip.
It has a structure in which a T electrode and a terminal conductor are formed, and is usually used mounted on a substrate. Conventionally, when a SAW element is mounted on a ceramic substrate, the back side of the SAW element having an IDT electrode formed on the surface is bonded and fixed to one surface of the substrate, and the IDT electrode on the surface is provided on the substrate by Au wire bonding. A method of connecting to a connection conductor has been adopted.

【0004】しかしながらこの方法によるとチップの面
積以外に、ワイヤーボンドを行うためのスペースが必要
となり、十分に小型化を行えない欠点がある。
However, according to this method, a space for performing wire bonding is required in addition to the area of the chip, and there is a disadvantage that the size cannot be sufficiently reduced.

【0005】そこで、たとえば特開平10−79638
号公報に示すように、フリップチップ搭載と呼ばれる方
法が一部では用いられている。フリップチップ搭載方法
では、IDT電極及び端子導体をを形成したSAW素子
の表面を、基板の一面と向きあわせ、基板の一面に形成
された接続導体に、SAW素子の端子導体を接触させて
接合するので、ワイヤボンディング方法に比べて、より
小型化に適している。
Therefore, for example, Japanese Patent Application Laid-Open No. 10-79638
As shown in the publication, a method called flip chip mounting is used in part. In the flip-chip mounting method, the surface of the SAW element on which the IDT electrode and the terminal conductor are formed is oriented to one surface of the substrate, and the terminal conductor of the SAW element is brought into contact with and joined to the connection conductor formed on one surface of the substrate. Therefore, it is more suitable for miniaturization than the wire bonding method.

【0006】フリップチップ搭載において、SAW素子
を搭載する基板としては、セラミック基板が用いられ
る。セラミック基板は、耐熱性及び耐薬品性に優れてい
る。しかも、セラミック基板に対して、ろう付け等の手
段によって、金属ケースを接合し、高度の気密性が確保
できる。
In flip chip mounting, a ceramic substrate is used as a substrate on which a SAW element is mounted. Ceramic substrates have excellent heat resistance and chemical resistance. In addition, the metal case is joined to the ceramic substrate by means such as brazing, so that a high degree of airtightness can be secured.

【0007】また、セラミック基板は、それ自体が有す
る電気絶縁性を利用して、その表面または内部に、接続
用導体または電気回路要素となる導体層を形成すること
ができる。しかも、一般的な樹脂基板にくらべて、高周
波損失が小さいこと、熱伝導がよいこと、寸法精度がよ
いこと、信頼性に優れることなどの特徴をも併せ持つ。
[0007] Further, the ceramic substrate can form a connection conductor or a conductor layer serving as an electric circuit element on the surface or inside thereof by utilizing the electric insulation property of the ceramic substrate itself. In addition, compared with a general resin substrate, it also has features such as low high-frequency loss, good heat conduction, good dimensional accuracy, and excellent reliability.

【0008】更に、多層化することもできる。セラミッ
ク多層基板においては、内導体をコイル形状にしたり、
あるいは平行に対向させることによって、それぞれ内部
にインダクタンス、キャパシタンス等の回路要素を形成
することが可能である。しかも、低損失で寸法精度がよ
いことから、Qが高く、また、公差の小さい回路要素素
子を内部に形成することができる。
Further, it is possible to form a multilayer structure. In ceramic multilayer boards, the inner conductor may be coiled,
Alternatively, by facing them in parallel, it is possible to form circuit elements such as inductance and capacitance therein. Moreover, since the loss is low and the dimensional accuracy is good, a circuit element having a high Q and a small tolerance can be formed inside.

【0009】こうした特徴は、特に、携帯電話などの高
周波回路において、特性に優れ、小型化された集合素
子、つまり、モジュールを得る場合に、最大に活かされ
る。
[0009] These features are most utilized in obtaining high-performance and compact integrated elements, that is, modules, particularly in high-frequency circuits such as mobile phones.

【0010】ところが、SAW素子は単結晶であり、結
晶軸に対する切り出し方向により、同一面内で見た熱膨
張率が、縦方向及び横方向で大きく異なる。たとえば、
単結晶チップとして、最も一般的なリチウムタンタレー
トを用いた場合、切り出し方向36度で、縦方向の熱膨
張率が8ppm/℃、横方向の熱膨張率が16ppm/℃であ
り、縦横方向で、おおよそ2倍の熱膨張率の差が生じ
る。
However, the SAW element is a single crystal, and the coefficient of thermal expansion in the same plane greatly differs in the vertical and horizontal directions depending on the cutting direction with respect to the crystal axis. For example,
When the most common lithium tantalate is used as a single crystal chip, the thermal expansion coefficient in the vertical direction is 8 ppm / ° C., the thermal expansion coefficient in the horizontal direction is 16 ppm / ° C., and the vertical and horizontal directions are 36 ° in the cutting direction. , A difference of about twice the coefficient of thermal expansion occurs.

【0011】一方、セラミック基板の熱膨張率は略6pp
m/℃であり、SAW素子を構成する単結晶チップの熱膨
張率との差が著しい。
On the other hand, the thermal expansion coefficient of the ceramic substrate is approximately 6 pp
m / ° C., which is remarkably different from the coefficient of thermal expansion of the single crystal chip constituting the SAW element.

【0012】このため、特に、熱膨張率の大きい方向
(横方向)において、熱膨張率の不整合が大きくなり、
熱衝撃が加わった場合、この方向に大きな熱応力が発生
することになる。
For this reason, especially in a direction (lateral direction) where the coefficient of thermal expansion is large, mismatch of the coefficient of thermal expansion becomes large,
When a thermal shock is applied, a large thermal stress is generated in this direction.

【0013】例えば、SAW素子を構成する単結晶チッ
プを、各辺が1mmの正方形のチップとした場合を仮定
すると、温度が100℃上昇したとき、単結晶チップは
縦方向に0.8μm、横方向に1.6μmの膨張を生じ
ることになる。セラミック基板は、等方的に0.6μm
伸びる。この熱膨張の差のために、単結晶チップとセラ
ミック基板との間に熱応力が発生する。
For example, assuming that the single crystal chip constituting the SAW element is a square chip having each side of 1 mm, when the temperature rises by 100 ° C., the single crystal chip becomes 0.8 μm vertically and horizontally. This would result in a 1.6 μm expansion in the direction. Ceramic substrate isotropically 0.6μm
extend. Due to this difference in thermal expansion, thermal stress is generated between the single crystal chip and the ceramic substrate.

【0014】しかも、フリップチップ塔載においては、
IDT電極の形成されたSAW素子の表面と、セラミッ
ク基板の表面との間に間隔を保ち、端子導体のみを、セ
ラミック基板上に形成された接続導体と接続する構造を
採用しなければならない。このことは、SAW素子が、
端子導体と接続導体との接続によって、セラミック基板
に点的に接着されていることを意味し、上述した熱膨張
の差によって発生する熱応力に対して弱い構造となって
いる。
In addition, when mounted on a flip chip tower,
It is necessary to adopt a structure in which a space is maintained between the surface of the SAW element on which the IDT electrode is formed and the surface of the ceramic substrate, and only the terminal conductor is connected to the connection conductor formed on the ceramic substrate. This means that the SAW element
The connection between the terminal conductor and the connection conductor means that the terminal conductor is point-bonded to the ceramic substrate, and the structure is weak against the thermal stress generated due to the difference in thermal expansion described above.

【0015】更に加えて、SAW素子の表面またはセラ
ミック基板の表面で見た熱応力は、SAW素子の端子導
体の配置、及び、セラミック基板上の接続導体の配置等
に応じた極めて複雑な分布になり、熱応力が特定の接合
部で極度に大きくなることがある。
[0015] In addition, the thermal stress seen on the surface of the SAW element or the surface of the ceramic substrate has an extremely complicated distribution according to the arrangement of the terminal conductors of the SAW element and the arrangement of the connection conductors on the ceramic substrate. And the thermal stress can be extremely high at certain joints.

【0016】このため、フリップチップ搭載において、
SAW素子を構成する単結晶チップの端子導体と、セラ
ミック基板に設けられた接続導体との接合部が熱応力に
よって破壊され、機能を発現できなくなることがある。
For this reason, in flip chip mounting,
The junction between the terminal conductor of the single crystal chip constituting the SAW element and the connection conductor provided on the ceramic substrate may be broken by thermal stress, and the function may not be exhibited.

【0017】この問題は、基板を構成する材料として、
SAW素子を構成する単結晶チップと熱膨張率の近い材
料を選ぶことで、ある程度緩和される。たとえば、基板
の材料として、熱膨張率が中間的な値を持つBTレジン
(12ppm/℃)を用いることである。この場合は熱
膨張率の差がかなり緩和されるが、それでも方向による
その差は残っており、完全な対策とはならない。しか
も、この場合は、セラミック基板による利点を得ること
ができなくなる。
[0017] This problem is caused by the following problems.
By selecting a material having a coefficient of thermal expansion close to that of the single crystal chip constituting the SAW element, it can be alleviated to some extent. For example, BT resin (12 ppm / ° C.) having an intermediate value of the coefficient of thermal expansion is used as the material of the substrate. In this case, the difference in the coefficient of thermal expansion is considerably reduced, but the difference depending on the direction still remains, and is not a complete measure. Moreover, in this case, the advantage of the ceramic substrate cannot be obtained.

【0018】[0018]

【発明が解決しようとする課題】そこで、本発明の課題
は、単結晶チップの熱膨張率の異方性による影響を極力
小さくして、耐熱衝撃特性及び信頼性を向上させたSA
W素子及びこのSAW素子を組み込んだ電子部品を提供
することである。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the influence of the anisotropy of the coefficient of thermal expansion of a single crystal chip as much as possible to improve the thermal shock resistance and reliability.
An object of the present invention is to provide a W element and an electronic component incorporating the SAW element.

【0019】本発明のもう1つの課題は、上述した電子
部品を得るのに好適な製造方法を提供することである。
Another object of the present invention is to provide a manufacturing method suitable for obtaining the above-mentioned electronic component.

【0020】[0020]

【課題を解決するための手段】上述した課題を解決する
ため、本発明は、2つの態様に係るSAW素子を開示す
る。第1の態様に係るSAW素子は、単結晶チップと、
電極と、複数の端子導体とを含む。前記電極は、前記単
結晶チップの一面上に備えられている。前記端子導体の
それぞれは、前記電極に電気的に導通し、前記単結晶チ
ップの前記一面上に想定された同一の楕円線上に載るよ
うに、前記単結晶チップの前記一面上に備えられてい
る。前記楕円線は、前記単結晶チップの熱膨張係数の大
きい方向に対して短径を持つ。
In order to solve the above-mentioned problems, the present invention discloses SAW elements according to two aspects. The SAW element according to the first aspect includes a single crystal chip,
An electrode and a plurality of terminal conductors are included. The electrode is provided on one surface of the single crystal chip. Each of the terminal conductors is provided on the one surface of the single crystal chip so as to be electrically connected to the electrode and to be placed on the same elliptical line assumed on the one surface of the single crystal chip. . The elliptical line has a minor axis in a direction in which the coefficient of thermal expansion of the single crystal chip is large.

【0021】本発明に係るSAW素子は、基板に搭載し
て用いられる。基板は、好ましくは、セラミック基板で
ある。
The SAW element according to the present invention is used by being mounted on a substrate. The substrate is preferably a ceramic substrate.

【0022】本発明に係るSAW素子において、電極は
単結晶チップの一面上に備えられており、この電極に電
気的に導通する端子導体のそれぞれも、電極の備えられ
た単結晶チップの一面上に備えられている。従って、本
発明に係るSAW素子は、電極及び端子導体を形成した
一面側を、基板の一面と対向させ、端子導体を、基板の
一面に設けられた接続導体に接合するフリップチップ搭
載が可能である。
In the SAW element according to the present invention, the electrodes are provided on one surface of the single crystal chip, and the terminal conductors electrically connected to the electrodes are also provided on one surface of the single crystal chip provided with the electrodes. It is provided in. Therefore, the SAW element according to the present invention can be flip-chip mounted such that one surface on which electrodes and terminal conductors are formed is opposed to one surface of the substrate, and the terminal conductors are joined to connection conductors provided on one surface of the substrate. is there.

【0023】端子導体のそれぞれは、単結晶チップの一
面上に想定された同一の楕円線上に載るように、単結晶
チップの一面上に備えられており、この楕円線は、単結
晶チップの熱膨張係数の大きい方向に対して短径を持
つ。この端子導体の配置によれば、SAW素子をセラミ
ック基板上にフリップチップ搭載した場合、端子導体と
接続導体との接合部で見た熱膨張量は、楕円線の楕円中
心からほぼ均一になる。このため、SAW素子を構成す
る単結晶チップと、セラミック基板との間の熱膨張率の
違いに起因して発生する熱応力が、単結晶チップの熱膨
張率の異方性にも関わらず、端子導体と接続導体との接
合部のそれぞれに対して、等方的にかかることになる。
このため、単結晶チップの一面上に設けられた端子導体
に加わる熱応力を均一化し、耐熱衝撃性を向上させるこ
とができる。
Each of the terminal conductors is provided on one surface of the single-crystal chip so as to be placed on the same elliptical line assumed on one surface of the single-crystal chip. It has a short diameter in the direction with a large expansion coefficient. According to the arrangement of the terminal conductors, when the SAW element is flip-chip mounted on the ceramic substrate, the amount of thermal expansion at the joint between the terminal conductor and the connection conductor becomes substantially uniform from the center of the elliptical line. For this reason, the thermal stress generated due to the difference in the coefficient of thermal expansion between the single crystal chip constituting the SAW element and the ceramic substrate, despite the anisotropy of the coefficient of thermal expansion of the single crystal chip, It isotropically applied to each of the joints between the terminal conductor and the connection conductor.
Therefore, the thermal stress applied to the terminal conductor provided on one surface of the single crystal chip can be made uniform, and the thermal shock resistance can be improved.

【0024】第2の態様に係る表面弾性波素子では、単
結晶チップと、電極と、複数の端子導体とを含む。前記
電極は、前記単結晶チップの一面上に備えられている。
The surface acoustic wave device according to the second aspect includes a single crystal chip, an electrode, and a plurality of terminal conductors. The electrode is provided on one surface of the single crystal chip.

【0025】前記単結晶チップの前記一面上に、第1の
楕円線及び第2の楕円線を想定したとき、前記第1の楕
円線は中心が第2の楕円線の中心とほぼ一致し、長径及
び短径が前記第2の楕円線のそれよりも小さくなってい
る。前記第1及び前記第2の楕円線は、前記単結晶チッ
プの熱膨張係数の大きい方向に対して短径を持つ。
Assuming a first elliptic line and a second elliptical line on the one surface of the single crystal chip, the center of the first elliptical line substantially coincides with the center of the second elliptic line; The major axis and the minor axis are smaller than those of the second elliptical line. The first and second elliptical lines have a minor axis in a direction in which the coefficient of thermal expansion of the single crystal chip is large.

【0026】前記端子導体のそれぞれは、前記電極に電
気的に導通し、中心が、前記第1の楕円線と前記第2の
楕円線との間の領域内にある。
Each of the terminal conductors is electrically connected to the electrode and has a center in a region between the first elliptic line and the second elliptical line.

【0027】この第2の態様に係る表面弾性波素子も、
第1の態様に係る表面弾性波と同等の作用効果を奏す
る。
The surface acoustic wave device according to the second aspect also has
The same operation and effect as those of the surface acoustic wave according to the first aspect are obtained.

【0028】本発明に係るSAW素子は基板上に搭載し
て、電子部品化される。セラミック基板に対するSAW
素子の接合に当たっては、SAW素子を、電極及び端子
導体を形成した一面が、基板の一面に対向するように配
置する。セラミック基板には、予め、接続導体は、SA
W素子に備えられた端子導体の配置に対応する位置に、
接続導体を形成しておく。
The SAW element according to the present invention is mounted on a substrate to form an electronic component. SAW for ceramic substrate
In joining the elements, the SAW elements are arranged such that one surface on which the electrodes and terminal conductors are formed faces one surface of the substrate. On the ceramic substrate, the connection conductor is previously set to SA
At a position corresponding to the arrangement of the terminal conductors provided in the W element,
A connection conductor is formed.

【0029】次に、SAW素子上の端子導体を、セラミ
ック基板上の接続導体上に、荷重をかけて接触させ端子
導体及び接続導体を、超音波によって接続する。
Next, the terminal conductor on the SAW element is brought into contact with the connection conductor on the ceramic substrate by applying a load, and the terminal conductor and the connection conductor are connected by ultrasonic waves.

【0030】本発明の他の目的、構成及び利点について
は、実施例である添付図面を参照し、更に詳しく説明す
る。添付図面は、単なる例示に過ぎない。
Other objects, configurations and advantages of the present invention will be described in more detail with reference to the accompanying drawings which are embodiments. The accompanying drawings are merely examples.

【0031】[0031]

【発明の実施の形態】図1は本発明に係る電子部品の正
面図、図2は図1に示した電子部品に含まれるSAW素
子を、電極形成面側(図1において下面側)から見た平
面図である。図示された電子部品は、SAW素子1と、
基板2とを含む。基板2には、ろう付け等の手段によっ
て、Au金属ケース3が接合されており、これによって
高度の気密性が確保されている。
FIG. 1 is a front view of an electronic component according to the present invention, and FIG. 2 is a view of a SAW element included in the electronic component shown in FIG. 1 viewed from an electrode forming surface side (a lower surface side in FIG. 1). FIG. The illustrated electronic components include a SAW element 1,
And a substrate 2. The Au metal case 3 is joined to the substrate 2 by means such as brazing, thereby ensuring a high degree of airtightness.

【0032】SAW素子1は、単結晶チップ11と、電
極12と、複数の端子導体131〜136とを含む。単
結晶チップ11の具体例としては、LiNbO3や、LiTaO3
を挙げることができる。この単結晶チップ11は、所定
の結晶角度を持つように切り出される。
The SAW element 1 includes a single crystal chip 11, an electrode 12, and a plurality of terminal conductors 131 to 136. Specific examples of the single crystal chip 11 include LiNbO 3 and LiTaO 3 . This single crystal chip 11 is cut out to have a predetermined crystal angle.

【0033】電極12は、単結晶チップ11の一面上に
備えられている。電極12は、SAW素子1として有効
な構造であれば、全て利用することができる。電極12
は、一般には、IDT電極として形成される。IDT電
極は、単数組また複数組の直列接続もしくは並列接続の
組み合わせとして構成される。
The electrode 12 is provided on one surface of the single crystal chip 11. The electrode 12 can be used as long as it has a structure effective as the SAW element 1. Electrode 12
Are generally formed as IDT electrodes. The IDT electrode is configured as a single set or a combination of a plurality of sets connected in series or in parallel.

【0034】端子導体131〜136のそれぞれは、ス
タッドバンプとも称されるもので、電極12に電気的に
導通し、単結晶チップ11のIDT電極上に想定された
同一の楕円線OV1上に載るように、単結晶チップ11
の上に備えられている。楕円線OV1は、単結晶チップ
11の熱膨張係数の大きい方向に対して短径aを持つ。
端子導体131〜136の個数は、電極12の組数に応
じて選定される。端子導体131〜136は、表面にA
u膜が現れるような膜構造を有することが好ましい。具
体的には、単結晶チップ11の一面上に、Ni膜を形成
し、その上にAu膜を形成する。端子導体131〜13
6の平面形状は任意であり、図示の形状に限定されるも
のではない。
Each of the terminal conductors 131 to 136 is also called a stud bump, is electrically connected to the electrode 12, and is placed on the same elliptical line OV1 assumed on the IDT electrode of the single crystal chip 11. As shown, the single crystal chip 11
On top of. The elliptical line OV1 has a minor axis a in a direction in which the thermal expansion coefficient of the single crystal chip 11 is large.
The number of the terminal conductors 131 to 136 is selected according to the number of sets of the electrodes 12. The terminal conductors 131 to 136 have A
It is preferable to have a film structure in which a u film appears. Specifically, a Ni film is formed on one surface of the single crystal chip 11, and an Au film is formed thereon. Terminal conductors 131 to 13
The planar shape of 6 is arbitrary and is not limited to the illustrated shape.

【0035】図1の実施例において、SAW素子1は、
基板2に搭載されている。基板2は、好ましくは、セラ
ミック基板である。基板2として、セラミック基板を用
いることの利点は、既に述べた通りである。セラミック
基板2には、SAW素子1に備えられた端子導体131
〜136に対応する位置に、端子導体131〜136と
同数の接続導体21を、予め、形成しておく。端子導体
131〜136の表面がAu膜によって構成されている
場合、セラミック基板2上の接続導体21も、表面をA
u膜とすることが好ましい。これにより、SAW素子1
とセラミック基板2との間に、AuーAu接合による信
頼性の高い接合構造を形成することができる。より具体
的には、セラミック基板2の表面にAg等の焼結導体を
形成し、その上にNi膜を形成し、その上にAu膜を形
成する。
In the embodiment of FIG. 1, the SAW element 1
It is mounted on the substrate 2. Substrate 2 is preferably a ceramic substrate. The advantages of using a ceramic substrate as the substrate 2 are as described above. The terminal conductor 131 provided on the SAW element 1 is provided on the ceramic substrate 2.
To 136, the same number of connection conductors 21 as the terminal conductors 131 to 136 are formed in advance. When the surfaces of the terminal conductors 131 to 136 are made of an Au film, the connection conductor 21 on the ceramic substrate 2 also
It is preferable to use a u film. Thereby, the SAW element 1
A highly reliable bonding structure by Au-Au bonding can be formed between the substrate and the ceramic substrate 2. More specifically, a sintered conductor such as Ag is formed on the surface of the ceramic substrate 2, a Ni film is formed thereon, and an Au film is formed thereon.

【0036】上述したSAW素子1において、電極12
は、単結晶チップ11の一面上に備えられており、この
電極12に電気的に導通する端子導体131〜136の
それぞれも、電極12の備えられた単結晶チップ11の
一面上に備えられている。従って、このSAW素子1
は、電極12及び端子導体131〜136を形成した一
面側を、基板2の一面と対向させ、端子導体131〜1
36を、基板2の一面に設けられた接続導体21に接合
するフリップチップ搭載を行うことができる。
In the above-described SAW element 1, the electrode 12
Are provided on one surface of the single crystal chip 11, and the terminal conductors 131 to 136 electrically connected to the electrodes 12 are also provided on one surface of the single crystal chip 11 having the electrodes 12. I have. Therefore, this SAW element 1
The terminal conductors 131 to 1 are formed such that one surface on which the electrode 12 and the terminal conductors 131 to 136 are formed is opposed to one surface of the substrate 2.
Flip chip mounting can be performed in which the substrate 36 is connected to the connection conductor 21 provided on one surface of the substrate 2.

【0037】端子導体131〜136のそれぞれは、単
結晶チップ11の一面上に想定された同一の楕円線OV
1上に載るように、単結晶チップ11の一面上に備えら
れている。この楕円線OV1は、単結晶チップ11の熱
膨張係数の大きい方向に対して短径aを持つ。単結晶チ
ップ11の熱膨張係数は、結晶軸に対する切り出し方向
によって定まる。この端子導体131〜136の配置に
よれば、SAW素子1をセラミック基板2上にフリップ
チップ搭載した場合、端子導体131〜136と接続導
体21との接合部で見た熱膨張量は、楕円線OV1の楕
円中心からほぼ均一になる。このため、SAW素子1を
構成する単結晶チップ11と、セラミック基板2との間
の熱膨張率の違いに起因して発生する熱応力が、単結晶
チップ11の熱膨張の異方性にも関わらず、端子導体1
31〜136と接続導体21との接合部のそれぞれに対
して、等方的に加わることになる。従って、単結晶チッ
プ11の一面上に設けられた端子導体131〜136に
加わる熱応力を均一化し、耐熱衝撃性を向上させること
ができる。
Each of terminal conductors 131 to 136 has the same elliptical line OV assumed on one surface of single crystal chip 11.
1 is provided on one surface of the single crystal chip 11. The elliptical line OV1 has a minor axis a in the direction in which the thermal expansion coefficient of the single crystal chip 11 is large. The coefficient of thermal expansion of the single crystal chip 11 is determined by the cutting direction with respect to the crystal axis. According to the arrangement of the terminal conductors 131 to 136, when the SAW element 1 is flip-chip mounted on the ceramic substrate 2, the amount of thermal expansion seen at the joint between the terminal conductors 131 to 136 and the connection conductor 21 is an elliptical line. It becomes almost uniform from the center of the ellipse of OV1. For this reason, the thermal stress generated due to the difference in the coefficient of thermal expansion between the single crystal chip 11 constituting the SAW element 1 and the ceramic substrate 2 causes the thermal expansion of the single crystal chip 11 to be anisotropic. Regardless, terminal conductor 1
It isotropically applied to each of the joints between the connection conductors 31 and 136 and the connection conductor 21. Therefore, the thermal stress applied to the terminal conductors 131 to 136 provided on one surface of the single crystal chip 11 can be made uniform, and the thermal shock resistance can be improved.

【0038】SAW素子1がリチウムタンタレートを主
成分とする場合、SAW素子1の端子導体131〜13
6を配置する楕円線OV1は、短径aと長径bの比
(a:b)が約1:2であることが好ましい。
When the SAW element 1 contains lithium tantalate as a main component, the terminal conductors 131 to 13 of the SAW element 1
It is preferable that the elliptical line OV1 on which the number 6 is arranged has a ratio (a: b) of the minor axis a to the major axis b of about 1: 2.

【0039】実施例において、単結晶チップ11は、略
四角形状であって、相対する2辺の長辺と、相対する2
辺の短辺とを有している。この形状の単結晶チップ11
においては、楕円線OV1は、長径bの方向が、長辺の
延びる方向に一致する。
In the embodiment, the single crystal chip 11 has a substantially quadrangular shape, and has two long sides facing each other and two
And a short side of the side. Single crystal chip 11 of this shape
In the ellipse OV1, the direction of the major axis b coincides with the direction in which the longer side extends.

【0040】図3は本発明の第2の態様に係るSAW素
子を示す図である。図3において、単結晶チップ11の
一面上に、第1の楕円線OV11及び第2の楕円線OV
12を想定する。第1の楕円線OV11は中心が第2の
楕円線OV12の中心とほぼ一致し、長径b1及び短径
a1が第2の楕円線OV12の長径b2及び短径a2よ
りも小さくなっている。端子導体131〜136は、そ
の中心が、第1の楕円線OV11と第2の楕円線OV1
2との間の領域内に位置するように、配置されている。
FIG. 3 is a view showing a SAW element according to a second embodiment of the present invention. In FIG. 3, a first elliptical line OV11 and a second elliptical line OV
12 is assumed. The center of the first elliptical line OV11 substantially coincides with the center of the second elliptical line OV12, and the major axis b1 and the minor axis a1 are smaller than the major axis b2 and the minor axis a2 of the second elliptic line OV12. The center of each of the terminal conductors 131 to 136 has a first elliptical line OV11 and a second elliptical line OV1.
2 so as to be located in a region between the two.

【0041】好ましくは、第1の楕円線OV11は、長
径b1の長さが、単結晶チップ11の長辺長L1の約6
0%とする。第2の楕円線OV12は、長径b2の長さ
が単結晶チップ11の長辺長L1の約90%とする。こ
の配置であれば、単結晶チップ11の熱膨張率の異方性
の影響を、より確実に小さくし得る。
Preferably, the first elliptical line OV11 has a major axis b1 whose length is about 6 times longer than the long side length L1 of the single crystal chip 11.
0%. The length of the major axis b2 of the second elliptical line OV12 is about 90% of the long side length L1 of the single crystal chip 11. With this arrangement, the influence of the anisotropy of the coefficient of thermal expansion of the single crystal chip 11 can be reduced more reliably.

【0042】図1〜図3に示したSAW素子1は、基板
2上に搭載して、電子部品化される。セラミック基板2
に対するSAW素子1の接合に当たっては、SAW素子
1を、電極12及び端子導体131〜136を形成した
一面が、基板2の一面に対向するように配置する。セラ
ミック基板2の一面(搭載面)には、予め、SAW素子
1に備えられた端子導体131〜136に対応する位置
に、接続導体21を形成しておく。
The SAW element 1 shown in FIGS. 1 to 3 is mounted on a substrate 2 to be made into an electronic component. Ceramic substrate 2
When the SAW element 1 is bonded to the substrate 2, the SAW element 1 is arranged such that one surface on which the electrodes 12 and the terminal conductors 131 to 136 are formed faces one surface of the substrate 2. On one surface (mounting surface) of the ceramic substrate 2, connection conductors 21 are formed in advance at positions corresponding to the terminal conductors 131 to 136 provided in the SAW element 1.

【0043】次に、SAW素子1上の端子導体131〜
136を、セラミック基板2上の接続導体21上に、荷
重をかけて接触させ、端子導体131〜136及び接続
導体21を、超音波によって接続する。これにより、図
1に図示した電子部品が得られる。
Next, the terminal conductors 131 to 131 on the SAW element 1
136 is brought into contact with the connection conductor 21 on the ceramic substrate 2 by applying a load, and the terminal conductors 131 to 136 and the connection conductor 21 are connected by ultrasonic waves. Thus, the electronic component shown in FIG. 1 is obtained.

【0044】次に、実施例を挙げて、本発明を更に具体
的に説明する。 実施例1 基板2にセラミック多層基板を用いた。セラミック多層
基板において、アルミナ.ガラス複合セラミックを絶縁
層とし、内導体層を15層とした。基板2は長さ2m
m、幅2.5mmの長方形とし、厚みは0.3mmとし
た。
Next, the present invention will be described more specifically with reference to examples. Example 1 A ceramic multilayer substrate was used as the substrate 2. In a ceramic multilayer substrate, alumina. The glass composite ceramic was used as an insulating layer, and the inner conductor layer was used as 15 layers. Substrate 2 is 2m long
m, a rectangle having a width of 2.5 mm and a thickness of 0.3 mm.

【0045】基板2の接続導体21は、最下層を銀の焼
結導体で形成した。接続導体用銀ペーストを、基板2の
一面上にスクリーン印刷した後、焼結前に、その表面を
プレスし、平坦化した。銀の焼結導体膜の上に、厚さ5
μmのNi層、続いて0.5μmのAu層を、それぞ
れ、無電解めっきで形成した。
The lowermost layer of the connection conductor 21 of the substrate 2 was formed of a sintered silver conductor. After the connection conductor silver paste was screen-printed on one surface of the substrate 2, the surface was pressed and flattened before sintering. On the silver sintered conductor film, a thickness of 5
A μm Ni layer and then a 0.5 μm Au layer were each formed by electroless plating.

【0046】一方、単結晶チップ11は、長辺長1.4
mm、短辺長0.8mm、厚さ0.35mmの四角形状
とし、これにAuでなる端子導体131〜136を形成
した。端子導体131〜136は図2に示した楕円配置
とした。端子導体131〜136の径は、試料A〜Hの
それぞれにおいて、接着前で約50μm、接着後は潰れ
て110μmとなった。
On the other hand, the single crystal chip 11 has a long side length of 1.4.
mm, a short side length of 0.8 mm, and a thickness of 0.35 mm were formed in a square shape, and terminal conductors 131 to 136 made of Au were formed thereon. The terminal conductors 131 to 136 have the elliptical arrangement shown in FIG. The diameter of each of the terminal conductors 131 to 136 was about 50 μm before bonding and crushed to 110 μm after bonding in each of the samples A to H.

【0047】得られたSAW素子を、基板2に伏せた形
で、所定の位置におき、SAW側から9Wの超音波を
O.6秒間照射し、同時に300gの荷重を印加して、
端子導体131〜136と基板2の接続導体21との接
合を行った。この後、横押し強度を測定するとともに、
電子顕微鏡で断面の観察を行った。
The obtained SAW element is placed at a predetermined position in a state in which the SAW element is faced down on the substrate 2, and 9 W ultrasonic waves are applied from the SAW side to the O.D. Irradiate for 6 seconds, simultaneously apply 300g load,
The terminal conductors 131 to 136 and the connection conductor 21 of the substrate 2 were joined. Then, while measuring the lateral pressing strength,
The cross section was observed with an electron microscope.

【0048】その後、熱衝撃試験を行った。熱衝撃試験
は、一40℃の温度で30分間保持し、85℃の温度で
30分間保持するサイクルを1サイクルとして、100
サイクルまで行った。熱衝撃試験の評価に当たっては、
挿入損失の測定を行い、初期に2dB程度であったもの
が、5dB以上となったものを不合格とし、その個数で
判断した。
Thereafter, a thermal shock test was performed. The thermal shock test was conducted at a temperature of 140 ° C. for 30 minutes and a temperature of 85 ° C. for 30 minutes as one cycle.
It went up to the cycle. In evaluating the thermal shock test,
The insertion loss was measured, and what was about 2 dB in the initial stage was judged to be rejected when it became 5 dB or more, and the number was judged.

【0049】比較例1 上記実施例1との対比のために、図11に示すように、
単結晶チップ11の上に、端子導体131〜136を、
長方形の上に配置した従来の試料を用意し、実施例1の
試料と同様の評価を行った。
Comparative Example 1 For comparison with Example 1, as shown in FIG.
Terminal conductors 131 to 136 are formed on the single crystal chip 11,
A conventional sample arranged on a rectangle was prepared, and the same evaluation as the sample of Example 1 was performed.

【0050】表1に実施例1及び比較例1についての横
押し試験による剥離強度及び熱衝撃試験の不合格数を示
す。熱衝撃試験の不合格数は、熱衝撃試験に供された1
00個の試料中の個数である。
Table 1 shows the peel strength and the number of rejects of the thermal shock test in Example 1 and Comparative Example 1 by the lateral push test. The number of failures in the thermal shock test was 1 for the thermal shock test.
This is the number in the 00 samples.

【0051】表1に示すように、比較例1の場合、剥離
強度が520(gf)で、100個中の不合格数が6個
となったが、本発明に係る実施例1の試料では、剥離強
度が530(gf)で、100個中の不合格数が0個と
なり、剥離強度及び耐熱衝撃特性の何れにおいても、比
較例1よりも優れた結果が得られた。
As shown in Table 1, in the case of Comparative Example 1, the peel strength was 520 (gf), and the number of rejects out of 100 was 6. However, in the sample of Example 1 according to the present invention, The peel strength was 530 (gf), the number of rejects out of 100 was 0, and results superior to Comparative Example 1 in both peel strength and thermal shock resistance were obtained.

【0052】次に、第2の態様に係る試料についての実
験を行った。まず、単結晶チップ11は、長辺長1.4
mm、短辺長0.8mm、厚さ0.35mmの四角形状
とし、これにAuでなる端子導体131〜136を形成
した。このとき、端子導体131〜136の位置を適宜
変化させた試料A〜Hを、図3〜図10に示す。端子導
体131〜136の径は、試料A〜Hのそれぞれにおい
て、接着前で約50μm、接着後は潰れて110μmと
なった。
Next, an experiment was performed on the sample according to the second embodiment. First, the single crystal chip 11 has a long side length of 1.4.
mm, a short side length of 0.8 mm, and a thickness of 0.35 mm were formed in a square shape, and terminal conductors 131 to 136 made of Au were formed thereon. At this time, samples A to H in which the positions of the terminal conductors 131 to 136 are appropriately changed are shown in FIGS. The diameter of each of the terminal conductors 131 to 136 was about 50 μm before bonding and crushed to 110 μm after bonding in each of the samples A to H.

【0053】次に、試料A〜Hのそれぞれについて、基
板2に伏せた形で、所定の位置におき、SAW素子側か
ら9Wの超音波をO.6秒間照射し、同時に300gの
荷重を印加して、端子導体131〜136と基板2の接
続導体21との接合を行った。この後、各試料A〜Hの
横押し強度を測定するとともに、電子顕微鏡で断面の観
察を行った。
Next, each of the samples A to H was placed at a predetermined position in a form prone to the substrate 2, and 9 W ultrasonic waves were applied from the SAW element side to the O.D. Irradiation was performed for 6 seconds, and at the same time, a load of 300 g was applied to join the terminal conductors 131 to 136 and the connection conductor 21 of the substrate 2. Thereafter, the lateral pressing strength of each of the samples A to H was measured, and the cross section was observed with an electron microscope.

【0054】その後、熱衝撃試験を行った。熱衝撃試験
は、一40℃の温度で30分間保持し、85℃の温度で
30分間保持するサイクルを1サイクルとして、100
サイクルまで行った。熱衝撃試験の評価に当たって
は、、挿入損失の測定を行い、初期に2dB程度であっ
たものが、5dB以上となったものを不合格とし、その
個数で判断した。表2にその結果を示す。
Thereafter, a thermal shock test was performed. The thermal shock test was conducted at a temperature of 140 ° C. for 30 minutes and a temperature of 85 ° C. for 30 minutes as one cycle.
It went up to the cycle. In the evaluation of the thermal shock test, the insertion loss was measured, and the insertion loss was about 2 dB in the initial stage, and the one that became 5 dB or more was rejected, and the number was judged. Table 2 shows the results.

【0055】表2に示すように、端子導体131〜13
6が第1の楕円線OV11と第2の楕円線OV12の間
の領域に入っている試料A〜C、E、G、Hは良好な特
性を示しているが、これを外れる試料D、Fは表2に示
すように、熱衝撃特性の劣化による不合格数が著しく増
大した。
As shown in Table 2, the terminal conductors 131 to 13
Samples A to C, E, G, and H in which the sample No. 6 is in the region between the first elliptical line OV11 and the second elliptical line OV12 show good characteristics, but the samples D and F deviate from these. As shown in Table 2, as shown in Table 2, the number of rejects due to the deterioration of the thermal shock characteristics was significantly increased.

【0056】[0056]

【発明の効果】以上述べたように、本発明によれば、単
結晶チップの熱膨張率の異方性による影響を極力小さく
して、耐熱衝撃特性及び信頼性を向上させたSAW素子
及びこのSAW素子を組み込んだ電子部品を提供するこ
とができる。
As described above, according to the present invention, a SAW element having improved thermal shock resistance and reliability by minimizing the influence of the anisotropy of the coefficient of thermal expansion of a single crystal chip, and a SAW element having improved reliability. An electronic component incorporating a SAW element can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る電子部品の正面図である。FIG. 1 is a front view of an electronic component according to the present invention.

【図2】図1に示した電子部品に含まれるSAW素子
を、電極形成面側から見た平面図である。
FIG. 2 is a plan view of a SAW element included in the electronic component shown in FIG. 1, as viewed from an electrode forming surface side.

【図3】本発明の第2の態様に係るSAW素子(試料
A)を電極形成面側から見た平面図である。
FIG. 3 is a plan view of a SAW element (sample A) according to a second embodiment of the present invention as viewed from an electrode forming surface side.

【図4】本発明の第2の態様に係る別のSAW素子(試
料B)を電極形成面側から見た平面図である。
FIG. 4 is a plan view of another SAW element (sample B) according to a second embodiment of the present invention as viewed from an electrode forming surface side.

【図5】本発明の第2の態様に係る別のSAW素子(試
料C)を電極形成面側から見た平面図である。
FIG. 5 is a plan view of another SAW element (sample C) according to a second embodiment of the present invention, as viewed from an electrode forming surface side.

【図6】本発明の第2の態様に係るSAW素子と比較さ
れるSAW素子(試料D)を電極形成面側から見た平面
図である。
FIG. 6 is a plan view of a SAW element (sample D) to be compared with the SAW element according to the second embodiment of the present invention, as viewed from an electrode forming surface side.

【図7】本発明の第2の態様に係る別のSAW素子(試
料E)を電極形成面側から見た平面図である。
FIG. 7 is a plan view of another SAW element (sample E) according to the second embodiment of the present invention as viewed from an electrode forming surface side.

【図8】本発明の第2の態様に係るSAW素子と比較さ
れるSAW素子(試料F)を電極形成面側から見た平面
図である。
FIG. 8 is a plan view of a SAW element (sample F) to be compared with the SAW element according to the second embodiment of the present invention, as viewed from the electrode forming surface side.

【図9】本発明の第2の態様に係る別のSAW素子(試
料G)を電極形成面側から見た平面図である。
FIG. 9 is a plan view of another SAW element (sample G) according to the second embodiment of the present invention, as viewed from an electrode forming surface side.

【図10】本発明の第2の態様に係る別のSAW素子
(試料H)を電極形成面側から見た平面図である。
FIG. 10 is a plan view of another SAW element (sample H) according to the second embodiment of the present invention, as viewed from an electrode forming surface side.

【図11】従来のSAW素子を電極形成面側から見た平
面図である。
FIG. 11 is a plan view of a conventional SAW element viewed from an electrode forming surface side.

【符号の説明】[Explanation of symbols]

1 SAW素子 11 単結晶チップ 12 電極 131〜136 端子導体 2 基板 21 接続導体 DESCRIPTION OF SYMBOLS 1 SAW element 11 Single crystal chip 12 Electrode 131-136 Terminal conductor 2 Substrate 21 Connection conductor

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H03H 3/08 H01L 41/08 U 9/145 C 41/22 Z ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H03H 3/08 H01L 41/08 U 9/145 C 41/22 Z

Claims (14)

【特許請求の範囲】[Claims] 【請求項1】 単結晶チップと、電極と、複数の端子導
体とを含む表面弾性波素子であって、 前記電極は、前記単結晶チップの一面上に備えられてお
り、 前記端子導体のそれぞれは、前記単結晶チップの前記一
面上に想定された同一の楕円線上に載るように、前記単
結晶チップの前記一面上に備えられ、前記電極に電気的
に導通し、 前記楕円線は、前記単結晶チップの熱膨張係数の大きい
方向に対して短径を持つ表面弾性波素子。
1. A surface acoustic wave device including a single crystal chip, an electrode, and a plurality of terminal conductors, wherein the electrode is provided on one surface of the single crystal chip, and each of the terminal conductors Is provided on the one surface of the single crystal chip so as to be placed on the same elliptical line assumed on the one surface of the single crystal chip, and is electrically connected to the electrode. A surface acoustic wave device having a minor axis in the direction of a large thermal expansion coefficient of a single crystal chip.
【請求項2】 請求項1に記載された表面弾性波素子で
あって、前記楕円線は、短径aと長径bの比(a:b)
が約1:2である表面弾性波素子。
2. The surface acoustic wave device according to claim 1, wherein the elliptical line is a ratio (a: b) of a minor axis a to a major axis b.
Is about 1: 2.
【請求項3】 単結晶チップと、電極と、複数の端子導
体とを含む表面弾性波素子であって、 前記電極は、前記単結晶チップの一面上に備えられてお
り、 前記単結晶チップの前記一面上に、第1の楕円線及び第
2の楕円線を想定したとき、前記第1の楕円線は中心が
第2の楕円線の中心とほぼ一致し、長径及び短径が前記
第2の楕円線のそれよりも小さくなっており、 前記第1及び前記第2の楕円線は、前記単結晶チップの
熱膨張係数の大きい方向に対して短径を持っており、 前記端子導体のそれぞれは、前記電極に電気的に導通
し、中心が、前記第1の楕円線と前記第2の楕円線との
間の領域内にある表面弾性波素子。
3. A surface acoustic wave device including a single crystal chip, an electrode, and a plurality of terminal conductors, wherein the electrode is provided on one surface of the single crystal chip. Assuming a first ellipse and a second ellipse on the one surface, the center of the first ellipse substantially coincides with the center of the second ellipse, and the major axis and the minor axis are the second ellipse. The first and second elliptical lines have a shorter diameter in a direction in which the coefficient of thermal expansion of the single crystal chip is larger, and each of the terminal conductors Is a surface acoustic wave device that is electrically connected to the electrode and whose center is in a region between the first elliptic line and the second elliptical line.
【請求項4】 請求項3に記載された表面弾性波素子で
あって、 前記第1の楕円線は、長径の長さが前記単結晶チップの
前記長辺長の約60%であり、 前記第2の楕円線は、長径の長さが前記単結晶チップの
前記長辺長の約90%である表面弾性波素子。
4. The surface acoustic wave device according to claim 3, wherein a length of a major axis of the first elliptical line is about 60% of a length of the long side of the single crystal chip. The second elliptical line is a surface acoustic wave device in which the length of the major axis is about 90% of the length of the long side of the single crystal chip.
【請求項5】 請求項1乃至4の何れかに記載された表
面弾性波素子であって、 前記単結晶チップは、略四角形状であって、相対する2
辺の長辺と、相対する2辺の短辺とを有しており、 前記楕円線は、長径の方向が、前記長辺の延びる方向に
一致する表面弾性波素子。
5. The surface acoustic wave device according to claim 1, wherein the single-crystal chip has a substantially square shape,
A surface acoustic wave device having a long side and two opposite short sides, wherein the elliptical line has a major axis whose direction coincides with a direction in which the long side extends.
【請求項6】 請求項1乃至5の何れかに記載された表
面弾性波素子であって、前記端子導体は、表面がAu膜
である表面波弾性素子。
6. The surface acoustic wave device according to claim 1, wherein a surface of said terminal conductor is an Au film.
【請求項7】 基板と、表面弾性波素子とを含む電子部
品であって、 前記基板は、一面に複数の接続導体を有しており、 前記表面弾性波素子は、請求項1乃至6の何れかに記載
されたものでなり、前記電極及び端子導体を形成した前
記一面が、前記基板の前記一面に対向するように配置さ
れ、前記端子導体が前記接続導体に接続されている電子
部品。
7. An electronic component including a substrate and a surface acoustic wave device, wherein the substrate has a plurality of connection conductors on one surface, and wherein the surface acoustic wave device is An electronic component according to any one of the above, wherein the one surface on which the electrode and the terminal conductor are formed is arranged so as to face the one surface of the substrate, and the terminal conductor is connected to the connection conductor.
【請求項8】 請求項7に記載された電子部品であっ
て、前記基板は、セラミックスを主成分とする電子部
品。
8. The electronic component according to claim 7, wherein the substrate is mainly composed of ceramics.
【請求項9】 請求項7または8の何れかに記載された
電子部品であって、前記接続導体は、前記表面弾性波素
子に備えられた前記端子導体の配置に対応する位置に配
置されている電子部品。
9. The electronic component according to claim 7, wherein the connection conductor is arranged at a position corresponding to an arrangement of the terminal conductor provided on the surface acoustic wave device. Electronic components.
【請求項10】 請求項9に記載された電子部品であっ
て、前記接続導体は、表面がAu膜でなる電子部品。
10. The electronic component according to claim 9, wherein a surface of the connection conductor is made of an Au film.
【請求項11】 基板と、表面弾性波素子とを含む電子
部品を製造する方法であって、 前記基板は、一面に複数の接続導体を有しており、 前記表面弾性波素子は、請求項1乃至6の何れかに記載
されたものでなり、 前記表面弾性波素子を、前記電極及び端子導体を形成し
た前記一面が、前記基板の前記一面に対向するように配
置し、 前記表面波弾性素子上の前記端子導体を、前記基板上の
前記接続導体上に、荷重をかけて接触させ、 前記端子導体及び前記接続導体を、超音波によって接続
する工程を含む製造方法。
11. A method of manufacturing an electronic component including a substrate and a surface acoustic wave device, wherein the substrate has a plurality of connection conductors on one surface, and wherein the surface acoustic wave device is 7. The surface acoustic wave device according to any one of 1 to 6, wherein the surface acoustic wave element is disposed such that the one surface on which the electrode and the terminal conductor are formed is opposed to the one surface of the substrate, A manufacturing method comprising: a step of bringing the terminal conductor on an element into contact with the connection conductor on the substrate by applying a load, and connecting the terminal conductor and the connection conductor by ultrasonic waves.
【請求項12】 請求項11に記載された製造方法であ
って、前記基板は、セラミックスを主成分とする製造方
法。
12. The manufacturing method according to claim 11, wherein the substrate is mainly composed of ceramics.
【請求項13】 請求項11または12の何れかに記載
された製造方法であって、前記接続導体は、前記表面弾
性波素子に備えられた前記端子導体の配置に対応する位
置に配置されている製造方法。
13. The manufacturing method according to claim 11, wherein the connection conductor is arranged at a position corresponding to an arrangement of the terminal conductor provided on the surface acoustic wave element. Manufacturing method.
【請求項14】 請求項11乃至13の何れかに記載さ
れた製造方法であって、前記接続導体は、表面がAu膜
でなる製造方法。
14. The method according to claim 11, wherein the surface of the connection conductor is made of an Au film.
JP2000316470A 2000-10-17 2000-10-17 Surface acoustic wave element, electronic component and its mounting method Withdrawn JP2002124848A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299996A (en) * 2001-03-30 2002-10-11 Kyocera Corp Electronic component device
JP2008508739A (en) * 2004-08-04 2008-03-21 エプコス アクチエンゲゼルシャフト Flip chip electrical element
JP2020065158A (en) * 2018-10-17 2020-04-23 太陽誘電株式会社 Acoustic wave device and composite substrate
JP2020201134A (en) * 2019-06-11 2020-12-17 新日本無線株式会社 Elastic surface wave sensor and measurement system using the same
JP2022002260A (en) * 2020-06-22 2022-01-06 株式会社村田製作所 Surface-mounted passive component

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299996A (en) * 2001-03-30 2002-10-11 Kyocera Corp Electronic component device
JP2008508739A (en) * 2004-08-04 2008-03-21 エプコス アクチエンゲゼルシャフト Flip chip electrical element
JP2020065158A (en) * 2018-10-17 2020-04-23 太陽誘電株式会社 Acoustic wave device and composite substrate
JP7199195B2 (en) 2018-10-17 2023-01-05 太陽誘電株式会社 Acoustic wave devices and composite substrates
JP2020201134A (en) * 2019-06-11 2020-12-17 新日本無線株式会社 Elastic surface wave sensor and measurement system using the same
JP7235378B2 (en) 2019-06-11 2023-03-08 日清紡マイクロデバイス株式会社 Surface acoustic wave sensor and measurement system using it
JP2022002260A (en) * 2020-06-22 2022-01-06 株式会社村田製作所 Surface-mounted passive component
CN114093592A (en) * 2020-06-22 2022-02-25 株式会社村田制作所 Surface mounting type passive component

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