JP3283119B2 - Circuit board - Google Patents

Circuit board

Info

Publication number
JP3283119B2
JP3283119B2 JP23512793A JP23512793A JP3283119B2 JP 3283119 B2 JP3283119 B2 JP 3283119B2 JP 23512793 A JP23512793 A JP 23512793A JP 23512793 A JP23512793 A JP 23512793A JP 3283119 B2 JP3283119 B2 JP 3283119B2
Authority
JP
Japan
Prior art keywords
conductive layer
circuit board
ceramic substrate
lead
active metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23512793A
Other languages
Japanese (ja)
Other versions
JPH0794623A (en
Inventor
和男 池田
隆之 那波
高志 日野
成敬 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23512793A priority Critical patent/JP3283119B2/en
Publication of JPH0794623A publication Critical patent/JPH0794623A/en
Application granted granted Critical
Publication of JP3283119B2 publication Critical patent/JP3283119B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体素子等に使用され
る回路基板に係り、特に動作中に作用する熱サイクルに
よって基板にクラックが発生することが少なく、信頼性
が高く、また容易に製造することが可能な回路基板に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board used for a semiconductor device or the like, and more particularly to a circuit board which is hardly cracked by a thermal cycle acting during operation, has high reliability, and is easily manufactured. The present invention relates to a circuit board capable of doing so.

【0002】[0002]

【従来の技術】近年、絶縁材としてのセラミックス基板
に、銅または銅合金から成る導電層を直接接合した回路
基板の実用化が試みられている。この回路基板1は、図
3に示すように、例えば酸化アルミニウム(アルミナ:
Al2 3 )などのセラミックス基板2表面の所定位置
に、CuまたはCu合金から成る導電層3a,3bを配
置し、基板方向に押圧した状態で銅と酸素との共晶温度
以上に加熱し、生成したCu−O共晶液相を接合剤とし
て利用し、導電層3a,3bを直接的に接合する銅直接
接合法(Direct Bonding Copper 法)によって製造され
る。また導電層3a上部には導出端子4の一端が接合さ
れる。
2. Description of the Related Art In recent years, practical use of a circuit board in which a conductive layer made of copper or a copper alloy is directly joined to a ceramic substrate as an insulating material has been attempted. As shown in FIG. 3, the circuit board 1 is made of, for example, aluminum oxide (alumina:
Conductive layers 3a, 3b made of Cu or Cu alloy are arranged at predetermined positions on the surface of a ceramic substrate 2 such as Al 2 O 3 ), and heated to a temperature higher than the eutectic temperature of copper and oxygen in a state pressed in the substrate direction. The Cu—O eutectic liquid phase thus generated is used as a bonding agent, and is manufactured by a direct bonding copper method for directly bonding the conductive layers 3a and 3b. One end of the lead terminal 4 is joined to the upper part of the conductive layer 3a.

【0003】上記回路基板1によれば導電層3a,3b
とセラミックス基板2との間に、汎用の接着剤等の介在
物が存在しないため、両者間の熱抵抗が小さく、導電層
3a,3b上に設けられた半導体素子の発熱を系外に迅
速に放散させることが可能である。
According to the circuit board 1, the conductive layers 3a, 3b
Since there is no intervening material such as a general-purpose adhesive between the ceramic substrate 2 and the ceramic substrate 2, the thermal resistance between the two is small, and the heat generated by the semiconductor elements provided on the conductive layers 3a and 3b is quickly discharged to the outside of the system. It is possible to dissipate.

【0004】しかしながら、上記導電層3aに接続され
た導出端子4は半導体素子の作動に伴い繰り返しの熱衝
撃を受けて伸縮するために、導出端子4の接合部付近の
セラミックス基板2にクラックが発生し易く、耐久性が
低い欠点があった。その対策として図3に示すように、
導出端子4を接合した導電層3a部分とセラミックス基
板2との間に空間部分5を形成し、この空間部分5によ
り導出端子4の熱変形を吸収する構造も採用されてい
る。
However, the lead terminal 4 connected to the conductive layer 3a expands and contracts due to repeated thermal shock accompanying the operation of the semiconductor element, so that cracks occur in the ceramic substrate 2 near the joint of the lead terminal 4. There was a defect that it was easy to perform and had low durability. As a countermeasure, as shown in FIG.
There is also employed a structure in which a space portion 5 is formed between the conductive layer 3a to which the lead-out terminal 4 is joined and the ceramic substrate 2, and the space portion 5 absorbs thermal deformation of the lead-out terminal 4.

【0005】[0005]

【発明が解決しようとする課題】しかしながら上記構成
に係る回路基板においては、導出端子4を接合した導電
層3a部分が、セラミックス基板2表面に接合しないよ
うに、高さが0.3〜0.5mm程度の空間部分5をプレ
ス成形等によって形成することが必須となり、必然的に
製造コストが上昇する欠点があった。
However, in the circuit board according to the above configuration, the height of the conductive layer 3a to which the lead-out terminal 4 is joined is set to 0.3 to 0. It is essential to form the space portion 5 having a size of about 5 mm by press molding or the like, which inevitably increases the manufacturing cost.

【0006】また突出した空間部分5を設けたために導
電層3aが平坦にならず、銅直接接合法によって接合す
る際に導電層3a全体をセラミックス基板2表面に均一
に押圧することが困難になり、導電層3aの接合強度に
ばらつきを生じる問題点がある。
Further, since the protruding space portion 5 is provided, the conductive layer 3a is not flattened, and it is difficult to uniformly press the entire conductive layer 3a against the surface of the ceramic substrate 2 when joining by the copper direct joining method. In addition, there is a problem that the bonding strength of the conductive layer 3a varies.

【0007】さらに空間部分5をプレス加工にて形成す
る際に、空間部分5に対応する部分の導電層3aの肉厚
が減少し易く、導電層3a部分の通電容量が低下してし
まう問題点があった。
Further, when the space portion 5 is formed by press working, the thickness of the conductive layer 3a corresponding to the space portion 5 tends to decrease, and the current carrying capacity of the conductive layer 3a decreases. was there.

【0008】一方、半導体装置および電子機器の小型化
と歩調を合せて、半導体素子等の電子部品の高集積化お
よび高出力化が進行し、動作時における電子部品からの
発熱量も比例して増大し、より耐熱サイクル性、放熱特
性および耐久性が優れた回路基板の開発が要請されてい
る。
On the other hand, in accordance with miniaturization of semiconductor devices and electronic equipment, electronic components such as semiconductor elements have been becoming more highly integrated and higher in output, and the amount of heat generated from the electronic components during operation has been proportionally increased. There is an increasing demand for the development of circuit boards having better heat cycle resistance, heat radiation characteristics, and durability.

【0009】本発明は上記課題を解決するためになされ
たものであり、半導体素子の作動中にセラミックス基板
の割れや導電層の剥離が発生せず、信頼性が高い回路基
板を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a highly reliable circuit board which does not crack the ceramic substrate or peel off the conductive layer during operation of the semiconductor element. Aim.

【0010】[0010]

【課題を解決するための手段】本発明者らは上記目的を
達成するため、セラミックス基板にクラックが発生する
現象を解明し、次のような知見を得た。すなわちセラミ
ックス基板と銅製導電層との熱膨脹差は100〜140
×10-7/℃と大きく、このようなセラミックス基板に
銅製導電層を一体に接合した回路基板においては、両者
の接合面に熱膨脹差による熱応力を生じ、この熱応力が
セラミックス基板の強度以上となるとセラミックス基板
が破壊する。そこでセラミックス基板と銅製導電層との
間で発生する熱応力が小さくなるように両者の板厚を選
定し、無理のない状態で使用している。
Means for Solving the Problems In order to achieve the above object, the present inventors have clarified a phenomenon in which a crack occurs in a ceramic substrate and obtained the following knowledge. That is, the thermal expansion difference between the ceramic substrate and the copper conductive layer is 100 to 140.
× 10 -7 / ° C. In a circuit board in which a copper conductive layer is integrally bonded to such a ceramic substrate, a thermal stress is generated due to a difference in thermal expansion between the two bonded surfaces, and the thermal stress is higher than the strength of the ceramic substrate. Then, the ceramic substrate is broken. Therefore, the thicknesses of the ceramic substrate and the copper conductive layer are selected so as to reduce the thermal stress generated between the ceramic substrate and the copper conductive layer.

【0011】しかしながら、上記セラミックス基板に半
導体素子を実装した状態では、外部回路と接続するため
の導出端子が銅製導電層に接合され、この接合部におい
て熱応力が局部的に増大することになる。したがってこ
の状態で半導体素子を作動させ、温度上昇−下降サイク
ルを繰り返すと、導出端子付近のセラミックス基板に過
大な熱応力が作用し、基板が破壊に至ることを確認し
た。
However, when the semiconductor element is mounted on the ceramic substrate, a lead terminal for connecting to an external circuit is joined to the copper conductive layer, and the thermal stress locally increases at this joint. Therefore, it was confirmed that when the semiconductor element was operated in this state and the temperature rise-fall cycle was repeated, an excessive thermal stress acted on the ceramic substrate near the lead-out terminal and the substrate was broken.

【0012】そして本発明者らは導出端子部分の導電層
の接合構造を工夫することにより、接合部分の熱応力を
大幅に緩和することに成功した。すなわち、活性金属を
含有する接合剤組成物(活性金属ペースト)を所定形状
に基板表面に印刷し、導出端子接合部分を除く導電層
を、活性金属層を介してセラミックス基板に接合したと
きに、導電層とセラミックス基板との接合強度が高まる
とともに、セラミックス基板の割れを大幅に低減するこ
とが可能になった。また上記活性金属層を介する接合構
造によれば、平板状の導電層をそのまま接合する場合に
おいても、未接合部を容易に形成することが可能となる
ことが判明した。本発明は上記知見に基づいて完成され
たものである。
The inventors of the present invention have succeeded in relieving the thermal stress in the joint portion significantly by devising the joint structure of the conductive layer in the lead terminal portion. That is, when a bonding agent composition (active metal paste) containing an active metal is printed on a substrate surface in a predetermined shape, and a conductive layer except for a lead terminal bonding portion is bonded to a ceramic substrate via the active metal layer, The joint strength between the conductive layer and the ceramic substrate has been increased, and the cracking of the ceramic substrate has been greatly reduced. In addition, it has been found that according to the bonding structure with the active metal layer interposed therebetween, it is possible to easily form an unbonded portion even when a flat conductive layer is bonded as it is. The present invention has been completed based on the above findings.

【0013】すなわち本発明に係る回路基板は、セラミ
ックス基板の表面に形成された活性金属層を介して平板
状の導電層がセラミックス基板に一体に接合され、上記
導電層に導出端子が接続されるとともに、上記導出端子
を接続した導電層とセラミックス基板との間に未接合部
を設けたことを特徴とする。また活性金属層は、Ti,
Zr,HfおよびNbから選択される少くとも1種の活
性金属を含有するろう材から構成するとよい。さらに導
出端子は湾曲部を有し、この湾曲部において軸方向に伸
縮自在に構成するとよい。またセラミックス基板は、酸
化アルミニウム(Al)、窒化アルミニウム(A
lN)、酸化ベリリウム(BeO),炭化けい素(Si
C)および窒化けい素(Si)から選択される少
なくとも1種のセラミックス材料で形成する。
That is, in the circuit board according to the present invention, a flat conductive layer is integrally joined to the ceramic substrate via the active metal layer formed on the surface of the ceramic substrate, and a lead terminal is connected to the conductive layer. In addition, an unbonded portion is provided between the conductive layer to which the lead-out terminal is connected and the ceramic substrate. The active metal layer is made of Ti,
It is preferable to use a brazing material containing at least one active metal selected from Zr, Hf and Nb. Further, the lead-out terminal may have a curved portion, and the curved portion may be configured to be able to expand and contract in the axial direction. The ceramic substrate is made of aluminum oxide (Al 2 O 3 ), aluminum nitride (A
1N), beryllium oxide (BeO), silicon carbide (Si
C) and at least one type of ceramic material selected from silicon nitride (Si 3 N 4 ).

【0014】本発明の回路基板に使用するセラミックス
基板としては、電気絶縁特性に優れた酸化アルミニウム
(Al2 3 )を使用することができる。特に放熱性に
優れた回路基板を形成するためには、熱伝導率が高い窒
化アルミニウム(AlN)、酸化ベリリウム(Be
O)、炭化けい素(SiC)が好ましい。なお、炭化け
い素は絶縁抵抗がやや低い一方、酸化ベリリウムは毒性
の点で難点がある。したがって、電気絶縁性および放熱
性に共に優れた回路基板を形成するためにはセラミック
ス基板として窒化アルミニウムを使用することが望まし
い。またセラミックス基板の厚さを0.3〜1mmの範囲
とする一方、後述する導電層の厚さを0.1〜0.5mm
の範囲に設定して両者を組み合せると、熱膨脹差による
影響を受けにくくなる。
As the ceramic substrate used for the circuit board of the present invention, aluminum oxide (Al 2 O 3 ) having excellent electric insulation properties can be used. In particular, in order to form a circuit board having excellent heat dissipation, aluminum nitride (AlN) and beryllium oxide (Be) having high thermal conductivity are required.
O) and silicon carbide (SiC) are preferred. In addition, silicon carbide has a somewhat low insulation resistance, while beryllium oxide has a problem in toxicity. Therefore, it is desirable to use aluminum nitride as the ceramic substrate in order to form a circuit board having both excellent electrical insulation and heat dissipation. Also, while the thickness of the ceramic substrate is in the range of 0.3 to 1 mm, the thickness of the conductive layer described later is 0.1 to 0.5 mm.
When they are set in the range described above, they are hardly affected by the difference in thermal expansion.

【0015】本発明に係る回路基板において、平板状の
導電層の接合を行なうために形成される活性金属層は、
Ti,Zr,HfおよびNb等の活性金属を含有し適切
な組成比を有するAg−Cu−Ti系ろう材等で構成さ
れ、このろう材組成物を有機溶媒中に分散して調製した
接合用組成物ペーストをセラミックス基板表面にスクリ
ーン印刷する等の方法で形成される。
[0015] In the circuit board according to the present invention, the active metal layer formed for bonding the flat conductive layer includes:
It is composed of an Ag-Cu-Ti brazing material or the like containing an active metal such as Ti, Zr, Hf and Nb and having an appropriate composition ratio, and is prepared by dispersing this brazing material composition in an organic solvent. The composition paste is formed by a method such as screen printing on the surface of the ceramic substrate.

【0016】上記接合用組成物ペーストの具体例として
は、下記のようなものがある。すなわち重量%でCuを
15〜35%、Ti、Zr、HfおよびNbから選択さ
れる少くとも1種の活性金属を1〜10%、残部が実質
的にAgから成る組成物を有機溶媒中に分散して調製し
た接合用組成物ペースト、または重量%でCuを15〜
35%、Ti、Zr、HfおよびNbから選択される少
くとも1種の活性金属を1〜10%、W,Mo,Al
N,Si3 4 およびBNから選択される少くとも1種
を5〜40%含有し、残部が実質的にAgから成る組成
物を有機溶媒中に分散して調製した接合用組成物ペース
トを使用するとよい。
The following are specific examples of the bonding composition paste. That is, a composition consisting of 15 to 35% by weight of Cu, 1 to 10% of at least one active metal selected from Ti, Zr, Hf and Nb, and a balance substantially composed of Ag is prepared in an organic solvent. A bonding composition paste prepared by dispersion, or 15% by weight of Cu
35%, 1 to 10% of at least one active metal selected from Ti, Zr, Hf and Nb, W, Mo, Al
A bonding composition paste prepared by dispersing a composition containing 5 to 40% of at least one selected from N, Si 3 N 4 and BN and substantially consisting of Ag in an organic solvent in an organic solvent. Good to use.

【0017】上記活性金属はセラミックス基板に対する
ろう材の濡れ性を改善するための成分であり、特に窒化
アルミニウム(AlN)基板に対して有効である。それ
らの活性金属の配合量は、接合用組成物全体に対して1
〜10重量%が適量である。W,Mo,AlN,Si3
4 およびBNは、セラミックス基板と導電層との接合
部における応力緩和を図るために有効な成分であり、5
〜40重量%添加される。すなわちセラミックス基板と
導電層とを接合する場合において、両部材の熱膨脹係数
差に起因する残留熱応力を緩和するため、接合用組成物
に、セラミックス基板と金属とを接合する反応層を形成
させる作用の他に、反応層自身に応力緩和作用をもたせ
ることが有効である。
The active metal is a component for improving the wettability of the brazing material to the ceramic substrate, and is particularly effective for an aluminum nitride (AlN) substrate. The amount of the active metal is 1 to the entire bonding composition.
An appropriate amount is 10 to 10% by weight. W, Mo, AlN, Si 3
N 4 and BN are effective components for relaxing stress at the joint between the ceramic substrate and the conductive layer.
~ 40% by weight is added. In other words, when a ceramic substrate and a conductive layer are joined, an action of forming a reaction layer for joining the ceramic substrate and the metal to the joining composition in order to reduce residual thermal stress caused by a difference in thermal expansion coefficient between the two members. In addition, it is effective to have the reaction layer itself have a stress relaxation effect.

【0018】本発明では、接合用組成物の成分として、
導電性を有するAg−Cuを主体にしたろう材に、熱膨
脹係数がセラミックス基板に比較的に近いW,Mo,A
lN,Si3 4 ,BNを添加することにより、反応層
に応力緩和作用を発揮させ、高い接合強度を有し、かつ
熱衝撃試験(TCT)特性に優れた回路基板を得ること
ができる。特にセラミックス基板が窒化アルミニウム
(AlN)焼結体の場合には、Ag−Cuろう材にW,
Mo,AlNを添加したろう材を使用すると割れや剥離
が少ない接合体を得ることができる。
In the present invention, as components of the bonding composition,
A brazing material mainly composed of conductive Ag-Cu is added to W, Mo, A having a coefficient of thermal expansion relatively close to that of a ceramic substrate.
By adding 1N, Si 3 N 4 , and BN, it is possible to obtain a circuit board having a high bonding strength and excellent thermal shock test (TCT) characteristics by exerting a stress relaxing action on the reaction layer. In particular, when the ceramic substrate is an aluminum nitride (AlN) sintered body, W,
When a brazing material to which Mo and AlN are added is used, a joined body with less cracking and peeling can be obtained.

【0019】導電性を発揮するAg−Cu成分は、セラ
ミックス基板とTiとの接合層の形成を促進する成分と
して有効であり、Tiを拡散させ強固な接合体を形成す
るのに寄与するのみならず、導体層としての微細な回路
を形成する材料ともなる。
The Ag-Cu component exhibiting conductivity is effective as a component for promoting the formation of a bonding layer between the ceramic substrate and Ti, and only contributes to the diffusion of Ti to form a strong bonded body. Instead, it is also a material for forming a fine circuit as a conductor layer.

【0020】また本発明のように、微細な導電層パター
ンを接合用組成物によって形成する場合には、生成する
液相の流れによってパターンがくずれることを防止する
ために、Ag−Cu成分が共晶組成物(72wt%Ag
−28Cu)を生成し易い組成比から離れた組成比を有
する接合用組成物を使用し、液相の生成量を低減するこ
とが肝要である。すなわち、ろう接合時に加熱昇温する
温度700〜950℃の範囲で必要最少量の液相を生成
する金属成分を含む化合物系で構成された接合用組成物
を使用することが重要となる。
In the case where a fine conductive layer pattern is formed of the bonding composition as in the present invention, the Ag-Cu component is used in order to prevent the pattern from being broken by the flow of the generated liquid phase. Crystal composition (72 wt% Ag)
It is important to use a bonding composition having a composition ratio deviating from the composition ratio at which −28Cu) is easily generated, and to reduce the amount of liquid phase generated. That is, it is important to use a bonding composition composed of a compound system containing a metal component that generates a minimum necessary liquid phase in a temperature range of 700 to 950 ° C. at which the temperature rises during brazing.

【0021】一方、導電層および導出端子の構成材とし
ては、導電性および熱膨脹性を考慮して、Cu,Cu合
金,53Fe−28Ni−18Co(コバール合金)等
のFe−Ni−Co合金,42Ni−Fe等のFe−N
i合金,Cu−Mo−Cuクラッド材,Cu−(Fe−
Ni−Co合金)−Cuクラッド材等が好適である。特
に上記コバール合金や42Ni−Fe合金はセラミック
ス基板に近似した低い熱膨脹係数を有しており、基板と
導電層との熱膨脹差に起因する疲労劣化を効果的に防止
することができる。
On the other hand, as the constituent materials of the conductive layer and the lead-out terminal, Cu, Cu alloy, Fe—Ni—Co alloy such as 53Fe-28Ni-18Co (Kovar alloy), 42Ni -Fe-N such as Fe
i-alloy, Cu-Mo-Cu clad material, Cu- (Fe-
A Ni-Co alloy) -Cu clad material or the like is preferable. In particular, the above-mentioned Kovar alloy and 42Ni-Fe alloy have a low coefficient of thermal expansion close to that of a ceramic substrate, and can effectively prevent fatigue deterioration due to a difference in thermal expansion between the substrate and the conductive layer.

【0022】また導出端子の途中に複数の切込み等を形
成することにより、湾曲部を形成し、この湾曲部におい
て導出端子が伸縮自在となるように構成し、導出端子自
体に伸縮機能をもたせて熱膨脹の影響を低減することも
効果的である。すなわち導電層に接合した導出端子に湾
曲部を形成し、熱応力を緩和吸収する構造を採用するこ
とにより、未接合部による応力吸収効果と相俟ってセラ
ミックス基板に作用する応力の影響を大幅に低減するこ
とができる。
Also, a curved portion is formed by forming a plurality of cuts or the like in the middle of the lead-out terminal, and the lead-out terminal is configured to be able to expand and contract at this bent portion. It is also effective to reduce the effects of thermal expansion. In other words, the effect of the stress acting on the ceramic substrate is significantly increased by forming a curved portion on the lead-out terminal joined to the conductive layer and adopting a structure that relaxes and absorbs thermal stress, in combination with the stress absorption effect of the unjoined portion. Can be reduced.

【0023】上記回路基板は、例えば次のような工程で
製造される。すなわち、未接合部を形成する部位を除い
たセラミックス基板表面に、前記接合用組成物ペースト
(活性金属ペースト)をスクリーン印刷法等によって塗
布し乾燥して活性金属層パターンを形成する。次に、こ
の活性金属層パターン上に導電層となる銅板等を接触配
置した状態で、真空中または不活性ガス雰囲気中で、例
えばAg−Cu共融温度である780℃以上、銅の融点
である1083℃以下の温度に加熱することにより、上
記導電層となる銅板等を活性金属層を介してセラミック
ス基板表面に一体に接合する。このとき接合用組成物ペ
ーストを塗布しない部分においては、導電層とセラミッ
クス基板とが接合されず未接合部を形成する。また未接
合部に対向した導電層表面に導出端子がろう接合され
る。
The circuit board is manufactured, for example, by the following steps. That is, the bonding composition paste (active metal paste) is applied by a screen printing method or the like to the surface of the ceramic substrate excluding a portion where an unbonded portion is to be formed, and dried to form an active metal layer pattern. Next, in a state where a copper plate or the like serving as a conductive layer is placed in contact with the active metal layer pattern, in a vacuum or an inert gas atmosphere, for example, at a melting point of 780 ° C. or higher, which is the Ag-Cu eutectic temperature, By heating to a certain temperature of 1083 ° C. or less, the copper plate or the like serving as the conductive layer is integrally joined to the surface of the ceramic substrate via the active metal layer. At this time, in a portion where the bonding composition paste is not applied, the conductive layer and the ceramic substrate are not bonded, and an unbonded portion is formed. In addition, the lead-out terminal is brazed to the surface of the conductive layer facing the unbonded portion.

【0024】上記活性金属層の厚さにほぼ等しい未接合
部の隙間幅は、0.01mm以上であれば、十分に熱応力
を吸収できる一方、隙間幅を0.3mmを超えるように設
定すると活性金属層の厚さが過大になり、基板と導電層
との間の熱抵抗が増大し、回路基板の放熱性が低下す
る。したがって未接合部の隙間幅は0.01〜0.3mm
の範囲が好適である。また導出端子の伸縮によってセラ
ミックス基板に作用する熱応力を低減するために、未接
合部の長さは、導出端子と導電層との接合部の長さより
大きくすることが望ましい。
If the gap width of the unbonded portion, which is substantially equal to the thickness of the active metal layer, is 0.01 mm or more, the thermal stress can be sufficiently absorbed, while the gap width is set to exceed 0.3 mm. The thickness of the active metal layer becomes excessive, the thermal resistance between the substrate and the conductive layer increases, and the heat dissipation of the circuit board decreases. Therefore, the gap width of the unjoined part is 0.01 to 0.3 mm
Is suitable. Further, in order to reduce thermal stress acting on the ceramic substrate due to expansion and contraction of the lead-out terminal, it is desirable that the length of the unbonded portion is larger than the length of the bond between the lead-out terminal and the conductive layer.

【0025】[0025]

【作用】上記構成に係る回路基板によれば、導出端子が
接続された導電層部分とセラミックス基板とが接合され
ず、両者間に未接合部が形成されているため、導出端子
に生じた熱応力は未接合部において吸収され、この熱応
力が直接セラミックス基板に作用することがない。した
がって、セラミックス基板の割れの発生が少なく、耐久
性に優れた回路基板を提供することができる。
According to the circuit board having the above-described structure, the conductive layer portion to which the lead-out terminal is connected and the ceramic substrate are not joined, and an unjoined portion is formed between the two. The stress is absorbed in the unjoined portion, and this thermal stress does not directly act on the ceramic substrate. Therefore, it is possible to provide a circuit board which is less likely to crack the ceramic substrate and has excellent durability.

【0026】また、未接合部を形成する部位を除くセラ
ミックス基板表面に接合用組成物ペーストを印刷し、印
刷された活性金属層パターンに、平板状の導電層を部分
的に接合することにより、未接合部が容易に形成するこ
とができる。特に突出したブリッジ部や凹凸部を形成し
ない平板状の導電層をそのまま使用した場合においても
未接合部が容易に形成でき、ブリッジ部等を形成した導
電層を使用する場合と比較して構成部品の加工工数が少
なく、回路基板を安価に製造できる。またプレス加工等
をせずに平板状の導電層をそのまま使用できるため、加
工による導電層の減肉がなく、導電層の通電容量が低下
するおそれもなくなる等、優れた効果が発揮される。
Further, by printing a bonding composition paste on the surface of the ceramic substrate excluding the portion where an unbonded portion is to be formed, and by partially bonding a flat conductive layer to the printed active metal layer pattern, An unbonded portion can be easily formed. In particular, even when a flat conductive layer having no protruding bridge portion or uneven portion is used as it is, an unbonded portion can be easily formed, and the component parts are compared with the case where a conductive layer having a bridge portion or the like is used. The number of processing steps is small, and a circuit board can be manufactured at low cost. In addition, since the flat conductive layer can be used as it is without performing press working or the like, excellent effects are exhibited, such as no reduction in the thickness of the conductive layer due to the processing, and no possibility that the conductive capacity of the conductive layer is reduced.

【0027】[0027]

【実施例】次に本発明の一実施例について添付図面を参
照して説明する。
An embodiment of the present invention will be described below with reference to the accompanying drawings.

【0028】実施例1 図1は実施例1に係る回路基板の構成示す斜視図、図2
は図1におけるII−II矢視部分断面図である。
Embodiment 1 FIG. 1 is a perspective view showing the structure of a circuit board according to Embodiment 1, and FIG.
FIG. 2 is a partial sectional view taken along the line II-II in FIG. 1.

【0029】すなわち実施例1に係る回路基板1aは、
セラミックス基板2aの表面に形成された活性金属層6
を介して平板状の導電層3c,3dがセラミックス基板
2aに一体に接合され、上記導電層3cに導出端子4a
が接続されるとともに、上記導出端子4aを接続した導
電層3cとセラミックス基板2aとの間に未接合部7を
設けて構成される。また導出端子4aの途中には複数の
切込み8が形成されて湾曲部9が形成されており、この
湾曲部9において導出端子4aが軸方向に伸縮自在とな
るよう構成されている。さらに導電層3dの表面には半
導体素子10が半田付けされている。
That is, the circuit board 1a according to the first embodiment
Active metal layer 6 formed on the surface of ceramic substrate 2a
The flat conductive layers 3c and 3d are integrally joined to the ceramics substrate 2a through the through hole, and the conductive terminal 3a is connected to the conductive layer 3c.
Are connected, and an unbonded portion 7 is provided between the conductive layer 3c to which the lead-out terminal 4a is connected and the ceramic substrate 2a. A plurality of cuts 8 are formed in the middle of the lead-out terminal 4a to form a curved portion 9, and the lead-out terminal 4a is configured to be able to expand and contract in the axial direction in the curved portion 9. Further, the semiconductor element 10 is soldered to the surface of the conductive layer 3d.

【0030】上記回路基板1aは下記のような手順で製
造した。すなわち厚さ0.6mmの窒化アルミニウム基板
2aの両面の所定位置、すなわち未接合部を形成する部
位を除いた表面に、30wt%Ag−65%Cu−5%
Tiろう材をスクリーン印刷し乾燥して活性金属層パタ
ーンを形成した。この活性金属層パターン上の所定位置
に導電層3c,3d,3eとしての平板状銅回路板を接
触配置させた状態で、真空中で温度850℃で10分間
保持し、接合体を得た。さらに銅から成る導出端子4a
を、導電層3cの未接合部7に対向する部位に半田接合
する一方、導電層3d表面に半導体素子10を半田接合
するとともに、半導体素子10の電極と導電層3cと
を、Au,Al等の金属細線11によって電気的に接続
して、実施例1に係る回路基板1aを調製した。
The circuit board 1a was manufactured in the following procedure. That is, 30 wt% Ag-65% Cu-5% is added to a predetermined position on both surfaces of the aluminum nitride substrate 2a having a thickness of 0.6 mm, that is, a surface excluding a portion where an unbonded portion is formed.
The Ti brazing material was screen printed and dried to form an active metal layer pattern. With the flat copper circuit boards as the conductive layers 3c, 3d, and 3e in contact with the predetermined positions on the active metal layer pattern, they were held in a vacuum at a temperature of 850 ° C. for 10 minutes to obtain a joined body. Lead terminal 4a made of copper
Is solder-bonded to a portion of the conductive layer 3c facing the unbonded portion 7, while the semiconductor element 10 is solder-bonded to the surface of the conductive layer 3d, and the electrodes of the semiconductor element 10 and the conductive layer 3c are connected to each other using Au, Al, or the like. The circuit board 1a according to Example 1 was prepared by electrically connecting with the thin metal wires 11 described above.

【0031】上記回路基板は、通常、樹脂ケース内に配
置され、その周囲にシリコン樹脂ゲル剤を充填した後
に、エポキシ樹脂等の熱硬化性樹脂で封止した状態で使
用される。
The above-mentioned circuit board is usually used in a state where it is placed in a resin case, and its periphery is filled with a silicone resin gel agent and then sealed with a thermosetting resin such as an epoxy resin.

【0032】そして上記回路基板1aの耐久性および信
頼性を評価するために下記のような熱衝撃試験(ヒート
サイクル試験:TCT)を実施し、回路基板におけるク
ラック発生状況を調査した。ヒートサイクル試験は、−
50℃から+150℃までの範囲で加熱し、引き続いて
+150℃から−50℃まで冷却するまでを1サイクル
とする昇温−降温サイクルを繰り返して付加するもので
ある。
Then, in order to evaluate the durability and reliability of the circuit board 1a, the following thermal shock test (heat cycle test: TCT) was performed, and the state of occurrence of cracks in the circuit board was investigated. Heat cycle test-
Heating is performed in the range of 50 ° C. to + 150 ° C., and subsequently, a heating and cooling cycle in which cooling is performed from + 150 ° C. to −50 ° C. as one cycle is repeatedly added.

【0033】その結果、実施例1に係る回路基板は、3
00サイクル経過後においても、AlN基板の割れや導
電層の剥離が皆無であり、優れた耐久性と信頼性とを有
することが確認された。
As a result, the circuit board according to the first embodiment
Even after the lapse of 00 cycles, there was no cracking of the AlN substrate or peeling of the conductive layer, and it was confirmed that the AlN substrate had excellent durability and reliability.

【0034】比較例1 実施例1において導電層3cに対向するAlN基板2a
全面に接合用組成物ペーストをスクリーン印刷して、未
接合部を形成せずに導電層3cを接合した以外は実施例
1と同様に処理して同一寸法を有する比較例1に係る回
路基板を製造した。
COMPARATIVE EXAMPLE 1 In Example 1, the AlN substrate 2a opposed to the conductive layer 3c
A circuit board according to Comparative Example 1 having the same dimensions was processed in the same manner as in Example 1 except that the bonding composition paste was screen-printed on the entire surface and the conductive layer 3c was bonded without forming an unbonded portion. Manufactured.

【0035】この比較例1に係る回路基板について、実
施例1と同一条件のTCT試験を実施したところ、10
0サイクル後において、58%の試料について導出端子
付近のAlN基板にクラックが発生し、実用に耐えない
ことが判明した。
A TCT test was performed on the circuit board according to Comparative Example 1 under the same conditions as in Example 1.
After 0 cycles, it was found that cracks occurred on the AlN substrate near the lead-out terminals for 58% of the samples, and the samples were not practical.

【0036】実施例2 厚さ0.8mmの窒化アルミニウム基板2aの両面の所定
位置、すなわち未接合部を形成する部位を除いた表面
に、30wt%Ag−65%Cu−5%Tiろう材をス
クリーン印刷し乾燥して活性金属層パターンを形成し
た。この活性金属層パターン上に平板状銅板を接触配置
させた状態で、真空中で温度850℃で10分間保持
し、接合体を得た。次に得られた接合体の銅板部をエッ
チング処理して、所定の回路パターンを有する導電層3
c,3d,3eを形成した。さらに銅から成る導出端子
4aを、導電層3cの未接合部7に対向する部位に半田
接合する一方、導電層3d表面に半導体素子10を半田
接合して、実施例2に係る回路基板を調製した。
Example 2 A 30 wt% Ag-65% Cu-5% Ti brazing material was applied to predetermined positions on both surfaces of an aluminum nitride substrate 2a having a thickness of 0.8 mm, that is, a surface excluding a portion where an unbonded portion was formed. The screen was printed and dried to form an active metal layer pattern. In a state where a flat copper plate was placed in contact with the active metal layer pattern, the plate was held at 850 ° C. for 10 minutes in a vacuum to obtain a joined body. Next, the copper plate portion of the obtained joined body is subjected to an etching treatment, so that the conductive layer 3 having a predetermined circuit pattern is formed.
c, 3d and 3e were formed. Further, the lead-out terminal 4a made of copper is solder-bonded to a portion of the conductive layer 3c facing the unbonded portion 7, and the semiconductor element 10 is solder-bonded to the surface of the conductive layer 3d to prepare the circuit board according to the second embodiment. did.

【0037】そして上記実施例2に係る回路基板の耐久
性および信頼性を評価するために実施例1と同一条件で
熱衝撃試験(ヒートサイクル試験:TCT)を実施し、
回路基板におけるクラック発生状況を調査した。
A thermal shock test (heat cycle test: TCT) was performed under the same conditions as in Example 1 in order to evaluate the durability and reliability of the circuit board according to Example 2 above.
The state of crack occurrence on the circuit board was investigated.

【0038】その結果、実施例2に係る回路基板は、3
00サイクル経過後においても、AlN基板の割れや導
電層の剥離が皆無であり、優れた耐久性と信頼性とを有
することが確認された。
As a result, the circuit board according to the second embodiment
Even after the lapse of 00 cycles, there was no cracking of the AlN substrate or peeling of the conductive layer, and it was confirmed that the AlN substrate had excellent durability and reliability.

【0039】比較例2 実施例2において導電層3cに対向するAlN基板2a
全面に接合用組成物ペーストをスクリーン印刷して、未
接合部を形成せずに導電層3cを接合した以外は実施例
2と同様に処理して同一寸法を有する比較例2に係る回
路基板を製造した。
COMPARATIVE EXAMPLE 2 In Example 2, the AlN substrate 2a opposed to the conductive layer 3c
A circuit board according to Comparative Example 2 having the same dimensions was processed in the same manner as in Example 2 except that the bonding composition paste was screen-printed on the entire surface and the conductive layer 3c was bonded without forming an unbonded portion. Manufactured.

【0040】この比較例2に係る回路基板について、実
施例2と同一条件でTCT試験を実施したところ、10
0サイクル後において、32%の試料について導出端子
付近のAlN基板にクラックが発生し、実用に耐えない
ことが判明した。
A TCT test was performed on the circuit board according to Comparative Example 2 under the same conditions as in Example 2.
After 0 cycles, it was found that cracks occurred in the AlN substrate near the lead-out terminal for 32% of the samples, and the samples were not practical.

【0041】[0041]

【発明の効果】以上の説明の通り、本発明に係る回路基
板によれば、導出端子が接続された導電層部分とセラミ
ックス基板とが接合されず、両者間に未接合部が形成さ
れているため、導出端子に生じた熱応力は未接合部にお
いて吸収され、この熱応力が直接セラミックス基板に作
用することがない。したがって、セラミックス基板の割
れの発生が少なく、耐久性に優れた回路基板を提供する
ことができる。
As described above, according to the circuit board of the present invention, the conductive layer portion to which the lead-out terminal is connected and the ceramic substrate are not joined, and an unjoined portion is formed therebetween. Therefore, the thermal stress generated in the lead-out terminal is absorbed in the unjoined portion, and the thermal stress does not directly act on the ceramic substrate. Therefore, it is possible to provide a circuit board which is less likely to crack the ceramic substrate and has excellent durability.

【0042】また、未接合部を形成する部位を除くセラ
ミックス基板表面に接合用組成物ペーストを印刷し、印
刷された活性金属層パターンに、平板状の導電層を部分
的に接合することにより、未接合部が容易に形成するこ
とができる。特に突出したブリッジ部や凹凸部を形成し
ない平板状の導電層をそのまま使用した場合においても
未接合部が容易に形成でき、ブリッジ部等を形成した導
電層を使用する場合と比較して構成部品の加工工数が少
なく、回路基板を安価に製造できる。またプレス加工等
をせずに平板状の導電層をそのまま使用できるため、加
工による導電層の減肉がなく、導電層の通電容量が低下
するおそれもなくなる等、優れた効果が発揮される。
Further, a bonding composition paste is printed on the surface of the ceramic substrate except for the portion where an unbonded portion is to be formed, and a flat conductive layer is partially bonded to the printed active metal layer pattern. An unbonded portion can be easily formed. In particular, even when a flat conductive layer having no protruding bridge portion or uneven portion is used as it is, an unbonded portion can be easily formed, and the component parts are compared with a case where a conductive layer having a bridge portion or the like is used. The number of processing steps is small, and a circuit board can be manufactured at low cost. In addition, since the flat conductive layer can be used as it is without performing press working or the like, excellent effects are exhibited, such as no reduction in the thickness of the conductive layer due to the processing and no risk of reducing the current carrying capacity of the conductive layer.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る回路基板の一実施例を示す斜視
図。
FIG. 1 is a perspective view showing one embodiment of a circuit board according to the present invention.

【図2】図1におけるII−II矢視部分断面図。FIG. 2 is a partial cross-sectional view taken along the line II-II in FIG.

【図3】従来の回路基板の構成例を示す断面図。FIG. 3 is a cross-sectional view illustrating a configuration example of a conventional circuit board.

【符号の説明】[Explanation of symbols]

1,1a 回路基板 2,2a セラミックス基板(AlN基板) 3a,3b,3c,3d,3e 導電層(銅板) 4,4a 導出端子 5 空間部分 6 活性金属層 7 未接合部 8 切込み 9 湾曲部 10 半導体素子(Siチップ) 11 金属細線 Reference Signs List 1, 1a circuit board 2, 2a ceramic substrate (AlN substrate) 3a, 3b, 3c, 3d, 3e conductive layer (copper plate) 4, 4a lead-out terminal 5 space 6 active metal layer 7 unjoined portion 8 cut 9 curved portion 10 Semiconductor element (Si chip) 11 Fine metal wire

───────────────────────────────────────────────────── フロントページの続き (72)発明者 田村 成敬 神奈川県横浜市鶴見区末広町2の4 株 式会社東芝 京浜事業所内 (56)参考文献 特開 平5−21641(JP,A) 特開 昭61−245555(JP,A) 特開 平5−136290(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Shigetaka Tamura 2-4 Suehirocho, Tsurumi-ku, Yokohama-shi, Kanagawa Prefecture Toshiba Keihin Works (56) References JP-A-5-21641 (JP, A) JP-A-61-245555 (JP, A) JP-A-5-136290 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/12

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 セラミックス基板の表面に形成された活
性金属層を介して平板状の導電層がセラミックス基板に
一体に接合され、複数の湾曲部を有する導出端子が上記
導電層に接続されるとともに、上記導出端子を接続した
導電層とセラミックス基板との間に未接合部を設けたこ
とを特徴とする回路基板。
1. A flat conductive layer is integrally joined to a ceramic substrate via an active metal layer formed on a surface of the ceramic substrate, and a lead terminal having a plurality of curved portions is connected to the conductive layer. And a non-joined portion is provided between the conductive layer to which the lead-out terminal is connected and the ceramic substrate.
【請求項2】 活性金属層は、Ti,Zr,Hfおよび
Nbから選択される少くとも1種の活性金属を含有する
ろう材から成ることを特徴とする請求項1記載の回路基
板。
2. The circuit board according to claim 1, wherein the active metal layer is made of a brazing material containing at least one active metal selected from Ti, Zr, Hf and Nb.
【請求項3】 導出端子は湾曲部を有し、この湾曲部に
おいて軸方向に伸縮自在に構成したことを特徴とする請
求項1記載の回路基板。
3. The circuit board according to claim 1, wherein the lead-out terminal has a curved portion, and the curved portion is configured to be able to expand and contract in the axial direction.
【請求項4】 セラミックス基板は、酸化アルミニウム
(Al)、窒化アルミニウム(AlN)、酸化ベ
リリウム(BeO),炭化けい素(SiC)および窒化
けい素(Si)から選択される少なくとも1種の
セラミックス材料で形成されたことを特徴とする請求項
1記載の回路基板。
4. The ceramic substrate is selected from aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), beryllium oxide (BeO), silicon carbide (SiC), and silicon nitride (Si 3 N 4 ). The circuit board according to claim 1, wherein the circuit board is formed of at least one kind of ceramic material.
JP23512793A 1993-09-21 1993-09-21 Circuit board Expired - Lifetime JP3283119B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23512793A JP3283119B2 (en) 1993-09-21 1993-09-21 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23512793A JP3283119B2 (en) 1993-09-21 1993-09-21 Circuit board

Publications (2)

Publication Number Publication Date
JPH0794623A JPH0794623A (en) 1995-04-07
JP3283119B2 true JP3283119B2 (en) 2002-05-20

Family

ID=16981456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23512793A Expired - Lifetime JP3283119B2 (en) 1993-09-21 1993-09-21 Circuit board

Country Status (1)

Country Link
JP (1) JP3283119B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4057407B2 (en) * 2002-12-12 2008-03-05 三菱電機株式会社 Semiconductor power module
US7776426B2 (en) 2005-03-04 2010-08-17 Dowa Metaltech Co., Ltd. Ceramic circuit substrate and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61245555A (en) * 1985-04-24 1986-10-31 Toshiba Corp Terminal connecting structure for semiconductor
JPH05136290A (en) * 1991-11-11 1993-06-01 Toshiba Corp Ceramics circuit substrate
JP2955399B2 (en) * 1991-07-12 1999-10-04 株式会社東芝 Ceramic circuit board

Also Published As

Publication number Publication date
JPH0794623A (en) 1995-04-07

Similar Documents

Publication Publication Date Title
EP2006895B1 (en) Electronic component module
JPH07202063A (en) Ceramic circuit board
JP3461829B2 (en) Power semiconductor device having buffer layer
JPH04162756A (en) Semiconductor module
JPH0455339B2 (en)
JPH065401A (en) Chip type resistor element and semiconductor device
JP6907546B2 (en) Power module
KR102588854B1 (en) Power module and manufacturing method thereof
JPH04192341A (en) Semiconductor device
JPH077810B2 (en) Semiconductor device
JP3283119B2 (en) Circuit board
WO2017006916A1 (en) Semiconductor device and method for manufacturing semiconductor device
JPH10144967A (en) Thermoelectric element module for cooling
JP3794454B2 (en) Nitride ceramic substrate
JP6927829B2 (en) Bonded structure and semiconductor package
JP3260512B2 (en) Aluminum nitride circuit board
JPH10200219A (en) Circuit board
JPH0794624A (en) Circuit board
KR102575288B1 (en) Semiconductor package and manufacturing method thereof
JP2001135902A (en) Ceramic circuit board
JP3194791B2 (en) Ceramic circuit board
JP2004014827A (en) Manufacturing method of package for high frequency
JPH10224059A (en) Heat sink
JPH07211822A (en) Package for accommodating semiconductor element
JP2004134703A (en) Circuit board with terminal

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 6

Free format text: PAYMENT UNTIL: 20080301

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

Free format text: JAPANESE INTERMEDIATE CODE: R313114

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080301

Year of fee payment: 6

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080301

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 7

Free format text: PAYMENT UNTIL: 20090301

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100301

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 8

Free format text: PAYMENT UNTIL: 20100301

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 9

Free format text: PAYMENT UNTIL: 20110301

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 10

Free format text: PAYMENT UNTIL: 20120301

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130301

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140301

Year of fee payment: 12