JP2002121357A - Epoxy resin composition and semiconductor device - Google Patents

Epoxy resin composition and semiconductor device

Info

Publication number
JP2002121357A
JP2002121357A JP2000311387A JP2000311387A JP2002121357A JP 2002121357 A JP2002121357 A JP 2002121357A JP 2000311387 A JP2000311387 A JP 2000311387A JP 2000311387 A JP2000311387 A JP 2000311387A JP 2002121357 A JP2002121357 A JP 2002121357A
Authority
JP
Japan
Prior art keywords
epoxy resin
resin composition
semiconductor device
area
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000311387A
Other languages
Japanese (ja)
Inventor
Hironori Osuga
浩規 大須賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2000311387A priority Critical patent/JP2002121357A/en
Publication of JP2002121357A publication Critical patent/JP2002121357A/en
Pending legal-status Critical Current

Links

Landscapes

  • Compositions Of Macromolecular Compounds (AREA)
  • Epoxy Resins (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an epoxy resin composition which has little warpage after molding, during ball soldering and after a soldering treatment such as a reflow treatment for sealing an area-packaging semiconductor device, particularly the one which has a high ratio of the area occupied with a semiconductor element. SOLUTION: In an epoxy resin composition for sealing a semiconductor using an epoxy resin, a phenol resin, a curable accelerator and an inorganic filler as main components, the epoxy resin composition for sealing a semiconductor has characteristics of a cured substance from thermosetting of the epoxy resin composition which are a <=10R (wherein R is 7-10×(b+c)), 300<=a<=500 and 0.15<=b+c, wherein a (N/mm2) is a flexural modulus at a molding temperature, b (%) is a curing contraction rate and c (%) is a heat contraction rate from a molding temperature to a room temperature.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、プリント配線板や
金属リードフレームの片面に半導体素子を搭載し、その
搭載面側の実質的に片面のみを樹脂封止されたいわゆる
エリア実装型半導体装置に適した半導体封止用エポキシ
樹脂組成物、及びこれを用いた半導体装置に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called area mounting type semiconductor device in which a semiconductor element is mounted on one surface of a printed wiring board or a metal lead frame, and substantially only one of the mounting surfaces is resin-sealed. The present invention relates to a suitable epoxy resin composition for semiconductor encapsulation and a semiconductor device using the same.

【0002】[0002]

【従来の技術】近年の電子機器の小型化、軽量化、高性
能化の市場動向において、半導体素子の高集積化が年々
進み、又、半導体装置の表面実装化が促進されるなか
で、新規にエリア実装型半導体装置が開発され、従来構
造の半導体装置から移行し始めている。エリア実装型半
導体装置としては、BGA(ボールグリッドアレイ)、
或いは更に小型化を追求したCSP(チップスケールパ
ッケージ)等が代表的であるが、これらは従来QFP、
SOPに代表される表面実装型半導体装置では限界に近
づいている多ピン化・高速化への要求に対応するために
開発されたものである。構造としては、BT樹脂/銅箔
回路基板(ビスマレイミド・トリアジン樹脂/ガラスク
ロス基板)に代表される硬質回路基板、或いはポリイミ
ド樹脂フィルム/銅箔回路基板に代表されるフレキシブ
ル回路基板の片面上に半導体素子を搭載し、その半導体
素子搭載面、即ち基板の片面のみがエポキシ樹脂組成物
等で成形・封止されている。又、基板の半導体素子搭載
面の反対面には半田ボールを2次元的に並列して形成
し、半導体装置を実装する回路基板との接合を行う特徴
を有している。更に、半導体素子を搭載する基板として
は、上記の有機回路基板以外にもリードフレーム等の金
属基板を用いる構造も開発されている。
2. Description of the Related Art In recent years, in the market trend of miniaturization, weight reduction and high performance of electronic equipment, high integration of semiconductor elements has been progressing year by year, and surface mounting of semiconductor devices has been promoted. In recent years, area-mounted semiconductor devices have been developed, and are beginning to shift from semiconductor devices having conventional structures. Area mounting type semiconductor devices include BGA (ball grid array),
Alternatively, a CSP (chip scale package) or the like pursuing further miniaturization is a typical example.
The surface-mount type semiconductor device represented by the SOP has been developed in order to meet the demand for increasing the number of pins and increasing the speed, which is approaching the limit. As the structure, on one side of a rigid circuit board represented by a BT resin / copper foil circuit board (bismaleimide / triazine resin / glass cloth board) or a flexible circuit board represented by a polyimide resin film / copper foil circuit board A semiconductor element is mounted, and only the semiconductor element mounting surface, that is, only one side of the substrate is molded and sealed with an epoxy resin composition or the like. Further, on the surface opposite to the semiconductor element mounting surface of the substrate, solder balls are formed two-dimensionally in parallel, and are characterized in that they are joined to a circuit board on which a semiconductor device is mounted. Further, as a substrate on which a semiconductor element is mounted, a structure using a metal substrate such as a lead frame has been developed in addition to the above-described organic circuit substrate.

【0003】これらエリア実装型半導体装置の構造は、
基板の半導体素子搭載面のみをエポキシ樹脂組成物で封
止し、半田ボール形成面側は封止しないという片面封止
の形態をとっている。リードフレーム等の金属基板等で
は、半田ボール形成面でも数十μm程度の封止樹脂層が
存在することもあるが、半導体素子搭載面では数百μm
から数mm程度の封止樹脂層が形成されるため、実質的
に片面封止となっている。このため、有機基板や金属基
板とエポキシ樹脂組成物の硬化物との間での熱膨張・熱
収縮の不整合、或いはエポキシ樹脂組成物の成形硬化時
の硬化収縮による影響で、これらの半導体装置では成形
直後から反りが発生しやすい。又、半導体装置の小型化
に伴い、樹脂封止面積に対する半導体素子面積の占める
割合も増大しつつあり、半導体素子とエポキシ樹脂組成
物の硬化物との間での熱膨張・熱収縮の不整合、或いは
エポキシ樹脂組成物の成形硬化時の硬化収縮による影響
で、反りが更に発生しやすくなってきている。更に、こ
れらの半導体装置を実装する回路基板上に半田接合を行
う場合、200℃以上の加熱工程を経るが、この際に半
導体装置の反りが発生し、多数の半田ボールが平坦とな
らず、半導体装置を実装する回路基板から浮き上がって
しまい、電気的接合の信頼性が低下する問題も起こる。
The structure of these area-mounted semiconductor devices is as follows:
A single-sided sealing configuration is adopted in which only the semiconductor element mounting surface of the substrate is sealed with the epoxy resin composition and the solder ball forming surface is not sealed. On a metal substrate such as a lead frame, a sealing resin layer of about several tens of μm may be present even on the surface on which the solder ball is formed, but several hundred μm on the surface on which the semiconductor element is mounted.
Since a sealing resin layer having a thickness of about several mm is formed, substantially single-sided sealing is achieved. For this reason, these semiconductor devices may be affected by mismatch of thermal expansion and thermal shrinkage between the organic substrate or the metal substrate and the cured product of the epoxy resin composition, or the effect of curing shrinkage during molding and curing of the epoxy resin composition. In this case, warpage tends to occur immediately after molding. Also, with the miniaturization of semiconductor devices, the ratio of the semiconductor element area to the resin sealing area is also increasing, and the mismatch between the thermal expansion and thermal contraction between the semiconductor element and the cured product of the epoxy resin composition. Alternatively, warpage is more likely to occur due to the influence of curing shrinkage during molding and curing of the epoxy resin composition. Furthermore, when soldering is performed on a circuit board on which these semiconductor devices are mounted, a heating step of 200 ° C. or more is performed. At this time, the semiconductor device is warped, and many solder balls are not flattened. There is also a problem that the semiconductor device floats up from the circuit board on which the semiconductor device is mounted, and the reliability of the electrical connection is reduced.

【0004】基板上の実質的に片面のみをエポキシ樹脂
組成物で封止した半導体装置において、反りを低減する
には、基板の熱膨張係数とエポキシ樹脂組成物の硬化物
の熱膨張係数とを近づけること、及びエポキシ樹脂組成
物の成形硬化時の硬化収縮を小さくすることの二つの方
法が重要である。つまり、エポキシ樹脂組成物の成形硬
化時の硬化収縮と、成形温度から室温までの熱収縮を小
さくすることが、反りの低減に必要となる。基板として
は、有機基板ではBT樹脂やポリイミド樹脂のような高
いガラス転移温度(以下、Tgという)を有する樹脂が
広く用いられており、これらはエポキシ樹脂組成物の成
形温度である170℃近辺よりも高いTgを有する。従
って、成形温度から室温までの冷却過程では有機基板の
α1の領域のみで収縮する。よって、エポキシ樹脂組成
物の硬化物も、Tgが高く且つα1が有機基板と同じ
で、更に硬化収縮がゼロであれば、反りはほぼゼロであ
ると考えられる。このため、多官能型エポキシ樹脂と多
官能型フェノール樹脂との組み合わせによりTgを高く
し、無機充填材の配合量でα1を合わせる手法が既に提
案されている。
In a semiconductor device in which substantially only one surface on a substrate is sealed with an epoxy resin composition, in order to reduce warpage, the thermal expansion coefficient of the substrate and the thermal expansion coefficient of a cured product of the epoxy resin composition are determined. Two approaches are important: approaching and reducing curing shrinkage during molding and curing of the epoxy resin composition. That is, it is necessary to reduce the curing shrinkage during the molding and curing of the epoxy resin composition and the heat shrinkage from the molding temperature to room temperature in order to reduce the warpage. As the substrate, resins having a high glass transition temperature (hereinafter, referred to as Tg), such as BT resin and polyimide resin, are widely used for organic substrates, and these are used at temperatures around 170 ° C., which is the molding temperature of the epoxy resin composition. Also have a high Tg. Accordingly, during the cooling process from the molding temperature to room temperature, the organic substrate contracts only in the region of α1. Therefore, if the cured product of the epoxy resin composition has a high Tg and the same α1 as that of the organic substrate, and if the curing shrinkage is zero, the warpage is considered to be almost zero. For this reason, a method has already been proposed in which Tg is increased by combining a polyfunctional epoxy resin and a polyfunctional phenol resin, and α1 is adjusted by the amount of the inorganic filler.

【0005】一方、樹脂封止面積に対する半導体素子面
積の占める割合が大きい半導体装置では、半導体素子と
エポキシ樹脂組成物の硬化物との熱膨張係数を近づける
ことも重要となってくる。しかし、半導体素子の熱膨張
が小さすぎるため、半導体素子とエポキシ樹脂組成物の
硬化物の熱膨張を等しくすることが困難であり、よって
半導体素子占有面積の比率が大きい半導体装置では、反
りの問題を解決できないのが現状であった。
On the other hand, in a semiconductor device in which the ratio of the semiconductor element area to the resin sealing area is large, it is important to make the thermal expansion coefficients of the semiconductor element and the cured product of the epoxy resin composition close to each other. However, since the thermal expansion of the semiconductor element is too small, it is difficult to equalize the thermal expansion of the semiconductor element and the cured product of the epoxy resin composition. Was unable to solve the problem.

【0006】[0006]

【発明が解決しようとする課題】本発明は、エリア実装
型半導体装置、特に半導体素子占有面積の比率が大きい
エリア実装型半導体装置において、成形後の反りが小さ
く、且つ半田ボール付けや実装時におけるリフロー処理
等の半田処理後の反りが小さい半導体封止用エポキシ樹
脂組成物、及びこれを用いた半導体装置を提供するもの
である。
SUMMARY OF THE INVENTION The present invention relates to an area mounting type semiconductor device, particularly, an area mounting type semiconductor device having a large ratio of an occupied area of a semiconductor element. An object of the present invention is to provide an epoxy resin composition for semiconductor encapsulation with a small warpage after a soldering process such as a reflow process, and a semiconductor device using the same.

【0007】[0007]

【課題を解決するための手段】本発明は、(A)エポキ
シ樹脂、(B)フェノール樹脂、(C)硬化促進剤、及
び(D)無機充填材を主成分とするエポキシ樹脂組成物
において、該エポキシ樹脂組成物を加熱硬化した硬化物
の特性が、成形温度での曲げ弾性率をa(N/m
)、硬化収縮率をb(%)、成形温度から室温まで
の熱収縮率をc(%)とするとき、a≦10(式中、
R=7−10×(b+c)である)、300≦a≦50
00、0.15≦b+cであることを特徴とする半導体
封止用エポキシ樹脂組成物、及びこれを用いて半導体素
子を封止してなるエリア実装型半導体装置であり、特
に、樹脂封止面積に対する半導体素子面積の比率が25
%以上を占める前記半導体装置である。
The present invention relates to an epoxy resin composition comprising (A) an epoxy resin, (B) a phenolic resin, (C) a curing accelerator, and (D) an inorganic filler as main components. The properties of a cured product obtained by heating and curing the epoxy resin composition indicate that the flexural modulus at the molding temperature is a (N / m
m 2 ), when the curing shrinkage is b (%) and the heat shrinkage from the molding temperature to room temperature is c (%), a ≦ 10 R (where:
R = 7−10 × (b + c)), 300 ≦ a ≦ 50
The present invention relates to an epoxy resin composition for semiconductor encapsulation, characterized by satisfying 00, 0.15 ≦ b + c, and an area mounting type semiconductor device obtained by encapsulating a semiconductor element using the same. The ratio of the semiconductor element area to 25
% Of the semiconductor device.

【0008】[0008]

【発明の実施の形態】本発明者は、鋭意検討を進めた結
果、(A)〜(D)成分を主成分とするエポキシ樹脂組
成物を加熱硬化した硬化物を成形時の温度で測定した曲
げ弾性率が、反りに大きな影響を与えることを見出し
た。つまり、成形温度での曲げ弾性率を低くすること
で、半導体素子とエポキシ樹脂組成物の硬化物との熱膨
張係数の差から発生する応力を緩和する現象が起こり、
反りが小さくなることが判明した。更に、成形温度での
曲げ弾性率と、硬化収縮率、成形温度から室温までの熱
収縮率は、反りに対し複合的に影響を与えていることが
分かった。そして、前記硬化物の成形温度での曲げ弾性
率をa(N/mm)、硬化収縮率をb(%)、成形温
度から室温までの熱収縮率をc(%)とするとき、a≦
10(式中、R=7−10×(b+c)である)、3
00≦a≦5000、0.15≦b+cを満足すること
により、基板上の実質的に片面のみをエポキシ樹脂組成
物で封止したいわゆるエリア実装型半導体装置、特に、
半導体素子占有面積の比率が大きいエリア実装型半導体
装置において、反りが低減することを見出した。
BEST MODE FOR CARRYING OUT THE INVENTION As a result of intensive studies, the present inventor measured a cured product obtained by heat-curing an epoxy resin composition containing components (A) to (D) as a main component at a molding temperature. It has been found that the flexural modulus has a large effect on warpage. In other words, by lowering the flexural modulus at the molding temperature, a phenomenon occurs in which the stress generated from the difference in the thermal expansion coefficient between the semiconductor element and the cured product of the epoxy resin composition is relaxed,
It has been found that the warpage is reduced. Furthermore, it was found that the bending elasticity at the molding temperature, the curing shrinkage, and the heat shrinkage from the molding temperature to room temperature have a composite effect on the warpage. When the flexural modulus at the molding temperature of the cured product is a (N / mm 2 ), the curing shrinkage is b (%), and the heat shrinkage from the molding temperature to room temperature is c (%), a ≤
10 R (where R = 7−10 × (b + c)), 3
By satisfying 00 ≦ a ≦ 5000 and 0.15 ≦ b + c, a so-called area-mounted semiconductor device in which substantially only one surface on a substrate is sealed with an epoxy resin composition,
It has been found that the warpage is reduced in an area-mounted semiconductor device having a large ratio of the occupied area of the semiconductor element.

【0009】本発明における成形温度とは、エポキシ樹
脂組成物を加熱硬化する時の金型温度を指し、通常は1
60〜190℃の範囲であるが、この温度範囲に限定さ
れるものではない。aの値は、JIS K 6911に
準じて測定した。b+cの値は、トランスファー成形機
を用いて、金型温度175℃、注入圧力6.9MPa、
硬化時間90秒で、直径100mm、厚さ3mmの円板
を成形し、175℃での金型キャビティの内径と、室温
(25℃)での円板の外径を測定し、b+c=[{(1
75℃での金型キャビティの内径)−(25℃での円板
の外径)}/(175℃での金型キャビティの内径)]
×100の式から算出した。単位は%。なお、用いる成
形物については、後硬化処理は行わないもので評価す
る。a、b、cの関係において、aが10又は500
0を越えると反りが大きくなるので好ましくない。又、
aが300未満だと、成形硬化時の硬化物が柔らかくな
るために金型からの離型性が悪くなり成形性が低下する
ので好ましくない。更に、b+cが0.15未満だと、
成形硬化時の硬化収縮が小さくなり金型からの離型性が
悪くなり成形性が低下するので好ましくない。前記の様
な物性に調整するための手法としては、特に限定しない
が、樹脂成分の組み合わせによって無機充填材量を調整
したり、シリコーンオイル、ゴム等の低応力成分を配合
し硬化物の弾性率を下げたりする方法等が挙げられる。
In the present invention, the molding temperature refers to a mold temperature at which the epoxy resin composition is cured by heating.
The temperature is in the range of 60 to 190 ° C., but is not limited to this temperature range. The value of a was measured according to JIS K 6911. The value of b + c was determined using a transfer molding machine at a mold temperature of 175 ° C., an injection pressure of 6.9 MPa,
With a curing time of 90 seconds, a disk having a diameter of 100 mm and a thickness of 3 mm was molded, and the inner diameter of the mold cavity at 175 ° C. and the outer diameter of the disk at room temperature (25 ° C.) were measured. (1
Inner diameter of mold cavity at 75 ° C .− (outer diameter of disk at 25 ° C.)} / (Inner diameter of mold cavity at 175 ° C.)]
It calculated from the formula of x100. Units%. In addition, about the molded product to be used, evaluation is made without post-curing treatment. In the relationship of a, b and c, a is 10 R or 500
Exceeding 0 is not preferable because warpage increases. or,
When a is less than 300, the cured product at the time of molding and curing becomes soft, so that the releasability from the mold is deteriorated and the moldability is undesirably reduced. Furthermore, if b + c is less than 0.15,
It is not preferable because the curing shrinkage during the molding and curing becomes small, the releasability from the mold becomes poor, and the moldability decreases. The method for adjusting the physical properties as described above is not particularly limited, but the amount of the inorganic filler is adjusted by a combination of resin components, or the elastic modulus of the cured product is adjusted by blending a low stress component such as silicone oil or rubber. And the like.

【0010】本発明のエポキシ樹脂組成物は、基板上の
実質的に片面のみを封止したいわゆるエリア実装型半導
体装置、特に、半導体素子占有面積の比率が大きいエリ
ア実装型半導体装置において、反りが非常に小さく、最
適である。半導体素子占有面積の比率が大きい半導体装
置では、成形温度での曲げ弾性率を低くすることで、半
導体素子とエポキシ樹脂組成物の硬化物との熱膨張係数
の差から発生する応力を緩和する現象が起こり、反りが
小さくなるからである。特に、樹脂封止面積に対する半
導体素子占有面積の比率が25%以上の半導体装置にお
いて、反りを低減させる効果を最大限に発揮する。25
%未満の半導体装置では、半導体素子とエポキシ樹脂組
成物の硬化物との熱膨張係数の差から発生する応力が小
さいために、エポキシ樹脂組成物の硬化収縮や熱収縮
が、反りに対する支配的な要因となるが、エポキシ樹脂
組成物の成形温度での曲げ弾性率は、反りに対して影響
を及ぼさない。なお、本発明で言う樹脂封止面積とは、
半導体素子をエポキシ樹脂組成物によって覆って形成し
た封止部の面積であり、すなわち半導体素子面積及びエ
ポキシ樹脂組成物と配線基板との接触部分の面積の合計
である。又、半導体素子占有面積の比率とは、半導体装
置の樹脂封止面積と半導体素子面積から、{(半導体素
子面積)/(樹脂封止面積)}×100で算出するもの
である(単位%)。
The epoxy resin composition of the present invention has warpage in a so-called area-mounted semiconductor device in which substantially only one surface of a substrate is sealed, particularly in an area-mounted semiconductor device having a large ratio of an occupied area of a semiconductor element. Very small and optimal. In a semiconductor device having a large ratio of the occupied area of a semiconductor element, a phenomenon in which a bending elastic modulus at a molding temperature is reduced to reduce a stress generated due to a difference in a thermal expansion coefficient between the semiconductor element and a cured product of the epoxy resin composition. This is because warpage is reduced. In particular, in a semiconductor device in which the ratio of the semiconductor element occupation area to the resin sealing area is 25% or more, the effect of reducing the warpage is exerted to the maximum. 25
%, The stress generated due to the difference in the coefficient of thermal expansion between the semiconductor element and the cured product of the epoxy resin composition is small, so that the curing shrinkage and the heat shrinkage of the epoxy resin composition dominantly warp. As a factor, the flexural modulus at the molding temperature of the epoxy resin composition does not affect the warpage. The resin sealing area in the present invention is:
It is the area of the sealing portion formed by covering the semiconductor element with the epoxy resin composition, that is, the sum of the area of the semiconductor element and the area of the contact portion between the epoxy resin composition and the wiring board. The ratio of the occupied area of the semiconductor element is calculated by {(semiconductor element area) / (resin sealed area)} × 100 from the resin sealing area of the semiconductor device and the semiconductor element area (unit%). .

【0011】本発明で用いられるエポキシ樹脂として
は、エポキシ基を有するモノマー、オリゴマー、ポリマ
ー全般を指し、例えば、トリフェノールメタン型エポキ
シ樹脂、アルキル変性トリフェノールメタン型エポキシ
樹脂、ビフェニル型エポキシ樹脂、ビスフェノール型エ
ポキシ樹脂、スチルベン型エポキシ樹脂、オルソクレゾ
ールノボラック型エポキシ樹脂、フェノールノボラック
型エポキシ樹脂、フェノールアラルキル型エポキシ樹
脂、トリアジン核含有エポキシ樹脂、ナフタレン骨格を
含むエポキシ樹脂、ジシクロペンタジエン変性フェノー
ル型エポキシ樹脂等が挙げられ、これらは単独でも混合
して用いてもよい。
The epoxy resin used in the present invention refers to all monomers, oligomers and polymers having an epoxy group, such as triphenolmethane epoxy resin, alkyl-modified triphenolmethane epoxy resin, biphenyl epoxy resin, bisphenol Epoxy resin, stilbene epoxy resin, ortho-cresol novolak epoxy resin, phenol novolak epoxy resin, phenol aralkyl epoxy resin, epoxy resin containing triazine nucleus, epoxy resin containing naphthalene skeleton, dicyclopentadiene-modified phenol epoxy resin, etc. And these may be used alone or as a mixture.

【0012】本発明で用いられるフェノール樹脂として
は、上記のエポキシ樹脂と硬化反応して架橋構造を形成
することができる少なくとも2個以上のフェノール性水
酸基を有するモノマー、オリゴマー、ポリマー全般を指
し、例えば、フェノールノボラック樹脂、クレゾールノ
ボラック樹脂、パラキシリレン変性フェノール樹脂、メ
タキシリレン・パラキシリレン変性フェノール樹脂等の
フェノールアラルキル樹脂、ナフタレン骨格を含む樹
脂、テルペン変性フェノール樹脂、ジシクロペンタジエ
ン変性フェノール樹脂、トリフェノールメタン樹脂等が
挙げられ、これらは単独でも混合して用いてもよい。
The phenolic resin used in the present invention refers to all monomers, oligomers and polymers having at least two or more phenolic hydroxyl groups capable of forming a crosslinked structure by curing reaction with the epoxy resin. Phenol novolak resin, cresol novolak resin, para-xylylene-modified phenol resin, phenol aralkyl resin such as meta-xylylene / para-xylylene-modified phenol resin, resin containing a naphthalene skeleton, terpene-modified phenol resin, dicyclopentadiene-modified phenol resin, triphenol methane resin, etc. These may be used alone or as a mixture.

【0013】本発明で用いられる硬化促進剤としては、
前記エポキシ樹脂とフェノール樹脂との架橋反応の触媒
となり得るものを指し、例えば、1,8−ジアザビシク
ロ(5,4,0)ウンデセン−7、トリブチルアミン等
のアミン化合物、トリフェニルホスフィン、テトラフェ
ニルホスフォニウム・テトラフェニルボレート塩等の有
機リン系化合物、2−メチルイミダゾール等のイミダゾ
ール化合物等が挙げられるが、これらに限定されるもの
ではない。これらは単独でも混合して用いてもよい。
The curing accelerator used in the present invention includes:
It refers to a compound that can serve as a catalyst for a crosslinking reaction between the epoxy resin and the phenol resin, for example, amine compounds such as 1,8-diazabicyclo (5,4,0) undecene-7, tributylamine, triphenylphosphine, and tetraphenylphosphine. Examples include, but are not limited to, organophosphorus compounds such as phonium tetraphenylborate salts, and imidazole compounds such as 2-methylimidazole. These may be used alone or as a mixture.

【0014】本発明で用いられる無機充填材の種類につ
いては特に制限はなく、一般に封止材料に用いられてい
るものを使用することができる。例えば、溶融シリカ、
結晶シリカ、2次凝集シリカ、アルミナ、チタンホワイ
ト、水酸化アルミニウム、タルク、クレー、ガラス繊維
等が挙げられ、特に溶融シリカが好ましい。溶融シリカ
は、破砕状、球状のいずれでも使用可能であるが、配合
量を高め、且つエポキシ樹脂組成物の溶融粘度の上昇を
抑えるためには、球状シリカを主に用いる方がより好ま
しい。更に球状シリカの配合量を高めるためには、球状
シリカの粒度分布をより広くとるよう調整することが望
ましい。又、無機充填材は、予めカップリング剤等で表
面処理されているものを用いてもよい。
The kind of the inorganic filler used in the present invention is not particularly limited, and those generally used for a sealing material can be used. For example, fused silica,
Examples thereof include crystalline silica, secondary aggregated silica, alumina, titanium white, aluminum hydroxide, talc, clay, and glass fiber, with fused silica being particularly preferred. Fused silica can be used in any of a crushed form and a spherical form. However, in order to increase the blending amount and suppress an increase in the melt viscosity of the epoxy resin composition, it is more preferable to mainly use the spherical silica. In order to further increase the content of the spherical silica, it is desirable to adjust the particle size distribution of the spherical silica to be wider. Further, as the inorganic filler, a material which has been surface-treated with a coupling agent or the like in advance may be used.

【0015】本発明のエポキシ樹脂組成物は、(A)〜
(D)成分の他、必要に応じて臭素化エポキシ樹脂、酸
化アンチモン、リン化合物等の難燃剤、無機イオン交換
体、カップリング剤、カーボンブラックに代表される着
色剤、天然ワックス、合成ワックス、高級脂肪酸及びそ
の金属塩類もしくはパラフィン等の離型剤、シリコーン
オイル、ゴム等の低応力成分、酸化防止剤等の各種添加
剤が適宜配合可能である。特に、シリコーンオイル、ゴ
ム等の低応力成分を配合させると、弾性率が低くなり、
反りが小さくなるため好ましい。本発明のエポキシ樹脂
組成物は、(A)〜(D)成分、及びその他の添加剤等
をミキサー等を用いて混合後、加熱ニーダ、熱ロール、
押し出し機等の混練機で加熱混練し、冷却、粉砕して得
られる。本発明のエポキシ樹脂組成物を用いて、半導体
素子等の電子部品を封止し、半導体装置を製造するに
は、トランスファーモールド、コンプレッションモール
ド、インジェクションモールド等の従来からの成形方法
で硬化成形すればよい。特に、本発明のエポキシ樹脂組
成物は、エリア実装型半導体装置の封止に適しており、
更には、半導体素子占有面積の比率が大きいエリア実装
型半導体装置の封止に最適である。
The epoxy resin composition of the present invention comprises (A)
In addition to the component (D), if necessary, brominated epoxy resins, antimony oxide, flame retardants such as phosphorus compounds, inorganic ion exchangers, coupling agents, coloring agents represented by carbon black, natural waxes, synthetic waxes, Release agents such as higher fatty acids and metal salts thereof or paraffin, low stress components such as silicone oil and rubber, and various additives such as antioxidants can be appropriately compounded. In particular, when low-stress components such as silicone oil and rubber are compounded, the elastic modulus decreases,
This is preferable because warpage is reduced. The epoxy resin composition of the present invention is obtained by mixing the components (A) to (D) and other additives using a mixer or the like, and then heating the kneader, a hot roll,
It is obtained by heating and kneading with a kneading machine such as an extruder, cooling and pulverizing. Using the epoxy resin composition of the present invention, to seal electronic components such as semiconductor elements, and to manufacture a semiconductor device, transfer molding, compression molding, injection molding and other conventional molding methods such as curing molding Good. In particular, the epoxy resin composition of the present invention is suitable for sealing area-mounted semiconductor devices,
Further, it is most suitable for sealing an area-mounted semiconductor device in which the ratio of the occupied area of the semiconductor element is large.

【0016】[0016]

【実施例】以下、本発明を実施例で具体的に説明する。
配合割合は重量部とする。 実施例1 式(1)で示される樹脂を主成分とするエポキシ樹脂(融点105℃、エポキ シ当量195) 8.7重量部
The present invention will be specifically described below with reference to examples.
The mixing ratio is by weight. Example 1 8.7 parts by weight of an epoxy resin containing a resin represented by the formula (1) as a main component (melting point: 105 ° C., epoxy equivalent: 195)

【化1】 Embedded image

【0017】 式(2)で示されるフェノール樹脂(軟化点105℃、水酸基当量97) 4.3重量部A phenol resin represented by the formula (2) (softening point: 105 ° C., hydroxyl equivalent: 97) 4.3 parts by weight

【化2】 トリフェニルホスフィン 0.15重量部 球状溶融シリカ(平均粒径15μm) 86.25重量部 カーボンブラック 0.3重量部 カルナバワックス 0.3重量部 をミキサーで混合した後、表面温度が90℃と45℃の
2本ロールを用いて混練し、冷却後粉砕してエポキシ樹
脂組成物とした。得られたエポキシ樹脂組成物を以下の
方法で評価した。結果を表1に示す。
Embedded image Triphenylphosphine 0.15 parts by weight Spherical fused silica (average particle size 15 μm) 86.25 parts by weight Carbon black 0.3 part by weight Carnauba wax 0.3 part by weight was mixed with a mixer. The mixture was kneaded using two rolls at a temperature of ℃, cooled and pulverized to obtain an epoxy resin composition. The obtained epoxy resin composition was evaluated by the following method. Table 1 shows the results.

【0018】評価方法 スパイラルフロー:EMMI−1−66に準じたスパイ
ラルフロー測定用の金型を用いて、金型温度175℃、
注入圧力6.9MPa、硬化時間120秒で測定した。 硬化性:ショアD硬度計を用い、金型温度175℃、注
入圧力6.9MPa、硬化時間90秒で測定した。 成形温度での曲げ弾性率a:前記した通り、JIS K
6911に準じて測定した。トランスファー成形機を
用いて、金型温度175℃、注入圧力6.9MPa、硬
化時間90秒で硬化物を成形し、175℃で曲げ弾性率
を測定した。単位はN/mm。 b+c:前記した通り、トランスファー成形機を用い
て、金型温度175℃、注入圧力6.9MPa、硬化時
間90秒で、直径100mm、厚さ3mmの円板を成形
し、175℃での金型キャビティの内径と、室温(25
℃)での円板の外径を測定し、[{(175℃での金型
キャビティの内径)−(25℃での円板の外径)}/
(175℃での金型キャビティの内径)]×100の式
から算出した。単位は%。 パッケージ反り量:トランスファー成形機を用いて、金
型温度175℃、注入圧力6.9MPa、硬化時間90
秒で、192pBGA(厚さ0.36mmBT樹脂基
板、チップサイズ9.0mm×9.0mm×厚さ0.3
5mm、パッケージサイズ16.0mm×16.0m
m、樹脂封止面積15.5mm×15.5mm、封止樹
脂の厚さ0.8mm)を成形し、175℃、2時間で後
硬化した。室温まで冷却後、パッケージのゲートから対
角線方向に、表面粗さ計を用いて高さ方向の変位を測定
し、変位差の最も大きい値を反り量とした。単位はμ
m。なお、本評価で用いたパッケージの半導体素子占有
面積の比率は、{(9.0mm×9.0mm)/(1
5.5mm×15.5mm)}×100=34%であ
る。 離型性:前記の192pBGAの成形時に、金型からの
離型性を調べた。スムーズに金型から離型しないものを
不良と判定した。
Evaluation method Spiral flow: Using a mold for measuring spiral flow according to EMMI-1-66, a mold temperature of 175 ° C.
The measurement was performed at an injection pressure of 6.9 MPa and a curing time of 120 seconds. Curability: Measured using a Shore D hardness meter at a mold temperature of 175 ° C., an injection pressure of 6.9 MPa, and a curing time of 90 seconds. Flexural modulus at molding temperature a: As described above, JIS K
It was measured according to 6911. Using a transfer molding machine, a cured product was molded at a mold temperature of 175 ° C., an injection pressure of 6.9 MPa, and a curing time of 90 seconds, and the flexural modulus was measured at 175 ° C. The unit is N / mm 2 . b + c: As described above, a disk having a diameter of 100 mm and a thickness of 3 mm was formed using a transfer molding machine at a mold temperature of 175 ° C., an injection pressure of 6.9 MPa, and a curing time of 90 seconds, and a mold at 175 ° C. The inner diameter of the cavity and the room temperature (25
C)), the outer diameter of the disc was measured at [{(inner diameter of mold cavity at 175 ° C.) − (Outer diameter of disc at 25 ° C.)} /
(Inner diameter of mold cavity at 175 ° C.)] × 100. Units%. Package warpage: Using a transfer molding machine, mold temperature 175 ° C., injection pressure 6.9 MPa, curing time 90
In seconds, 192pBGA (0.36mm thick BT resin substrate, chip size 9.0mm × 9.0mm × thickness 0.3)
5mm, package size 16.0mm x 16.0m
m, resin sealing area: 15.5 mm × 15.5 mm, thickness of sealing resin: 0.8 mm), and post-cured at 175 ° C. for 2 hours. After cooling to room temperature, the displacement in the height direction was measured using a surface roughness meter diagonally from the gate of the package, and the largest value of the displacement difference was defined as the amount of warpage. Unit is μ
m. The ratio of the area occupied by the semiconductor element of the package used in this evaluation is {(9.0 mm × 9.0 mm) / (1
(5.5 mm × 15.5 mm)} 100 = 34%. Releasability: The releasability from the mold was examined during the molding of 192pBGA. Those that did not release smoothly from the mold were judged to be defective.

【0019】実施例2〜5、比較例1〜5 表1、表2に従って配合し、実施例1と同様にしてエポ
キシ樹脂組成物を得、実施例1と同様にして評価した。
結果を表1、表2に示す。実施例、比較例で使用したエ
ポキシ樹脂、フェノール樹脂、及び添加剤を以下に示
す。式(3)で示されるエポキシ樹脂(軟化点60℃、
エポキシ当量170)、
Examples 2 to 5 and Comparative Examples 1 to 5 Epoxy resin compositions were prepared according to Tables 1 and 2 in the same manner as in Example 1 and evaluated in the same manner as in Example 1.
The results are shown in Tables 1 and 2. The epoxy resins, phenolic resins, and additives used in Examples and Comparative Examples are shown below. An epoxy resin represented by the formula (3) (softening point: 60 ° C.,
Epoxy equivalent 170),

【化3】 Embedded image

【0020】式(4)で示されるエポキシ樹脂(軟化点
60℃、エポキシ当量245)、
An epoxy resin represented by the formula (4) (softening point: 60 ° C., epoxy equivalent: 245);

【化4】 Embedded image

【0021】式(5)で示されるフェノール樹脂(軟化
点87℃、水酸基当量210)、
A phenolic resin represented by the formula (5) (softening point: 87 ° C., hydroxyl equivalent: 210);

【化5】 Embedded image

【0022】式(6)で示されるフェノール樹脂(軟化
点83℃、水酸基当量175)、
A phenolic resin represented by the formula (6) (softening point: 83 ° C., hydroxyl equivalent: 175);

【化6】 Embedded image

【0023】フェノールノボラック樹脂(軟化点80
℃、水酸基当量105)、シリコーンゴム(平均粒径5
μm)。
Phenol novolak resin (softening point 80
° C, hydroxyl equivalent 105), silicone rubber (average particle size 5
μm).

【表1】 [Table 1]

【0024】[0024]

【表2】 [Table 2]

【0025】[0025]

【発明の効果】本発明に従うと、成形性に優れ、エリア
実装型半導体封止用、特に半導体素子占有面積の比率が
大きいエリア実装型半導体装置の封止に適したエポキシ
樹脂組成物が得られ、これを用いた半導体装置は、成形
後の反りが小さく、且つ半田ボール付けや実装時のリフ
ロー処理等の半田処理後の反りが非常に小さい。
According to the present invention, there can be obtained an epoxy resin composition which has excellent moldability and is suitable for encapsulating an area-mounted semiconductor, particularly for encapsulating an area-mounted semiconductor device having a large ratio of an occupied area of a semiconductor element. In a semiconductor device using this, the warpage after molding is small, and the warpage after soldering such as solder balling and reflow processing during mounting is very small.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 実施例及び比較例のエポキシ樹脂組成物の成
形温度での曲げ弾性率(a)、硬化収縮率(b)、及び
熱収縮率(c)の関係を示すグラフである。
FIG. 1 is a graph showing the relationship among the flexural modulus (a), the curing shrinkage (b), and the heat shrinkage (c) at the molding temperature of the epoxy resin compositions of Examples and Comparative Examples.

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 4J002 CC03X CC04X CC05X CC06X CD04W CD05W CD06W CD07W CD13W CE00X DE137 DE147 DJ017 DJ037 DJ047 DL007 EN026 EU116 EU136 EW016 EY016 FA047 FA087 FD017 FD090 FD130 FD14X FD156 FD160 GJ02 GQ01 4J036 AA01 DA02 FA01 FB07 JA07 4M109 AA01 BA01 BA04 CA21 CA22 DB17 EA02 EB03 EB04 EB06 EB07 EB08 EB09 EB13 EB18 EB19 EC04 GA10  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M109 AA01 BA01 BA04 CA21 CA22 DB17 EA02 EB03 EB04 EB06 EB07 EB08 EB09 EB13 EB18 EB19 EC04 GA10

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 (A)エポキシ樹脂、(B)フェノール
樹脂、(C)硬化促進剤、及び(D)無機充填材を主成
分とするエポキシ樹脂組成物において、該エポキシ樹脂
組成物を加熱硬化した硬化物の特性が、成形温度での曲
げ弾性率をa(N/mm)、硬化収縮率をb(%)、
成形温度から室温までの熱収縮率をc(%)とすると
き、a≦10(式中、R=7−10×(b+c)であ
る)、300≦a≦5000、0.15≦b+cである
ことを特徴とする半導体封止用エポキシ樹脂組成物。
1. An epoxy resin composition containing (A) an epoxy resin, (B) a phenolic resin, (C) a curing accelerator, and (D) an inorganic filler as main components, wherein the epoxy resin composition is heat-cured. The properties of the cured product are as follows: a (N / mm 2 ), the flexural modulus at the molding temperature, b (%), the curing shrinkage,
When the heat shrinkage from the molding temperature to room temperature is c (%), a ≦ 10 R (where R = 7−10 × (b + c)), 300 ≦ a ≦ 5000, 0.15 ≦ b + c An epoxy resin composition for semiconductor encapsulation, wherein
【請求項2】 基板の片面に半導体素子が搭載され、こ
の半導体素子が搭載された基板面側の実質的に片面のみ
が請求項1記載のエポキシ樹脂組成物によって封止され
ていることを特徴とする半導体装置。
2. A semiconductor device is mounted on one surface of a substrate, and substantially only one surface on the substrate surface side on which the semiconductor device is mounted is sealed with the epoxy resin composition according to claim 1. Semiconductor device.
【請求項3】 樹脂封止面積に対する半導体素子面積の
比率が、25%以上である請求項2記載の半導体装置。
3. The semiconductor device according to claim 2, wherein the ratio of the semiconductor element area to the resin sealing area is 25% or more.
JP2000311387A 2000-10-12 2000-10-12 Epoxy resin composition and semiconductor device Pending JP2002121357A (en)

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