JP2002111061A - Nitride semiconductor element and electrode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure of a low-resistance ohmic contact by suppressing formation of a pin hole using an electrode structure which suppresses diffusion of a nickel after an electrode metal is thermally processed, for improved adhesion and contact area between a semiconductor and the electrode metal. SOLUTION: On a nickel layer 5 of 20 nm or less over a nitride semiconductor 3, a platinum layer 6 of 20 nm and a gold layer 7 of 20 nm are formed repeatedly more than once. Such property as a nickel is harder to disperse in a gold layer than a platinum layer as well as such fact as a dispersion is suppressed at a interface between different elements are utilized to make the gold layer such as 7 and 9 inserted between the platinum layers suppress dispersion of the nickel, thus suppressing formation of a void such as a pin hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride semiconductor electrode.

[0002]

2. Description of the Related Art Gallium nitride-based materials are mainly used for light emitting diodes and laser diodes in the ultraviolet to blue wavelength region. By combining a p-type semiconductor and an n-type semiconductor in which an impurity is added to a gallium nitride-based compound semiconductor, it can be used as an optical device such as a blue-violet light emitting diode or a laser.

In order to make such devices more practical, it is necessary to reduce the drive current and drive voltage, and realizing a low-resistance contact electrode having ohmic characteristics is the most important issue. As one means for solving such a problem, it is necessary to reduce the contact resistance generated at the interface between the semiconductor layer and the electrode metal. Conventionally, a good ohmic contact has been obtained by forming a laminated structure of nickel (Ni) and gold (Au) as an electrode of a p-type gallium nitride based compound semiconductor and performing a heat treatment.

In general, as an electrode of a p-type gallium nitride based compound semiconductor, a structure in which nickel (Ni) and gold (Au) are laminated, as disclosed in Japanese Patent Application Laid-Open No. H5-291621, is famous. In the case of an electrode having only a gold layer, the contact between gold and a gallium nitride-based compound semiconductor is poor, and most of the electrode is peeled off during the process. Therefore, a technique has been devised to increase the adhesion between the electrode metal and the nitride semiconductor by sandwiching nickel between them.

As shown in FIG. 2, a nickel layer 5 and a gold layer 1
Barrier metal (platinum is taken here) layer 6 between 1
Has a role of reducing the contact potential and preventing the diffusion of other elements into the gold layer, and is preferable in terms of maintaining the performance of the electrode. In this way, nickel (Ni) and gold (Au)
Can be compensated for in the structure in which the two metals are directly mixed together with the heat treatment to increase the sheet resistance.

[0006]

As described above, a nickel-gold (Ni / Au) structure and a nickel-platinum-gold (Ni / Pt / Au) structure are known as the conventional electrode structures. (Fig. 2). Such an electrode metal is mainly formed by using an electron beam evaporator. However, when the thickness of the lowermost layer of nickel 5 is small, the nickel 5 does not exist flatly.
As shown as 5, it is formed in an island shape. However, when heat treatment is applied to such an electrode structure,
The island-shaped nickel 5 passes through the grain boundaries 12 of the platinum layer 6 and the gold layer 11 and reaches the surface. This grain boundary refers to between crystal grains. At this time, the island portion after the movement of the nickel becomes pinhole (hollow). As a result, the contact area of the conventional gallium nitride-based compound semiconductor electrode is reduced and the current injection path is deviated, so that a high contact resistance is generated at the interface between the electrode metal and the semiconductor. In order to reduce the drive voltage and drive current, it is necessary to prevent such hollowing and prevent the current injection path from being biased.

[0007] As described above, nickel is greatly diffused by the heat treatment, and part of the nickel reaches the electrode surface through the grain boundaries of the platinum layer and the gold layer to form an oxide (NiO or the like) at the surface portion. Since nickel oxide has high resistance, a high-resistance layer is formed on the surface portion. Further, when the nickel layer and the gold layer are mixed with each other by the heat treatment, the sheet resistance increases, so that it is necessary to suppress the diffusion of the nickel layer.

The present invention provides an electrode structure that suppresses the diffusion of an electrode metal such as nickel and obtains an ohmic contact with a gallium nitride-based compound semiconductor. By reducing the drive current and drive voltage, the life of the element itself is improved, thereby contributing to the practical use of the device.

The island-shaped nickel
As a means for preventing the diffusion of 5 through the grain boundaries 12 of the platinum layer 6 and the gold layer 11 to the surface, it is conceivable to make the platinum layer 6 which is a barrier metal sufficiently thick. However, increasing the thickness of platinum makes it difficult to obtain an ohmic contact, which is not practical.

[0010]

According to the present invention, in order to suppress the diffusion of nickel (or titanium), the gold layer is more difficult to diffuse than the platinum layer, and the diffusion is suppressed at the interface of elements different from each other. Utilizing such a property, an electrode structure in which a platinum-containing layer and a gold-containing layer are repeatedly laminated is used.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a first embodiment, a nickel (Ni) layer is provided on a nitride semiconductor, and a platinum (Pt) layer is formed thereon.
An electrode in which a gold (Au) layer is formed twice or more is used for a nitride semiconductor device. In the second embodiment, a nickel layer is provided on a nitride semiconductor, and a platinum layer is laminated thereon,
An electrode in which a nickel layer is provided again and a platinum layer and a gold layer are formed thereon one or more times is used for a nitride semiconductor device. In the third embodiment, an electrode in which nickel and platinum layers mixed on a nitride semiconductor are formed is used for a nitride semiconductor device. In the fourth embodiment, an electrode in which nickel and platinum layers are alternately formed two or more times on a nitride semiconductor is used for a nitride semiconductor element. In the fifth embodiment, the thickness of nickel is set to 20 nm or less in the first to fourth embodiments. In the first to fifth embodiments, titanium may be used instead of nickel.

Further, a sixth embodiment is a nitride semiconductor device having an electrode above a p-type nitride semiconductor,
The electrode includes a first layer having Ni or Ti, a second layer formed above the first layer, and a third layer formed above the second layer. , The second layer and the third layer have Au. Note that a layer that is more easily thermally diffused than the second layer may be provided between the first layer and the second layer. Further, a layer which is more easily thermally diffused than the third layer may be provided between the second layer and the third layer.

Hereinafter, specific embodiments will be described with reference to the drawings.

The following electrodes are provided on a p-type nitride semiconductor.

First, nickel 5 is deposited to a thickness of 20 nm or less, and then a platinum layer 6 is formed thereon to a thickness of about 20 nm, and a gold layer 7 is similarly formed to a thickness of about 20 nm. The thickness of the platinum and gold layers is desirably between 5 and 50 nm. Such a platinum layer and a gold layer are repeatedly formed two or more times, and the uppermost gold layer 11 is formed to have a thickness of about 200 nm in order to strike a wiring wire. Since the diffusion of nickel is suppressed by the structure in which the platinum layer and the gold layer are repeatedly laminated, formation of a cavity such as a pinhole can be prevented.

By adopting the above-mentioned structure, by preventing cavitation in the electrode metal, the adhesion and the contact area are greatly improved, and it is possible to prevent the current injection path from being biased. As a result, the contact resistance at the interface between the electrode metal and the semiconductor can be reduced, and the drive voltage and drive current of the device can be reduced by forming an electrode with good ohmic properties on the p-type nitride semiconductor. it can.

The above is the electrode of the p-type nitride semiconductor, and the electrode on the n-type nitride semiconductor is not particularly limited.

FIG. 3 shows a sample of the p-type gallium nitride semiconductor studied this time. All of these samples were obtained by crystal growth on the sapphire substrate 1 by metal organic chemical vapor deposition (MOVPE). Mg as a dopant for p-type Ga _x Al _1-x N
And crystal growth was performed using Si for n-type Ga _x Al ₁ -xN. p
The type electrode is formed on the gallium nitride semiconductor layer containing such a p-type impurity.

Since the present invention relates to a p-type electrode portion, the layer structure of the gallium nitride semiconductor is not particularly limited. Further, the crystal growth method may be a method other than the above-mentioned metal organic chemical vapor deposition method.

The surface of the p-type gallium nitride semiconductor thus formed is washed with an organic solvent such as acetone or methanol and dried, and then heat-treated at 700 to 800 ° C. to activate magnesium as a p-type dopant. For about 20 to 30 minutes. Subsequently, after buffer etching, washing and drying, an electrode metal layer is formed by a technique such as electron beam evaporation or sputtering. FIG. 1 is an enlarged view of the p-type electrode portion 5-11 of FIG. Nickel 5 is deposited to a thickness of less than 20 nm. When the film thickness of nickel is small, nickel located in the lowermost layer does not exist flat, and is formed in an island shape as shown in 5 in FIG. Subsequently, a platinum layer 6 having a thickness of about 20 nm is formed thereon, and then a gold layer 7 is formed with a thickness of about 20 nm. The thickness of the platinum and gold layers is desirably between 5 and 50 nm. Such a platinum layer and a gold layer are repeatedly formed two or more times, and the uppermost gold layer 11 is formed to have a thickness of about 200 nm in order to strike a wiring wire.

After electrode deposition, heat treatment is performed in a nitrogen atmosphere by an infrared annealing furnace. The temperature of the heat treatment is preferably in the range of 200 ° C. or more and 700 ° C. or less. If it exceeds 700 ° C., there is a possibility that the gallium nitride semiconductor layer will be affected.

When heat treatment is applied to such an electrode structure, in the case of a conventional nickel-platinum-gold structure as shown in FIG. 2, the nickel layer passes through the grain boundaries 12 of the platinum layer 6 and the gold layer 11. Reach the surface. This grain boundary refers to between crystal grains. At this time, the island portion after the movement of the nickel 5 becomes a pinhole (hollows).
As a result, the contact area of the conventional gallium nitride-based compound semiconductor electrode is reduced and the current injection path is deviated, so that a high contact resistance is generated at the interface between the electrode metal and the semiconductor. The diffusion of nickel during the heat treatment is more difficult in the gold layer than in the platinum layer. Also,
Diffusion is greatly suppressed at different element interfaces. In order to utilize such properties, a multilayer structure in which a platinum layer and a gold layer are repeatedly laminated is employed, whereby surface diffusion of nickel due to heat treatment is suppressed, and the formation of cavities such as pinholes can be prevented.

In place of the above-mentioned nickel, a titanium (Ti) layer having a high work function and having the same adhesiveness as nickel may be used.

FIG. 4 shows another method for preventing the formation of cavities.
As described above, nickel 5 is deposited in a thickness of 20 nm or less, a platinum layer 6 is formed in a thickness of about 20 nm, and then, instead of gold, nickel 13 is formed again in a thickness of 20 nm or less instead of gold. Subsequently, a platinum layer 8 is formed on the order of 20 nm, and then the gold layer 9 is
Form about 0 nm. The thickness of the above platinum and gold layers is 5-50
Preferably between nm. Such platinum layer and gold layer
It is formed repeatedly two or more times, but the uppermost gold layer 11 is formed to have a thickness of about 200 nm in order to strike a wiring wire. After electrode deposition, heat treatment is performed in a nitrogen atmosphere by an infrared annealing furnace. The temperature of the heat treatment is preferably in the range of 200 ° C. or more and 700 ° C. or less. At this time, nickel 5 and nickel layer 7
Between them, mutual diffusion occurs up and down via the grain boundaries 12 in the platinum layer 6, and cavitation can be suppressed.

FIG. 5 shows another method for preventing the formation of cavities.
As described above, when the nickel 5 and the platinum layer 6 are formed, they are formed at once using an alloy 14 of nickel and platinum. The film thickness using this alloy is desirably 50 nm or less. By forming a mixed nickel and platinum layer, the grain boundary diffusion of nickel in platinum 6 can be further suppressed.

FIG. 6 shows another method for preventing the formation of cavities.
As described above, when the nickel 5 and the platinum layer 6 are formed, nickel and platinum are alternately formed with a thickness of every 5 nm. The thicknesses of the nickel and platinum are not particularly limited, but the total thickness of the alternately formed portions is desirably 50 nm or less. By forming such a structure, the grain boundary diffusion of nickel in platinum 6 can be further suppressed.

By adopting the above-described manufacturing method, it is possible to prevent cavitation in the electrode metal and prevent the current injection path from being biased. As a result, the contact resistance at the interface between the electrode metal and the semiconductor can be reduced, and the drive voltage and drive current of the device can be reduced by forming an electrode with good ohmic properties on the p-type nitride semiconductor. it can.

The present invention relates to an electrode in a p-type nitride semiconductor, and the electrode on the n-type nitride semiconductor is not particularly limited.

[0029]

As described above, according to the present invention, it is possible to prevent cavitation in the electrode metal and prevent the current injection path from being biased. As a result, the contact resistance at the interface between the electrode metal and the semiconductor can be reduced, and by forming an electrode with good ohmic properties on the p-type nitride semiconductor, the device drive voltage and
The drive current can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a light emitting device according to one embodiment of the present invention.

FIG. 2 is a diagram showing a conventional electrode structure (example: nickel-platinum-gold structure)

FIG. 3 is an enlarged schematic sectional view of an electrode structure according to an embodiment of the present invention.

FIG. 4 is an enlarged sectional view of an electrode structure according to an embodiment of the present invention, in which a gold layer 7 of FIG.

5 is an enlarged cross-sectional view of an electrode structure according to an embodiment of the present invention, in which nickel 5 and platinum layer 6 in FIG. 1 are replaced with a mixed layer 14 of nickel and platinum.

FIG. 6 is an enlarged view of an electrode structure according to an embodiment of the present invention, in which a nickel 5 and a platinum layer 6 of FIG. 1 are replaced with a portion 15 in which thin films of nickel and platinum are alternately formed.

[Explanation of symbols]

 Reference Signs List 1 sapphire substrate 2 n-type gallium nitride (GaN) layer 3 p-type gallium nitride (GaN) layer 4 n-type electrode 5 nickel (Ni) layer 6 platinum (Pt) layer 7 gold (Au) layer 8 platinum layer 9 gold layer 10 Platinum layer 11 Gold layer Wire bonding 12 Grain boundary of platinum layer 13 Nickel layer 14 Mixed layer of nickel and platinum 15 Part where thin films of nickel and platinum are alternately formed

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA04 BB05 BB14 DD34 DD37 DD78 FF13 GG04 HH05 HH15 5F041 AA21 AA24 CA34 CA57 CA65 CA73 CA82 CA92 5F073 CA02 CA07 CB05 CB22 CB23 EA29

Claims (9)

[Claims] An electrode having a nickel (Ni) layer provided on a nitride semiconductor and a platinum (Pt) layer and a gold (Au) layer formed thereon two or more times. 2. An electrode in which a nickel layer is provided on a nitride semiconductor, a platinum layer is laminated thereon, a nickel layer is provided again, and a platinum layer and a gold layer are formed thereon one or more times. 3. An electrode, wherein a mixed nickel and platinum layer is formed on a nitride semiconductor. 4. A nickel and platinum layer on a nitride semiconductor.
An electrode characterized by being formed alternately at least twice. 5. The electrode according to claim 1, wherein the thickness of the nickel is 20 nm or less. 6. The electrode according to claim 1, wherein titanium is used instead of nickel. 7. A nitride semiconductor device having an electrode above a p-type nitride semiconductor, wherein the electrode is made of Ni or Ti.
And a second layer formed above the first layer, and a third layer formed above the second layer, wherein the second layer Layer and the third layer are made of Au
A nitride semiconductor device comprising: 8. The nitride semiconductor device according to claim 7, further comprising a layer between the first layer and the second layer, the layer being more easily thermally diffused than the second layer. 9. The nitride according to claim 7, further comprising, between the second layer and the third layer, a layer that is more easily thermally diffused than the third layer. Semiconductor element.