TW565933B - Method of forming ohmic electrode - Google Patents

Method of forming ohmic electrode Download PDF

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TW565933B
TW565933B TW091125046A TW91125046A TW565933B TW 565933 B TW565933 B TW 565933B TW 091125046 A TW091125046 A TW 091125046A TW 91125046 A TW91125046 A TW 91125046A TW 565933 B TW565933 B TW 565933B
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layer
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ohmic electrode
compound semiconductor
based compound
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Mayuko Fudeta
Toshio Hata
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Sharp Kk
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40Materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Led Devices (AREA)
  • Semiconductor Lasers (AREA)
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Abstract

There is provided a method of forming an ohmic electrode, including the steps of: forming a hafnium layer on a surface of an n type nitride-based compound semiconductor layer to have a thickness of 1 to 15 nm; forming an aluminum layer on the hafnium layer; and annealing the hafnium layer and the aluminum layer to form a layer formed of hafnium and aluminum mixed together.

Description

565933565933

玟、發明說明 貝ie方式及圖式簡單說明) (發明說明應敘明:發明所屬之技術領域、先前技術、内容、 發明領域 本發明係屬於形成一個形成於一n型氮化基之化合物半 導體層上之歐姆電極,以及特別是關於形成具有低電阻、 難以剝離一η型氮化基之化合物半導體層以及提供良好歐 姆接觸之一歐姆電極之方法。 發明背景(Ii) Brief description of the invention and the method and drawings) (The description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the field of the invention. The invention belongs to the formation of a compound semiconductor formed on an n-type nitride group. An ohmic electrode on a layer, and in particular, a method for forming an ohmic electrode having a low resistance, difficult to peel an n-type nitride-based compound semiconductor layer, and providing a good ohmic contact. BACKGROUND OF THE INVENTION

傳統上已知氮化基之化合物半導體例如以Ιηχ(}^Αι^Ν 代表,可使用為藍色發光裝置,其中 及X + y^l,而且在近幾年中藍色發光二極體、紫色半導體 雷射以及類似物正被研究。這些發光二極體以及半導體^ 射需要由外部接收一電流。因此,提供之歐姆電極材料以 及形成相同歐姆電極之技術非常重要。Conventionally known nitride-based compound semiconductors are represented by, for example, Iηχ (} ^ Αι ^ N, which can be used as blue light-emitting devices, and X + y ^ l, and in recent years, blue light-emitting diodes, Purple semiconductor lasers and the like are being studied. These light-emitting diodes and semiconductors need to receive a current from the outside. Therefore, the ohmic electrode material provided and the technology for forming the same ohmic electrode are very important.

+形成於一 η型氮化基之化合物半導體層上之一典型歐姆 兒極例如在曰本專利已公開專利案案號為第7-45 867號中 揭示^該電極是以堆疊之一鈦(丁丨)層以及一鋁層(αι)形成以 及之仗退火之一歐姆電極(此後視為” Ti/Al電極,,)。此外在 曰本應用物理學會第6〇週年會議論文集第3()2頁(演講報告 編號第n14號)具有Ti/A1電極之熱穩定度極優越以及允 許在攝氏400度至600度之較寬溫度範圍内退火之一歐姆電 極之報σ。依據泫報告,該歐姆電極由形成於η型氮化基之 化合物半導體層上之一铪(Hf)層以及堆疊於該铪層上之αι 層形成(此後視為一”Hf/Al電極")。 然而,上文報告之Hf/Al電極,藉由堆疊HfAAi而形成不 565933+ A typical ohmic pole formed on an n-type nitride-based compound semiconductor layer is disclosed, for example, in Japanese Patent Publication No. 7-45 867. The electrode is a stack of titanium ( Ding) and an aluminum layer (αι) are formed and annealed as an ohmic electrode (hereinafter referred to as "Ti / Al electrode,"). In addition, in the Proceedings of the 60th Anniversary Conference of the Applied Physics Society, 3 ( ) 2 pages (speech report No. n14) Report σ with excellent thermal stability of Ti / A1 electrodes and an ohmic electrode that allows annealing in a wide temperature range of 400 ° C to 600 ° C. According to the report, The ohmic electrode is formed of a hafnium (Hf) layer formed on an n-type nitride-based compound semiconductor layer and an αι layer stacked on the hafnium layer (hereinafter referred to as a "Hf / Al electrode"). However, the Hf / Al electrode reported above was formed by stacking HfAAi.

用特別控制包含右# 3在遠電極内之Hf及A1内容。因此製造之該Use special controls to include Hf and A1 content of the right # 3 in the far electrode. So make it

Hf/Al電極具有_非& #吊粗糙表面以及提供與該η型氮化基 “ 〇物半‘ 層之不良接觸,以致於具有高電阻。此外 4包極可以被剝離該半導體層而因此無法提供良好歐姆 接觸。 發明總結 鑑於上述情況’本發明仔細考量一種形成具有低電阻、 難以剝離一 11型氮化基之化合物半導體層以及提供良好歐 姆接觸之一歐姆電極之方法。 本舍明本發明提供一種形成一歐姆電極之方法,包含下 列步驟:形成一铪層於n型氮化基之化合物半導體層之一表 面上以具有1至15 nm之厚度;形成一鋁層於該铪層上;以 及將該铪層與該鋁層退火以形成由铪與混合一起形成之一 層。請注意在本規範中,”〇/〇”代表,,質量之%”。 本發明前述以及其他目的、態樣、特徵以及優點當由本 發明下文之詳細說明與附圖結合時將變成更明顯。 圖式之簡單說明 在附圖中: 圖1代表介於Hf内容與介於一 η型氮化基之化合物半導體 層與Hf及Α1混合一起形成之一層之間之一介面鄰近區域之 電阻之間之一關係; 圖2為一第一例子之一發光氮化基之化合物半導體裝置 之一圖式橫截面; 圖3代表量測介於第一例子之發光氮化基之化合物半導 (3)565933 體裝置提供之該等歐姆電極之間之電流_電壓特徵之一結 果; 、、’° 圖4為一第一例子之發光氮化基之化合物半導體裝置之 一圖式上視圖; 之 圖5為一第二例子之發光氮化基之化合物半導體裝置 一圖式橫截面; 圖6為一第三例子之發光氮化基之化合物半導體裝置之 一圖式橫截面; 圖7為一第三例子之發光氮化基之化合物半導體裝置之 一圖式上視圖; 圖8為正製造之一第四例子之發光氮化基之化合物半導 體裝置之一圖式橫戴面; 圖9為完成之一第四例子之發光氮化基之化合物半導體 裝置之一圖式橫截面; 圖10為一第五例子之發光氮化基之化合物半導體裝置之 一圖式橫截面; 圖11為正製造之一第六例子之發光氮化基之化合物半導 體裝置之一圖式橫戴面;以及 圖12為完成之一第六例子之發光氮化基之化合物半導體 裝置之一圖式橫截面; 圖式之詳細說明 本發明提供一歐姆電極,具有特徵為在介於一 ^型氮化基 之化合物半導體層與該歐姆電極之間之一介面鄰近區域具 有小於0.001 %至小於或等於50%之Hf内容以及小於或等於The Hf / Al electrode has a non-smooth surface and provides poor contact with the n-type nitride-based "〇 物 半 '" layer, so as to have a high resistance. In addition, the 4 clad electrode can be peeled off the semiconductor layer and therefore Unable to provide good ohmic contact. Summary of the invention In view of the above, the present invention carefully considers a method of forming an ohmic electrode with a low resistance, difficult to peel a type 11 nitride-based compound semiconductor layer, and providing a good ohmic contact. The invention provides a method for forming an ohmic electrode, comprising the following steps: forming a hafnium layer on a surface of an n-type nitride-based compound semiconductor layer to have a thickness of 1 to 15 nm; forming an aluminum layer on the hafnium layer And annealed the hafnium layer with the aluminum layer to form a layer formed by hafnium and mixing. Please note that in this specification, "〇 / 〇" stands for "% by mass". The foregoing and other objects, aspects, features, and advantages of the present invention will become more apparent when the following detailed description of the present invention is combined with the accompanying drawings. A brief description of the figure is in the drawings: Figure 1 represents the resistance between an interface adjacent region between the Hf content and a compound semiconductor layer interposed between an n-type nitride group and Hf and A1. A relationship; FIG. 2 is a schematic cross-section of a light emitting nitride-based compound semiconductor device according to a first example; FIG. 3 represents the measurement of a semiconductor compound of a light emitting nitride-based compound according to the first example (3) 565933 One of the results of the current-voltage characteristics between the ohmic electrodes provided by the bulk device; Figure 4 is a schematic top view of a first example of a light-emitting nitride-based compound semiconductor device; Figure 5 A schematic cross-section of a light-emitting nitride-based compound semiconductor device as a second example; FIG. 6 is a schematic cross-section of a light-emitting nitride-based compound semiconductor device as a third example; FIG. 7 is a third example A schematic top view of a light-emitting nitride-based compound semiconductor device; FIG. 8 is a schematic cross-sectional view of a light-emitting nitride-based compound semiconductor device that is being manufactured as a fourth example; FIG. 9 is a completed first Four examples A schematic cross-section of a nitride-based compound semiconductor device; FIG. 10 is a schematic cross-section of a fifth example of a light-emitting nitride-based compound semiconductor device; FIG. 11 is a light-emitting nitrogen of a sixth example being manufactured A schematic cross-sectional view of a compound semiconductor device based on a chemical compound; and FIG. 12 is a schematic cross-section view of a light-emitting nitride-based compound semiconductor device completed as a sixth example; Detailed description of the drawings The present invention provides one ohm An electrode having an Hf content of less than 0.001% to less than or equal to 50% and an area of less than or equal to an interface adjacent region between a compound semiconductor layer of a ^ -type nitride-based compound and the ohmic electrode

565933 50%至小於或等於99.999%之A1内容。此情形以及由本發明 從下列電阻量測及通電測試結果發現; 電阻量測 由AI及Hf形成之一歐姆電極被製造於一 n型GaN半導體 之一表面上。圖丨代表介KHf内容與介於〇型氮化基之化合 物半導體層與該歐姆電極之間之一介面鄰近區域之電阻之 間之一關係。在圖1中,水平軸代表内容(質量百分比)以 及垂直軸代表電阻。 ⑴樣本之準備 由間隔500 μηι以及配置於摻雜矽之GaN半導體之一表面 上之歐姆電極形成之點電極被提供為一樣本。該等歐姆電 極藉由次相沈積一 Hf層於一摻雜矽之GaN半導體及一 A!層 上以在該Hf層上具有15〇 nm2厚度以及之後以攝氏$㈧度 相同退火二分鐘而形成。對各樣本而言,該Hf層之厚度由 0.5 nm至15〇 nm作變化以允許Hf内容在介於該n型氮二基 之化合物半導體層與該歐姆電極之間之一介面鄰近區域在 小於0.001%至小於或等於90%之範圍内。 (ii) 電阻量測之方法 電阻為藉由增加-電壓直到5〇 mA之一電流在介於各樣 本之鄰近點電極之間流動時為止所獲得之圖形加以計算。 (iii) 量測結果 如圖1所示,在該介面鄰近區域具有小K〇〇〇i%2Hf内容 之樣本提供南電阻。此外,在該介面鄰近區域具有大於 50%之Hf内容之-樣本亦提供高電阻。在這些案例中,介 (5) (5)565933 於该n型氮化基之化合物半導體層與該等點電極之間之一 些介面無法提供足夠之歐姆接觸。 此外’在該介面鄰近區域具有小於〇.〇〇1 %至小於或等於 50%之Hf内容之樣本在電阻方面沒有變化以及在介於任意 二點電極之間具有低電阻。 請注意上述Hf内容量測被使用二次離子質譜儀(SIMS)、 電子微探儀(ΕΡΜΑ)或類似物加以提供。 通電測試 ⑴樣本 在’丨於一 η型氮化基之化合物半導體層與該歐姆電極之 間之一介面鄰近區域具有小於〇·〇〇1%之HfR容之歐姆電極 之一發光氮化基之化合物半導體裝置、以及具有在該介面 鄰近區域具有大於50%之Hf内容以及小於5〇〇/〇2A1内容之 歐姆電極之一發光氮化基之化合物半導體裝置被提供為樣 本。 (ii)通電測試程序 在大氣壓中’該等樣本以3〇 之電流通電5〇〇〇小時, 同時各歐姆電極之表面狀況及剝離以及各樣本之發光以及 類似情形被觀察。 (i i i)測試結果 具有小於0.001%之Hf内容之樣本早先衰減以及失去歐姆 接觸,例如剝離以及在可靠度上被削弱。 具有大於50%之Hf内容以及小於50%之A1内容之樣本在 介於η型氮化基之化合物半導體層與該歐姆電極之間之介 -10· 565933565933 50% to less than or equal to 99.999% of A1 content. This situation and the present invention are found from the following resistance measurement and energization test results; resistance measurement An ohmic electrode formed of AI and Hf is fabricated on a surface of an n-type GaN semiconductor. Figure 丨 represents a relationship between the content of the intermediary KHf and the resistance of a region adjacent to the interface between the 0-type nitride-based compound semiconductor layer and the ohmic electrode. In Figure 1, the horizontal axis represents content (mass percentage) and the vertical axis represents resistance. ⑴Sample preparation A spot electrode consisting of an ohmic electrode spaced 500 μm apart and arranged on one surface of a silicon-doped GaN semiconductor was provided as a sample. The ohmic electrodes are formed by secondarily depositing an Hf layer on a silicon-doped GaN semiconductor and an A! Layer to have a thickness of 150 nm2 on the Hf layer and then annealing at the same temperature for two minutes at the same temperature. . For each sample, the thickness of the Hf layer was changed from 0.5 nm to 150 nm to allow the Hf content to be less than one interface adjacent to the interface between the n-type nitrogen-based compound semiconductor layer and the ohmic electrode. The range is from 0.001% to 90%. (ii) Method of resistance measurement Resistance is calculated by increasing the -voltage until a current of 50 mA flows when a current flows between adjacent point electrodes of each sample. (iii) Measurement results As shown in Fig. 1, samples with a small content of KOOi% 2Hf in the vicinity of the interface provide south resistance. In addition, samples with Hf content greater than 50% in the vicinity of the interface also provide high resistance. In these cases, some of the interfaces between (5) (5) 565933 between the n-type nitride-based compound semiconductor layer and the point electrodes did not provide sufficient ohmic contact. In addition, a sample having Hf content in the vicinity of the interface of less than 0.0001% to less than or equal to 50% has no change in resistance and has low resistance between any two-point electrodes. Please note that the above Hf content measurement is provided using a secondary ion mass spectrometer (SIMS), an electronic microprobe (EPMA), or the like. Power-on test: The sample is one of the light-emitting nitride-based ohmic electrodes in an area adjacent to an interface between an n-type nitride-based compound semiconductor layer and the ohmic electrode and having an HfR capacity of less than 0.001%. Compound semiconductor devices, and light emitting nitride-based compound semiconductor devices having one of the ohmic electrodes having an Hf content of more than 50% and an ohmic content of less than 5000 / 002A1 in the vicinity of the interface were provided as samples. (ii) Power-on test procedure At atmospheric pressure, the samples were energized at a current of 30 for 5,000 hours. At the same time, the surface condition and peeling of each ohmic electrode and the luminescence and similar conditions of each sample were observed. (i i i) Test results Samples with Hf content less than 0.001% were previously attenuated and lost ohmic contact, such as peeling and impaired reliability. Samples with Hf content greater than 50% and A1 content less than 50% between the n-type nitride-based compound semiconductor layer and the ohmic electrode -10 · 565933

面具有一不足之接觸部分,以及該歐姆電極具有一非常粗 糙之表面。因此,該樣本在可靠度上被削弱。 由這些結果發現,形成於一n型氮化基之化合物半導體層 之一表面上之一歐姆電極在介於該n型氮化基之化合物半 ‘體層與έ亥i姆電極之間之一介面鄰近區域具有小於 〇_〇〇1%至小於或等於50%之Hf内容與小於5〇%至小於或等 於99.999 %之A1内容為較佳。這是因為相信為獲得介於一歐 姆電極與一 η型氮化基之化合物半導體層之間之良好接觸 ,該電極需要具有一特定量之Hf以及與該半導體層接觸之 特定量A1。 此外,亦已經發現該歐姆電極之Hf&Al内容可以容易藉 由形成一 Hf層於一 n型氮化基之化合物半導體層之一表面 上以具有1至15 nm之一厚度以及形成一 μ層於該層上而被 控制為落於上述範圍内。 例子The mask has an insufficient contact portion, and the ohmic electrode has a very rough surface. Therefore, the sample is weakened in reliability. From these results, it was found that an interface between an ohmic electrode formed on a surface of an n-type nitride-based compound semiconductor layer and an intermediate electrode layer between the n-type nitride-based compound semi-body layer and a helium electrode It is preferable that the adjacent area has an Hf content of less than 0.001% to 50% and an A1 content of less than 50% to 99.999%. This is because it is believed that in order to obtain a good contact between an ohmic electrode and an n-type nitride-based compound semiconductor layer, the electrode needs to have a specific amount of Hf and a specific amount of contact A1 with the semiconductor layer. In addition, it has also been found that the Hf & Al content of the ohmic electrode can be easily formed by forming an Hf layer on a surface of an n-type nitride-based compound semiconductor layer to have a thickness of 1 to 15 nm and forming a μ layer It is controlled to fall within the above range on this layer. example

此後之例子被用以使用本發明之歐姆電極更特定說明 發光氮化基之化合物半導體裝置。 第一例子 參考圖2,一第一例子提供包含一藍寶石基板丨、一緩$ 層2、- n型氮化基之化合物半導體層3、一歐姆電極… 塾電極5、一 η型電極6、一發光層7、一卩型披覆層8、1 型接觸層9、一ρ型歐姆電極1〇、_ρ型墊電極丨丨以及一透明 導電膜12之一發光氮化基之化合物半導體裝置。 第一例子之發光氮化基之化合料導體裝置如此後特定 說明般被製造。 -11· 565933The following example is used to more specifically illustrate a light emitting nitride-based compound semiconductor device using the ohmic electrode of the present invention. First Example Referring to FIG. 2, a first example provides a sapphire substrate, a buffer layer, a compound semiconductor layer of an n-type nitride group, an ohmic electrode, a rhenium electrode, an n-type electrode, A light emitting layer 7, a yoke-type cladding layer 8, a type 1 contact layer 9, a p-type ohmic electrode 10, a p-type pad electrode, and a light-emitting nitride-based compound semiconductor device of one of the transparent conductive films 12. The light emitting nitride-based compound conductor device of the first example is manufactured as described below. -11 · 565933

⑺ 在一藍寶石基板1上緩衝層2被形成以及在該層上面11型 氮化基之化合物半導體層3由摻雜矽(Si)之GaN形成。之後 在半導體層3上多量子井發光層7由GaN形成之一障蔽層以 及由InGaN形成之一井層形成。在發光層了上口型披覆層8由 摻雜鎂(Mg)之AlGaN形成。在p型披覆層8上1)型接觸層9由 摻一 Mg之GaN形成。在p型接觸層9上p型歐姆電極iq藉由汽 相沈積7 nm厚度之把(Pd)層形成。 在p型歐姆電極10上p型墊電極^由厚度15 nm2Pd層形 成以及厚度500 nm之一金(Au)層形成於上面。p型墊電極" 藉由汽相沈積使用一金屬遮罩形成。 一發光區域之後被形成。更特定地是,光阻劑被應用於p 型歐姆電極10以及p型墊電極丨丨上,以及p型歐姆電極1〇在 無光阻劑部分以鹽酸基之蝕刻劑蝕刻以形成一發光圖樣。 之後該光阻劑被移除。 摻雜Sn之Iri2〇3(ITO)之透明導電膜12被形成以藉由濺鍍 而覆蓋一部份ρ型墊電極U以及ρ型歐姆電極1〇之一表面。 以及一部份透明導電膜12以氣化鐵基之溶液蝕刻。 之後,光阻劑被使用為一乾式蝕刻之一遮罩以及反應性 離子蝕刻(RIE)被利用以蝕刻該中間產物以暴露半導體層3 之一表面。 歐姆電極4之後藉由剝離形成。更特定地是,光阻劑被均 勾一致地應用於該暴露之半導體層3上以及在將提供歐姆 電極4之一部份上該光阻劑被移除以提供一視窗。 之後包含厚度5 nm之一 Hf層以及形成於該Hf層上之厚度 565933缓冲 A buffer layer 2 is formed on a sapphire substrate 1 and an 11-type nitride-based compound semiconductor layer 3 on the layer is formed of GaN doped with silicon (Si). Thereafter, the multiple quantum well light emitting layer 7 on the semiconductor layer 3 is formed of a barrier layer formed of GaN and a well layer formed of InGaN. The light-emitting layer 8 is formed of AlGaN doped with magnesium (Mg). The 1) -type contact layer 9 on the p-type cladding layer 8 is formed of GaN doped with Mg. A p-type ohmic electrode iq is formed on the p-type contact layer 9 by vapor-depositing a 7 nm thick (Pd) layer. On the p-type ohmic electrode 10, a p-type pad electrode ^ is formed of a 15 nm2Pd layer and a gold (Au) layer having a thickness of 500 nm is formed thereon. The p-type pad electrode is formed by vapor deposition using a metal mask. A light emitting area is formed later. More specifically, a photoresist is applied to the p-type ohmic electrode 10 and the p-type pad electrode, and the p-type ohmic electrode 10 is etched with a hydrochloric acid-based etchant in a photoresist-free portion to form a light-emitting pattern. . The photoresist is then removed. Sn-doped Iri203 (ITO) transparent conductive film 12 is formed to cover a portion of a surface of a p-type pad electrode U and a p-type ohmic electrode 10 by sputtering. And a part of the transparent conductive film 12 is etched with a vaporized iron-based solution. Thereafter, a photoresist is used as a mask for a dry etching and a reactive ion etching (RIE) is used to etch the intermediate product to expose a surface of the semiconductor layer 3. The ohmic electrode 4 is then formed by peeling. More specifically, the photoresist is uniformly applied to the exposed semiconductor layer 3 and the photoresist is removed to provide a window on a portion where the ohmic electrode 4 will be provided. It then includes a Hf layer with a thickness of 5 nm and a thickness of 565933 formed on the Hf layer.

150 nm之八丨層被藉由剝離形成以在該半導體層3暴露之 表面上具有10 μιη之寬度。 孩Hf層以及该Hf層之後在真空中以攝氏5〇〇度退火3分鐘 以在歐姆電極4與半導體層3之介面鄰近區域形成八丨混 合區域。 圖3代表量測介於第一例子之發光氮化基之化合物半導 體裝置之泫等歐姆電極4之間之電流-電壓特徵之一結果以 確認歐姆接觸。已經發現良好歐姆接觸被獲得。Eighty 150 nm layers are formed by peeling to have a width of 10 μm on the exposed surface of the semiconductor layer 3. The Hf layer and the Hf layer are then annealed at 500 ° C. for 3 minutes in a vacuum to form eight mixed regions in the vicinity of the interface between the ohmic electrode 4 and the semiconductor layer 3. Fig. 3 represents a result of measuring one of the current-voltage characteristics between the ohmic electrode 4 and the ohmic electrode 4 of the luminescent nitride-based compound semiconductor device of the first example to confirm the ohmic contact. It has been found that good ohmic contact is obtained.

Hf及Α1在半導體層3與歐姆電極4之間之一介面鄰近區域 被混合一起,如已經說明般,以及已經發現介於11型氮化基 之化合物半導體層3與歐姆電極4之間之一介面鄰近區域包 含近似0.5%量之Hf以及近似99.5%量之A1。 由具有厚度15 nm之Pd層以及形成於該?4層上具有厚度 500 nm之A1層形成之非歐姆墊電極5之後藉由汽相沈積被 形成於歐姆電極4上以形成η型電極6。為非歐姆之塾電極5 允許一電流被足夠地導入,以致於一低電壓驅動之發光氮 化基之化合物半導體裝置可以被製造。 之後,基板1被接地以及拋光以具有近似100 μιη之厚度以 及劃分為350 μπι X 350 μιη之正方形以及一 Au線(沒有顯示) 被接合至p型墊電極11以及墊電極5以完成一發光氮化基之 化合物半導體裝置。 圖4為如此製造之發光氮化基之化合物半導體裝置之一 圖式上視圖。 此外,該如此製造之發光氮化基之化合物半導體裝置可 -13- 565933Hf and A1 are mixed together at an interface adjacent area between the semiconductor layer 3 and the ohmic electrode 4, as already explained, and have been found to be between one of the 11-type nitride-based compound semiconductor layer 3 and the ohmic electrode 4 The adjacent area of the interface contains approximately 0.5% of Hf and approximately 99.5% of A1. From a Pd layer with a thickness of 15 nm and formed there? A non-ohmic pad electrode 5 formed of an A1 layer having a thickness of 500 nm on 4 layers is then formed on the ohmic electrode 4 by vapor deposition to form an n-type electrode 6. The non-ohmic osmium electrode 5 allows a current to be sufficiently introduced so that a low-voltage driven luminescent nitride-based compound semiconductor device can be manufactured. After that, the substrate 1 is grounded and polished to have a thickness of approximately 100 μm and a square divided into 350 μm X 350 μm and an Au line (not shown) is bonded to the p-type pad electrode 11 and the pad electrode 5 to complete a luminescent nitrogen Chemical compound semiconductor device. Fig. 4 is a schematic top view of one of the light-emitting nitride-based compound semiconductor devices thus manufactured. In addition, the light-emitting nitride-based compound semiconductor device thus manufactured may be -13-565933

以用3.0 V之電壓驅動。-低電壓驅動之發光氮化基之化合 物半導體裝置因此可以被製造。 此外,該發光裝置被受到一通電測試以及在經過1〇,〇〇〇 小時週期之後該裝置沒有一電極例如剝離,而且已經發現 將具有高可靠度。 雖然η型氮化基之化合物半導體層3已經被由摻雜以之 GaN形成,但可以由例如摻雜Si之inGaN形成。 此外’雖然歐姆電極4起初已經藉由形成一 層於半導體 層3上以及之後形成一 A1層於該層上而被形成,但其起初可 以藉由形成一 A1層於半導體層3上以及之後形成一 層於 該層上而被形成。 第二例子 在第一例子中,Hf及A1層藉由汽相沈積提供以及之後在 真空中退火以形成具有Hf及A1層混合一起之一歐姆電極。 在第二例子中,在沈積一 Hf層或是一八丨層時一晶圓被加熱 以形成具有Hf及A1混合一起之一層之一電極。 參考圖5’該第一例子提供包含一藍寶石基板21、一緩衝 層22、一 n型氣化基之化合物半導體層23、一歐姆電極24 、一墊電極25、一 η型電極26、一發光層27、一p型披覆層 28、一 ρ型接觸層29、一 ρ型歐姆電極11〇、一 ρ型墊電極m 以及一透明導電膜112之一發光氮化基之化合物半導體裝 置。 第二例子之發光氮化基之化合物半導體裝置如此後特定 說明般被製造。 -14- 565933It is driven with a voltage of 3.0 V. -A low-voltage driven light-emitting nitride-based compound semiconductor device can therefore be manufactured. In addition, the light-emitting device was subjected to a power-on test and the device did not have an electrode such as peeling after a 10,000-hour period had passed, and it has been found that it will have high reliability. Although the n-type nitride-based compound semiconductor layer 3 has been formed of GaN doped with it, it may be formed of, for example, Si-doped inGaN. In addition, 'Although the ohmic electrode 4 has been initially formed by forming a layer on the semiconductor layer 3 and then forming an A1 layer on the layer, it can be initially formed by forming an A1 layer on the semiconductor layer 3 and thereafter It is formed on this layer. Second Example In the first example, the Hf and A1 layers were provided by vapor deposition and then annealed in a vacuum to form an ohmic electrode with the Hf and A1 layers mixed together. In the second example, when a Hf layer or an eighteen layer is deposited, a wafer is heated to form an electrode having a layer in which Hf and A1 are mixed together. Referring to FIG. 5 ′, the first example provides a sapphire substrate 21, a buffer layer 22, an n-type gasification-based compound semiconductor layer 23, an ohmic electrode 24, a pad electrode 25, an n-type electrode 26, and a light emitting device. A layer 27, a p-type cladding layer 28, a p-type contact layer 29, a p-type ohmic electrode 110, a p-type pad electrode m, and a light-emitting nitride-based compound semiconductor device of one of the transparent conductive films 112. The light emitting nitride-based compound semiconductor device of the second example is manufactured as described below. -14- 565933

(ίο) 第-例子中說明之相同程序被遵守直到該中間產物被乾 二蝕刻以暴露半導體層23之一表面為止。 歐姆電極24之後藉由剝離形成。更特定料,光阻劑被 均^-致地應用於該暴露之半導體層23上以及在將提供歐 姆電極24之一部份上該光阻劑被移除以提供一視窗。 ^後在,飞相沈積之前一晶圓被加熱至攝氏8〇度。由於該 曰曰圓保持在攝氏80度,一 Hf層被沈積以具有厚度3 _以及 在該層上一 A1層被沈積以具有厚度15〇 nmw及剝離被利用 以相同形成在該半導體層23之暴露表面上以具有寬度ι〇 Pm以形成歐姆電極24。 介於該等歐姆電極24之間之電流-電壓特徵被量測以及 類似於第一例子之特徵。已經發現在汽相沈積期間加熱一 晶圓可以刪除退火之需要性,如第一例子所說明,以提供 低電阻之一歐姆電極。 在歐姆電極24與半導體層23之間之一介面鄰近區域Hf及 A1被混合一起,以及已經發現介於半導體層23與歐姆電極 24之間之介面鄰近區域包含近似〇·5%量之Hf以及近似 99.5%量之A卜 形成非歐姆墊電極25之步驟以及該等後續步驟類似於第 一例子之那些步驟。 此外,該如此製造之發光氮化基之化合物半導體裝置可 以用3 ·0 V之電壓驅動。一低電壓驅動之發光氮化基之化合 物半導體裝置因此可以被製造。 此外,該發光裝置被受到一通電測試以及在經過1 〇,〇〇〇 -15- 565933(ίο) The same procedure described in the first example is followed until the intermediate product is dry-etched to expose one surface of the semiconductor layer 23. The ohmic electrode 24 is then formed by peeling. More specifically, the photoresist is uniformly applied to the exposed semiconductor layer 23 and the photoresist is removed to provide a window on a portion where an ohmic electrode 24 will be provided. Later, a wafer was heated to 80 degrees Celsius before flying deposition. Since the circle is maintained at 80 degrees Celsius, an Hf layer is deposited to have a thickness of 3 mm, and an A1 layer is deposited to have a thickness of 150 nmw and peeling is utilized to form the same in the semiconductor layer 23 The exposed surface has a width of 10 μm to form an ohmic electrode 24. The current-voltage characteristics between the ohmic electrodes 24 are measured and similar to the characteristics of the first example. It has been found that heating a wafer during vapor deposition can eliminate the need for annealing, as illustrated in the first example, to provide a low-resistance one-ohm electrode. One of the interface adjacent areas Hf and A1 between the ohmic electrode 24 and the semiconductor layer 23 is mixed together, and it has been found that the interface adjacent area between the semiconductor layer 23 and the ohmic electrode 24 contains approximately 0.5% Hf and The steps of forming a non-ohmic pad electrode 25 in an amount of approximately 99.5% and the subsequent steps are similar to those of the first example. In addition, the light-emitting nitride-based compound semiconductor device thus manufactured can be driven with a voltage of 3.0 V. A low-voltage driven light-emitting nitride-based compound semiconductor device can therefore be manufactured. In addition, the light-emitting device was subjected to a power-on test and after being subjected to 100,000--15-565933

小時週期之後該裝i沒有使一電極例如剝離,而且已經發 現將具有高可靠度。 此外雖然^姆電極24起初已經藉由形成一層於半導 體層23上以及之後形成一 A1層於該層上而被形成,但其起 初可以藉由形成一 A1層於半導體層23上以及之後形成一 Hf 層於該層上而被形成。 第三例子 苓考圖6,該一第三例子提供包含一歐姆電極34、一基板 31、一緩衝層32、一 n型氮化基之化合物半導體層33、一發 光層37、一p型披覆層38、一p型接觸層39、一 p型歐姆電極 210、一 p型墊電極211以及一透明導電膜212之一發光氮化 基之化合物半導體裝置。 第二例子之發光氮化基之化合物半導體裝置如此後特定 說明般被製造。 在η型GaN藍寶石基板31上,緩衝層32以及摻雜矽(Si)之 GaN η型氮化基之化合物半導體層33以此順序被形成。在該 層上多量子井發光層37由GaN形成之一障蔽層以及由 InGaN形成之一井層形成。在發光層^上^型彼覆層38由? 型AlGaN形成。在p型披覆層“上卩型接觸層39*p型^他形 成。在p型接觸層39之一表面上p型透明歐姆電極210藉由汽 相沈積6 nm厚度之鈀(Pd)層形成。p型歐姆電極210在真空 中以攝氏500度退火3分鐘以處理p型接觸層39以及該p型歐 姆電極210以提供一合金。 之後在p型歐姆電極210上光阻劑被應用以及一決定之區 -16- 565933After the hour period, the device did not peel off an electrode, for example, and has been found to have high reliability. In addition, although the electrode 24 has been initially formed by forming a layer on the semiconductor layer 23 and then forming an A1 layer on the layer, it can be formed by forming an A1 layer on the semiconductor layer 23 and thereafter. The Hf layer is formed on this layer. A third example is shown in FIG. 6. This third example provides an ohmic electrode 34, a substrate 31, a buffer layer 32, an n-type nitride-based compound semiconductor layer 33, a light-emitting layer 37, and a p-type substrate. The cladding layer 38, a p-type contact layer 39, a p-type ohmic electrode 210, a p-type pad electrode 211, and a transparent conductive film 212 are a light emitting nitride-based compound semiconductor device. The light emitting nitride-based compound semiconductor device of the second example is manufactured as described below. On the n-type GaN sapphire substrate 31, a buffer layer 32 and a silicon (Si) -doped GaN n-type nitride-based compound semiconductor layer 33 are formed in this order. On this layer, the multiple quantum well light emitting layer 37 is formed of a barrier layer formed of GaN and a well layer formed of InGaN. On the light-emitting layer ^ is the cladding layer 38 formed? AlGaN is formed. On the p-type cladding layer "upper-type contact layer 39 * p-type" is formed. On one surface of the p-type contact layer 39, a p-type transparent ohmic electrode 210 is vapor-deposited with a palladium (Pd) layer having a thickness of 6 nm. Formed. The p-type ohmic electrode 210 is annealed in a vacuum at 500 ° C for 3 minutes to process the p-type contact layer 39 and the p-type ohmic electrode 210 to provide an alloy. A photoresist is then applied on the p-type ohmic electrode 210 and Decision Zone -16- 565933

域之光阻劑被移除。p型歐姆電極21〇在無光阻劑部分以鹽 酸基之蝕刻劑蝕刻以形成一發光圖樣。之後該光阻劑被: 除。 在一部份p型歐姆電極210上1)型接合墊電極211被形成。 更特定地是,光阻劑被均勻一致地應用於該p型歐姆電極 210以及pi接觸層39上以及在將提供p型塾電極211之一部 份上該光阻劑被移除以提供一視窗。一堆疊形式之一 ^層 以及該Pd層上之一八丨層藉由汽相沈積形成以在該暴露之p 型歐姆電極210上具有近似1 μιη之厚度以及剝離被利用以 移除邊光阻劑上之堆疊以形成ρ型墊電極2 1 1。在ρ型墊電極 211被形成之後,ιτο之透明導電膜212藉由在攝氏25〇溫度 錢鑛在一基板而被形成以在ρ型歐姆電極2丨〇以及一部份ρ 型塾電極211上具有近似1〇〇 nm之一厚度。 之後,光阻劑被應用在透明導電膜2 12上以及該光阻劑由 一預先決定之區域被移除以及位於無光阻劑部分之透明導 電膜2 12以氯化鐵基之溶液姓刻被鞋刻。之後,該光阻劑被 移除。 請注意透明導電膜212如此蝕刻除了一部份連續覆蓋p型 塾電極211之一上表面之一端、p型歐姆電極21〇之一側表面 以及一部份鄰近p型歐姆電極210之p型接觸層39之一部份 和暴露部分以外。 之後在基板31之一背表面上厚度5 nm之一Hf層藉由汽相 沈積而提供以及在該層上厚度200 nm之一 A1層藉由汽相沈 積而提供以及之後它們在真空中以攝氏500度退火3分鐘以 -17- 565933The domain photoresist was removed. The p-type ohmic electrode 21 is etched in a photoresist-free portion with a hydrochloric acid-based etchant to form a light-emitting pattern. The photoresist was then removed. A 1) -type bonding pad electrode 211 is formed on a part of the p-type ohmic electrode 210. More specifically, the photoresist is uniformly applied to the p-type ohmic electrode 210 and the pi contact layer 39 and the photoresist is removed to provide a Windows. A stack of one layer and one eighth layer on the Pd layer are formed by vapor deposition to have a thickness of approximately 1 μm on the exposed p-type ohmic electrode 210 and peeling is used to remove edge photoresist Stack on the agent to form a p-type pad electrode 2 1 1. After the p-type pad electrode 211 is formed, a transparent conductive film 212 of ιτο is formed by depositing a substrate at 25 ° C on a p-type ohmic electrode 2 and a portion of the p-type 塾 electrode 211 It has a thickness of approximately 100 nm. After that, the photoresist is applied to the transparent conductive film 2 12 and the photoresist is removed from a predetermined area and the transparent conductive film 2 12 located in the photoresist-free portion is engraved with a ferric chloride-based solution. Carved by shoes. After that, the photoresist is removed. Please note that the transparent conductive film 212 is etched in this way except that it partially covers one end of one upper surface of the p-type 塾 electrode 211, one side surface of the p-type ohmic electrode 21, and part of the p-type contact adjacent to the p-type ohmic electrode 210 Except for a portion of the layer 39 and the exposed portion. One Hf layer with a thickness of 5 nm on one of the back surfaces of the substrate 31 is then provided by vapor deposition and one A1 layer with a thickness of 200 nm on this layer is provided by vapor deposition and then they are in vacuum at Celsius 500 degree annealing for 3 minutes to -17-565933

(13) 形成歐姆電極3 4。 歐姆電極34以及基板31之一背表面具有一 Hf及A1混合一 起之一介面以及已經發現介於基板31與歐姆電極34之一介 面鄰近區域包含近似1%量之Hf以及近似99%量之A卜 圖7為如此製造之發光氮化基之化合物半導體裝置之一 圖式上視圖。 雖然在第三例子中p型歐姆電極21〇以及由一pa層形成, 但其可以由允許一薄透明膜被形成之任何金屬或是合金形 成。 此外,雖然在第三例子中透明導電膜2丨2已經由IT〇形成 ,但其可以另外由包含至少一選自鋅(Ζη)、銦(Ιη)、錫(丁η) 、鎮(Mg)、鎘(Cd)、鎵(Ga)以及鉛(Pb)組成之一群組之一金 屬之一氧化物形成。 此外’雖然在第三例子中發光層37已經為由GaN形成之 一障蔽層以及由InGaN形成之一井層形成之一多量子井,但 其可以為單一量子井或是其可以為AlGalnN、GaNAs、GaNP 或是任何四基或三基混合之水晶。 此外’雖然η型氮化基之化合物半導體層33已經為摻雜si 之GaN ’但其可以由例如摻雜siiInGaN形成。 此外’雖然歐姆電極34起初已經藉由形成一 Hf層於基板 3 1之一背表面上以及之後形成一八丨層於該層上而被形成, 但其起初可以藉由形成一 A1層於基板3丨之一背表面上以及 之後形成一 Hf層於該層上而被形成。 第四例子 -18- 565933(13) Form ohmic electrodes 34. The back surface of one of the ohmic electrode 34 and the substrate 31 has an interface in which Hf and A1 are mixed together, and it has been found that the vicinity of the interface between the substrate 31 and the one of the ohmic electrode 34 contains approximately 1% of Hf and approximately 99% of A FIG. 7 is a schematic top view of a light-emitting nitride-based compound semiconductor device manufactured in this manner. Although the p-type ohmic electrode 21 is formed of a pa layer in the third example, it may be formed of any metal or alloy that allows a thin transparent film to be formed. In addition, although the transparent conductive film 2 丨 2 has been formed of IT0 in the third example, it may be additionally composed of at least one selected from zinc (Zη), indium (Ιη), tin (butylη), and town (Mg). , Cadmium (Cd), gallium (Ga), and lead (Pb). In addition, 'Although the light emitting layer 37 has been a barrier layer formed of GaN and a multiple quantum well formed of a well layer formed of InGaN in the third example, it may be a single quantum well or it may be AlGalnN, GaAs , GaNP, or any four- or three-base mixed crystal. Further, although the n-type nitride-based compound semiconductor layer 33 is already si-doped GaN, it may be formed of, for example, siiInGaN. In addition, 'Although the ohmic electrode 34 has been initially formed by forming an Hf layer on a back surface of the substrate 31 and then forming an eighteen layer on this layer, it can be initially formed by forming an A1 layer on the substrate A Hf layer is formed on one of the back surfaces and after that on the layer. Fourth example -18- 565933

(14) 如圖8所示,磊晶成長之晶圓包含一基板41、一緩衝層42 、一 η型氮化基之化合物半導體層43、一發光層47、一 p型 披覆層48、一 ρ型接觸層49、一 ρ型歐姆電極310、一錢金、 基本電極13以及一保有金屬層14之一發光氮化基之化合物 半導體裝置。如圖9所示,基板41之後被移除以及一歐姆電 極44被形成於緩衝層42上以完成一發光氮化基之化合物半 導體裝置。 第四例子之發光氮化基之化合物半導體裝置尤其如此後 特定說明般被製造。 起初,如圖8所示,於Si基板41上InAIN之η型缓衝層42以 及摻雜Si之GaN之η型氮化基之化合物半導體層43被以此順 序形成以及在該層上由GaN形成之一障蔽層以及由InGaN 形成之一井層形成之多量子井發光層47被堆疊。在發光層 47上p型披覆層48由p型AlGaN形成。在p型披覆層48上p型 接觸層49由p型GaN形成。在p型接觸層49上一以層藉由汽 相沈積提供以形成具有厚度1〇 nm之p型歐姆電極310以及 匕們在真空中以攝氏5〇〇度退火3分鐘以處理該pd層以及p 型接觸層49以提供一合金。在p型歐姆電極31〇上,厚度3〇〇 nm之一 Au層藉由汽相沈積提供以形成鍍金、基本電極13。 在電極13上,由Ni形成以及具有厚度丨⑽μπι之保有金屬層 14為藉由電解鍵金提供。 基板41之後被移除。更特定地,保有金屬層14之一上表 面以及排除基板4 1之晶圓之一側表面以電子蠟覆蓋。氫氟 酸、乙酸以及硝酸以一比率5 : 2 ·· 2混合一起以及使用為一 -19- (15) (15)565933(14) As shown in FIG. 8, the epitaxial growth wafer includes a substrate 41, a buffer layer 42, a n-type nitride-based compound semiconductor layer 43, a light-emitting layer 47, a p-type cladding layer 48, A p-type contact layer 49, a p-type ohmic electrode 310, gold, a basic electrode 13, and a light emitting nitride-based compound semiconductor device holding one of the metal layers 14. As shown in Fig. 9, the substrate 41 is then removed and an ohmic electrode 44 is formed on the buffer layer 42 to complete a light emitting nitride-based compound semiconductor device. The light-emitting nitride-based compound semiconductor device of the fourth example is manufactured as specifically described later. Initially, as shown in FIG. 8, the n-type buffer layer 42 of InAIN and the n-type nitride-based compound semiconductor layer 43 of Si doped GaN are formed in this order on the Si substrate 41 and GaN is formed on the layer. A barrier layer formed and a multiple quantum well light emitting layer 47 formed of a well layer formed of InGaN are stacked. A p-type cladding layer 48 is formed on the light-emitting layer 47 from p-type AlGaN. A p-type contact layer 49 on the p-type cladding layer 48 is formed of p-type GaN. A layer is provided on the p-type contact layer 49 by vapor deposition to form a p-type ohmic electrode 310 having a thickness of 10 nm and the kneads are annealed at 500 ° C for 3 minutes in a vacuum to process the pd layer and The p-type contact layer 49 provides an alloy. On the p-type ohmic electrode 31, an Au layer having a thickness of 300 nm is provided by vapor deposition to form a gold-plated, basic electrode 13. On the electrode 13, a retaining metal layer 14 formed of Ni and having a thickness of ⑽μm is provided by electrolytic bonding gold. The substrate 41 is then removed. More specifically, an upper surface of one of the metal layers 14 and a side surface of a wafer excluding the substrate 41 are covered with electronic wax. Hydrofluoric acid, acetic acid and nitric acid are mixed together at a ratio of 5: 2 ... 2 and used as a -19- (15) (15) 565933

蝕刻劑以溶解以及因此移除基板41以暴露緩衝層42之一 表面。該電子蠟以丙酮或是任何其他類似有機溶劑移除。 之後,參考圖9,在緩衝層42之表面上一 51^厚1^層以及 之後一 200 nm厚A1層藉由汽相沈積提供以及在真空中以攝 氏500度退火:>刀在里以形成歐姆電極44。緩衝層42以及歐姆 電極44具有Hf及A1混合一起之一介面以及已經發現該介面 鄰近區域包含近似5%量之Hf以及近似95°/。量之A1。 最後,該中間產物被被切成具有300 μηι X 3〇〇 μηι大小之 小方塊。 雖然在第四例子中ρ型歐姆電極3丨〇已經由pd形成,但其 可以由可以提供p層歐姆電極之任何金屬或是合金形成。 此外,雖然在第四例子中,保有金屬層14藉由無電解電 鍵由Ni形成,但其可以由導電之任何金屬形成,以及其可 以藉由除了 A相沈積與電錢以外之技術形成。例如,其可 以為一簡易固定導電板。 此外,雖然在第四例子中,發光層47已經為GaN形成之 一 I1早蔽層以及由In GaN形成之一井層之一多量子井,但其可 以為一單一量子井以及可以為A1GaInN、GaNAs、GaNP或 是任何四基或是三基混合之水晶。 此外’雖然在第四例子中,基板41已經由Si形成,但其 可以為容易蝕刻以及亦允許氮化基之化合物半導體層被形 成之任何基板。 此外,雖然半導體層43已經為摻雜Si之GaN,但其可以由 例如摻雜Si之InGaN形成。 -20- 565933The etchant dissolves and thus removes the substrate 41 to expose one surface of the buffer layer 42. The electronic wax is removed with acetone or any other similar organic solvent. Then, referring to FIG. 9, a 51 ^ thick 1 ^ layer and then a 200 nm thick A1 layer are provided by vapor deposition on the surface of the buffer layer 42 and annealed at 500 degrees Celsius in vacuum: > Ohmic electrode 44 is formed. The buffer layer 42 and the ohmic electrode 44 have an interface where Hf and A1 are mixed together, and it has been found that the adjacent area of the interface contains approximately 5% of Hf and approximately 95 ° /.量 的 A1。 The amount of A1. Finally, the intermediate product was cut into small cubes having a size of 300 μm × 300 μm. Although the p-type ohmic electrode 3 has been formed of pd in the fourth example, it may be formed of any metal or alloy that can provide a p-layer ohmic electrode. Further, although in the fourth example, the retaining metal layer 14 is formed of Ni by an electroless bond, it may be formed of any metal that conducts electricity, and it may be formed by a technique other than A-phase deposition and electric money. For example, it may be a simple fixed conductive plate. In addition, in the fourth example, although the light-emitting layer 47 has been formed as an I1 early shielding layer formed of GaN and a multi-quantum well formed as a well layer formed by In GaN, it may be a single quantum well and may be A1GaInN, GaNAs, GaNPs or any four-based or three-based mixed crystal. In addition, although in the fourth example, the substrate 41 has been formed of Si, it may be any substrate that is easy to etch and also allows a nitride-based compound semiconductor layer to be formed. Further, although the semiconductor layer 43 is already Si-doped GaN, it may be formed of, for example, Si-doped InGaN. -20- 565933

(16) 此外,雖然歐姆電極44起初已經藉由形成一 Hf層於緩衝 層42上以及之後形成一 A1層於該層上而被形成,但其起初 可以藉由形成一 A1層於緩衝層42上以及之後形成一 Hf層於 該層上而被形成。 第五例子 參考圖10,一第五例子提供包含一歐姆電極54、一基板 51、一緩衝層52、一 n型氮化基之化合物半導體層53、一裂 縫防止層15、一 η型披覆層16、一 η型光學導引層17、一發 光層57、一 ρ型載體區塊層18、一 ρ型光學導引層19、一ρ 型披覆層58、一 ρ型接觸層59、一 ρ型歐姆電極410以及一介 電膜20之一氮化基之化合物半導體雷射裝置。 使用本發明之電極之該氮化基之化合物半導體雷射裝置 如下文說明般被製造。 起初,在η型GaN基板51上GaN緩衝層52在低溫被形成以 具有100 nm之厚度。之後在該層上n型GaN η型氮化基之化 合物半導體層53被形成以具有3 μηι之厚度。 接著,40 nm厚,In〇 〇7Ga〇 93Ν η型裂縫防止層15被形成。 接著,0·8μπι厚,Al〇 iGa^N η型彼覆層16被形成。接著, 0.1 μτη厚,GaN η型光學導引層17被形成。之後,發光層57 由一4 nm厚,GaN〇97P0.03井層與一 8 nm厚,0&amp;1^〇99?〇〇1障 蔽層之三堆疊形成。 之後在發光層57上20 nm厚,Al〇 2Ga〇 sN ρ型載體區塊層 1 8被形成。在該層上〇. i 厚,GaNp型光學導引層19被形 成。在該層上0.5 μιη厚,AloiGaoWp型彼覆層58被形成。 -21- 565933 (17) 幽默明· 在該層上0·1 μηι厚,GaN p型接觸層59被形成。 雖然上述說明已經連結GaN基板51iC平面{〇〇〇1}提供 ,但作用為該基板主平面之方位可以為A平面{11-2〇}、R 平面{1-1 02}、Μ平面{1-1 〇〇}或是{卜1〇1}平面。此外,已 經發現具有一補償角在上述方位之二度内之任何基板提供 良好表面型態。 雖然上述說明基板5 1已經由GaN形成,但其可以為除了 GaN以外之一n型氮化基之化合物半導體基板。對氮化基之 化合物半導體雷射裝置而言,為允許一垂直側向模式為單 峰’具有較一披覆層小之折射率之一層為鄰近該彼覆層之 一外側為較佳,以及一 AlGaN基板適合被使用。 獲得一氮化基之化合物半導體雷射裝置之程序現在將被 說明。 歐姆電極54藉由汽相沈積具有厚度5 nm之一Hf層於基板 5 1之一背表面上而形成,之後汽相沈積具有厚度2〇〇 一 A1層於該層上,以及之後在真空中以攝氏5〇〇度相同退火 三分鐘而形成。 ^姆電極54以及基板51之一背表面具有Hf與A1混合一起 之一介面而且已經發現該介面鄰近區域包含近似3%量之 Hf以及近似97%量之A1。 p型歐姆電極410沿著氮化物半導體結晶&lt;M00〉方向之 一線姓刻以形成一脊狀線Rs。脊狀線Rs被形成為具有2 μηι 之一寬度。之後,Si〇2之介電膜20藉由汽相沈積提供。之 後,p型接觸層59被暴露。之後在該暴露之p型接觸層59以 -22- (18) (18)565933(16) In addition, although the ohmic electrode 44 has been initially formed by forming an Hf layer on the buffer layer 42 and then forming an A1 layer on the buffer layer, it can be initially formed by forming an A1 layer on the buffer layer 42 An Hf layer is formed on and after this layer. Fifth Example Referring to FIG. 10, a fifth example provides an ohmic electrode 54, a substrate 51, a buffer layer 52, an n-type nitride-based compound semiconductor layer 53, a crack prevention layer 15, and an n-type coating. Layer 16, an n-type optical guiding layer 17, a light-emitting layer 57, a p-type carrier block layer 18, a p-type optical guiding layer 19, a p-type cladding layer 58, a p-type contact layer 59, A p-type ohmic electrode 410 and a nitride-based compound semiconductor laser device of a dielectric film 20. The nitride-based compound semiconductor laser device using the electrode of the present invention is manufactured as described below. Initially, a GaN buffer layer 52 was formed on the n-type GaN substrate 51 at a low temperature to have a thickness of 100 nm. An n-type GaN n-type nitride-based compound semiconductor layer 53 is then formed on this layer to have a thickness of 3 µm. Next, a 40 nm thick In07Ga9N n-type crack prevention layer 15 is formed. Next, a thickness of 0.8 μm is used to form an AlOiGa ^ N n-type cladding layer 16. Next, a 0.1 μτη thickness is formed, and a GaN n-type optical guide layer 17 is formed. After that, the light emitting layer 57 is formed by stacking a 4 nm thick, GaN〇97P0.03 well layer and an 8 nm thick three-layer barrier layer. After that, the light-emitting layer 57 was 20 nm thick, and an Al 2 Ga 0 sN ρ type carrier block layer 18 was formed. On this layer, a thickness of 0.1 i is formed, and a GaNp-type optical guiding layer 19 is formed. On this layer, 0.5 μm thick, an AloiGaoWp type cladding layer 58 is formed. -21- 565933 (17) The humor is clear. On this layer, a GaN p-type contact layer 59 is formed to a thickness of 0.1 μm. Although the above description has been provided in conjunction with the GaN substrate 51iC plane {00〇〇1}, the orientation of the main plane of the substrate can be the A plane {11-2〇}, the R plane {1-1 02}, and the M plane {1 -1 〇〇} or {卜 1〇1} plane. In addition, any substrate having a compensation angle within two degrees of the above orientation has been found to provide good surface texture. Although the above description substrate 51 has been formed of GaN, it may be an n-type nitride-based compound semiconductor substrate other than GaN. For nitride-based compound semiconductor laser devices, it is preferable to allow a vertical lateral mode to be a single peak, and a layer having a refractive index smaller than that of a coating layer is adjacent to the outer side of the other coating layer, An AlGaN substrate is suitable for use. A procedure for obtaining a nitride-based compound semiconductor laser device will now be described. The ohmic electrode 54 is formed by vapor-depositing a Hf layer having a thickness of 5 nm on a back surface of the substrate 51, and then vapor-depositing a layer having a thickness of 2000-A1 on the layer, and then in a vacuum. It was formed by annealing the same at 500 ° C for three minutes. One of the rear surfaces of the electrode 54 and the substrate 51 has an interface in which Hf is mixed with A1 and it has been found that the vicinity of the interface contains approximately 3% of Hf and approximately 97% of A1. The p-type ohmic electrode 410 is engraved along a line of the nitride semiconductor crystal <M00> direction to form a ridge line Rs. The ridge line Rs is formed to have a width of 2 μm. Thereafter, the dielectric film 20 of SiO 2 is provided by vapor deposition. After that, the p-type contact layer 59 is exposed. After that, the exposed p-type contact layer 59 is -22- (18) (18) 565933

及介電膜20上,一 Pd層、之後一 M〇層以及之後一 Au層藉由 汽相沈積提供以形成p型歐姆電極41〇。或是,p型歐姆電極 410可以為Pd、Pt以及Au層依序汽相沈積或是可以藉由汽相 沈積提供一 Pd層以及一 Au層於該Pd層上或是藉由汽相沈 積提供一 Ni層以及一 Au層於該Ni層上而形成。 最後,基板51之一分裂平面被利用以提供具有5〇〇 之 一孔穴長度之一Fabry-P6rot共振器。 該Fabry-Pdrot共振器被提供一鏡端面,其依次藉由汽相 沈積交替提供70°/。反射比,Si〇2以及Ti〇2介電膜以提供一多 介電層反射膜。 雖然在第五例子中於形成歐姆電極54時,一電極被形成 在基板5 1之一背表面,但其可以藉由使用乾式蝕刻形成以 暴露半導體層53在一磊晶晶圓之一前側以及藉由形成歐姆 電極54於該暴露之表面上而被形成。 此外,雖然歐姆電極54起初已經藉由形成一 Hf層於基板 5 1之一背表面上以及之後形成一 A1層於該層上而被形成, 但其起初可以藉由形成一 A1層於一 η型基板上以及之後形 成一 Hf層於該層上而被形成。 第六例子 如圖11所示’ 一磊晶成長之晶圓包含一基板6丨、一緩衝 層62、一 n型氮化基之化合物半導體層63、一發光層67、一 Ρ型披覆層68、一 ρ型接觸層69、一 ρ型歐姆電極510、一錢 金、基本電極113以及一保有金屬層114之一發光氮化基之 化合物半導體裝置。如圖12所示,基板61及層61之後被移 -23- 565933On the dielectric film 20, a Pd layer, then a Mo layer, and then an Au layer are provided by vapor deposition to form a p-type ohmic electrode 41. Alternatively, the p-type ohmic electrode 410 may be sequentially vapor-deposited for the Pd, Pt, and Au layers, or a Pd layer and an Au layer may be provided on the Pd layer by vapor deposition or provided by vapor deposition. A Ni layer and an Au layer are formed on the Ni layer. Finally, a split plane of the substrate 51 is utilized to provide a Fabry-P6rot resonator with a hole length of 500. The Fabry-Pdrot resonator is provided with a mirror end face, which in turn provides 70 ° / by alternating vapor deposition. Reflectivity, Si02 and Ti02 dielectric films to provide a multi-dielectric reflective film. Although an electrode is formed on a back surface of the substrate 51 when the ohmic electrode 54 is formed in the fifth example, it may be formed by using dry etching to expose the semiconductor layer 53 on the front side of one epitaxial wafer and It is formed by forming an ohmic electrode 54 on the exposed surface. In addition, although the ohmic electrode 54 has been initially formed by forming an Hf layer on a back surface of the substrate 51 and then forming an A1 layer on the layer, it can be initially formed by forming an A1 layer on an n An Hf layer is formed on the substrate and thereafter. A sixth example is shown in FIG. 11 'An epitaxially grown wafer includes a substrate 6, a buffer layer 62, an n-type nitride-based compound semiconductor layer 63, a light-emitting layer 67, and a P-type cladding layer. 68. A p-type contact layer 69, a p-type ohmic electrode 510, gold, a basic electrode 113, and a light emitting nitride-based compound semiconductor device holding one of the metal layers 114. As shown in Figure 12, the substrate 61 and the layer 61 are subsequently moved -23- 565933

(19) 除以及一歐姆電極64被形成於n型氮化基之化合物半導體 層63上以完成一發光氮化基之化合物半導體裝置。 使用本發明之電極之該氮化基之化合物半導體雷射裝置 如下文說明般被製造。 起初,如圖11所示,於Si基板61上Α1Ν之η型緩衝層62以 及摻雜Si之GaN之η型氮化基之化合物半導體層63以此順序 被形成以及在該層上由GaN形成之一障蔽層以及由InGaN 形成之一井層形成之多量子井發光層67被堆疊。在發光層 67上p型披覆層68*p$A1GaN形成。在p型披覆層“上卩型 接觸層69由p型GaN形成。在p型接觸層的之一表面上一 pd 層藉由汽相沈積提供以形成具有厚度5〇 nm2p型歐姆電極 510以及匕們在真空中以攝氏5〇q度退火3分鐘以處理該% 層以及P型接觸層69以提供一合金。在p型歐姆電極51〇上, 厚度300 nm之一 Au層藉由汽相沈積提供以形成鍍金、基本 電極113。在電極113上,由Ni形成以及具有厚度1〇〇 ^^^之 保有金屬層114為藉由電解鍍金提供。 基板61之後被移除。更特定地,保有金屬層114之一上表 面以及排除基板61之晶圓一側表面以電子蠟覆蓋。氫敦酸 、乙酸以及石肖酸以-比率5:2:2混合—起以及使用為一姓 刻劑以溶解以及因此移除基板61以暴露緩衝層62之一表面 。該電子蠟以丙酮或是任何其他類似有機溶劑移除。 缓衝層62之後被乾式蝕刻以暴露半導體層63之一表面。 之後,如圖12所示,在半導體層63之一表面上一Hf層以 及-⑽被同時形成以提供具有厚度· 之歐姆電㈣ -24- 565933(19) A ohmic electrode 64 is formed on the n-type nitride-based compound semiconductor layer 63 to complete a light-emitting nitride-based compound semiconductor device. The nitride-based compound semiconductor laser device using the electrode of the present invention is manufactured as described below. Initially, as shown in FIG. 11, an A1N n-type buffer layer 62 and a Si-doped GaN-type nitride-based compound semiconductor layer 63 on a Si substrate 61 are formed in this order and formed of GaN on the layer. One of the barrier layers and the multiple quantum well light emitting layer 67 formed of one well layer formed of InGaN are stacked. A p-type cladding layer 68 * p $ A1GaN is formed on the light emitting layer 67. The p-type cladding layer "upper-type contact layer 69 is formed of p-type GaN. On one surface of the p-type contact layer, a pd layer is provided by vapor deposition to form a p-type ohmic electrode 510 having a thickness of 50 nm2 and They were annealed in vacuum at 50 ° C for 3 minutes to process the% layer and the P-type contact layer 69 to provide an alloy. On the p-type ohmic electrode 51, an Au layer with a thickness of 300 nm was passed through the vapor phase. Deposition is provided to form a gold-plated, basic electrode 113. On the electrode 113, a retaining metal layer 114 formed of Ni and having a thickness of 100 ^^^ is provided by electrolytic gold plating. The substrate 61 is subsequently removed. More specifically, An upper surface of one of the metal layers 114 and a side surface of the wafer excluding the substrate 61 is covered with an electronic wax. Hydrogen acid, acetic acid, and lithocholic acid are mixed at a ratio of 5: 2: 2 and used as a nicking agent. The substrate 61 is dissolved and thus removed to expose one surface of the buffer layer 62. The electronic wax is removed with acetone or any other similar organic solvent. The buffer layer 62 is then dry-etched to expose one surface of the semiconductor layer 63. After that As shown in FIG. 12, in the semiconductor layer 63 A surface of the upper layer and the Hf -⑽ are simultaneously formed to provide ohmic electrical iv * having a thickness of -24-565933

(20) 。該Hf層以及A1層在真空中以攝氏500度退火3分鐘。歐姆 電極64包含混合一起之Hf及A1以及已經發現介於該半導體 層63與一歐姆電極64之間之一介面鄰近區域包含近似5% 量之Hf以及近似95%量之A1。 最後’ ό亥中間產物被被切成具有3〇〇 μπι X 300 μηι大小之 小方塊。 雖然在第六例子中ρ型歐姆電極5 1 〇已經由Pd形成,但其 可以由可以提供一 p層歐姆電極之任何金屬或是合金形成。 此外’雖然在第六例子中,保有金屬層1 1 4藉由無電艘由 Ni形成,但其可以由導電之任何金屬形成,以及其可以藉 由除了汽相沈積與電鍍以外之技術形成。例如,其可以為 一簡易固定導電板。 此外’雖然在第六例子中,發光層67已經為〇aN形成之 ^蔽層以及由InGaN形成之一井層之一多量子井,但其可 以為一單一量子井以及可以為AlGalnN、GaNAs、GaNP或 是任何四基或是三基混合之水晶。 此外’雖然在第六例子中,基板6 1已經由s i形成,但其 可以為容易姓刻以及亦允許氮化基之化合物半導體層被形 成之任何基板。 卜雖然半導體層63已經為推雜Si之GaN,但里可以由 例如摻雜Si之InGaN形成。 在本發明中,如上文說明,一n型氮化基之化合物半導體 層亚不限制材料只要該材料為由InxGayAl i x yN代表之材料 形成,其中OSd,〇$# i以及x+y$卜此外,該η型氮 -25- 565933(20). The Hf layer and the A1 layer were annealed in a vacuum at 500 ° C for 3 minutes. The ohmic electrode 64 includes Hf and A1 mixed together and an interface adjacent region between the semiconductor layer 63 and an ohmic electrode 64 has been found to contain approximately 5% of Hf and approximately 95% of A1. Finally, the intermediate product is cut into small cubes with a size of 300 μm X 300 μm. Although the p-type ohmic electrode 5 1 0 has been formed of Pd in the sixth example, it may be formed of any metal or alloy that can provide a p-layer ohmic electrode. In addition, although in the sixth example, the retaining metal layer 1 1 4 is formed of Ni by an electroless boat, it may be formed of any metal that conducts electricity, and it may be formed by a technique other than vapor deposition and electroplating. For example, it may be a simple fixed conductive plate. In addition, although in the sixth example, the light-emitting layer 67 has been a shielding layer formed of 0aN and a multiple quantum well formed of a well layer formed of InGaN, it may be a single quantum well and may be AlGalnN, GaAs, GaNP is any four-based or three-based mixed crystal. In addition, although in the sixth example, the substrate 61 has been formed of s i, it may be any substrate that can be easily carved and also allows a nitride-based compound semiconductor layer to be formed. Although the semiconductor layer 63 is already doped with GaN, it may be formed of, for example, Si-doped InGaN. In the present invention, as explained above, an n-type nitride-based compound semiconductor layer is not limited as long as the material is formed of a material represented by InxGayAl ix yN, where OSd, 〇 $ # i and x + y $ , The η-type nitrogen-25- 565933

(21) 化基之化合物半導體層藉由一傳統已知之技術,例如汽相 屋晶、分子束蟲晶或是類似技術加以堆疊。 此外,本發明之η型氮化基之化合物半導體層,如上文 說明,以及一歐姆電極形成於該層上具有Hf及Α1混合一起 之一介面,可以具有該Hf及A1與額外金屬混合一起之一介 面0 此外’該歐姆電極亦可以被藉由賤鍍、真空沈積、汽相 沈積、電子束汽相沈積或是任何其他類似傳統已知技術、 或是技術之一組合提供於該n型氮化基之化合物半導體層 上。 此外,雖然退火於一 Hf層被形成於該η型氮化基之化合物 半導體層上以及一 A1被提供於該層上之後被執行,但可以 選擇於該Hf層以及該A1層被形成時藉由將該半導體層加熱 而執行〇 此外,除了該Hf層以及該A1層 可以被提供於該η型氮化基之化合物半導體層上一 斤由上述說明顯而易見的是,本發明可以提供一種提供與 氮化基之化合物半導體之優越接觸之歐姆電極。本發明可 乂因此提供低電壓與兩可靠發光1化基之化合物半導體裝 置之高生產良率。 、 雖然本發明已經詳細說明及解釋,但清楚地瞭解相同之 情形僅為解釋與舉例方式而已並且不為限制之方式,本發 明之精神與範⑽由申請專利之項目所限制。 ^ 圖式代表符號說明 -26- 565933 (22) 卜21 藍寶石基板 2、22、32、42、52、 缓衝層 62 3、23、33、43、53、 η型氮化基之化合物半導體層 63 4、24、34、44、54 歐姆電極 5、25 塾電極 6、26 η型電極 7、27、37、47、57、 發光層 67 8、28、38、48、58、 ρ型披覆層 68 9、29、39、49、59、 ρ型接觸層 69 10、110、210、310、 Ρ型歐姆電極 410 、 510 11 ^ 111 &gt; 211 ρ型墊電極 12、112、212 透明導電膜 31、4卜 51、61 基板 13 、 113 鍍金、基本電極 14 、 114 保有金屬層 15 η型裂縫防止層 16 η型披覆層 17 η型光學導引層(21) Chemical-based compound semiconductor layers are stacked by a conventionally known technique such as a vapor-phase house crystal, a molecular beam insect crystal, or the like. In addition, the n-type nitride-based compound semiconductor layer of the present invention, as described above, and an ohmic electrode formed on the layer has an interface in which Hf and A1 are mixed together, and may have the Hf and A1 mixed with additional metals. An interface 0 In addition, the ohmic electrode can also be provided to the n-type nitrogen by base plating, vacuum deposition, vapor deposition, electron beam vapor deposition, or any other similar conventional known technology, or a combination of technologies. On a compound semiconductor layer. In addition, although annealing is performed after a Hf layer is formed on the n-type nitride-based compound semiconductor layer and an A1 is provided on the layer, it may be selected when the Hf layer and the A1 layer are formed. It is performed by heating the semiconductor layer. In addition, in addition to the Hf layer and the A1 layer, which can be provided on the n-type nitride-based compound semiconductor layer, it is obvious from the above description that the present invention can provide a providing and Ohmic electrode with superior contact for nitride-based compound semiconductors. The present invention can thus provide a high production yield of a compound semiconductor device with a low voltage and two reliable light emitting compounds. Although the present invention has been described and explained in detail, it is clearly understood that the same situation is only for explanation and example and is not a limitation. The spirit and scope of the present invention are limited by the patent application project. ^ Explanation of Symbols of the Drawings-26- 565933 (22) Bu 21 Sapphire substrate 2, 22, 32, 42, 52, buffer layer 62 3, 23, 33, 43, 53, n-type nitride compound semiconductor layer 63 4, 24, 34, 44, 54 ohm electrodes 5, 25 塾 electrodes 6, 26 n-type electrodes 7, 27, 37, 47, 57, light-emitting layer 67 8, 28, 38, 48, 58, ρ-type coating Layer 68 9, 29, 39, 49, 59, ρ-type contact layer 69 10, 110, 210, 310, P-type ohmic electrode 410, 510 11 ^ 111 &gt; 211 ρ-type pad electrode 12, 112, 212 Transparent conductive film 31, 4 51, 61 substrates 13, 113 gold plating, basic electrodes 14, 114 metal layer 15 η-type crack prevention layer 16 η-type coating layer 17 η-type optical guide layer

-27- 565933 (23) 18 19 20 P型載體區塊層 P型光學導引層 介電膜 -28--27- 565933 (23) 18 19 20 P-type carrier block layer P-type optical guide layer Dielectric film -28-

Claims (1)

565933 拾、申請專利範圍 1. 一種形成一歐姆電極之方法,該方法包括下列步驟: 形成一給層於一型氮化基之化合物半導體層之一表 面上,以具有1至1 5 nm之厚度; 形成一鋁層於該铪層上;以及 將該铪層與該鋁層退火以形成一由混合在一起之銓 與鋁所形成之層。565933, patent application scope 1. A method for forming an ohmic electrode, the method includes the following steps: forming a given layer on a surface of a type nitride compound semiconductor layer to have a thickness of 1 to 15 nm Forming an aluminum layer on the hafnium layer; and annealing the hafnium layer and the aluminum layer to form a layer made of hafnium and aluminum mixed together.
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