JP2012216877A - Metallized structure for high electric power microelectronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a metal interconnection system capable of withstanding thermal stress generated by a device having high electric power and high performance.SOLUTION: A semiconductor device structure comprises: a wide bandgap semiconductor portion selected from a group consisting of silicon carbide and Group III nitride; and an interconnect structure to the semiconductor portion including at least two diffusion barrier layers alternating with two respective high electrical conductivity layers. The diffusion barrier layers have a coefficient of thermal expansion different from the high electrical conductivity layers and have the lower coefficient of thermal expansion than that of the high electrical conductivity layers. Difference in the respective coefficients of thermal expansions is large enough to constrain expansion of the high electrical conductivity layers but less than difference that would create strain between adjacent layers that would exceed bond strength between the layers.

Description

  The present invention relates to interconnect metal structures for semiconductor devices with three or more terminals that operate at relatively high power. Examples include a metal semiconductor field effect transistor (MESFET) formed of silicon carbide (SiC), a high electron mobility transistor (HEMT) formed of a group III nitride material system, and a gate periphery (or wider range). Other devices such as devices that operate at a nominal power loss of 1 watt per millimeter (1 W / mm) or devices that undergo thermal excursions above 150 ° C. under nominal operating conditions.

  As is generally recognized in the semiconductor technology field, the operating characteristics and performance (or limitations) of a semiconductor device depend on the characteristics of the semiconductor material. Silicon and gallium arsenide (GaAs) are used in a wide range of semiconductor electronic devices, but some of their operating performance is due to their band gap (eg, Si at 1.12 electron volts (eV) at 300K). GaAs is 1.42 eV), and is limited by their physical properties (eg, melting point). Thus, for higher power devices, wide band gap materials such as silicon carbide, III-nitrides, and diamond are becoming preferred.

  From an electronic point of view, silicon carbide has many theoretical and practical advantages that make it desirable for use in microelectronic devices. Silicon carbide has a wide band gap (at 300 K, α-SiC is 3.0 eV), high critical breakdown field (about 2 megavolts per centimeter), and high thermal conductivity (centimeters-about 5 watts per Kelvin). Have. Silicon carbide is also physically very hard. Silicon carbide has a high electron drift velocity, excellent thermal stability, and excellent radiation resistance, that is, “hardness”. These advantages are well recognized and explained in the patent and non-patent literature.

  The III-nitride material system provides similar advantages, including a wide bandgap (eg, 300K, gallium nitride 3.36 eV, AlN 6.2 eV). In addition, group III nitrides form a number of binary, ternary, and tertiary compounds with band gaps of 3.4-6.2 eV, based on specific atomic fractions. . As a result, the compound provides the ability to form heterojunctions and related structures between III-nitride materials. GaN / AlGaN heterostructures are particularly useful for high electron mobility transistors (HEMTs).

  Because such devices are most commonly used in combination in a circuit, they typically connect to other devices using some form of conductive path (“interconnect”). Is done. Of these semiconductor devices, these interconnections (often formed with metal) between them are the operating parameters desired or required for such devices, most commonly Must be able to withstand current, power, and heat (temperature).

  As one of many examples, wide bandgap devices such as metal semiconductor field effect transistors and high electron mobility transistors are used in conventional radar frequencies (eg, 16 for Ku-band radars), including long pulse radar systems. It is useful as a component of MMIC (microwave integrated circuits) capable of generating an increased power output at .7 GHz. However, it has been observed that in such systems, as the power density increases, the metal interconnect system begins to fail. This problem also occurs relatively early compared to other benefits of semiconductor electronics having a long life. For example, it was observed that such MESFETs and HEMTs operating at about 8-10 watts per millimeter (around the gate) would fail as early as 10 million cycles. Since the device cycles at about 1 millisecond per cycle, it will fail in a few hours.

  In other applications, the device need not be operated at such power levels. Nevertheless, the failure of high power devices in a relatively short period of time indicates that similar problems will eventually occur in low power devices and also in unacceptably short periods of time.

  One aspect of this problem arises by using multiple metals to form the interconnect. Conventional systems use a diffusion barrier metal such as, for example, molybdenum adjacent to the semiconductor. A layer of a highly conductive material such as gold, silver, or aluminum is then laminated over the diffusion barrier metal. However, these metals can move between and within adjacent layers of material. This in turn causes problems such as undesirable metallurgical reactions, voids, uneven interfaces, and corrosion. Literally, the diffusion barrier metal prevents the high conductivity metal from reacting with the semiconductor in an undesired manner.

  In addition, molybdenum layers, or alternative metals such as titanium, may be included as an adhesion layer to help maintain ohmic contacts or interconnections within or to the device.

  High power devices generate relatively high temperatures and high thermal cycles (eg, in the range above 150 ° C.), so the thermal effects associated with these metals (and other materials) must be considered. As a result, and because wider bandgap materials can operate at higher power than lower bandgap materials (for other devices of similar size and structure), thermal stress on the interconnect metal Is larger in a wide bandgap material than in a silicon-based or gallium arsenide-based device.

  Of course, expansion is also a thermal effect. The degree to which the material expands depends on the application temperature and the coefficient of thermal expansion. As is well understood in the prior art, the coefficient of linear thermal expansion is the ratio of the change in length per 1K to the length at 273K. When considering expansion in three dimensions, the body expansion coefficient is generally about three times the linear expansion coefficient. Furthermore, the value of the coefficient depends on the temperature.

  In general, semiconductor materials have a relatively low coefficient of thermal expansion. Metals have a higher coefficient of thermal expansion than semiconductors. Among metals, high conductivity metals tend to have a much higher coefficient of thermal expansion than low conductivity materials. The nature of the diffusion barrier tends to be related to a low coefficient of thermal expansion.

  To provide ohmic properties, adhesion, diffusion barriers, and conductivity, metal interconnect systems on semiconductors often include layers for each purpose. For example, one layer for ohmic contacts, a second layer of different material for adhesion, a third layer of yet another material that serves as a diffusion barrier, and another that provides high conductivity. And a fourth layer of material. As a result, the interconnect is generally composed of three or four different materials having a relatively wide range of thermal expansion coefficients. Thus, when high power, wide bandgap devices cycle over a given temperature range, thermal expansion stresses tend to delaminate each other's layers. In particular, the thermal effect causes shear stress (transverse) between the layers as well as the main (Z direction) stress across the layers. As a result, stress and other potential factors can lead to increased resistance, film delamination, passivation cracking, and catastrophic device failure.

  Since improved devices have reached power levels not previously seen in devices of comparable size and structure made of conventional materials, the occurrence of delamination problems has not been observed. Thus, to some extent, these new problems are due to the design and manufacture of high power devices with wide band gap materials.

  Of course, in practical use, if the relevant materials, such as metal interconnects, tend to fail at a relatively early stage, the theoretical power capability of the device will not make sense.

  Therefore, there is a need for a metal interconnect system that can withstand the thermal stresses generated by these higher performance devices.

(Overview)
In one aspect, the invention is a semiconductor device structure that includes a wide bandgap semiconductor portion selected from the group consisting of silicon carbide and group III nitride. An interconnect structure is fabricated for the semiconductor portion, the interconnect structure including at least two diffusion barrier layers, each alternating with two highly conductive layers. The diffusion barrier layer has a different thermal expansion coefficient from that of the highly conductive layer, and has a lower thermal expansion coefficient than that of the highly conductive layer. The difference between the respective thermal expansion coefficients is large enough to suppress the expansion of the highly conductive layer, but is smaller than the difference that causes a strain exceeding the adhesive strength between layers to occur between adjacent layers.

  In another aspect, the present invention is a wide bandgap insulated gate field effect transistor (IGFET). In this aspect, the present invention includes a first semiconductor portion selected from the group consisting of silicon carbide and group III nitride and has a first conductivity type (p or n). Each source and drain portion is in the first semiconductor portion and has a conductivity type opposite to that of the first semiconductor portion. The gate insulator is on the first semiconductor portion between the source portion and the drain portion, and the gate contact is on the gate insulator. The interconnect structure is on at least one of the source, the gate contact, and the drain. The interconnect structure includes at least two diffusion barrier layers, each alternating with two highly conductive layers. The diffusion barrier layer has a thermal expansion coefficient different from that of the highly conductive layer and has a lower thermal expansion coefficient than that of the highly conductive layer, and the difference in the respective thermal expansion coefficients causes the expansion of the highly conductive layer. Although it is large enough to suppress, it is smaller than the difference that causes distortion exceeding the adhesive strength between layers between adjacent layers.

  In yet another aspect, the present invention includes a gallium nitride layer and an aluminum gallium nitride layer overlying the gallium nitride layer, forming a heterojunction between the gallium nitride layer and the aluminum gallium nitride layer. It is a high electron mobility transistor. Each source and drain contact is on the gallium nitride layer and the gate contact is on the aluminum gallium nitride layer. The transistor includes a metal interconnect structure for at least one of a source contact, a drain contact, and a gate contact. The interconnect structure includes at least two diffusion barrier layers, each alternating with two highly conductive layers. The diffusion barrier layer has a thermal expansion coefficient different from that of the highly conductive layer and has a lower thermal expansion coefficient than that of the highly conductive layer, and the difference in the respective thermal expansion coefficients causes the expansion of the highly conductive layer. Although it is large enough to suppress, it is smaller than the difference that causes distortion exceeding the adhesive strength between layers between adjacent layers.

Therefore, the present invention provides the following items.
(Item 1)
A semiconductor device structure,
A wide band gap semiconductor portion selected from the group consisting of silicon carbide and group III nitrides;
An interconnect structure for the semiconductor portion, each comprising two highly conductive layers and alternatingly including at least two diffusion barrier layers;
The diffusion barrier layer has a different thermal expansion coefficient than the highly conductive layer, and has a lower thermal expansion coefficient than the highly conductive layer;
The difference in the respective thermal expansion coefficients is large enough to suppress the expansion of the highly conductive layer, but is smaller than the difference causing a strain exceeding the adhesive strength between the layers between adjacent layers. .
(Item 2)
Item 2. The semiconductor device structure of item 1, comprising two or more highly conductive layers and two or more diffusion barrier layers alternately.
(Item 3)
Adjacent to one of the diffusion barrier layers, the diffusion barrier layer, and a portion of the device selected from the group consisting of the wide bandgap semiconductor portion, ohmic contact, Schottky contact, and dielectric layer; 2. The semiconductor device structure of item 1, further comprising an adhesive layer between.
(Item 4)
The highly conductive layer is selected from the group consisting of gold and aluminum;
Item 2. The semiconductor device structure according to Item 1, wherein the diffusion barrier layer is selected from the group consisting of platinum, chromium, nickel, and alloys thereof.
(Item 5)
Item 4. The semiconductor device structure according to Item 3, wherein the adhesive layer is selected from the group consisting of titanium, chromium, tungsten, and molybdenum.
(Item 6)
The coefficient of thermal expansion of the highly conductive layer is about 1.5 to 2 times greater than the coefficient of thermal expansion of the diffusion barrier layer,
The semiconductor device structure of claim 1, wherein the interconnect structure has a thickness of about 0.1 to 10 microns.
(Item 7)
Including an ohmic contact to the semiconductor part,
Item 2. The semiconductor device structure according to Item 1, comprising the metal wiring structure on the ohmic contact.
(Item 8)
Item 2. The semiconductor device structure according to Item 1, wherein the diffusion barriers have the same composition, and the highly conductive layers have the same composition.
(Item 9)
Item 2. The semiconductor device structure according to Item 1, wherein the diffusion barrier layer has a different composition, and the highly conductive layer has a different composition.
(Item 10)
The wide band gap semiconductor portion has a first conductivity type;
Insulated gate field effect transistor (IGFET)
Respective source and drain portions within the wide band gap semiconductor portion having a conductivity type opposite to that of the first semiconductor portion;
A gate insulator overlying the wide band gap semiconductor portion between the source portion and the drain portion;
A gate contact overlying the gate insulator;
The IGFET of item 1, wherein the interconnect structure is on at least one of the source, the gate contact, and the drain.
(Item 11)
The semiconductor portion includes silicon carbide,
The diffusion barrier layer includes platinum,
Item 11. The IGFET according to Item 10, wherein the highly conductive layer includes gold.
(Item 12)
A titanium adhesion layer between at least one of the diffusion barrier layers and at least one of the source, the gate contact, and the drain;
Item 11. The IGFET of item 10, further comprising a respective ohmic contact overlying the source and the drain having the interconnect on one of the ohmic contacts.
(Item 13)
An adhesive layer selected from the group consisting of titanium, tungsten, and molybdenum between at least one of the diffusion barrier layers and at least one of the source, the gate contact, and the drain; Item 10. The IGFET according to Item 10.
(Item 14)
The wide band gap semiconductor portion is a gallium nitride layer having an aluminum gallium nitride layer overlying the gallium nitride layer, and a heterojunction between the gallium nitride layer and the aluminum gallium nitride layer Form the
High electron mobility transistor (HEMT)
Respective source and drain contacts to the gallium nitride layer;
A gate contact to the aluminum gallium nitride layer,
Item 2. The high electron mobility transistor of item 1, wherein the interconnect structure is fabricated for the source contact, the drain contact, and the gate contact.
(Item 15)
A substrate selected from the group consisting of silicon carbide and sapphire;
A Group III nitride buffer layer on the substrate;
Item 15. The high electron mobility transistor according to Item 14, wherein the substrate and the buffer layer support the gallium nitride layer.
(Item 16)
Item 16. The high electron mobility transistor of item 15, wherein the buffer layer comprises aluminum gallium nitride, and the gallium nitride layer has a resistivity of at least 5000 ohm centimeters.
(Item 17)
15. The high electron mobility transistor according to item 14, further comprising an adhesive layer selected from the group consisting of titanium, tungsten, and molybdenum and adjacent to at least one of the diffusion barrier layers.
(Item 18)
18. The high electron mobility transistor according to item 17, wherein the adhesive layer is between the diffusion barrier layer and the source contact, the gate contact, and the drain contact.

(Summary)
Disclosed is a semiconductor device structure comprising a wide bandgap semiconductor portion selected from the group consisting of silicon carbide and group III nitride. An interconnect structure is fabricated for the semiconductor portion, the interconnect structure including at least two diffusion barrier layers, each alternating with two highly conductive layers. The diffusion barrier layer has a different thermal expansion coefficient from that of the highly conductive layer, and has a lower thermal expansion coefficient than that of the highly conductive layer. The difference between the respective thermal expansion coefficients is large enough to suppress the expansion of the highly conductive layer, but is smaller than the difference that causes a strain exceeding the adhesive strength between layers to occur between adjacent layers.

FIG. 1 is a schematic cross-sectional view of a metal interconnect system according to the present invention. FIG. 2 is a schematic cross-sectional view of a metal interconnect system according to the present invention in an insulated gate field effect transistor. 3-4 are schematic cross-sectional and schematic perspective views, respectively, of a high electron mobility transistor incorporating an interconnection system according to the present invention. 3-4 are schematic cross-sectional and schematic perspective views, respectively, of a high electron mobility transistor incorporating an interconnection system according to the present invention. FIG. 5 is a schematic cross-sectional view of a metal interconnect system according to the present invention in a metal semiconductor field effect transistor.

  The foregoing and other objects and advantages of the invention, as well as the manner in which the same are accomplished, will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

(Detailed explanation)
FIG. 1 is a schematic cross-sectional view of a semiconductor device structure according to the present invention, generally designated by the reference numeral 10. In particular, the part 11 enclosed in parentheses is not exclusive but represents the basic structure of the present invention. In the most common situation, the device structure includes a wide band gap semiconductor portion 12 selected from the group consisting of silicon carbide and group III nitride. In the schematic diagram of FIG. 1, a basic interconnect structure 11 is made for a semiconductor portion 12. In other situations, the interconnect structure 11 can be made to ohmic contacts, Schottky contacts, or dielectric materials. FIG. 1 also illustrates that the interconnect structure 11 can be covered with or placed under other structural elements schematically illustrated by layer 17 (eg, dielectric, polymer, metal). It is.

  The interconnect structure 11 includes at least two diffusion barrier layers 13 (four are shown in FIG. 1), alternately with two highly conductive layers 14 (three are shown in FIG. 1). The diffusion barrier layer 13 has a thermal expansion coefficient different from that of the high conductivity layer 14 and has a lower thermal expansion coefficient than that of the high conductivity layer. The difference in coefficient of thermal expansion is large enough to suppress the expansion of the highly conductive layer 14, but is smaller than the difference causing distortion exceeding the adhesive strength between layers between adjacent layers.

  FIG. 1 also illustrates that an adhesive layer 15 is used adjacent to one or more of the diffusion barrier layers 13 in many embodiments. The adhesive layer is selected for a higher reactive property that provides the ability to bond adjacent layers and remain attached to the adjacent layers.

  The diffusion barrier layer 13 has a low thermal expansion coefficient, but is selected from materials (including alloys) having more appropriate diffusion barrier performance. As is known to those skilled in the semiconductor art, some highly conductive metals can also react with specific semiconductor materials or easily migrate into them and thus react with semiconductor layers, Or they can move into these to modify the operating characteristics of the device in an undesirable way. In the exemplary embodiment, diffusion barrier layer 13 is selected from metals and alloys such as platinum, tungsten, and titanium tungsten (TiW).

  The highly conductive layer 14 with the diffusion barrier layer 13 in place can illustratively be selected for conductivity properties with gold and aluminum. As described above, the adhesive layer 15 is selected for their appropriate reaction characteristics, illustratively titanium and chromium. In any case, the layers serving their respective purposes can be the same or different from each other. For example, all diffusion barrier layers can be formed of the same material. Alternatively, a thin film outer surface configuration such that the residual and thermomechanical strains are sufficiently low will differ from one or more of the diffusion barrier layers to maintain structural integrity in the desired application. Material can be used. The same possibility applies to highly conductive layers and adhesive layers.

  Table 1 lists some representative metals and their coefficient of thermal expansion (CTE) expressed in units of 106K-1.

これらの異なる層が、意図した機能を果たす能力を有し、他の層、すなわち下層の半導体デバイスに悪影響を及ぼさなければ、他の材料をそれらの異なる層に対して選択することができる。熱膨張係数に基づいて選択する場合、高導電性層は、拡散バリア層１３の熱膨張係数よりも約１．５〜２倍大きい熱膨張係数を有さなければならない。換言すると、高導電性層の熱膨張係数は、拡散バリア層の熱膨張係数の約１．５〜２倍でなければならない。

If these different layers have the ability to perform their intended functions and do not adversely affect the other layers, ie the underlying semiconductor devices, other materials can be selected for those different layers. When selecting based on the coefficient of thermal expansion, the highly conductive layer must have a coefficient of thermal expansion that is about 1.5 to 2 times greater than the coefficient of thermal expansion of the diffusion barrier layer 13. In other words, the coefficient of thermal expansion of the highly conductive layer should be about 1.5 to 2 times the coefficient of thermal expansion of the diffusion barrier layer.

  The alternating diffusion barrier layers 13 and highly conductive layers 14, with or without the adhesive layer 15, generally have a thickness of about 0.1 to 10 microns (μm). In terms of thickness, the present invention uses multiple thin layers and is the same (better in most cases) as a conventional two-layer or three-layer (adhesion layer / diffusion barrier layer / conductive layer) structure. Provides an opportunity to achieve performance. Using multiple thin layers effectively increases the total area of the interface between the layer of restraining material and the layer of high expansion material, effectively reducing thermomechanical strain parallel to the layer. , The stress between the layers is reduced. Furthermore, since the thickness of the high-expansion layer is reduced, the layer is further closer to the low-expansion layer. Volume expansion in the vertical direction is reduced.

  Thus, the present invention can be used in various proportions and is not limited to a specific absolute size. The diffusion barrier has been observed to work best when its thickness is about 5 times the average particle size. The manner of depositing the thin film can assist in the formation of the particle structure, and thus the particle structure can form different diffusion barrier layer properties.

  The adhesive layer 15 generally has the same thickness as the diffusion barrier. That is, it is an amount sufficient to bond each desired layer without requiring a thickness greater than that. The thickness of the highly conductive layer 14 can be based on the expected current.

  In one exemplary embodiment, when the semiconductor portion 12 is silicon carbide, the diffusion barrier layer 13 is platinum, the highly conductive layer 14 is gold, and the adhesion layer 15 is titanium.

  In one exemplary embodiment, but not limited to, the structure described in FIG. 1 includes a titanium (Ti) adhesion layer 15 having a thickness of about 200 nanometers. The diffusion barrier layer 13 has a thickness of about 50 nanometers and is formed of platinum (Pt), tungsten (W), molybdenum (Mo), and a conductive alloy, or nitrides of these materials. (If not conductive, the nitride forms an undesirable capacitor structure). The highly conductive layer is typically formed of about 1.5 microns of gold (Au).

  The term device is widely used herein and includes junction diodes, insulated gate field effect transistors (IGFETs), metal semiconductor field effect transistors (MESFETs), and high electron mobility transistors (HEMTs). It will be understood that any suitable device can be used.

  The basic structure and operation of such devices is generally well understood in the prior art. Exemplary references include Sze, “PHYSICS OF SEMICONDUCTOR DEVICES”, Second Edition (1981), John Wiley & Sons, Inc. Sze, “MODEL SEMICONDUCTOR DEVICE PHYSICS (1998)”, John Wiley & Sons, Inc. , And ZETTERING, “PROCESS TECHNOLOGY FOR SILICON CARBIDE DEVICES”, Electronic Materials Information Service (2002).

  FIG. 2 is a diagram illustrating the present invention in an insulated gate field effect transistor (IGFET), generally designated by the reference numeral 20. Transistor 20 includes a first semiconductor portion 21 selected from the group consisting of silicon carbide and group III nitride. The semiconductor portion 21 has the first conductivity type (p or n).

  Each of the source portion 22 and the drain portion 23 is in the first semiconductor portion 21 and has a conductivity type opposite to that of the first semiconductor portion 21. A gate insulator 24 is on the first semiconductor portion 21 between the source 22 and the drain portion 23 and defines a channel 25. When an oxide, typically silicon dioxide, is used as the gate insulator, the transistor is generally referred to as a metal oxide semiconductor field effect transistor (MOSFET).

  A gate contact 26, typically formed of a conductive material such as metal or polysilicon, overlies the gate insulator and applies a voltage to the gate in a well-understood manner, and also includes a source 22 and a drain 23. Adjust the current between. In many cases, transistor 20 is isolated from neighboring devices by a portion of field oxide layer 27.

  As described with respect to FIG. 1, the interconnect structure 30 is made to at least one of the source 22, the gate contact 26, or the drain 23. FIG. 2 shows an interconnect structure 30 on each of these members. As illustrated in FIG. 1, the interconnect structure includes at least two diffusion barrier layers, each alternating with two highly conductive layers. The diffusion barrier layer has a different thermal expansion coefficient from that of the highly conductive layer, and has a lower thermal expansion coefficient than that of the highly conductive layer. The difference between the thermal expansion coefficients is to suppress the expansion of the diffusion barrier layer. However, it is smaller than the difference that causes distortion exceeding the adhesive strength between the layers between adjacent layers. In many cases, one or more adhesive layers (15 in FIG. 1) are also present.

  As also shown in FIG. 2, the transistor 20 generally includes an ohmic contact 32 to the source 22 and an ohmic contact 33 to the drain 23, with the interconnect structure overlying the ohmic contact 32 or 33.

  When the semiconductor portion 21 includes silicon carbide, the diffusion barrier layer typically includes tungsten, TiW, or nickel, and the highly conductive layer includes gold or aluminum.

  3 and 4 are diagrams illustrating a high electron mobility transistor (HEMT), generally designated by reference numeral 35, incorporating an interconnect structure according to the present invention. The structure shown in FIG. 3 is similar to that described in commonly assigned US Pat. No. 7,230,284, which is incorporated herein by reference in its entirety. . Since high electron mobility transistors are based on the use of heterostructures, such transistors are also referred to as heterostructure field effect transistors (HFETs).

  In this embodiment, transistor 35 often includes a gallium nitride layer 36 supported by a substrate 37 and is typically formed of silicon carbide or sapphire. In either case, the buffer layer 40 is typically aluminum gallium nitride, which is used to account for the difference in unit cell dimensions between these materials and in the substrate 37 and Proper transition between the gallium nitride layer 36 is provided.

The aluminum gallium nitride layer 41 is on the gallium nitride layer 36 and has a wider band gap than gallium nitride. As explained in the background art, at room temperature, the band gap of gallium nitride is about 3.4 eV, and that of aluminum nitride is 6.2 eV. Therefore, the band gap of the layer 41 depends on the atomic fraction (x) of aluminum and gallium in the composition formula Al _x Ga _1-x N.

  As is generally well understood in the art, a wide bandgap AlGaN layer 41 separates the gate electrode 42 from the gallium nitride layer 36. When the threshold voltage is exceeded, the two-dimensional electron gas (2DEG), schematically illustrated by the thin layer 43, becomes a heterointerface between the wide band gap AlGaN layer and the narrow band gap GaN layer (or channel) 36. Formed. The two-dimensional electron gas carries a drain-source current. The high mobility electron gas provides the capacity for the device to operate at a higher frequency than more conventional transistors.

  3 and 4 are also diagrams showing a source contact 44 and a drain contact 45 and a passivation or insulating layer 46 generally formed of silicon dioxide, silicon nitride, or a preferred combination of silicon dioxide and silicon nitride. is there. An exemplary but non-limiting passivation layer is disclosed in commonly assigned US Pat. No. 5,766,837 or US Pat. No. 6,246,076, which is incorporated by reference in its entirety. This is incorporated herein by reference.

  Metal interconnect structure 47 is made for at least one, two, or all of source contact 44, drain contact 45, or gate contact 42. As with the embodiments described above, the interconnect structure includes at least two (potentially two or more) diffusion barrier layers, each alternating with two highly conductive layers. The diffusion barrier layer has a thermal expansion coefficient different from that of the highly conductive layer and has a lower thermal expansion coefficient than that of the highly conductive layer, and the difference in the respective thermal expansion coefficients causes the expansion of the highly conductive layer. Although it is large enough to suppress, it is smaller than the difference that causes distortion exceeding the adhesive strength between layers between adjacent layers. As with the embodiments described above, the interconnect structure 47 can include an adhesive layer adjacent to at least one of the diffusion barrier layers.

  In the transistor as indicated by reference numeral 35 in FIGS. 3 and 4, the gallium nitride layer 36 generally means having a resistivity of at least about 5000 ohm centimeters, potentially higher, It can be semi-insulating.

  Devices formed in accordance with the present invention operated at 10 watts per millimeter (based on a nominal design of 4 watts per millimeter) for hundreds of hours without failure.

  FIG. 5 is a cross-sectional view of a metal semiconductor field effect transistor (MESFET), generally designated 50, illustrating aspects of the present invention. The illustrated MESFET generally corresponds to that disclosed in commonly assigned US Pat. No. 6,686,616, which is hereby incorporated by reference in its entirety. Nevertheless, it will be understood that the illustrated MESFET is illustrative of the structure of the MESFET and the present invention and is not limiting.

  N-type 50 includes a silicon carbide substrate 51 that is generally (but not exclusively) semi-insulating. In the illustrated diode, a wide bandgap p-type epitaxial layer 52 is on the substrate 51 and a wide bandgap n-type epitaxial layer 53 is on the p-type layer 52. N-type epitaxial layer 53 optionally includes more heavily doped wells 54 and 55. Overlying the n-type epitaxial layer 53 is a gate contact structure, indicated generally by the reference numeral 56. The gate contact 56 (which is a Schottky contact in the MESFET) can be formed of multiple metal layers. In the illustrated embodiment, these layers are formed of a metal such as chromium, for example, a first gate layer 57, preferably having Schottky properties, a suitable metal barrier layer 60 such as platinum, and gold. A highly conductive layer 61 formed of a metal such as the above can be included. The source and drain include ohmic contacts 62 and 63, respectively, generally formed of nickel or nickel silicide. Ohmic contacts 62 and 63 also include metallization layers 64 and 65, respectively, which typically include titanium, platinum, and gold layers, respectively.

  The passivation layer 58 is generally included and can be formed by the method disclosed in commonly assigned US Pat. No. 5,972,801, which is hereby incorporated by reference in its entirety. Incorporated.

  The metallized structure according to the present invention can then be used to contact any one or more of the source, gate, or drain. FIG. 5 is a diagram illustrating a metallization structure indicated by reference numeral 66 having portions thereof on each of the source, gate, and drain.

  Although the present invention is disclosed with respect to high power transistors, it has advantages for any electronic device that dissipates high power density or operates under periodic thermal stress, or a combination of high power density and thermal stress. Can be provided. Thus, the present invention can be combined with optoelectronic devices, passive electronic and electromechanical devices, and optical communication devices in addition to microwave and power transistors. The present invention provides certain advantages in switching power supplies, electronic warfare systems, microwave communication systems, conventional and alternative energy power generation, and electric vehicle propulsion systems in addition to long pulse radar systems.

  Although a preferred embodiment of the present invention has been described in the drawings and specification and specific terms have been employed, they are merely used in a general and descriptive sense and are intended to be limiting. Rather, the scope of the invention is defined in the claims.

Claims (18)

A semiconductor device structure,
A wide band gap semiconductor portion selected from the group consisting of silicon carbide and group III nitrides;
An interconnect structure for the semiconductor portion, each comprising two highly conductive layers and alternately comprising at least two diffusion barrier layers;
The diffusion barrier layer has a different thermal expansion coefficient than the highly conductive layer, and has a lower thermal expansion coefficient than the highly conductive layer;
The difference in the respective thermal expansion coefficients is large enough to suppress the expansion of the highly conductive layer, but is smaller than the difference causing a strain exceeding the adhesive strength between the layers between adjacent layers. .   The semiconductor device structure of claim 1, comprising two or more diffusion barrier layers alternately with two or more highly conductive layers.   A portion of the device adjacent to one of the diffusion barrier layers and selected from the group consisting of the wide band gap semiconductor portion, ohmic contact, Schottky contact, and dielectric layer; The semiconductor device structure of claim 1, further comprising an adhesive layer between the two. The highly conductive layer is selected from the group consisting of gold and aluminum;
The semiconductor device structure of claim 1, wherein the diffusion barrier layer is selected from the group consisting of platinum, chromium, nickel, and alloys thereof.   4. The semiconductor device structure of claim 3, wherein the adhesion layer is selected from the group consisting of titanium, chromium, tungsten, and molybdenum. The coefficient of thermal expansion of the highly conductive layer is about 1.5 to 2 times greater than the coefficient of thermal expansion of the diffusion barrier layer,
The semiconductor device structure of claim 1, wherein the interconnect structure has a thickness of about 0.1 to 10 microns. Including an ohmic contact to the semiconductor portion;
The semiconductor device structure according to claim 1, wherein the metal wiring structure is provided on the ohmic contact.   The semiconductor device structure according to claim 1, wherein the diffusion barriers have the same composition, and the highly conductive layers have the same composition.   The semiconductor device structure according to claim 1, wherein the diffusion barrier layers have different compositions, and the highly conductive layers have different compositions. The wide band gap semiconductor portion has a first conductivity type;
Insulated gate field effect transistor (IGFET)
Respective source and drain portions within the wide band gap semiconductor portion having a conductivity type opposite to that of the first semiconductor portion;
A gate insulator overlying the wide band gap semiconductor portion between the source portion and the drain portion;
A gate contact overlying the gate insulator;
The IGFET of claim 1, wherein the interconnect structure is on at least one of the source, the gate contact, and the drain. The semiconductor portion comprises silicon carbide;
The diffusion barrier layer comprises platinum;
The IGFET of claim 10, wherein the highly conductive layer comprises gold. A titanium adhesion layer between at least one of the diffusion barrier layers and at least one of the source, the gate contact, and the drain;
11. The IGFET of claim 10, further comprising: a respective ohmic contact overlying the source and the drain having the interconnect on one of the ohmic contacts.   An adhesive layer selected from the group consisting of titanium, tungsten, and molybdenum between at least one of the diffusion barrier layers and at least one of the source, the gate contact, and the drain; The IGFET according to claim 10. The wide band gap semiconductor portion is a gallium nitride layer having an aluminum gallium nitride layer overlying the gallium nitride layer, and a heterojunction between the gallium nitride layer and the aluminum gallium nitride layer Form the
High electron mobility transistor (HEMT)
Respective source and drain contacts to the gallium nitride layer;
A gate contact to the aluminum gallium nitride layer;
The high electron mobility transistor of claim 1, wherein the interconnect structure is made to the source contact, the drain contact, and the gate contact. A substrate selected from the group consisting of silicon carbide and sapphire;
A III-nitride buffer layer on the substrate; and
The high electron mobility transistor of claim 14, wherein the substrate and the buffer layer support the gallium nitride layer.   The high electron mobility transistor of claim 15, wherein the buffer layer comprises aluminum gallium nitride, and the gallium nitride layer has a resistivity of at least 5000 ohm centimeters.   15. The high electron mobility transistor of claim 14, further comprising an adhesion layer selected from the group consisting of titanium, tungsten, and molybdenum and adjacent to at least one of the diffusion barrier layers.   The high electron mobility transistor of claim 17, wherein the adhesion layer is between a diffusion barrier layer and the source, gate, and drain contacts.

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