TWI662701B - High electron mobility transistor structure - Google Patents

Abstract

The disclosure provides a high electron mobility transistor structure including a substrate, a barrier layer, a buffer layer, a source and a drain, a multiple gate structure, and a multiple field plate structure. The barrier layer is disposed on the substrate, the buffer layer is disposed between the substrate and the barrier layer, and has a channel region adjacent to an interface between the barrier layer and the buffer layer. The source and the drain are disposed on the barrier layer, and the multiple gate structure is disposed between the source and the drain, and includes a plurality of first conductive fingers spaced apart from each other. The multiple field plate structure is disposed between the multiple gate structure and the drain electrode, and includes a plurality of second conductive fingers spaced apart from each other. The first conductive fingers and the second conductive fingers are alternately and parallelly arranged on the barrier layer.

Description

High electron mobility transistor structure

The present disclosure relates to a semiconductor device structure, and more particularly to a high electron mobility transistor (HEMT) structure with adjustable threshold voltage.

In the semiconductor industry, high-voltage switching transistors (such as high electron mobility transistors (HEMTs), junction filed effect transistors (JFETs), or power MOSFETs (power MOSFETs)) It is often used as a semiconductor switching element of a high-voltage high-power device (for example, a switched mode power supply (SMPS)). Among the above-mentioned high-voltage switching transistors, the high electron mobility transistor has advantages such as high power density, high breakdown voltage, high output voltage, and the like, and can operate at high voltage without damaging the device.

The high electron mobility transistor (HEMT) includes a depletion type high electron mobility transistor (depletion mode HEMT, D-mode HEMT) and an enhanced high electron mobility transistor (enhancement mode HEMT, E-mode HEMT). In the D-mode HEMT, the electric field generated by the gate is used to evacuate a two-dimensional electron gas (2DEG) channel near a heterostructure interface between semiconductor layers having a wide and narrow energy bandgap. For E-mode HEMT, there is no channel and current generation until the bias voltage is applied to the transistor operation.

The D-mode HEMT allows current to pass through when no gate-source voltage is applied (also referred to as a normally-on transistor). The E-mode HEMT prevents current from passing through when no gate-source voltage is applied (also known as a normally-off transistor).

Although the existing D-mode HEMT and E-mode HEMT generally meet the requirements, they are not satisfactory in all aspects. For example, the high electron mobility transistor structure is limited to a single threshold voltage and reduces its application elasticity. Furthermore, high-impedance semiconductor materials are often included under the gate, which can easily cause gate switching errors and conduction loss / condition loss.

Therefore, it is necessary to find a high electron mobility transistor structure which can solve or improve the above problems.

An embodiment of the present disclosure provides a high electron mobility transistor structure including: a substrate, a barrier layer, a buffer layer, a source and a drain, a multiple gate structure, and a multiple field plate structure. . The barrier layer is disposed on the substrate, the buffer layer is disposed between the substrate and the barrier layer, and has a channel region adjacent to an interface between the barrier layer and the buffer layer. The source and the drain are disposed on the barrier layer, and the multiple gate structure is disposed between the source and the drain, and includes a plurality of first conductive fingers spaced apart from each other. The multiple field plate structure is disposed between the multiple gate structure and the drain electrode, and includes a plurality of second conductive fingers spaced apart from each other. The first conductive fingers and the second conductive fingers are alternately and parallelly arranged on the barrier layer.

Another embodiment of the present disclosure provides a high electron mobility transistor structure including: a substrate, a barrier layer, a buffer layer, a source and a drain, a multiple gate structure, and an electrical connection structure. . The barrier layer is disposed on the substrate, The buffer layer is disposed between the substrate and the barrier layer, and has a channel region adjacent to an interface between the barrier layer and the buffer layer. The source electrode and the drain electrode are disposed on the barrier layer, and the multiple gate structure is disposed between the source electrode and the drain electrode, and includes a plurality of first conductive fingers spaced apart from each other and arranged in parallel on the barrier layer. The electrical connection structure is electrically connected to at least two of the first conductive finger portions, so that at least one of the first conductive finger portions is not electrically connected to the electrical connection structure.

10a, 10b, 10c‧‧‧‧High electron mobility transistor structure

100‧‧‧ substrate

102‧‧‧ buffer layer

103‧‧‧Channel area

110‧‧‧Barrier layer

112‧‧‧Source

114‧‧‧ Drain

120a, 120b, 120c ‧‧‧ the first conductive finger

121‧‧‧Multi-gate structure

130a, 130b, 130c‧‧‧Second conductive finger

130d‧‧‧Connection Department

131‧‧‧Multi-field plate structure

140a, 140b, 140c‧‧‧Wire connection structure

FIG. 1 is a schematic plan view illustrating a high electron mobility transistor structure according to some embodiments of the present disclosure.

Fig. 2 is a schematic cross-sectional view taken along line 2-2 'in Fig. 1.

FIG. 3 is a schematic plan view illustrating a high electron mobility transistor structure according to some embodiments of the present disclosure.

FIG. 4 is a schematic plan view illustrating a high electron mobility transistor structure according to some embodiments of the present disclosure.

The high electron mobility transistor structure of the embodiment of the present disclosure is described below. However, it can be easily understood that the embodiments provided in this disclosure are only used to illustrate that the present invention is made and used in a specific method, and not intended to limit the scope of the present invention.

Embodiments of the present disclosure provide a metal-oxide half-field-effect transistor structure, such as a high electron mobility transistor (HEMT) structure, which uses multiple gates to adjust the threshold voltage of the transistor, thereby increasing the application flexibility of the transistor. Furthermore, the high-electron-mobility transistor structure with a multi-gate design can shorten the channel length compared to a high-electron-mobility transistor structure with a single gate, which in turn reduces Low parasitic resistance under the gate to avoid false gate switching and reduce conduction loss / heat loss.

Please refer to FIGS. 1 and 2, wherein FIG. 1 is a schematic plan view showing a high electron mobility transistor structure 10 a according to some embodiments of the present disclosure, and FIG. Schematic cross-section of the 2 'line. As shown in FIG. 2, the high electron mobility transistor structure 10 a of the present disclosure includes a substrate 100, a buffer layer 102, a barrier layer 110, a source 112 and a drain 114, and a multiple The gate structure 121 and a selective multiple field plate structure 131.

In some embodiments, the barrier layer 110 is disposed on the substrate 100, and the buffer layer 102 is disposed between the substrate 100 and the barrier layer 110. Furthermore, the source 112 and the drain 114 are disposed on the barrier layer 110, and the multiple gate structure 121 is disposed on the barrier layer 110 between the source 112 and the drain 114. Furthermore, the multiple field plate structure 131 is disposed on the barrier layer 110 between the multiple gate structure 121 and the drain 114. Each feature of the above-mentioned high electron mobility transistor structure 10a will be discussed in more detail in the following paragraphs.

As shown in FIG. 1 or FIG. 2, the high electron mobility transistor structure 10 a of the embodiment of the present disclosure includes a substrate 100. In some embodiments, the substrate 100 may include a silicon substrate, a silicon carbide substrate, or a sapphire substrate. In other embodiments, the substrate 100 may also include a silicon on insulator (SOI) substrate.

In some embodiments, the high electron mobility transistor structure 10 a of the present disclosure further includes a buffer layer 102 disposed above the substrate 100. The buffer layer 102 may have a multilayer structure. For example, the buffer layer 102 includes a nucleation layer (not shown) and a III-V semiconductor compound thereon. Object layer (not shown). In some embodiments, the nucleus layer includes AlN, GaN, or AlGaN, and is used to reduce the stress caused by lattice mismatch between the substrate 100 and the III-V semiconductor compound layer above the nucleus layer. For example, the difference in lattice and thermal expansion coefficient between the AlN nucleus layer and the substrate 100 is small, so that the stress between the substrate 100 and the III-V semiconductor compound layer formed later can be relaxed.

In some embodiments, the III-V semiconductor compound layer on the nucleus layer can be used as a channel layer of the high electron mobility transistor structure 10a. For example, the buffer layer 102 includes a channel region 103 (shown as a dashed line in FIG. 2), such as a two-dimensional electron gas (2DEG) channel, which is adjacent to the upper surface of the buffer layer 102 ( That is, it is adjacent to the interface between the buffer layer 102 and a barrier layer to be formed later). In some embodiments, the III-V semiconductor compound layer on the core layer may include indium aluminum gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), gallium nitride (GaN ), Aluminum nitride (AlN), or a combination thereof.

In some embodiments, molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy, (HVPE) or other suitable deposition methods to form a buffer layer 102 on the substrate 100. In some embodiments, the thickness of the buffer layer 102 may be in a range of about 0.2 μm to 10 μm.

In some embodiments, the high electron mobility transistor structure 10a of the present disclosure further includes a barrier layer 110 disposed on the buffer layer 102 and in direct contact therewith. In some embodiments, the barrier layer 110 includes a III-V semiconductor compound layer, such as indium aluminum gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), nitrogen Indium gallium (InGaN), gallium nitride (GaN), or a combination thereof. It should be noted that the composition of the III-V semiconductor compound layer in the barrier layer 110 and the buffer layer 102 are different. For example, the barrier layer 110 is composed of aluminum gallium nitride (AlGaN), and the III-V semiconductor compound layer in the buffer layer 102 is composed of gallium nitride (GaN), so that the barrier layer 110 and the buffer layer 102 constitutes a different structure.

In some embodiments, a buffer can be formed on the buffer layer 102 using molecular beam epitaxy (MBE), organic metal vapor deposition (MOCVD), hydride vapor epitaxy (HVPE), or other suitable deposition methods. Layer 102. In some embodiments, the thickness of the barrier layer 110 may be in a range of about 1 nm to 100 nm.

The band gap discontinuity between the buffer layer 102 and the barrier layer 110 generates a carrier channel with high mobile conduction electrons (labeled as Channel region 103), which is called a two-dimensional electron gas (2DEG) channel. When a gate-source voltage is applied, the transistor can be turned on or off.

In some embodiments, the high electron mobility transistor structure 10a of the present disclosure further includes a source electrode 112, a drain electrode 114, and a multiple gate structure 121 disposed on and in contact with the barrier layer 110. The multiple gate structure 121 is disposed between the source 112 and the drain 114. In some embodiments, the source 112, the drain 114, and the multiple gate structure 121 each have a portion extending into the barrier layer 110, as shown in FIG. In this way, the recessed multiple gate structure 121 can change the thickness of the barrier layer 110, thereby reducing the density of the two-dimensional electron gas (2DEG). In some embodiments, the multiple gate structure 121, the source 112, and the drain 114 are disposed on the barrier layer 110 having a flat surface and are not dug into the barrier layer 110.

In some embodiments, as shown in FIGS. 1 and 2, the multiple gate structure 121 includes two or more first conductive finger portions spaced apart from each other and arranged in parallel. In order to simplify the figure and description here, only three first conductive fingers 120a, 120b, and 120c are shown. It can be understood that the number of the first conductive fingers in the multiple gate structure 121 depends on design requirements, and is not limited to the embodiments shown in FIGS. 1 and 2.

In some embodiments, the first conductive finger portion 120a has a width L1; the first conductive finger portion 120b has a width L2; and the first conductive finger portion 120c has a width L3. These widths L1, L2 and L3 define the corresponding channel length. In some embodiments, the widths L1, L2, and L3 are different from each other, so that the corresponding channel lengths are different from each other. In this way, when a voltage is applied to the first conductive fingers 120a, 120b, and 120c, different threshold voltages can be obtained.

Furthermore, compared to a conventional high electron mobility transistor having a single gate, the sum of the widths L1, L2, and L3 may be less than or equal to the width of the single gate. Since the widths L1, L2, and L3 of the first conductive fingers 120a, 120b, and 120c are smaller than the width of the single gate, respectively, the parasitic resistance under the gate in the high electron mobility transistor 10a is smaller than that of the conventional high electron mobility transistor. Parasitic resistance under the gate in the crystal. In this way, it can avoid causing the gate to switch erroneously and reduce the conduction loss / heat loss.

In some embodiments, the widths L1, L2, and L3 are the same as each other, so that the corresponding channel lengths are the same as each other. In this way, when a voltage is applied to the first conductive fingers 120a, 120b, and 120c, the same threshold voltage can be obtained. In other embodiments, the widths L1, L2, and L3, and wherein the channel lengths are the same as each other. In this way, when a voltage is applied to the first conductive fingers 120a, For 120b and 120c, two different threshold voltages can be obtained.

In some embodiments, the multiple gate structure 121 may include a conductive material, such as a metal (such as titanium (Ti), nickel (Ni), gold (Au), or an alloy thereof), and further, the source 112 and the drain 114 A conductive material such as a metal (such as titanium (Ti), aluminum (Al), nickel (Ni), molybdenum (Mo), gold (Au), or an alloy thereof) may be included. Multiple gate structures 121, source 112, and drain 114 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and sputtering ), Or other suitable processes.

In some embodiments, the high electron mobility transistor structure 10a of the present disclosure further includes an electrical connection structure 140a, which is electrically connected to at least two of the first conductive fingers 120a, 120b, and 120c, so that the first At least one of the conductive fingers 120a, 120b, and 120c is not electrically connected to the electrical connection structure 140a. For example, the electrical connection structure 140a is electrically connected to the first conductive fingers 120a and 120b, as shown in FIG. In some embodiments, the electrical connection structure 140a can be electrically connected to the first conductive fingers 120a and 120c. In other embodiments, the electrical connection structure 140a may be electrically connected to the first conductive fingers 120b and 120c.

In some embodiments, the electrical connection structure 140a may include an interconnect structure composed of a conductive plug and a conductive layer. In some embodiments, the electrical connection structure 140a may include wiring. In this way, by adjusting the number and width of the first conductive fingers and / or controlling the connection manner of the electrical connection structure 140a, the high electron mobility transistor structure 10a can have a function of adjusting the threshold voltage and can be used in different products. Get the required threshold voltage in your application.

In some embodiments, the high electron mobility transistor structure 10a of the present disclosure further includes a multiple field plate structure 131, wherein the multiple field plate structure 131 is disposed between the multiple gate structure 121 and the drain 114. In some embodiments, the multiple field plate structure 131 is disposed on the barrier layer 110 without being digged into the barrier layer 110.

In some embodiments, as shown in FIGS. 1 and 2, the multiple field plate structure 131 includes two or more second conductive finger portions spaced apart from each other and arranged in parallel. Here, in order to simplify the drawings and description, only three first conductive fingers 130a, 130b, and 130c are shown. In some embodiments, the first conductive fingers 120a, 120b, and 120c are alternately arranged with the second conductive fingers 130a, 130b, and 130c. It can be understood that the number of the second conductive finger portions in the multiple field plate structure 131 depends on the number of the first conductive finger portions, and is not limited to the embodiments shown in FIGS. 1 and 2.

In some embodiments, the multiple field plate structure 131 further includes a connecting portion 130d connected to one end of the second conductive finger portions 130a, 130b, and 130c, as shown in FIG. 1. In some embodiments, the multiple field plate structure 131 may include a conductive material, which may be the same as or similar to the multiple gate structure 121. For example, the multiple field plate structure 131 may include a metal such as titanium (Ti), nickel (Ni), gold (Au), or an alloy thereof. Furthermore, the multiple field plate structure 131 may be formed by chemical vapor deposition (CVD). , Physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or other suitable processes. The multiple gate structure 121 can alleviate the peak electric field under the multiple gate structure 121 to increase the breakdown voltage of the transistor and reduce the leakage current.

Please refer to FIG. 3, which is a schematic plan view illustrating a high electron mobility transistor structure 10 b according to some embodiments of the present disclosure. The same components as those in FIG. 1 are denoted by the same reference numerals and descriptions thereof are omitted. As shown in Fig. 3, the high electron mobility transistor structure 10b is similar to the high electron mobility transistor of Fig. 1 Structure 10a. Different from the high electron mobility transistor structure 10a, the high electron mobility transistor structure 10b includes an electrical connection structure 140b for electrically connecting the first conductive fingers 120a, 120b, and 120c. In some embodiments, the electrical connection structure 140a may include an interconnect structure and a fuse device composed of a conductive plug and a conductive layer. In some embodiments, the electrical connection structure 140a may include a wiring and a fuse device. In this way, by controlling the connection mode of the electrical connection structure 140b and / or adjusting the number and width of the first conductive fingers through the fuse device, the high electron mobility transistor structure 10a can have a function of adjusting the threshold voltage and The required threshold voltage is obtained in different product applications.

Please refer to FIG. 4, which is a schematic plan view illustrating a high electron mobility transistor structure 10 c according to some embodiments of the present disclosure. The same components as those in FIG. 1 are denoted by the same reference numerals and descriptions thereof are omitted. As shown in FIG. 4, the high electron mobility transistor structure 10 c is similar to the high electron mobility transistor structure 10 a of FIG. 1. Different from the high electron mobility transistor structure 10a, the high electron mobility transistor structure 10c includes an electrical connection structure 140c for electrically connecting one end of the second conductive fingers 130a, 130b, and 130c. In some embodiments, the electrical connection structure 140c can selectively electrically connect at least one of the first conductive finger portions 120a, 120b, and 120c (for example, the first conductive finger portion 120a). In some embodiments, the electrical connection structure 140c may include an interconnect structure composed of a conductive plug and a conductive layer. In some embodiments, the electrical connection structure 140c may include wiring. It can be understood that the high electron mobility transistor structure 10c may have an electrical connection structure 140b as shown in FIG. 3 instead of the electrical connection structure 140a.

According to the above embodiment, since the high electron mobility transistor structure has multiple gates, the number and width of the first conductive fingers can be adjusted by adjusting the number and width of the first conductive fingers. Modulate the critical voltage of the transistor. Furthermore, according to the above embodiment, since the high electron mobility transistor structure has an electrical connection structure to electrically connect the first conductive finger, the threshold voltage of the transistor can be further adjusted by controlling the connection of the electrical connection structure. That's it. Can increase the application flexibility of the transistor.

In addition, compared with a high-electron mobility transistor structure with a single gate, a high-electron mobility transistor structure with multiple gates has a shorter channel length per gate, thereby reducing parasitics below the gate. Resistance (ie, reducing the conduction group) to avoid causing gate mis-switching, reducing conduction loss / thermal loss, and improving power-conversion efficiency.

In addition, according to the above embodiment, since the high electron mobility transistor structure has multiple field plates and multiple gates arranged alternately, the peak electric field under the multiple gate structure can be relaxed to increase the breakdown voltage of the transistor and reduce the leakage current.

Although the present invention has been disclosed as above with the preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make changes and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (20)

A high electron mobility transistor structure includes: a substrate; a barrier layer disposed on the substrate; a buffer layer disposed between the substrate and the barrier layer, and having a channel region adjacent to the barrier An interface between the barrier layer and the buffer layer; a source electrode and a drain electrode disposed on the barrier layer; a multiple gate structure disposed between the source electrode and the drain electrode and including each other A plurality of spaced apart first conductive fingers; and a multiple field plate structure disposed between the multiple gate structure and the drain, and including a plurality of spaced apart second conductive fingers, wherein The first conductive fingers and the second conductive fingers are alternately and parallelly arranged on the barrier layer. The high electron mobility transistor structure described in item 1 of the patent application scope, wherein the multiple field plate structure further includes a connecting portion connected to one end of the second conductive fingers. The high-electron-mobility transistor structure described in item 1 of the patent application scope further includes an electrical connection structure electrically connected to the second conductive fingers. The high electron mobility transistor structure according to item 3 of the scope of the patent application, wherein the electrical connection structure is electrically connected to at least one of the first conductive fingers. The high electron mobility transistor structure described in item 1 of the patent application scope further includes an electrical connection structure that electrically connects one of the first conductive fingers and the second conductive finger. The high electron mobility transistor structure described in item 1 of the patent application scope, wherein the first conductive fingers each have a width to define a corresponding channel length, and wherein the channel lengths are different from each other. The high electron mobility transistor structure described in item 1 of the patent application scope, wherein each of the first conductive fingers has a width to define a corresponding channel length, and wherein the channel lengths are the same as each other. The high electron mobility transistor structure described in item 1 of the patent application range, wherein the first conductive fingers each have a width to define a corresponding channel length, and some of the channel lengths are the same as each other. According to the high electron mobility transistor structure described in item 1 of the scope of the patent application, a part of the multiple gate structure extends into the barrier layer. The high electron mobility transistor structure described in item 1 of the patent application scope, wherein the multiple gate structure is in direct contact with the barrier layer. The high electron mobility transistor structure described in item 1 of the patent application scope, wherein the substrate includes a silicon substrate, a silicon carbide substrate, or a sapphire substrate. The high electron mobility transistor structure described in item 1 of the patent application scope, wherein the barrier layer includes InAlGaN, AlGaN, InGaN, GaN, or a combination thereof. The high electron mobility transistor structure described in item 1 of the patent application scope, wherein the buffer layer includes InAlGaN, AlGaN, InGaN, GaN, AlN, or a combination thereof. The high electron mobility transistor structure described in item 1 of the patent application scope, wherein the source electrode and the drain electrode include Ti, Al, Ni, Mo, Au, or an alloy thereof. The high electron mobility transistor structure described in item 1 of the scope of the patent application, wherein the multiple gate structure or the multiple field plate structure includes Ti, Ni, Au, or an alloy thereof. A high electron mobility transistor structure includes: a substrate; a barrier layer disposed on the substrate; a buffer layer disposed between the substrate and the barrier layer, and having a channel region adjacent to the barrier An interface between the barrier layer and the buffer layer; a source electrode and a drain electrode disposed on the barrier layer; a multiple gate structure disposed between the source electrode and the drain electrode and including each other A plurality of first conductive fingers that are spaced apart and arranged in parallel on the barrier layer; and an electrical connection structure that electrically connects at least two of the first conductive fingers so that the first conductive fingers At least one of them is not electrically connected to the electrical connection structure. The high-electron-mobility transistor structure described in item 16 of the patent application scope further includes a multiple field plate structure disposed on the barrier layer between the multiple gate structure and the drain, including: a plurality of A second conductive finger portion, wherein the first conductive finger portions and the second conductive finger portions are alternately arranged; and a connecting portion is connected to one end of the second conductive finger portions. The high electron mobility transistor structure described in item 16 of the scope of patent application, wherein the first conductive fingers each have a width to define a corresponding channel length, and wherein the channel lengths are different from each other. The high electron mobility transistor structure described in item 16 of the scope of the patent application, wherein the first conductive fingers each have a width to define a corresponding channel length, and wherein the channel lengths are the same as each other. According to the high electron mobility transistor structure described in item 16 of the scope of the patent application, a part of the multiple gate structure extends into the barrier layer.