TW201914016A - High electron mobility transistor structure - Google Patents

Abstract

A high electron mobility transistor (HEMT) structure including a substrate, a barrier layer, a buffer layer, a source and a drain, a multi-gate structure, and a multi-field plate structure is provided. The barrier layer is disposed over the substrate. The buffer layer is disposed between the substrate and the barrier layer and includes a channel region adjacent to an interface between the barrier layer and the buffer layer. The source and the drain are disposed on the barrier layer. The multi-gate structure is disposed between the source and the drain and includes first conductive finger portions spaced apart from each other. The multi-field plate structure is disposed between the multi-gate structure and the drain and includes second conductive finger portions spaced apart from each other. The first conductive finger portions and the second conductive finger portions are in an alternate and parallel arrangement.

Description

 High electron mobility transistor structure  

The present disclosure relates to a semiconductor device structure, and more particularly to a high electron mobility transistor (HEMT) structure with a variable threshold voltage.

In the semiconductor industry, high voltage switching transistors (such as high electron mobility transistor (HEMT), junction filed effect transistor (JFET) or power MOS field power MOSFET) A semiconductor switching element commonly used as a high voltage, high power device (eg, a switched mode power supply (SMPS)). Among the above high-voltage switch transistors, the high electron mobility transistor can operate under high pressure without damaging the device due to its high power density, high breakdown voltage, high output voltage, and the like.

High Electron Mobility Transistors (HEMTs) include depletion mode HEMTs (D-mode HEMTs) and enhanced high emissivity mode HEMTs (E-mode HEMTs). In the D-mode HEMT, the electric field generated by the gate is used to evacuate a two-dimensional electron gas (2DEG) channel near the heterostructure interface between the energy bandgap semiconductor layers. For the E-mode HEMT, there is no channel and current generation until the transistor is operated to apply a bias voltage.

The D-mode HEMT allows current to pass when no gate-source voltage is applied (also known as a normally-on transistor). The E-mode HEMT blocks current flow when it is not applied with a gate-source voltage (also known as a normally-off transistor).

Although the existing D-mode HEMT and E-mode HEMT generally meet the requirements, they are not satisfactory in all aspects. For example, high electron mobility transistor structures are limited to a single threshold voltage and reduce their application flexibility. Moreover, the high-impedance semiconductor material is often included under the gate, which is liable to cause gate switching error and conduction loss/condition loss.

Therefore, it is necessary to find a high electron mobility transistor structure that can solve or improve the above problems.

An embodiment of the present disclosure provides a high electron mobility transistor structure, including: a substrate, a barrier layer, a buffer layer, a source and a drain, a multiple gate structure, and a multiple field plate structure. . The barrier layer is disposed on the substrate, and the buffer layer is disposed between the substrate and the barrier layer, and has a channel region adjacent to an interface between the barrier layer and the buffer layer. The source and the drain are disposed on the barrier layer, and the plurality of gate structures are disposed between the source and the drain, and include a plurality of first conductive fingers spaced apart from each other. The multiple field plate structure is disposed between the plurality of gate structures and the drain and includes a plurality of second conductive fingers spaced apart from each other. The first conductive fingers and the second conductive fingers are alternately and parallelly arranged on the barrier layer.

Another embodiment of the present disclosure provides a high electron mobility transistor structure, including: a substrate, a barrier layer, a buffer layer, a source and a drain, a multiple gate structure, and an electrical connection structure. . The barrier layer is disposed on the substrate, and the buffer layer is disposed between the substrate and the barrier layer, and has a channel region adjacent to an interface between the barrier layer and the buffer layer. The source and the drain are disposed on the barrier layer, and the plurality of gate structures are disposed between the source and the drain, and include a plurality of first conductive fingers spaced apart from each other and arranged in parallel on the barrier layer. The electrical connection structure electrically connects at least two of the first conductive fingers such that at least one of the first conductive fingers is not electrically connected to the electrical connection structure.

10a, 10b, 10c‧‧‧High electron mobility transistor structure

100‧‧‧Base

102‧‧‧buffer layer

103‧‧‧Channel area

110‧‧‧Barrier layer

112‧‧‧ source

114‧‧‧汲polar

120a, 120b, 120c‧‧‧ first conductive fingers

121‧‧‧Multiple gate structure

130a, 130b, 130c‧‧‧ second conductive fingers

130d‧‧‧Connecting Department

131‧‧‧Multiple plate structure

140a, 140b, 140c‧‧‧ wire connection structure

1 is a schematic plan view showing a high electron mobility transistor structure in accordance with some embodiments of the present disclosure.

Fig. 2 is a schematic cross-sectional view taken along line 2-2' in Fig. 1.

3 is a schematic plan view showing a high electron mobility transistor structure in accordance with some embodiments of the present disclosure.

4 is a plan view showing a high electron mobility transistor structure in accordance with some embodiments of the present disclosure.

The high electron mobility transistor structure of the disclosed embodiment will be described below. However, the present invention is to be understood as being limited to the details of the invention and is not intended to limit the scope of the invention.

Embodiments of the present disclosure provide a gold oxide half field effect transistor structure, such as a high electron mobility transistor (HEMT) structure, which utilizes multiple gates to modulate the threshold voltage of the transistor, thereby increasing the application flexibility of the transistor. Furthermore, a high electron mobility transistor structure with multiple gate designs can shorten the channel length and reduce the parasitic resistance under the gate to avoid causing the high electron mobility transistor structure with a single gate. The gate is incorrectly switched and reduces conduction loss/heat loss.

Please refer to FIGS. 1 and 2 , wherein FIG. 1 is a plan view showing a high electron mobility transistor structure 10 a according to some embodiments of the present disclosure, and FIG. 2 is a cross-sectional view of FIG. Schematic diagram of the 2' line. As shown in FIG. 2, the high electron mobility transistor structure 10a of the embodiment includes a substrate 100, a buffer layer 102, a barrier layer 110, a source 112, and a drain 114. The gate structure 121 and a selective multiple field plate structure 131.

In some embodiments, the barrier layer 110 is disposed on the substrate 100 and the buffer layer 102 is disposed between the substrate 100 and the barrier layer 110. Furthermore, the source 112 and the drain 114 are disposed on the barrier layer 110, and the multiple gate structure 121 is disposed on the barrier layer 110 between the source 112 and the drain 114. Furthermore, the multiple field plate structure 131 is disposed on the barrier layer 110 between the multiple gate structure 121 and the drain 114. Each of the above described high electron mobility transistor structures 10a will be discussed in greater detail in the following paragraphs.

As shown in FIG. 1 or 2, the high electron mobility transistor structure 10a of the disclosed embodiment includes a substrate 100. In some embodiments, the substrate 100 can include a germanium substrate, a tantalum carbide substrate, or a sapphire substrate. In other embodiments, the substrate 100 can also include a silicon on insulator (SOI) substrate.

In some embodiments, the high electron mobility transistor structure 10a of the disclosed embodiment further includes a buffer layer 102 disposed over the substrate 100. The buffer layer 102 can be a multi-layered structure. For example, the buffer layer 102 includes a nucleation layer (not shown) and a III-V semiconductor compound layer (not shown) thereon. In some embodiments, the nucleation layer includes AlN, GaN, or AlGaN for reducing stress caused by lattice mismatch between the substrate 100 and the III-V semiconductor compound layer above the nucleation layer. For example, the difference in lattice lattice and the coefficient of thermal expansion between the AlN nucleation layer and the substrate 100 is small, and the stress between the substrate 100 and the III-V semiconductor compound layer formed later is alleviated.

In some embodiments, the III-V semiconductor compound layer on the nucleation layer can serve as a channel layer for the high electron mobility transistor structure 10a. For example, the buffer layer 102 includes a channel region 103 (shown by the dashed line in FIG. 2), such as a two-dimensional electron gas (2DEG) channel adjacent to the upper surface of the buffer layer 102 ( That is, adjacent to the interface between the buffer layer 102 and the subsequently formed barrier layer). In some embodiments, the III-V semiconductor compound layer on the nucleation layer may include InAlGaN, AlGaN, InGaN, and GaN. ), aluminum nitride (AlN) or a combination thereof.

In some embodiments, molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (hydride vapor phase epitaxy) may be used. The buffer layer 102 is formed on the substrate 100 by HVPE) or other suitable deposition method. In some embodiments, the thickness of the buffer layer 102 can range from about 0.2 [mu]m to 10 [mu]m.

In some embodiments, the high electron mobility transistor structure 10a of the disclosed embodiment further includes a barrier layer 110 disposed on the buffer layer 102 and in direct contact therewith. In some embodiments, the barrier layer 110 includes a III-V semiconductor compound layer, such as indium aluminum gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), gallium nitride ( GaN) or a combination thereof. It should be noted that the composition of the barrier layer 110 and the III-V semiconductor compound layer in the buffer layer 102 are different. For example, the barrier layer 110 is composed of aluminum gallium nitride (AlGaN), and the III-V semiconductor compound layer in the buffer layer 102 is composed of gallium nitride (GaN), and the barrier layer 110 and the buffer layer are formed. 102 constitutes a different structure.

In some embodiments, buffering can be formed on the buffer layer 102 using molecular beam epitaxy (MBE), organometallic vapor deposition (MOCVD), hydride vapor epitaxy (HVPE), or other suitable deposition methods. Layer 102. In some embodiments, the thickness of the barrier layer 110 can range from about 1 nm to 100 nm.

A band gap discontinuity between the buffer layer 102 and the barrier layer 110 creates a carrier channel with high mobile conduction electrons in the buffer layer 102 adjacent to the interface between the buffer layer 102 and the barrier layer 110 (labeled as Channel zone 103), which is referred to as a two-dimensional electron gas (2DEG) channel. The transistor can be turned on or off when a gate-source voltage is applied.

In some embodiments, the high electron mobility transistor structure 10a of the disclosed embodiment further includes a source 112, a drain 114, and a multiple gate structure 121 disposed on and in contact with the barrier layer 110. The multiple gate structure 121 is disposed between the source 112 and the drain 114. In some embodiments, source 112, drain 114, and multiple gate structures 121 each have a portion that extends into barrier layer 110, as shown in FIG. As a result, the multiple gate structure 121 that is recessed can change the thickness of the barrier layer 110, thereby reducing the density of the two-dimensional electron gas (2DEG). In some embodiments, the multiple gate structure 121, the source 112, and the drain 114 are disposed on the barrier layer 110 having a flat surface without being immersed in the barrier layer 110.

In some embodiments, as shown in Figures 1 and 2, the multiple gate structure 121 includes two or more first conductive fingers spaced apart from each other by a distance and arranged in parallel. Here, for simplicity of illustration and description, only three first conductive fingers 120a, 120b, and 120c are shown. It will be appreciated that the number of first conductive fingers in the multiple gate structure 121 depends on the design requirements and is not limited to the embodiments shown in Figures 1 and 2.

In some embodiments, the first conductive finger 120a has a width L1; the first conductive finger 120b has a width L2; and the first conductive finger 120c has a width L3. These widths L1, L2 and L3 define the corresponding channel length. In some embodiments, the widths L1, L2, and L3 are different from each other such that the corresponding channel lengths are different from each other. As a result, different threshold voltages can be obtained when voltages are applied to the first conductive fingers 120a, 120b, and 120c, respectively.

Furthermore, the sum of the widths L1, L2, and L3 can be less than or equal to the width of the single gate described above compared to a conventional high electron mobility transistor having a single gate. Since the widths L1, L2, and L3 of the first conductive fingers 120a, 120b, and 120c are respectively smaller than the width of the single gate, the parasitic resistance under the gate in the high electron mobility transistor 10a is smaller than that of the conventional high electron mobility. Parasitic resistance under the gate in the crystal. In this way, it is possible to avoid causing the gate to be erroneously switched and to reduce the conduction loss/heat loss.

In some embodiments, the widths L1, L2, and L3 are identical to each other such that the corresponding channel lengths are identical to each other. In this way, when voltages are applied to the first conductive fingers 120a, 120b, and 120c, respectively, the same threshold voltage can be obtained. In other embodiments, the widths L1, L2, and L3, and wherein the lengths of the channels are the same as each other. In this way, when voltages are applied to the first conductive fingers 120a, 120b, and 120c, respectively, two different threshold voltages can be obtained.

In some embodiments, the multiple gate structure 121 can include a conductive material, such as a metal (such as titanium (Ti), nickel (Ni), gold (Au) or alloys thereof), and further, the source 112 and the drain 114 A conductive material such as a metal such as titanium (Ti), aluminum (Al), nickel (Ni), molybdenum (Mo), gold (Au), or an alloy thereof may be included. The multiple gate structure 121, the source 112 and the drain 114 may be subjected to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering (sputtering). ), or other suitable process is formed.

In some embodiments, the high electron mobility transistor structure 10a of the disclosed embodiment further includes an electrical connection structure 140a electrically connecting at least two of the first conductive fingers 120a, 120b, and 120c to make the first At least one of the conductive fingers 120a, 120b, and 120c is not electrically connected to the electrical connection structure 140a. For example, the electrical connection structure 140a is electrically connected to the first conductive fingers 120a and 120b, as shown in FIG. In some embodiments, the electrical connection structure 140a can electrically connect the first conductive fingers 120a and 120c. In some other embodiments, the electrical connection structure 140a can electrically connect the first conductive fingers 120b and 120c.

In some embodiments, the electrical connection structure 140a can include an interconnect structure composed of a conductive plug and a conductive layer. In some embodiments, the electrical connection structure 140a can include wiring. In this way, by adjusting the number and width of the first conductive fingers and/or controlling the connection manner of the electrical connection structure 140a, the high electron mobility transistor structure 10a can have the function of modulating the threshold voltage in different products. The desired threshold voltage is obtained in the application.

In some embodiments, the high electron mobility transistor structure 10a of the disclosed embodiment further includes a multiple field plate structure 131, wherein the multiple field plate structure 131 is disposed between the multiple gate structure 121 and the drain 114. In some embodiments, the multiple field plate structure 131 is disposed on the barrier layer 110 without being immersed in the barrier layer 110.

In some embodiments, as shown in Figures 1 and 2, the multiple field plate structure 131 includes two or more second conductive fingers spaced apart from each other and arranged in parallel at a distance. Here, for simplicity of illustration and description, only three first conductive fingers 130a, 130b, and 130c are shown. In some embodiments, the first conductive fingers 120a, 120b, and 120c are alternately arranged with the second conductive fingers 130a, 130b, and 130c. It will be appreciated that the number of second conductive fingers in the multiple field plate structure 131 depends on the number of first conductive fingers and is not limited to the embodiments shown in Figures 1 and 2.

In some embodiments, the multiple field plate structure 131 further includes a connecting portion 130d connecting one ends of the second conductive fingers 130a, 130b, and 130c, as shown in FIG. In some embodiments, the multiple field plate structure 131 can include a conductive material that can be the same or similar to the multiple gate structure 121. For example, the multiple field plate structure 131 may include a metal such as titanium (Ti), nickel (Ni), gold (Au), or an alloy thereof, and further, the multiple field plate structure 131 may be formed by chemical vapor deposition (CVD). , physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or other suitable process formation. The multiple gate structure 121 can alleviate the peak electric field under the multiple gate structure 121 to increase the breakdown voltage of the transistor and reduce the leakage current.

Referring to FIG. 3, there is shown a plan view of a high electron mobility transistor structure 10b according to some embodiments of the present disclosure, wherein components identical to those of FIG. 1 are given the same reference numerals and their description is omitted. As shown in Fig. 3, the high electron mobility transistor structure 10b is similar to the high electron mobility transistor structure 10a of Fig. 1. Unlike the high electron mobility transistor structure 10a, the high electron mobility transistor structure 10b includes an electrical connection structure 140b to electrically connect the first conductive fingers 120a, 120b, and 120c. In some embodiments, the electrical connection structure 140a can include an interconnect structure and a fuse device composed of a conductive plug and a conductive layer. In some embodiments, the electrical connection structure 140a can include wiring and fuse devices. In this way, by controlling the connection manner of the electrical connection structure 140b and/or adjusting the number and width of the first conductive fingers through the fuse device, the high electron mobility transistor structure 10a can have the function of modulating the threshold voltage. The required threshold voltage is obtained in different product applications.

Referring to FIG. 4, there is shown a plan view of a high electron mobility transistor structure 10c according to some embodiments of the present disclosure, wherein components identical to those of FIG. 1 are given the same reference numerals and their description is omitted. As shown in Fig. 4, the high electron mobility transistor structure 10c is similar to the high electron mobility transistor structure 10a of Fig. 1. Unlike the high electron mobility transistor structure 10a, the high electron mobility transistor structure 10c includes an electrical connection structure 140c to electrically connect one ends of the second conductive fingers 130a, 130b, and 130c. In some embodiments, the electrical connection structure 140c can selectively electrically connect at least one of the first conductive fingers 120a, 120b, and 120c (eg, the first conductive fingers 120a). In some embodiments, the electrical connection structure 140c can include an interconnect structure composed of a conductive plug and a conductive layer. In some embodiments, the electrical connection structure 140c can include wiring. It is to be understood that the high electron mobility transistor structure 10c may have an electrical connection structure 140b as shown in FIG. 3 instead of the electrical connection structure 140a.

According to the above embodiment, since the high electron mobility transistor structure has multiple gates, the threshold voltage of the transistor can be modulated by adjusting the number and width of the first conductive fingers. Moreover, according to the above embodiment, since the high electron mobility transistor structure has an electrical connection structure electrically connecting the first conductive fingers, the connection of the electrical connection structure can be controlled to further modulate the threshold voltage of the transistor. So come. It can increase the application flexibility of the transistor.

Furthermore, compared to a high electron mobility transistor structure having a single gate, a high electron mobility transistor structure having multiple gates has a shorter channel length per gate, thereby reducing parasitic below the gate. Resistor (ie, lowering the conduction group) avoids causing gate erroneous switching, reducing conduction loss/heat loss, and improving power-conversion efficiency.

In addition, according to the above embodiment, since the high electron mobility transistor structure has multiple field plates and multiple gates alternately arranged, the peak electric field under the multiple gate structure can be alleviated to increase the breakdown voltage of the transistor and reduce the leakage current.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Claims (20)

 A high electron mobility transistor structure includes: a substrate; a barrier layer disposed on the substrate; a buffer layer disposed between the substrate and the barrier layer and having a channel region adjacent to the resistor An interface between the barrier layer and the buffer layer; a source and a drain are disposed on the barrier layer; a plurality of gate structures are disposed between the source and the drain, and include each other a plurality of spaced apart first conductive fingers; and a plurality of field plate structures disposed between the plurality of gate structures and the drain and including a plurality of second conductive fingers spaced apart from each other, wherein The first conductive fingers and the second conductive fingers are alternately and parallelly arranged on the barrier layer.    The high electron mobility transistor structure of claim 1, wherein the multiple field plate structure further comprises a connecting portion connecting one ends of the second conductive fingers.    The high electron mobility transistor structure as described in claim 1 further includes an electrical connection structure electrically connected to the second conductive fingers.    The high electron mobility transistor structure of claim 3, wherein the electrical connection structure electrically connects at least one of the first conductive fingers.    The high electron mobility transistor structure of claim 1, further comprising an electrical connection structure electrically connecting one of the first conductive fingers and the second conductive fingers.    The high electron mobility transistor structure of claim 1, wherein the first conductive fingers each have a width to define a corresponding channel length, and wherein the channel lengths are different from each other.    The high electron mobility transistor structure of claim 1, wherein the first conductive fingers each have a width to define a corresponding channel length, and wherein the channel lengths are identical to each other.    The high electron mobility transistor structure of claim 1, wherein the first conductive fingers each have a width to define a corresponding channel length, and wherein some of the channel lengths are identical to each other.    The high electron mobility transistor structure of claim 1, wherein a portion of the multiple gate structure extends into the barrier layer.    The high electron mobility transistor structure of claim 1, wherein the multiple gate structure is in direct contact with the barrier layer.    The high electron mobility transistor structure of claim 1, wherein the substrate comprises a germanium substrate, a tantalum carbide substrate or a sapphire substrate.    The high electron mobility transistor structure of claim 1, wherein the barrier layer comprises InAlGaN, AlGaN, InGaN, GaN, or a combination thereof.    The high electron mobility transistor structure of claim 1, wherein the buffer layer comprises InAlGaN, AlGaN, InGaN, GaN, AlN, or a combination thereof.    The high electron mobility transistor structure according to claim 1, wherein the source and the drain include Ti, Al, Ni, Mo, Au or an alloy thereof.    The high electron mobility transistor structure of claim 1, wherein the multiple gate structure or the multiple field plate structure comprises Ti, Ni, Au or an alloy thereof.    A high electron mobility transistor structure includes: a substrate; a barrier layer disposed on the substrate; a buffer layer disposed between the substrate and the barrier layer and having a channel region adjacent to the resistor An interface between the barrier layer and the buffer layer; a source and a drain are disposed on the barrier layer; a plurality of gate structures are disposed between the source and the drain, and include each other a plurality of first conductive fingers spaced apart from each other and disposed in parallel with the barrier layer; and an electrical connection structure electrically connecting at least two of the first conductive fingers to the first conductive fingers At least one of them is not electrically connected to the electrical connection structure.    The high electron mobility transistor structure of claim 16, further comprising a multiple field plate structure disposed on the barrier layer between the multiple gate structure and the drain, including: plural And a second conductive finger, wherein the first conductive fingers are alternately arranged with the second conductive fingers; and a connecting portion connects one ends of the second conductive fingers.    The high electron mobility transistor structure of claim 16, wherein the first conductive fingers each have a width to define a corresponding channel length, and wherein the channel lengths are different from each other.    The high electron mobility transistor structure of claim 16, wherein the first conductive fingers each have a width to define a corresponding channel length, and wherein the channel lengths are identical to each other.    The high electron mobility transistor structure of claim 16, wherein a portion of the multiple gate structure extends into the barrier layer.