JP2008141094A - Semiconductor element and manufacturing method of semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element having an electrode having less stress while provided with high diffusion preventing effect, and a manufacturing method the semiconductor element. <P>SOLUTION: An electrode 44 to be formed on the semiconductor element 51 is divided into a first electrode layer 30 having ohmic characteristics through heat treatment and a second electrode layer 36 not subject to heat treatment, and thus, a stress generated in heat treatment can be reduced. Further, a barrier layer is made to be thin by dividing it into a first barrier layer 26 and a second barrier layer 28 to reduce a stress, and an intermediate layer 27 provided between the first barrier layer 26 and the second barrier layer 28 is eliminated by diffusion in solder bonding. In this way, the barrier layer works as a thick barrier layer 23, and thus, high diffusion preventing effect can be obtained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor element having an electrode having a barrier layer and a method for manufacturing the semiconductor element, and more particularly to a semiconductor element having an electrode having a low stress while having a high diffusion preventing effect, and a method for manufacturing the semiconductor element. is there.

  Semiconductor devices have been widely developed as active components such as diodes and transistors, recording devices such as memories, light receiving devices such as photodiodes, and light emitting devices such as semiconductor lasers. It is indispensable for. Many of these semiconductor elements include electrodes for supplying power and transmitting / receiving electrical signals. This electrode is used not only for electrically connecting the semiconductor elements, but also for use in joining the semiconductor elements to a base or the like in some cases.

  In general, a solder material is used for joining the electrodes of these semiconductor elements and other members. However, when the electrodes of the semiconductor element are joined by the solder material, it is necessary to pay attention to the diffusion of the solder material component to the electrode side and the diffusion of the metal constituting the electrode to the solder material side. If the solder material component diffuses to the electrode side and reaches the semiconductor portion through the electrode, there is a problem that the solder material component significantly deteriorates the characteristics of the semiconductor element. Further, if the metal constituting the electrode diffuses toward the solder material, the melting point of the solder material fluctuates, which makes it difficult to control the temperature at the time of bonding, which is not preferable in terms of process design. In particular, Au (gold), which is usually used for electrodes of semiconductor elements, has a characteristic of easily diffusing into Sn (tin) contained in a general solder material. In addition to changing the melting point of the solder material, there may be various adverse effects such as promoting the diffusion of the solder material component to the electrode side.

  Therefore, it is well known that a barrier layer using a refractory metal such as Mo (molybdenum), Ti (titanium), or Pt (platinum) is provided on the electrode of the semiconductor element in order to prevent the above diffusion. . By providing a barrier layer between predetermined layers in the electrode, this barrier layer acts as a barrier to prevent the diffusion of the solder material component into the semiconductor part and to prevent excessive diffusion of the metal constituting the electrode into the solder material. Can be suppressed. However, in order for this barrier layer to exhibit a sufficient diffusion preventing effect, a certain thickness is required.

  As described above, the barrier layer is extremely effective as an anti-diffusion measure in the electrode. However, on the other hand, there is a problem that a stress generated during film formation and a stress caused by heat treatment described later are large. The stress caused by heat treatment refers to the stress in the shrinking direction that occurs when a large number of defects existing in each electrode layer after film formation decrease with the rearrangement of atoms by heat treatment. This is several times larger than the stress during film formation. In addition, in order for the electrode layer formed in the semiconductor portion to function as an electrode, it is necessary to perform a predetermined heat treatment, and stress is inevitably generated in the electrode.

  Further, these stresses increase as the thickness of each electrode layer constituting the electrode increases. For this reason, if the thickness of the barrier layer is increased in order to obtain a high diffusion preventing effect, problems such as film peeling caused by the barrier layer due to the stress occur. Therefore, in order to increase the thickness of the barrier layer, some stress relaxation measures are required.

  In the invention related to the semiconductor light-emitting device disclosed in [Patent Document 1] below for this problem, the barrier layer is composed of a thin Ti layer and a Pt layer, and two layers are alternately provided, A layer having a high barrier property is formed while reducing the stress of the entire barrier layer.

JP 2000-183401 A

  However, in the invention disclosed in [Patent Document 1], the stress of the Ti layer and the Pt layer at the same thickness is substantially the same. Since the stress generated in each layer extends to the semiconductor part, the semiconductor part may be warped or cracked, and for example, it may cause kinks in the semiconductor laser, which may adversely affect the characteristics and reliability of the semiconductor element. is there. For this reason, the stress relaxation measure of each layer itself which comprises a barrier layer is calculated | required.

  This invention is made | formed in view of the said situation, and it aims at providing the manufacturing method of the semiconductor element which has an electrode with little stress, having the high diffusion prevention effect, and the semiconductor element.

The present invention
In the semiconductor element 51 including the electrode 44,
The electrode 44 has a stacked structure in which a first barrier layer (first barrier layer 26), an intermediate layer 27, and a second barrier layer (second barrier layer 28) are sequentially stacked. By providing the element 51, the above problem is solved.

In the semiconductor element 51 in which the electrode 44 is provided on the semiconductor portion 46,
The electrode 44 is provided on the first electrode layer and a first electrode layer (first electrode layer 30) in contact with the semiconductor portion 46 and having adhesiveness with the semiconductor portion 46. A second electrode layer (second electrode layer 36) having a stacked structure in which a barrier layer (first barrier layer 26), an intermediate layer 27, and a second barrier layer (second barrier layer 28) are sequentially stacked; The above-described problems are solved by providing a semiconductor element 51 including:

In the method for manufacturing a semiconductor element,
A first electrode layer forming step of forming a first electrode layer (first electrode layer 30) on the semiconductor portion 46;
A heat treatment step of heating the semiconductor portion 46 and the first electrode layer after the first electrode layer formation step;
After the heat treatment step, a first barrier layer (first barrier layer 26), an intermediate layer 27, and a second barrier layer (second barrier layer 28) are sequentially stacked on the first electrode layer. A second electrode layer forming step of forming a second electrode layer (second electrode layer 36) having a structure;
The above-described problems are solved by providing a method of manufacturing the semiconductor element 51 characterized by comprising:

The semiconductor element and the method for manufacturing the semiconductor element according to the present invention have the above-described configuration and procedure.
An electrode having a high anti-diffusion effect and low stress can be formed on the semiconductor element. In addition, the semiconductor element manufactured according to the present invention has no warpage or cracking of the semiconductor portion due to stress from the electrode, and has good element characteristics and reliability of the semiconductor element, and also when soldered with a solder material. Diffusion of the material component into the semiconductor layer and excessive diffusion of the electrode component into the solder material can be prevented.

  A method for manufacturing a semiconductor device and an embodiment of the semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the present invention. FIG. 2 is a schematic cross-sectional view when the semiconductor device according to the present invention is applied to a semiconductor laser. FIG. 3 is a partially enlarged view of the first form of the electrode in the semiconductor device according to the present invention. FIG. 4 is a diagram for explaining the behavior at the time of bonding of the semiconductor elements according to the present invention. FIG. 5 is a partially enlarged view of the second form of the electrode in the semiconductor device according to the present invention. FIG. 6 is a partially enlarged view of a third embodiment of the electrode in the semiconductor element according to the present invention.

  A semiconductor element 51 according to the present invention shown in FIG. 1 has an electrode 44 in a semiconductor portion 46. In FIG. 1, only one electrode 44 is shown for convenience, but it is usually provided on both the p-type semiconductor side and the n-type semiconductor side. One or more electrodes 44 may be formed on a part of the surface of the semiconductor portion 46 by using a photolithography method, a wet etching method, a dry etching method, or the like. Furthermore, only a part of the electrodes, for example, only the p-side electrode can be formed as the electrode 44 according to the present invention.

  The electrode 44 includes a first electrode layer 30 on the semiconductor portion 46 side having ohmic characteristics, and a second electrode layer 36 formed on the bonding side adjacent to the first electrode layer 30. The first electrode layer 30 includes the ohmic contact layer 20 and the first metal layer 22 that are in contact with the semiconductor portion 46. The second electrode layer 36 includes a connection layer 24, a first barrier layer 26, an intermediate layer 27, a second barrier layer 28, and a surface electrode 29 in order from the first electrode layer 30 side. The first electrode layer 30 may be provided with a third barrier layer, and the first electrode layer 30 may be provided with the first barrier layer 26. Furthermore, necessary layers may be appropriately added to the first electrode layer 30 and the second electrode layer 36. The first metal layer 22, the connection layer 24, and the surface layer electrode 29 of the first electrode layer 30 and the second electrode layer 36 are not necessarily essential.

  The main constituent material of the semiconductor portion 46 is GaAs (gallium arsenide) alone or a GaAs-based multi-component compound semiconductor in which one or more elements such as Al (aluminum), In (indium), and P (phosphorus) are alloyed with GaAs. In addition, known semiconductor materials such as InP (indium phosphide) and GaN (gallium nitride) can be used.

  The semiconductor portion 46 is formed by a CVD (Chemical Vapor Deposition) method including a MOCVD (Metalorganic Chemical Vapor Deposition) method or a MBE (Molecular Beam Epitaxy method: molecular beam epitaxial growth method). The semiconductor film formation method such as photolithography method, wet etching method, dry etching method, vapor deposition method, sputtering method, etc. is appropriately combined, and a semiconductor layer having a predetermined shape and characteristics is sequentially stacked. .

  An intermetallic compound is generally used for the ohmic contact layer 20 of the first electrode layer 30 formed so as to be in contact with the semiconductor portion 46. In particular, when the semiconductor portion 46 is a III-V group compound semiconductor, AuBe (gold beryllium) which is an intermetallic compound is used as the ohmic contact layer 20 on the p-type semiconductor side, and AuGeNi (gold germanium nickel) is an n-type semiconductor. Often used as the side ohmic contact layer 20. As materials for the first metal layer 22, the connection layer 24, the surface layer electrode 29, etc., it is preferable to use Au from the viewpoints of conductivity, bondability, and thermal conductivity.

  As materials of the first barrier layer 26, the second barrier layer 28, and the third barrier layer 25 described later, Ti, Mo, Pt, and Cr (chromium) having an effect of preventing the diffusion of a solder material component such as Sn. A high melting point metal such as The intermediate layer 27 is made of Au having high diffusibility with respect to Sn.

  The thickness of the ohmic contact layer 20 and the first metal layer 22 constituting the first electrode layer 30 is not particularly limited, but the stress associated with the heat treatment during the formation of the first electrode layer 30 and the addition of ohmic characteristics. From the viewpoint of reducing the thickness, it is preferable that the thickness of the first electrode layer 30 is set to be 500 nm or less.

  The thicknesses of the first barrier layer 26 and the second barrier layer 28 constituting the second electrode layer 36 are in the range of 50 nm to 150 nm where no significant stress is generated during film formation, and the first barrier layer 26 and the second barrier layer. It is preferable to set so that the total layer thickness with 28 is 150 nm or more. The layer thickness of the intermediate layer 27 is preferably in the range of 50 nm to 500 nm that can diffuse to the solder material side when bonded to the solder material.

  Each layer constituting the electrode 44 can be sequentially formed by a known method such as vapor deposition or sputtering.

  Next, a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be described in detail using examples. In the embodiment, the semiconductor laser 50 is used as the semiconductor element 51 and the p-side electrode 12 is used as the electrode 44 as an example.

  A semiconductor laser 50 that is the semiconductor element 51 of the present invention shown in FIG. 2 includes a semiconductor portion 46, a p-side electrode 12 formed on the p-type semiconductor layer side of the semiconductor portion 46, and an n-type semiconductor layer of the semiconductor portion 46. And an n-side electrode 13 formed on the side. Further, the p-side electrode 12 includes a first electrode layer 30 and a second electrode layer 36.

Here, the outline of the manufacturing method of the semiconductor part 46 which comprises the semiconductor laser 50 is demonstrated. First, an n-type Al _0.5 Ga _0.5 As (aluminum gallium arsenide) first cladding layer 3 (Si doping concentration is 1 × 10 ¹⁸ cm ⁻³ ) having a thickness of 1.5 μm is formed on an n-type GaAs substrate 2. 0.07 μm thick Al _0.13 Ga _0.87 As active layer 4 (undoped) and 0.3 μm thick p-type Al _0.5 Ga _0.5 As first cladding layer 5 (Zn doping concentration) 1 × 10 ¹⁸ cm ⁻³ ), a p-type Al _0.7 Ga _0.3 As etching stopper layer 6 having a thickness of 0.03 μm (Zn doping concentration is 1 × 10 ¹⁸ cm ⁻³ ), and a thickness of 0 .7 μm p-type Al _0.5 Ga _0.5 As second cladding layer 7 (Zn doping concentration is 1 × 10 ¹⁸ cm ⁻³ ) and 0.3 μm thick p-type GaAs cap layer 8 (Zn doping concentration) MOCV but a 5 × ¹⁰ 19 ^{cm -3),} the They are sequentially formed by using a.

Next, after a mask having a predetermined width is formed on the surface of the p-type GaAs cap layer 8 by a photolithography method, the p-type Al _0.5 Ga _0.5 As second cladding layer 7 and the p of the region not covered with the mask are formed. The type GaAs cap layer 8 is removed by wet etching. Thereby, a ridge stripe 9 is formed on the surface of the p-type Al _0.7 Ga _0.3 As etching stopper layer 6.

  Next, the n-type GaAs current confinement layers 101 and 102 are formed on both sides of the ridge stripe 9 by using the MOCVD method so that the total thickness of both layers becomes 1.0 μm. Finally, after removing the mask, the p-type GaAs contact layer 11 is formed using the MOCVD method. Thereby, the semiconductor portion 46 of the semiconductor laser 50 having the ridge stripe 9 is manufactured.

  Next, the p-side electrode 12 is formed on the surface of the p-type GaAs contact layer 11, which is the p-type semiconductor layer of the semiconductor portion 46, using a vapor deposition method according to the procedure described later. The n-side electrode 13 is formed on the n-type GaAs substrate 2 before and after the formation of the p-side electrode 12. The n-side electrode 13 is formed by polishing the n-type GaAs substrate 2 to a thickness of 100 μm, and sequentially depositing a 100 nm-thick AuGeNi layer and a 500 nm-thick Au layer by vapor deposition. An ohmic electrode is formed by performing a heat treatment at around ℃.

  Next, the semiconductor laser 46 is manufactured by performing primary cleavage and secondary cleavage of the semiconductor portion 46 on which the p-side electrode 12 and the n-side electrode 13 are formed to have predetermined dimensions. The semiconductor laser 50 is coated with a coating (not shown) having a different reflectance on a predetermined surface after the primary cleavage.

The semiconductor laser 50 manufactured by the above procedure oscillates by supplying a current with the p-side electrode 12 as a positive electrode and the n-side electrode 13 as a negative electrode. When this oscillation exceeds the oscillation threshold, laser oscillation occurs. Laser light is emitted from the Al _0.13 Ga _0.87 As active layer 4.

  Next, the configuration and formation method of the p-side electrode 12 will be described with reference to a partially enlarged view of the p-side electrode 12 shown in FIG. First, the p-side electrode 12 is formed as a first electrode layer forming step on the surface of the p-type GaAs contact layer 11 constituting the semiconductor portion 46, with an ohmic contact layer 20 made of AuBe having a thickness of 100 nm and a thickness of 100 nm. The first metal layer 22 made of Au is sequentially formed by vapor deposition. Thereby, the first electrode layer 30 is formed.

  Next, a heat treatment at 400 ° C. is performed on the first electrode layer 30 in a nitrogen atmosphere by a heat treatment step. By this heat treatment, the Au element and the Be element contained in the ohmic contact layer 20 diffuse near the interface of the p-type GaAs contact layer 11 in contact with the ohmic contact layer 20. By the diffusion of the Au element and the Be element, the vicinity of the interface between the ohmic contact layer 20 and the p-type GaAs contact layer 11 becomes ohmic characteristics, and thus the first electrode layer 30 having the ohmic contact layer 20 functions as an ohmic electrode layer.

  This heat treatment causes atomic rearrangement in the ohmic contact layer 20 and the first metal layer 22. As a result, a stress in the shrinking direction is generated in the first electrode layer 30, but since the thickness of the first electrode layer 30 is as thin as 500 nm or less, a large stress that adversely affects the characteristics of the semiconductor element does not occur. .

  Further, the Ga element and As element in the p-type GaAs contact layer 11 may diffuse to the first electrode layer 30 side and be deposited on the surface of the first electrode layer 30 by this heat treatment. The deposited Ga element and As element react with oxygen in the air to form Ga oxide and As oxide on the surface of the first electrode layer 30. The formed Ga oxide and As oxide significantly reduce the adhesion strength between the first electrode layer 30 and the second electrode layer 36. Therefore, as the next step, an etchant made of a halogen acid such as buffered hydrofluoric acid is used. Then, the Ga oxide and As oxide are removed by etching for a predetermined time.

  Next, the n-side electrode 13 is formed on the n-type GaAs substrate 2 before the second electrode layer 36 is formed on the surface of the first electrode layer 30. This is because the n-side electrode 13 is formed before the second electrode layer 36 is formed, so that heat at the time of imparting ohmic characteristics to the n-side electrode 13 does not reach the second electrode layer 36. It is. Therefore, if the process is designed so that heat that causes rearrangement of atoms is not applied to the second electrode layer 36, the n-side electrode 13 is not necessarily formed at this point.

  Next, as a second electrode layer formation step, a connection layer 24 made of Au having a thickness of 50 nm, a first barrier layer 26 made of Pt having a thickness of 100 nm, and Au having a thickness of 100 nm are formed on the surface of the first electrode layer 30. An intermediate layer 27 made of Pt, a second barrier layer 28 made of Pt having a thickness of 100 nm, and a surface layer electrode 29 made of Au having a thickness of 50 nm are sequentially formed by vapor deposition. As a result, the p-side electrode 12 including the first electrode layer 30 and the second electrode layer 36 is formed on the surface of the p-type GaAs contact layer 11 of the semiconductor portion 46.

  The second electrode layer 36 includes a first barrier layer 26 and a second barrier layer 28 made of a refractory metal. However, since the layer thickness is thin, no large stress is generated during film formation. In addition to this, since the second electrode layer 36 is formed on the surface of the first electrode layer 30 to which ohmic characteristics have already been imparted, it is not necessary to perform heat treatment to impart ohmic characteristics. Therefore, in each layer including the first barrier layer 26 and the second barrier layer 28 constituting the second electrode layer 36, no stress is generated due to the rearrangement of atoms during the heat treatment. Therefore, the stress generated in the p-side electrode 12 is extremely small, and the warp or crack of the semiconductor portion 46 due to the stress from the p-side electrode 12 does not occur. In addition, the characteristics and reliability of the semiconductor element are not adversely affected.

  Next, the behavior of the first barrier layer 26, the intermediate layer 27, and the second barrier layer 28 constituting the p-side electrode 12 will be described using an example in which the p-side electrode 12 is joined to the base 40 with the solder material 38. To do.

  First, as shown in FIG. 4A, the surface layer electrode 29 of the p-side electrode 12 and the solder material 38 provided on the base 40 are brought into contact with each other. As the solder material 38, it is preferable to use a material mainly containing Sn and containing one or more elements such as Au, Bi (bismuth), Cu (copper), Ag (silver). Thus, when the p-side electrode 12 is formed mainly of Au, it is preferable to use AuSn.

  Next, the solder material 38 is melted by heating. At this time, since Au used for the p-side electrode 12 has a property of being easily dissolved in Sn which is a component of the solder material 38, the Au element of the intermediate layer 27 close to the solder material 38 as well as the surface layer electrode 29 is used. However, the solid phase diffusion is quickly diffused into the solder material 38 through the second barrier layer 28 which is thin and insufficient in the diffusion preventing effect. By this solid phase diffusion, as shown in FIG. 4B, the intermediate layer 27 disappears, and the first barrier layer 26 and the second barrier layer 28 are adjacent to each other and function as a thick barrier layer 23. Since this barrier layer 23 has a sufficient thickness to exhibit a high diffusion preventing effect, this barrier layer 23 becomes a barrier, and the solder material component in the solder material 38 cannot diffuse to the semiconductor portion 46 side. . Similarly, the Au element of the connection layer 24 located closer to the semiconductor portion 46 than the barrier layer 23 cannot diffuse to the solder material 38 side. Therefore, the diffusion of the solder material component into the semiconductor portion 46 is prevented, and the characteristics of the semiconductor element are maintained favorably. Further, since the amount of Au in the intermediate layer 27 diffusing into the solder material 38 can be controlled in advance, the change in the melting point of the solder material 38 due to the diffusion of Au can be easily predicted, which causes a problem in designing the process. There is nothing.

  Next, as Example 2, a partially enlarged view of the second form of the p-side electrode 12 in the semiconductor laser 50 is shown in FIG. Since the semiconductor portion 46 of the semiconductor laser 50 is exactly the same as that of the first embodiment, description and explanation are omitted.

  In the p-side electrode 12 of the second embodiment shown in FIG. 5, the first electrode layer 30 constituting the p-side electrode 12 is made of an ohmic contact layer 20 made of AuBe having a thickness of 100 nm and Au having a thickness of 100 nm. In addition to the first metal layer 22, the third barrier layer 25 made of Pt with a thickness of 100 nm and the second metal layer 22a made of Au with a thickness of 50 nm are formed. In the second embodiment, the connection layer 24 of the second electrode layer 36 is formed with a layer thickness of 1 μm.

In the p-side electrode 12 of the second form, the third barrier layer 25 provided in the first electrode layer 30 serves as a barrier, and the first Ga element and As element in the p-type GaAs contact layer 11 in the heat treatment step. The diffusion to the surface layer of the electrode layer 30 is prevented. Therefore, the etching process for removing Ga oxide and As oxide, which has been performed after the heat treatment process at the time of forming the p-side electrode 12, becomes unnecessary, and the production efficiency of the semiconductor element can be improved. Furthermore, the use of a material such as SiO ₂ (silicon dioxide) or SiN (silicon nitride) that can be dissolved in the halogen-based acid used in the etching process because the etching process becomes unnecessary is used for the semiconductor portion 46. It becomes possible, and the restriction | limiting on the design in a semiconductor element can be eased.

  The third barrier layer 25 formed on the first electrode layer 30 in the second form is subjected to a heat treatment for imparting ohmic characteristics, and stress is generated due to the rearrangement of atoms. Since the layer thickness is as thin as 150 nm or less, a large stress that adversely affects the semiconductor element characteristics and the like does not occur.

  Further, as described above, since the second electrode layer 36 is not subjected to heat treatment, no stress is generated due to the rearrangement of atoms. Therefore, layers other than the barrier layer constituting the second electrode layer 36 can be formed relatively thick. For this reason, in the second electrode layer 36 shown in the second embodiment, the connection layer 24 is formed as thick as 1 μm. Thus, by forming a thick layer using Au or In, which is a soft metal with low hardness, in this second electrode layer 36, this layer (connection layer 24 in Example 2) is connected to the p-side electrode 12 after bonding. The stress caused by the difference in thermal expansion coefficient with the solder material 38 can also be relieved.

  In Example 2, as in Example 1, when joining with the solder material 38, the intermediate layer 27 disappears due to solid phase diffusion, and the first barrier layer 26 and the second barrier layer 28 are adjacent and thick. It functions as a single barrier layer 23 and exhibits a high diffusion preventing effect.

  Next, as Example 3, a partially enlarged view of the third form of the p-side electrode 12 in the semiconductor laser 50 is shown in FIG. Since the semiconductor portion 46 of the semiconductor laser 50 is exactly the same as that of the first embodiment, description and explanation are omitted.

  In the p-side electrode 12 of the third embodiment shown in FIG. 6, the first electrode layer 30 constituting the p-side electrode 12 is made of an ohmic contact layer 20 made of Ti having a thickness of 50 nm and Pt having a thickness of 100 nm. The first barrier layer 26 and the second metal layer 22a made of Au having a thickness of 50 nm are configured. The second electrode layer 36 includes a connection layer 24 made of Au having a thickness of 50 nm, a second barrier layer 28 made of Pt having a thickness of 100 nm, and a surface layer electrode 29 made of Au having a thickness of 50 nm. . In the third embodiment, the second metal layer 22a and the connection layer 24 have the same function as the intermediate layer 27.

  In the p-side electrode 12 of the third form, the first electrode layer 30 has a structure having ohmic characteristics with the semiconductor portion 46 and a barrier property against Sn. In this electrode structure, it is not necessary to perform heat treatment in order to obtain ohmic characteristics. Further, when heat treatment is performed, the first barrier layer 26 also has a function of the third barrier layer 25 in the second embodiment. That is, the first barrier layer 26 of the first electrode layer 30 prevents the diffusion of Ga element and As element in the heat treatment process, and at the time of joining with the solder material 38, an intermediate layer composed of the second metal layer 22a and the connection layer 24. 27 disappears and becomes a thick barrier layer 23 adjacent to the second barrier layer 28. According to this configuration, the number of layers of the p-side electrode 12 can be reduced, and an etching process is not necessary, as in the case of the p-side electrode 12 of the second embodiment, so that the production efficiency of the semiconductor element can be further improved.

  From the above, the electrode 44 formed on the semiconductor element 51 is divided into the first electrode layer 30 that imparts ohmic characteristics by heat treatment and the second electrode layer 36 that does not undergo heat treatment, and a barrier that generates particularly large stress. By forming the layer on the second electrode layer 36, the stress generated in the electrode 44 during the heat treatment can be reduced.

  Further, the electrode 44 is thinned by dividing the barrier layer into the first barrier layer 26 and the second barrier layer 28, thereby reducing the stress generated in the first barrier layer 26 and the second barrier layer 28 and solder bonding. Sometimes, the intermediate layer 27 provided between the first barrier layer 26 and the second barrier layer 28 is diffused and disappeared to function as a thick single barrier layer 23, thereby obtaining a high diffusion preventing effect. .

  For these reasons, according to the method for manufacturing a semiconductor element of the present invention, it is possible to form the semiconductor element 51 having the electrode 44 having a low diffusion stress and a high diffusion preventing effect. Therefore, the semiconductor element 51 manufactured by the method for manufacturing a semiconductor element of the present invention is free from warping and cracking of the semiconductor portion 46, has good element characteristics and reliability, and is high when bonded by the solder material 38. Exhibits diffusion prevention effect.

  In addition to the semiconductor laser 50, the semiconductor element 51 of the present invention includes a high frequency diode, a light emitting diode, a light emitting diode array, a semiconductor laser array, a light receiving element, an integrated element (OEIC) having a light emitting / receiving element, a field effect. The present invention can be applied to a semiconductor element that requires an electrode having a barrier layer in addition to a type transistor, a high frequency integrated circuit, and the like. The electrode 44 of the present invention is not limited to the p-side electrode, and can be applied to an n-side electrode or an electrode having other barrier layers. Furthermore, the layer thickness, layer structure, material, and the like of each layer constituting the electrode 44 of the present invention can be changed and implemented without departing from the gist of the present invention.

1 is a schematic cross-sectional view of a semiconductor element according to the present invention. It is a schematic cross section at the time of applying the semiconductor element concerning this invention to a semiconductor laser. It is the elements on larger scale of the 1st form of the electrode in the semiconductor element which concerns on this invention. It is a figure explaining the behavior at the time of joining of the semiconductor element concerning the present invention. It is the elements on larger scale of the 2nd form of the electrode in the semiconductor element which concerns on this invention. It is the elements on larger scale of the 3rd form of the electrode in the semiconductor element which concerns on this invention.

Explanation of symbols

12 p-side electrode
26 First barrier layer
27 Middle layer
28 Second barrier layer
30 First electrode layer
36 Second electrode layer
44 electrodes
46 Semiconductor Department
50 Semiconductor laser
51 Semiconductor device

Claims (3)

In a semiconductor device provided with an electrode,
The electrode has a stacked structure in which a first barrier layer, an intermediate layer, and a second barrier layer are sequentially stacked. In a semiconductor element in which an electrode is provided on a semiconductor part,
The electrode is in contact with the semiconductor portion and has a first electrode layer having adhesiveness with the semiconductor portion; a first barrier layer provided on the first electrode layer; an intermediate layer; and a second layer And a second electrode layer having a stacked structure in which barrier layers are sequentially stacked. In a method for manufacturing a semiconductor element,
A first electrode layer forming step of forming a first electrode layer on the semiconductor portion;
A heat treatment step for heating the semiconductor portion and the first electrode layer after the first electrode layer forming step;
A second electrode that forms a second electrode layer having a stacked structure in which a first barrier layer, an intermediate layer, and a second barrier layer are sequentially stacked on the first electrode layer after the heat treatment step. A layer forming step;
A method for manufacturing a semiconductor device, comprising:

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