JP2002110936A - Dielectric gate transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a structure of improving the holding time of written information at a low cost, in a ferrodielectric gate transistor. SOLUTION: In an MFMIS ferrodielectric gate transistor, a structure is realized in which at least two ferrodielectric capacitors are connected in series. Further, these two ferrodielectric capacitors connected in series are formed to be flush with each other, to suppress the cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a ferroelectric gate transistor which switches on / off of a transistor depending on the polarization state of a ferroelectric thin film, and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the advance of multimedia, the increase in capacity of semiconductor memories capable of handling large-capacity digital information at high speed is being accelerated. At the same time, with the increase in demand for portable products, “non-volatility” in which the memory is retained even after the power is turned off is regarded as more important than ever.

Under such a background, a ferroelectric gate transistor is a device expected to be a non-volatile memory having an extremely small area per bit and a high writing speed which is incomparably higher than that of a flash memory. .

In particular, a field effect transistor (hereinafter referred to as MI)
An MFMIS type ferroelectric gate transistor in which a ferroelectric capacitor (hereinafter referred to as an MFM part) is directly formed on the S part) has a great merit in that a conventional field-effect transistor can be used as it is.

However, as one of the problems in realizing this MFMIS ferroelectric gate memory (hereinafter abbreviated as MFMIS), there is a problem of voltage distribution due to a capacitance difference between the MFM section and the MIS section. That is, in general, the ferroelectric substance has a large effective relative dielectric constant, so that the capacitance of the MFM section is large. Even if a voltage is applied between the upper electrode of the MFM section and the semiconductor substrate of the MIS section, the voltage distribution to the MFM section is not increased. Smaller,
Sufficient polarization inversion for writing information cannot be obtained.

To solve such a problem, for example, Japanese Patent Laid-Open No.
As described in Japanese Patent Application Laid-Open No. 0-284624 (“Ferroelectric transistor and method of manufacturing the same”), one method for improving the voltage distribution by reducing the area of the capacitor in the MFM section relative to the MIS section is one. It has been proposed as a solution.

FIG. 20 is a cross-sectional view showing a memory cell configuration of a prior art example.

In FIG. 20, a MIS portion includes a substrate 112 and a diffusion region 134, a gate oxide film 118 and a gate electrode 12
0. On the other hand, the MFM part is the gate electrode 12.
0, a ferroelectric layer 122, and an upper electrode 124. The ferroelectric transistor of the configuration example shown in FIG. 20 has a basic structure in which a ferroelectric capacitor is sequentially stacked on a gate electrode of a so-called MOS transistor.
It has the configuration of an FMIS ferroelectric gate transistor.

In the prior art ferroelectric gate transistor, the area of the ferroelectric film 122 at the junction 144 with the gate electrode 120 is compared with the area of the ferroelectric film 122 at the junction 146 with the upper electrode 124. It is small. Since the ferroelectric film 122 is formed as described above, the capacitance of the ferroelectric film 122 can be reduced, and as a result, the distribution voltage to the MFM section can be improved.

[0010]

However, the above-mentioned prior art ferroelectric gate transistor has a MIS portion capacitance and MF.
Regarding changing the ratio of the capacitance of the M part, the MIS part / M
Only changing the area ratio of the FM section is considered, and in actual device fabrication, there is a problem that the fabrication is difficult and the cost increases.

In the prior art, attention is paid only to voltage distribution as an operation of a ferroelectric gate transistor. For example, a device structure from a comprehensive viewpoint such as conditions necessary for long-term memory retention is examined. Had not been.

[0012]

In order to solve the above-mentioned problems, a ferroelectric gate transistor according to the first invention of the present application comprises:
In a ferroelectric gate transistor in which a ferroelectric capacitor is connected to a gate electrode of a field effect transistor,
The ferroelectric capacitor has a structure in which at least two or more ferroelectric capacitors are connected in series.

A ferroelectric gate transistor according to a second aspect of the present invention has a structure in which a ferroelectric capacitor has two ferroelectric capacitors connected in series, and one of the ferroelectric capacitors has a first electrode. And the second electrode sandwiches the ferroelectric layer. The other ferroelectric capacitor has a structure sandwiching the ferroelectric layer between a second electrode and a third electrode. The first electrode and the third electrode are formed on the same interlayer insulating film.

Further, in the ferroelectric gate transistor according to the third invention of the present application, the potential stored as nonvolatile information in the gate electrode is VFG [V], the number of ferroelectric capacitors connected in series is n, The coercive electric field of the layer material is expressed as Ec [V /
m], the thickness tF [m] of the ferroelectric layer is tF ≧
It is characterized in that the film thickness satisfies VFG / (0.5 · n · Ec).

The ferroelectric gate transistor according to a fourth aspect of the present invention is such that at least a part of the gate electrode of the field effect transistor functions as the first electrode of the ferroelectric gate transistor according to the second aspect. It is.

Further, in the ferroelectric gate transistor according to the fifth aspect of the present invention, the first electrode and the third electrode have a parallel portion at least a part of which is arranged in parallel in a plane, and Electrodes are arranged so as to overlap these parallel portions, and are perpendicular to the longitudinal direction of the parallel portions.

[0017]

(Embodiment 1) Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a top view of a ferroelectric gate transistor according to an embodiment of the present invention. 2 and 3 are cross-sectional views respectively showing the AA 'section and the BB' section of FIG. 1, 2 and 3, the same items are denoted by the same reference numerals.

In FIG. 1, hatching is omitted for easy viewing. In addition, only the uppermost component is shown by a solid line. 2 and FIG. 3 are also partially omitted for easy viewing. Also, in FIGS. 2 and 3, some components that are deeper than the plane of the paper are omitted for easy viewing.

1, 2 and 3, reference numeral 1 denotes a substrate, for example, a P-type Si substrate. 3a and 3b are diffusion regions, and in this embodiment, 3a is a drain region and 3b is a source region. 5 is an element isolation oxide film. Reference numeral 7 denotes a gate insulating layer, which is 5 nm thick in this embodiment.
Consists of O ₂ . Reference numeral 9 denotes a gate electrode, which is made of polycrystalline silicon doped with phosphorus in this embodiment. 11 is the first
Is an interlayer insulating film of, for example, S formed by LPCVD.
consisting of iO _2. 13a, 13b and 13c are plug wirings. 14 is a first electrode. 15a and 15b are pad portions. The first electrode 14 is connected to the gate electrode 9 by a plug 13a. The pad portions 15a and 15b are connected to the drain region 3a and the source region 3b by plugs 13b and 13c, respectively. 16 is a third electrode. As will be described later, the first electrode 14 and the third electrode 1
6 are formed simultaneously. Reference numeral 17 denotes a ferroelectric layer. In this embodiment, a bismuth titanate (hereinafter referred to as B) having a thickness of 400 nm is used.
IT). Reference numeral 19 denotes a second electrode, which is Pt in this embodiment. Reference numeral 21 denotes a second interlayer insulating film made of, for example, silicon oxide formed at a low temperature by TEOS. 25a, b and c are wirings.

Next, a method of manufacturing the ferroelectric gate transistor according to the present embodiment having the above-described structure will be described below with reference to FIGS. FIG. 4 is a top view of a manufacturing process corresponding to FIG. 1, and FIG. 5 is a diagram showing a manufacturing process in a BB ′ section corresponding to FIG. 4 and 5, the same components as those in FIGS. 1, 2, and 3 are denoted by the same reference numerals, and description thereof will be omitted. In FIGS. 4 and 5, (a) to (f) showing each stage of the process show the same state.

(A) Substrate 1 made of, for example, a P-type Si substrate
Then, an oxidation process is performed by LOCOS using silicon nitride (not shown) as a mask to form an element isolation film 5. Thereafter, silicon nitride (not shown) is dissolved by, for example, heated phosphoric acid. Thereafter, for example, silicon oxide having a thickness of 5 nm is formed by pyro-oxidation at 900 ° C. for 5 minutes to form the gate insulating film 7. Thereafter, for example, phosphorus-doped polycrystalline silicon is deposited by LPCVD to form the gate electrode 9. The gate electrode 9 and the gate insulating film 7 are patterned by, for example, dry etching, and thereafter, for example, boron is implanted by using the gate electrode 9 as a mask, and then subjected to a heat treatment at, for example, 900 ° C. for 30 minutes, so that the drain region 3 a The region 3b is formed.
Next, a first interlayer insulating film 11 is formed by depositing SiO ₂ by, for example, the LPCVD method. A contact window is formed by forming a resist mask pattern on the interlayer insulating film 11 and performing dry etching.
The first plug wirings 13a, 13b and 13c are formed by depositing polycrystalline silicon by the D method and flattening the same by, for example, the CMP method. Next, after depositing 20 nm of titanium nitride by, for example, a sputtering method, depositing 50 nm of Pt by, for example, a sputtering method, and patterning, for example, Ar milling of Pt / TiN with, for example, a hard mask obtained by patterning SiO ₂ formed by sputtering. And the first electrode 14
And the pad portions 15a and 15b and the third electrode 16 are simultaneously formed.

(B) A substrate temperature of 5
BIT is deposited to a thickness of 400 nm under the conditions of 50 ° C., an oxygen partial pressure of 20%, and an RF power of 100 W to form a ferroelectric thin film 17.

(C) Pt is deposited by, for example, a sputtering method and patterned by Ar milling using a hard mask such as SiO ₂ to form a second electrode 19.

(D) Plasma CV using TEOS, for example
D, after depositing a silicon oxide film, for example, CMP
The second interlayer insulating film 21 is formed by flattening by a method.

(E) The second interlayer insulating film 21 is dry-etched to form contact windows 22a, b, c.

(F) AlSiC, for example, by sputtering
The wirings 25a, 25b and 25c are formed by depositing a u alloy and performing dry etching using a resist mask.

FIG. 6 is a top view of the MIS part (a) and the MFM part (b) of the ferroelectric gate transistor according to the embodiment of the present invention. In FIG. 6A, reference numeral 51 denotes a gate region. L and W in FIG. 6A indicate a gate length and a gate width, respectively. A and b in FIG. 6B are the width and length of the first electrode;
c is the overlap length of the second electrode 19 and the third electrode 16, d
Indicates the width of the third electrode 16. FIG. 6 (b)
In FIG. 1, the ferroelectric layer 17 is omitted, but in the present embodiment, the thickness of the ferroelectric layer 17 is 400 nm. What determines the capacitance of the MIS section is mainly the area determined by the product of L and W. In this embodiment, L = 0.2 μm, W =
It is 1 μm. On the other hand, in the MFM section, a ferroelectric capacitor having an area calculated by the product of a and b and a ferroelectric capacitor having an area calculated by the product of c and d are connected in series. In the present embodiment, “a ×
b = c × d ”, that is, the area of each ferroelectric capacitor is made equal.

As a result, the ferroelectric capacitor of this embodiment is a capacitor having an area of a × b and a film thickness of 800 nm which is twice as large.
And a capacitor having characteristics equivalent to those of the ferroelectric capacitor.

In the following text, "MIS area"
/ MFM area = (L × W) / (a × b)) is simply described as “area ratio” or “AR (Area Ratio)”.

The operation of the ferroelectric gate transistor having the structure manufactured by the above manufacturing method will be described below.

FIG. 7 shows the ferroelectric characteristics of the MFM portion of the ferroelectric gate transistor of this embodiment. According to the history of the voltage applied between the first electrode and the third electrode,
The polarization value indicates hysteresis.

FIG. 8 is a diagram showing the operation principle of the MFMIS type ferroelectric gate transistor. In FIG. 8, the ferroelectric capacitors connected in series are shown as one ferroelectric capacitor as being electrically equivalent. In FIG. 8, reference numeral 61 denotes a substrate. 62a and 62b are a source region and a drain region, respectively. 63 is a gate insulating film.
64 is a gate electrode. 65 is a ferroelectric layer.

Reference numeral 66 denotes an upper electrode. It should be noted that the gate electrode 64 in FIG. 8 is the same as the gate electrode 9 in FIGS.
The upper electrode 66 in FIG. 8 corresponds to the third electrode 16 in FIG. 1, FIG. 2, and FIG.

FIG. 8A shows a state where a positive voltage is applied to the upper electrode 66 and the upper electrode 66 is unloaded. At this time, the potential + VFG remains in the gate electrode 64 due to the residual polarization of the ferroelectric. An electric field is generated by this residual potential, and the field effect transistor is in a low resistance state even when the upper electrode is returned to 0 [V]. When a voltage is applied between the source 62a and the drain 62b, the drain current Id is detected. The state is hereinafter referred to as an On state).

On the other hand, FIG. 8B shows a state in which a negative voltage is applied to the upper electrode and the load is unloaded. In this case, the negative potential of -VFG remains on the gate electrode 64. .
Due to this residual potential, even if the upper electrode is returned to 0 [V], the field-effect transistor becomes in a high resistance state,
Even if a voltage is applied between the drains, the drain current Id becomes an extremely small value (this state is hereinafter referred to as an Off state).

When the voltage applied to the upper electrode 66 is swept based on such a principle, the drain current Id draws a counterclockwise hysteresis as shown in FIG. For example, by detecting Id with the potential of the upper electrode 66 being 0 [V], it is possible to read the written information of “1” and “0”.

However, in order to stabilize such an operation, it is necessary to increase the voltage distribution to the MFM unit. This is because the capacitance of the MFM section is larger than that of the MIS section due to the fact that the effective relative permittivity of the ferroelectric substance is very large, so that a large amount of voltage is distributed to the MIS section. is there.

FIG. 10 shows the MFMIS type ferroelectric gate transistor in which the thickness of the ferroelectric material is changed in the case of AR = 2, 4 when the gate insulating layer 7 is applied when 10 [V] is applied to the upper electrode. 5 shows the electric field intensity applied to. From FIG. 10, it is understood that the electric field strength of the gate insulating layer is greatly reduced by increasing the AR. It uses a SiO ₂ gate insulating layer in this embodiment, SiO ₂
Is about 8 MV / cm, an excessive electric field is applied to the gate insulating film when AR = 1 in the configuration of the present embodiment, so that proper operation cannot be obtained.

FIG. 11 shows the ON state shown in FIG.
In the state, that is, when the voltage is returned to 0 [V] after applying 10 [V] to the upper electrode, the drain current Id when 1 V is applied between the source and the drain is shown. As can be seen from this figure, as the AR is increased, Id is significantly increased.
It is understood that the operation characteristics of the FMIS are improved.

However, the present inventors have determined that the area ratio AR
It has been found that there is a limit to improving the operating characteristics of a ferroelectric gate transistor by simply changing the value of.

FIG. 12 shows a state where the ferroelectric gate transistor corresponding to the state of FIG. When holding written information, the upper electrode needs to be defined at a certain potential. For example, in the present embodiment, information is held by grounding. At this time, since the floating electrode has a potential of + VFG, an electric field (hereinafter, referred to as a depolarization electric field) in the direction of canceling the polarization of the ferroelectric shown in FIG. 12 is generated in the ferroelectric layer. Since this depolarizing electric field is generated in a direction in which the polarization of the ferroelectric layer is deteriorated (reversed), if the depolarizing electric field is large,
There is a fatal problem that the stored information cannot be stored for a long time, that is, the retention characteristics deteriorate.

FIG. 13 shows the respective depolarization electric field intensities for the MFMIS type ferroelectric gate transistor in which the thickness of the ferroelectric is changed when AR = 2 and 4. Although the BIT is used as the ferroelectric layer material of the present embodiment, the coercive electric field of this material is about 50 [kV / cm]. Generally, the polarization of a ferroelectric material is positively inverted when an electric field higher than the coercive electric field is applied. Therefore, it is desirable that the depolarizing electric field is sufficiently small with respect to the coercive electric field.

As a result of the analysis of the retention characteristics by the present inventors, remarkable deterioration of the retention characteristics was observed when at least the depolarizing electric field exceeded 50% of the coercive electric field. In order to maintain the memory for several days, it is desirable that the depolarizing electric field is at least 30% or less of the coercive electric field.

However, FIG. 13 shows that increasing AR increases the depolarizing electric field. However, the present inventors have found that increasing the ferroelectric film thickness significantly improves the depolarization electric field. Such suppression of the depolarizing electric field was particularly effective when the ferroelectric film thickness was 400 nm or more.

It has also been found that a ferroelectric gate transistor having extremely good memory retention characteristics can be realized particularly when the ferroelectric film thickness is 800 nm.

However, in view of the current semiconductor process, as the ferroelectric film thickness increases, the process cost for forming the film becomes extremely high. The thicker the film thickness, the more unsuitable for fine processing. For example, the formation of the contact windows 22a, b, and c shown in FIG. Further, considering the flow of the semiconductor manufacturing process in the future, for example, the direction in which an interlayer insulating film or the like is aimed at thinning by introducing a low dielectric constant material or the like will go against the direction of aiming at thinning. Furthermore, due to the steps that occur when patterning a thick ferroelectric layer,
There is a fear that the conduction of the wiring formed thereabove is hindered. Such a step is still avoided by forming a thick interlayer insulating film and flattening it by CMP or the like. However, when the ferroelectric layer is extremely thick, an interlayer insulating film having a thickness larger than that is used. Is required, and the aspect ratio of the contact window becomes larger, which makes the fabrication very difficult. For example, when the thickness of the ferroelectric film is 800 nm, the thickness of the interlayer insulating film becomes greater than that of the ferroelectric film. The size of the contact window is, for example, 0.2 μm
Even in this case, the aspect ratio becomes 10 or more, which makes the production extremely difficult.

Therefore, since the ferroelectric gate transistor of this embodiment has a structure in which the MFM portions are connected in series, the object is to set the ferroelectric formed film thickness in the process to be small. That is, when the target ferroelectric film thickness is t, the actual ferroelectric film thickness tF is calculated by the following equation when the number of ferroelectric capacitors connected in series is n. An equivalent operation can be obtained with the film thickness.

TF = t / n Therefore, for example, when n = 2, the film thickness is reduced by half to 400 m.
The same effect can be obtained with n. For this reason, the process cost for film formation can be suppressed. It is also advantageous for processing contact windows.

In summary, the potential stored as nonvolatile information in the gate electrode is VFG [V], the number of ferroelectric capacitors connected in series is n, and the coercive electric field of the material of the ferroelectric layer is Ec [V / m], the thickness tF [m] of the ferroelectric layer
However, by setting the film thickness to satisfy tF ≧ (VFG) / (0.5 · n · Ec), it was possible to realize the memory retention of the ferroelectric gate transistor. Further, by setting tF ≧ (VFG) / (0.3 · n · Ec), memory retention for several days was realized.

The drain current Id from which information is to be detected is determined from the viewpoint of actual sensing sensitivity.
Some value is needed. FIG. 14 shows the ratio of Id at the time of the positive potential VFG stored in the gate electrode as nonvolatile information at the time of On to Id at the time of the negative potential −VFG stored at the time of Off. As a result of this examination, such a change in Id is defined as On
When Id changed by a factor of 100 at the / Off ratio, stable detection was possible as a change in Id. That is, it is necessary to set the balance between the capacities of the MIS section and the MFM section so that VFG becomes 0.12 [V] or more. In the present embodiment, the value of VFG is set to about 1V. Therefore, a high On / Off ratio is obtained as shown in FIG. This is because the on-state resistance of the ferroelectric gate transistor of the present embodiment is reduced in order to realize a high-speed operation.

When the ferroelectric capacitors are connected in series, there is a concern that the area occupied by one ferroelectric gate transistor will increase. However, as can be understood from the effective area ratio data described above. , MFM area is MIS
Since the area is a fraction of the area of the part, the area occupied by the field-effect transistor becomes smaller even when connected in series. That is, the ferroelectric gate transistor of this embodiment is not disadvantageous in area as compared with the conventional ferroelectric gate transistor. In particular, by arranging capacitors in the gate width direction (x direction in FIG. 1) of the field effect transistor,
No area penalty occurred in the cell occupied area.

As described above, the ferroelectric gate transistor of this embodiment has a structure in which the MFM portions are connected in series in the MFMIS type ferroelectric gate transistor, and the ferroelectric layers of the ferroelectric capacitors connected in series are the same layer. By forming these in the same plane, it is possible to obtain characteristics equivalent to an MFMIS type ferroelectric gate transistor having a thick ferroelectric layer without increasing the number of steps in the manufacturing process. Since such a ferroelectric gate transistor can suppress the depolarization electric field to a small level, it can hold written information for a long period of time, and can be used as a non-volatile semiconductor memory or a non-volatile switch for an FPGA (Field Program).
The application to a wide range of applications, such as application to a movable gate array (MAT) device and a reconfigurable logic device, is wide and greatly contributes to the semiconductor industry.

In this embodiment, bismuth titanate has been described as a ferroelectric material. However, the present invention is not limited by ferroelectric materials. For example, strontium bismuth tantalate or zircon titanate may be used. Similar effects can be obtained with ferroelectric materials such as lead oxide, lead titanate and lanthanum.

Similarly, the field effect transistor has been described as a MOS transistor having a gate insulating film of SiO ₂ , but the gate insulating film may be made of another dielectric material.

In this embodiment, the so-called N
Although the case of the channel type transistor has been described, it goes without saying that the present invention is similarly effective in the case of a P-channel type transistor.

In the first embodiment, a ferroelectric gate transistor having two ferroelectric capacitors having the same area has been described. However, almost the same effect can be obtained even when these areas are not equal. Is self-evident. However, if ferroelectric capacitors having different capacities are connected in series, the voltage distributed to each of them changes, and for example, variations occur in the breakdown voltage and polarization state. It was desirable that the area of the body capacitors be equal.

In the first embodiment, the structure in which two ferroelectric capacitors are particularly connected has been described. However, it goes without saying that the same effect can be obtained when three or more ferroelectric capacitors are used.

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 15 is a top view (a) of the ferroelectric gate transistor according to the second embodiment and a sectional view (b) taken along the line CC ′. 15, the same elements as those in FIGS. 1, 2, and 3 are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 15, reference numeral 71 denotes a gate electrode.
In the second embodiment, the gate electrode 71 has the function of combining the gate electrode 9, the plug wiring 13a, and the first electrode 14 in FIG. 3 of the first embodiment. 72 is a wiring.
The wiring 72 has the same function as the third electrode 16 and the wiring 25a in FIG. 3 of the first embodiment. The wiring 72 is connected to, for example, a word line (not shown). 73 is a ferroelectric layer. 74 is an intermediate electrode. The intermediate electrode 74 has a function equivalent to that of the second electrode 19 in FIG.

The ferroelectric gate transistor according to the second embodiment has a structure in which the gate electrode of the field effect transistor is extended on the element isolation film 5. The overlapping portion of the extended gate electrode and the intermediate electrode 74 as viewed from the upper surface functions as a first ferroelectric capacitor, and the overlapping portion of the intermediate electrode 74 and the wiring 72 also functions as a second ferroelectric capacitor. .

The second embodiment is characterized in that there is no wiring connected to the gate electrode 71 and no contact window therefor. In general, the area occupied by the contact window in an LSI is relatively large. This is to add a deviation margin for mask alignment to the minimum processing size. However, the ferroelectric gate transistor according to the second embodiment has a structure in which there is no contact window to the gate electrode 9, so that the area occupied by the cell of the transistor can be further reduced. A ferroelectric gate transistor memory device can be realized.

Next, a manufacturing process of the ferroelectric gate transistor according to the second embodiment will be described with reference to FIG. In FIG. 16, the same components as those in FIG. 15 are denoted by the same reference numerals, and description thereof will be omitted.

(A) The device isolation film 5 and the gate insulating film 7 are formed by the same manufacturing method as in the first embodiment.

(B) Phosphorus-doped polycrystalline silicon is deposited, for example, by LPCVD, then titanium nitride is deposited to a thickness of 20 nm, for example, by sputtering, and then Pt is deposited to a thickness of 50 nm, for example, by sputtering. The gate electrode 71 and the wiring 72 are formed by patterning Pt / TiN / polycrystalline silicon by, for example, an Ar milling method using a hard mask formed by patterning SiO ₂ by sputtering. Thereafter, a Si (not shown)
Using an O ₂ hard mask as an implantation mask, for example, boron is implanted, and then a heat treatment is performed at, for example, 900 ° C. for 30 minutes to activate a source / drain region (not shown). Finally, the SiO ₂ hard mask (not shown) is removed by, for example, buffered hydrofluoric acid.

(C) The substrate temperature 5
BIT is deposited to a thickness of 400 nm under the conditions of 50 ° C., an oxygen partial pressure of 20%, and an RF power of 100 W to form a ferroelectric thin film 73.

(D) Pt is deposited by, for example, a sputtering method, and is patterned by Ar milling using a hard mask such as SiO ₂ to form an intermediate electrode 74.
At this time, wiring to a source region and a drain region (not shown) is also formed at the same time.

After this, there is a formation of a protective layer and the like, but the following is omitted.

In the ferroelectric gate transistor manufactured in this manner, in addition to the advantage of the reduction of the cell area described above, as understood from the description of the manufacturing method, the number of wiring layers is made smaller than in the first embodiment. It is possible to reduce the number of “two layers”. For this reason, suppression of the process cost is realized.

As described above, the ferroelectric gate transistor of the second embodiment has a very high integration and further reduces the process cost, and has the same function as the ferroelectric gate transistor of the first embodiment. To provide.

(Embodiment 3) In Embodiments 1 and 2, both the second electrode 19 in FIG. 3 and the intermediate electrode 74 in FIG. 15 are arranged above the ferroelectric film. The ferroelectric gate transistor according to the third embodiment has a structure in which these are reversed.

Embodiment 3 is a ferroelectric gate transistor having the same function as the ferroelectric gate transistor of Embodiment 2, and provides a different structure.

FIG. 17 is a top view (a) and a DD ′ cross-sectional view (b) of the ferroelectric gate transistor according to the third embodiment.
In FIG. 17, the same components as those in FIG. 15 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 17, reference numeral 81 denotes a gate electrode.
A wiring 82 is connected to, for example, a word line (not shown). 83 is a ferroelectric layer. 84 is an intermediate electrode. 88 is a first electrode.

As can be understood from FIG. 17B, the ferroelectric gate transistor according to the third embodiment differs from the ferroelectric gate transistor in that two ferroelectric capacitors are connected in series to the gate electrode of the field effect transistor. Embodiment 1, Embodiment 2
Has the same function as the ferroelectric gate transistor, but has a different structure. That is, the intermediate electrode 84 is formed on the element isolation film 5, the ferroelectric layer 83 is formed thereon, and the wiring 82 and the first electrode 88 are further formed thereon.

Hereinafter, a method of manufacturing the ferroelectric gate transistor according to the third embodiment will be described with reference to FIG. In FIG. 18, the same components as those in FIG. 17 are denoted by the same reference numerals, and description thereof will be omitted.

(A) The device isolation film 5 and the gate insulating film 7 are formed by the same manufacturing method as in the second embodiment.

(B) Phosphorus-doped polycrystalline silicon is deposited by, eg, LPCVD, and then titanium nitride is deposited to a thickness of 20 nm by, eg, sputtering, and then Pt is deposited to a thickness of 50 nm, eg, by sputtering. The gate electrode 81 and the intermediate electrode 84 are formed by patterning Pt / TiN / polycrystalline silicon by, for example, an Ar milling method using a hard mask (not shown) formed by sputtering and patterning SiO ₂ . Thereafter, a not-shown SiO ₂ hard mask is further implanted as, for example, boron as an implantation mask.
By performing a heat treatment at 00 ° C. for 30 minutes, a source / drain region (not shown) is activated. Finally, the SiO ₂ hard mask (not shown) is removed by, for example, buffered hydrofluoric acid.

(C) A substrate temperature of 5
BIT is deposited to a thickness of 400 nm under the conditions of 50 ° C., an oxygen partial pressure of 20%, and an RF power of 100 W to form a ferroelectric thin film 73, which is patterned by, for example, Ar milling.

(D) AlSiC, for example, by sputtering
A u-alloy is deposited and dry-etched with, for example, a chlorine-based gas, and is patterned to form a first electrode 88 and a wiring 82. At this time,
Wirings to a source region and a drain region (not shown) are also formed at the same time.

Further, after this, steps such as formation of a protective layer continue, but the following is omitted.

The ferroelectric gate transistor according to the third embodiment manufactured as described above has an advantage that it is easy to connect to a word line or the like since the wiring 82 is on the upper layer side.

(Embodiment 4) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 19 is a top view of the ferroelectric gate transistor according to the fourth embodiment. Note that FIG.
The same components as those described above are denoted by the same reference numerals and description thereof is omitted.

In FIG. 19, reference numeral 91 denotes a gate electrode.
For example, it is connected to a word line (not shown). 94
Is an intermediate electrode. In the drawing, w1 indicates the width of the wiring 72, and w2 indicates the width of a portion of the gate electrode 91 parallel to the wiring 72. Further, δ indicates a shift amount when performing alignment with a stepper or the like.

The ferroelectric gate transistor of the fourth embodiment is different from the ferroelectric gate transistor of the second embodiment in the configuration of the series ferroelectric capacitor. Therefore, the features of the ferroelectric gate transistor will be mainly described below.

As shown in FIG. 19, the gate electrode 91 of the ferroelectric gate transistor according to the fourth embodiment is
Is provided in parallel with. At this time, w1 and w2
Are manufactured to be equal in the fourth embodiment. The effect of such a layout will be described below.

In the present embodiment, the size and position of the intermediate electrode 94 are determined to include the misalignment amount δ as shown in FIG. Therefore, even if the intermediate electrode 94 is displaced, the area of the overlapping portion between the gate electrode 91 and the intermediate electrode 94 does not change. Similarly, the area of the overlapping portion between the intermediate electrode 94 and the wiring 72 does not change. Therefore, even if a deviation occurs during mask alignment, two ferroelectric capacitors having the same capacitance can be formed stably.

In the fourth embodiment, the gate electrode 91
Is bent in the middle, but the layout of other wirings may be changed so that this becomes a straight line.

[Brief description of the drawings]

FIG. 1 is a top view of a ferroelectric gate transistor according to a first embodiment of the present invention.

FIG. 2 is an AA ′ cross-sectional view of the ferroelectric gate transistor according to the first embodiment.

FIG. 3 is a cross-sectional view of the ferroelectric gate transistor according to the first embodiment, taken along line BB ';

FIG. 4 is an explanatory view (top view) of a method for manufacturing the ferroelectric gate transistor according to the first embodiment.

FIG. 5 is an explanatory diagram of a method of manufacturing the ferroelectric gate transistor according to the first embodiment (cross-sectional view taken along line BB ′).

FIG. 6 is a top view of the ferroelectric gate transistor according to the first embodiment.

FIG. 7 is an explanatory diagram of ferroelectric characteristics of an MFM portion of the ferroelectric gate transistor according to the first embodiment.

FIG. 8 is a diagram illustrating the operation principle of the ferroelectric gate transistor according to the first embodiment.

FIG. 9 is an operation explanatory diagram in the first embodiment.

FIG. 10 is an explanatory view of an electric field intensity applied to a gate insulating layer in the first embodiment.

FIG. 11 is an explanatory diagram of a drain current according to the first embodiment.

FIG. 12 is a diagram illustrating the principle of generating a depolarized electric field in the first embodiment.

FIG. 13 is an explanatory view of a depolarization electric field in the first embodiment.

FIG. 14 shows the drain current On in the first embodiment.
/ Off ratio illustration

FIG. 15 is a diagram showing a ferroelectric gate transistor according to a second embodiment of the present invention;

FIG. 16 is a view illustrating a method of manufacturing the ferroelectric gate transistor according to the second embodiment.

FIG. 17 is a diagram showing a ferroelectric gate transistor according to a third embodiment of the present invention.

FIG. 18 is a view illustrating a method of manufacturing the ferroelectric gate transistor according to the third embodiment.

FIG. 19 is a top view of a ferroelectric gate transistor according to a fourth embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a configuration of a ferroelectric gate transistor according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 3a, 3b Diffusion area 5 Element isolation oxide film 7 Gate insulating layer 9 Gate electrode 11 First interlayer insulating film 13a, 13b, 13c Plug wiring 14 First electrode 15a, 15b Pad portion 16 Third electrode 17 Strong Dielectric layer 19 Second electrode 21 Second interlayer insulating film 25a, b, c Wiring

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyoyuki Morita 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5F001 AA17 AD12 5F083 FR07 JA14 JA15 JA17 JA36 JA38 JA40 MA06 MA19 NA08 PR22 PR33 PR40 5F101 BA62 BD02

Claims (13)

[Claims] 1. A ferroelectric gate transistor in which a ferroelectric capacitor is provided on a gate electrode of a field effect transistor, wherein the ferroelectric capacitor has at least two or more ferroelectric capacitors connected in series. A ferroelectric gate transistor comprising: 2. The two or more ferroelectric capacitors,
2. The ferroelectric gate transistor according to claim 1, wherein the electrode area is equal to the ferroelectric film thickness. 3. The ferroelectric gate transistor according to claim 1, wherein the ferroelectric layers constituting the series-connected ferroelectric capacitors are formed of the same layer. 4. The ferroelectric capacitor has a structure in which two ferroelectric capacitors are connected in series, and one of the ferroelectric capacitors includes a first electrode and a second electrode, each of which has the ferroelectric layer. The other ferroelectric capacitor has a structure in which the ferroelectric layer is sandwiched between a second electrode and a third electrode, and the first electrode and the third electrode are:
4. The ferroelectric gate transistor according to claim 3, wherein the same conductive layer is formed by processing. 5. The plurality of capacitors connected in series,
The ferroelectric gate transistor according to claim 4, wherein the ferroelectric gate transistor is arranged in a width direction of the field effect transistor. 6. An absolute value of a maximum potential stored as nonvolatile information in the gate electrode, VFG [V], a natural number n of 2 or more which is the number of ferroelectric capacitors connected in series, and a material of the ferroelectric layer. When the coercive electric field of the ferroelectric layer is Ec [V / m], the thickness tF [m] of the ferroelectric layer is a thickness satisfying tF ≧ VFG / (0.5 · n · Ec). 2. The ferroelectric gate transistor according to claim 1, wherein 7. An absolute value of a maximum potential stored as nonvolatile information in the gate electrode, VFG [V], a natural number n of 2 or more which is the number of ferroelectric capacitors connected in series, and a material of the ferroelectric layer. When the coercive electric field of the ferroelectric layer is Ec [V / m], the thickness tF [m] of the ferroelectric layer is a thickness satisfying tF ≧ VFG / (0.3 · n · Ec). 2. The ferroelectric gate transistor according to claim 1, wherein 8. The ferroelectric gate transistor according to claim 1, wherein a positive potential stored as nonvolatile information in said gate electrode is 0.12 [V] or more. 9. The ferroelectric gate transistor according to claim 4, wherein at least a part of a gate electrode of the field effect transistor functions as a first electrode. 10. The ferroelectric gate transistor according to claim 9, wherein a portion of the gate electrode functioning as the first electrode is formed on an insulating layer. 11. The device according to claim 1, wherein the insulating layer is an element isolation oxide film for isolating a plurality of ferroelectric gate transistors.
0. The ferroelectric gate transistor according to 0. 12. The first electrode and the third electrode have a parallel portion at least partially arranged in parallel in a plane,
5. The ferroelectric gate transistor according to claim 4, wherein said second electrode is arranged so as to overlap with said parallel portions, and is orthogonal to a longitudinal direction of said parallel portions. 13. The ferroelectric device according to claim 12, wherein the first electrode and the third electrode of the parallel portion have a width equal to a direction perpendicular to a longitudinal direction of the parallel portion. Body gate transistor.