JP2002110895A - Package structure of chip - Google Patents

Package structure of chip

Info

Publication number
JP2002110895A
JP2002110895A JP2000299575A JP2000299575A JP2002110895A JP 2002110895 A JP2002110895 A JP 2002110895A JP 2000299575 A JP2000299575 A JP 2000299575A JP 2000299575 A JP2000299575 A JP 2000299575A JP 2002110895 A JP2002110895 A JP 2002110895A
Authority
JP
Japan
Prior art keywords
chip
substrate
projection
parent
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000299575A
Other languages
Japanese (ja)
Inventor
Wen Lo Shieh
文楽 謝
Chuang Yung Cheng
永成 荘
Huang Ning
寧 黄
Chen Hui Pin
慧萍 陳
華文 ▲蒋▼
Hua Wen Chiang
Chang Chuang Ming
衷銘 張
豊昌 ▲徐▼
Hosho Jo
Huang Fu Yu
富裕 黄
Chang Hsuan Jui
軒睿 張
Hu Chia Chieh
嘉傑 胡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orient Semiconductor Electronics Ltd
Original Assignee
Orient Semiconductor Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Orient Semiconductor Electronics Ltd filed Critical Orient Semiconductor Electronics Ltd
Priority to JP2000299575A priority Critical patent/JP2002110895A/en
Publication of JP2002110895A publication Critical patent/JP2002110895A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Abstract

PROBLEM TO BE SOLVED: To provide a package structure of a chip which enables chips to be stacked with small volume. SOLUTION: This is used to stack two chips of the same size on the same substrate. Here, provided is a stage where a master chip 21 having a 1st projection and a substrate 22 having a 2nd projection of a metal solding agent at a position corresponding to the 1st projection are pressed against each other and heated. Further, provided are a stage where a slave chip 23 is stuck on the master chip 21 and electrically connected to the substrate 22 with a metal wire 24 by a wire bonding method and a stage where the module comprising the substrate 22, master chip 21, and slave chip 23 is packaged. The master chip 21 and slave chip 23 can, therefore, be stuck tightly without wire bonding and the area of the metal wire of the slave chip 23 can be made small, so the volume of the whole package is reducible.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、チップのパッケー
ジ構造に関する。The present invention relates to a chip package structure.

【０００２】[0002]

【従来の技術】半導体チップはかなり多様に使用され、
近来、さらにモジュール化の傾向がある。チップが他の
チップとともに使用されるとき、チップ間の脚線距離が
長いと効果が減少するため、２枚のチップは積み重ね法
（stack）によりパッケージングされ、脚間距離は短く
設置される。図１に示すように、従来のチップの積み重
ね方法は、親チップ１１を基板（substrate）１２に貼
り付け、ワイヤボンディング法により金線１４で基板１
２と接続する。親チップ１１の頂面には子チップ１３を
貼り付け、ワイヤボンディング法により金線１５で基板
１２に接続する。さらに、全体を合成樹脂１６でパッケ
ージングする。２枚のワイヤボンドされたチップを重ね
合わせ、子チップを親チップの上部に貼り付けるとき、
子チップは銀ペーストにより高さが大きくなっている親
チップに貼り付けられるため、パッケージ全体の厚さは
増加する。2. Description of the Related Art Semiconductor chips are used in various ways.
In recent years, there is a tendency to be more modular. When chips are used with other chips, the effect is diminished if the leg distance between chips is long, so the two chips are packaged by stacking and the leg distance is set short. As shown in FIG. 1, in a conventional chip stacking method, a parent chip 11 is attached to a substrate (substrate) 12, and the substrate 1 is
Connect to 2. The child chip 13 is attached to the top surface of the parent chip 11, and is connected to the substrate 12 by a gold wire 15 by a wire bonding method. Further, the whole is packaged with the synthetic resin 16. When stacking two wire-bonded chips and pasting the child chip on top of the parent chip,
Since the child chip is attached to the parent chip whose height is increased by the silver paste, the thickness of the entire package increases.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、従来の
パッケージ方法によるチップは体積の小さい設備には使
用できない。そこで、本発明の目的は、小さい体積でチ
ップを積み重ることができるチップのパッケージ構造を
提供することにある。However, a chip manufactured by the conventional packaging method cannot be used for equipment having a small volume. Therefore, an object of the present invention is to provide a chip package structure in which chips can be stacked in a small volume.

【０００４】[0004]

【課題を解決するための手段】本発明請求項１記載のチ
ップのパッケージ構造によると、２枚の同サイズのチッ
プを同一基板に積み重ねた構造を有する。その製造方法
は以下の工程を有する。第１突起を有する親チップと、
第１突起と対応する位置に金属溶接剤の第２突起を有す
る基板を押し合わせ、加熱する工程を有する。さらに、
親チップの上部に子チップを貼り付け、子チップをワイ
ヤボンディング法により金線で前記基板と導通し、モジ
ュールを形成する工程と、基板、親チップおよび子チッ
プを有するモジュールをパッケージングする工程とを有
する。したがって、親チップと子チップを堅密に貼り付
けることができ、子チップの金線の面積を小さくするこ
とができるため、パッケージ全体の体積を減少すること
ができる。According to a first aspect of the present invention, there is provided a chip package having a structure in which two chips of the same size are stacked on the same substrate. The manufacturing method has the following steps. A parent chip having a first projection;
There is a step of pressing a substrate having a second projection of a metal welding agent at a position corresponding to the first projection and heating the substrate. further,
Bonding a child chip on top of the parent chip, conducting the child chip to the substrate by gold wire by a wire bonding method, forming a module, and packaging the module including the substrate, the parent chip and the child chip. Having. Therefore, the parent chip and the child chip can be firmly attached, and the area of the gold wire of the child chip can be reduced, so that the volume of the entire package can be reduced.

【０００５】[0005]

【発明の実施の形態】本発明の一実施例によるチップの
パッケージ構造によると、基板２２、下詰め剤２７、表
面に接合突起を有する親チップ２１、接着剤２８、親チ
ップ２１と同サイズの子チップ２３、金線２４および合
成樹脂２６を使用する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to a chip packaging structure according to one embodiment of the present invention, a substrate 22, a lower filler 27, a parent chip 21 having a bonding projection on its surface, an adhesive 28, and the same size as the parent chip 21 are provided. The child chip 23, the gold wire 24 and the synthetic resin 26 are used.

【０００６】図２から図６に本実施例の製造方法を段階
的に示す。 A：フリップチップ技術により親チップ２１と基板２２
を接合する。 ａ１（図２）：基板２２または金属溶接剤の突起２２１
の上部に下詰め剤（underfill）２７を設置する。 ａ２（図３）：親チップ２１を反転し、接合突起（bum
p）２１１と基板２２を押し付け、加熱し、電気接続す
る。FIGS. 2 to 6 show the manufacturing method of this embodiment step by step. A: Flip chip technology and parent chip 21 and substrate 22
To join. a1 (FIG. 2): Projection 221 of substrate 22 or metal welding agent
An underfill 27 is placed on top of the. a2 (FIG. 3): The parent chip 21 is inverted, and the joining protrusion (bum
p) The substrate 211 is pressed against the substrate 211, heated, and electrically connected.

【０００７】Ｂ：表面接着法により親チップ２１に子チ
ップ２３を貼り付ける。 ｂ（図４）：親チップ２１の上部に接着剤２８を塗布
し、子チップ23を接着する。 Ｃ：子チップ２３にワイヤボンディングする。 ｃ（図５）：金線２４で子チップ２３のアルミパッドと
基板２２に設置している釘脚を連結し、電気接続し、モ
ジュールを形成する。B: The child chip 23 is attached to the parent chip 21 by a surface bonding method. b (FIG. 4): The adhesive 28 is applied to the upper part of the parent chip 21 and the child chip 23 is bonded. C: Wire bonding to the sub chip 23 is performed. c (FIG. 5): The aluminum pad of the child chip 23 and the nail leg set on the substrate 22 are connected by the gold wire 24, and are electrically connected to form a module.

【０００８】Ｄ：モジュール全体をパッケージする。 ｄ（図６）：合成樹脂２６で基板２２、親チップ２１お
よび子チップ２３から形成したモジュールをパッケージ
する。親チップのワイヤボンディングプロセスが省略で
き、パッケージングに必要な面積と体積を大幅に減少す
ることができる。また、信号の遅延を低減できる。D: The entire module is packaged. d (FIG. 6): A module formed of the substrate 22, the parent chip 21, and the child chip 23 is packaged with the synthetic resin 26. The wire bonding process of the parent chip can be omitted, and the area and volume required for packaging can be greatly reduced. In addition, signal delay can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】従来のチップのパッケージ構造を示す模式図で
ある。FIG. 1 is a schematic diagram showing a package structure of a conventional chip.

【図２】本発明の一実施例によるチップのパッケージ構
造の製造工程を示す模式図であって、ａ１を示す図であ
る。FIG. 2 is a schematic view showing a manufacturing process of a chip package structure according to one embodiment of the present invention, and is a view showing a1.

【図３】本発明の一実施例によるチップのパッケージ構
造の製造工程を示す模式図であって、ａ２を示す図であ
る。FIG. 3 is a schematic view showing a manufacturing process of a chip package structure according to one embodiment of the present invention, and is a view showing a2.

【図４】本発明の一実施例によるチップのパッケージ構
造の製造工程を示す模式図であって、ｂを示す図であ
る。FIG. 4 is a schematic view showing a manufacturing process of a chip package structure according to an embodiment of the present invention, and is a view showing b.

【図５】本発明の一実施例によるチップのパッケージ構
造の製造工程を示す模式図であって、ｃを示す図であ
る。FIG. 5 is a schematic view showing a manufacturing process of a chip package structure according to an embodiment of the present invention, and is a view showing c.

【図６】本発明の一実施例によるチップのパッケージ構
造の製造工程を示す模式図であって、ｄを示す図であ
る。FIG. 6 is a schematic view illustrating a manufacturing process of a chip package structure according to an embodiment of the present invention, and is a view illustrating d.

【符号の説明】[Explanation of symbols]

２１ 親チップ ２２ 基板 ２３ 子チップ ２４ 金線 ２６ 合成樹脂 ２７ 下詰め剤 21 Parent chip 22 Substrate 23 Child chip 24 Gold wire 26 Synthetic resin 27 Underfill

───────────────────────────────────────────────────── フロントページの続き (72)発明者 ▲蒋▼ 華文 台湾高雄市三民区昌富街57号３樓之２ (72)発明者 張 衷銘 台湾嘉義県布袋鎭見龍里109号 (72)発明者 ▲徐▼ 豊昌 台湾高雄県鳥松郷中正路367之９号 (72)発明者 黄 富裕 台湾高雄市新興区光耀里22鄰渤海街29号 (72)発明者 張 軒睿 台湾高雄市前鎭区中山二路55巷35号 (72)発明者 胡 嘉傑 台湾高雄市楠梓区後昌路546巷11弄12号之 ５ ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor ▲ Chiang ▼ Hua Wen 3 No.57, No.57, Changfu Street, Sanmin District, Kaohsiung, Taiwan (72) Inventor ▲ Xu ▼ Fengchang 367-9, Zhongzheng Road, Torimatsu-go, Kaohsiung, Taiwan No. 35, Zhongshan 2nd Road 55, 72 Jinjin-gu, Taiwan (72) Inventor 5

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 ２枚の同サイズのチップを同一基板に積
み重ねたチップのパッケージ構造であって、 第１突起を有する親チップと、前記第１突起と対応する
位置に金属溶接剤の第２突起を有する基板を押し合わ
せ、加熱する工程と、 前記親チップの上部に子チップを貼り付け、前記子チッ
プをワイヤボンディング法により金線で前記基板と導通
し、モジュールを形成する工程と、 前記基板、前記親チップおよび前記子チップを有する前
記モジュールをパッケージングする工程とを含む製造方
法により製造されたことを特徴とするチップのパッケー
ジ構造。1. A chip package structure in which two chips of the same size are stacked on the same substrate, wherein a parent chip having a first projection and a second metal welding agent are provided at positions corresponding to the first projection. Pressing a substrate having protrusions and heating; bonding a child chip to the upper part of the parent chip, conducting the child chip to the substrate with gold wires by a wire bonding method, and forming a module; Packaging the module having the substrate, the parent chip, and the child chip.
JP2000299575A 2000-09-29 2000-09-29 Package structure of chip Pending JP2002110895A (en)

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Publications (1)

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JP2002110895A true JP2002110895A (en) 2002-04-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000299575A Pending JP2002110895A (en) 2000-09-29 2000-09-29 Package structure of chip

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235887B2 (en) 2003-08-22 2007-06-26 Samsung Electronics Co., Ltd. Semiconductor package with improved chip attachment and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235887B2 (en) 2003-08-22 2007-06-26 Samsung Electronics Co., Ltd. Semiconductor package with improved chip attachment and manufacturing method thereof

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