JP2002110817A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deposition failure of a silicide film on a gate electrode in a logic circuit using a CMOS. SOLUTION: A lightly doped region Y where both n+-type impurities and p+-type impurities do not exist is made on a gate electrode 14 by providing a predetermined interval between the openings of ion implantation masks, when forming the source/drain diffusion layer 37 in an n MOSFET region and the source/drain region 38 in a p MOSFET region in a self alignment process at the gate electrode. This way, a silicide film 15 of equal thickness is made without hindering the growth at the boundary section between the n+ ion implantation region and the p+ ion implantation region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a salicide technology (Self-aligned sili) in a system LSI.
ide).

[0002]

2. Description of the Related Art Conventionally, CMOS (Complement)
ary Metal Oxide Semiconductor
logic circuit and memory embedded LSI using
(Large Scale Integrated c
circuit), SRAM (Static Lando)
m Access read write Memory
y) etc., the system LSI
Salicide technology has been developed for the purpose of reducing the resistance of the gate, source, and drain electrodes of an OSFET (metal oxide semiconductor field effect transistor). The salicide technique is a technique in which low-resistance metal silicide is formed simultaneously and self-aligned on the gate electrode and on the surface of the source / drain diffusion region.

However, this salicide technology has been
When applied to logic circuits using MOS, etc.,
There were the following problems.

That is, in a normal CMOS, for example, as shown in FIG.
In addition, between the pMOSFET region 102 and the pMOSFET region 102, the ion implantation regions 101a and 102a of each impurity are formed so as to partially overlap each other. This is an overlap required for the gate electrode 103 on the field over the nMOSFET region 101 and the pMOSFET region 102 with an overlay accuracy, and the degree of overlap slightly changes due to misalignment of the resist mask. Further, these ion implantation regions 101
a and 102a are generally formed after processing the gate electrode 103. Therefore, for example, as shown in FIG.
As shown in (b), in the region B of the gate electrode 103 corresponding to the portion A where the ion-implanted regions 101a and 102a overlap, both n + -type impurities and p + -type impurities are present.

When a metal silicide is formed on such a gate electrode 103 by a salicide technique,
For example, as shown in FIG. 15, at the time of forming the metal silicide, the speed of the silicidation reaction in the region B where both the n + -type impurity and the p + -type impurity exist, which is the boundary between the ion-implanted regions 101 a and 102 a, As a result, the silicide film 10 in the region B is reduced.
There was a problem that the film thickness of No. 4 became thinner. Silicide film 10
The partial thinning of No. 4 deteriorates the cohesion resistance in the subsequent heat process, causing disconnection and an abnormal increase in resistance, and eventually causes a malfunction of the circuit.

[0006]

As described above, in the prior art, although the gate, source and drain electrodes can be reduced in resistance by the salicide technique, the n + type impurity and the p + type There has been a defect that a film formation defect of a silicide film on a gate electrode in which impurities are present together causes a malfunction of a circuit.

Accordingly, the present invention provides a method of manufacturing a semiconductor device capable of preventing a film formation failure of a silicide film, and improving a circuit breakage and an abnormal increase in resistance to cause a malfunction of a circuit. It is intended to provide a way.

[0008]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a gate electrode on a semiconductor substrate via an insulating film; Performing a self-aligned ion implantation with respect to the gate electrode in a first surface region on the semiconductor substrate including an electrode to form a first diffusion layer of a first conductivity type; Performing ion implantation in a self-aligned manner with respect to the gate electrode on a second surface region adjacent to the first surface region at a predetermined interval on the semiconductor substrate including Forming a second diffusion layer of a mold; and forming a silicide layer on at least an upper surface of the gate electrode.

According to the method of manufacturing a semiconductor device of the present invention, it is possible to suppress the rate of the silicidation reaction from becoming non-uniform in sticking the silicide onto the gate electrode. Thereby, it is possible to prevent the silicide film from being partially thinned and the cohesion resistance from being deteriorated in the subsequent heating step.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of a semiconductor device according to an embodiment of the present invention. Here,
An example in which the present invention is applied to a logic circuit using CMOS as a system LSI will be described.

Referring to FIG. 1, a logic circuit using CMOS includes an nMOSFET region 12 and a p-type
MOSFET region 13 is provided close to
The gate electrode 14 is provided commonly to the MOSFET region 12 and the pMOSFET region 13.

In this case, the n + ion implantation region (first surface region) 12a on the nMOSFET region 12 side and the p + ion implantation region (second surface region) 13a on the pMOSFET region 13 side are formed by the nMOSFET region 12
And the gate electrode 14 on the field across the pMOSFET region 13 does not overlap as required with the accuracy of the overlay, and has a predetermined interval X, for example, the gate electrode 1.
4 are formed so as to have a width equal to or larger than the grain size (average particle size) of polysilicon or polysilicon germanium, which is a material for forming the gate electrode 4.
In particular, in order to prevent a predetermined gap X from being secured due to misalignment of the resist mask for forming the n + ion implanted region 12a and the p + ion implanted region 13a, the misalignment of the resist mask is taken into consideration. It is desirable that the grain size be equal to or larger than the grain size of polysilicon or polysilicon germanium.

Here, the grain growth of silicide is greatly affected by the crystal structure of underlying polysilicon or polysilicon germanium. Therefore, the range in which the underlying crystal structure affects crystal growth such as the orientation of silicide is considered to be approximately the grain size. Further, impurities are diffused into the grains by activation annealing. Therefore, when the predetermined interval X provided between the n + ion implanted region and the p + ion implanted region is equal to or smaller than the grain size of polysilicon or polysilicon germanium, even if the region is not doped with an impurity or a low portion corresponding to the extension portion. Even if a high concentration region is formed, n + dopant and p
The + dopant is present at a high concentration by diffusion. Therefore, the growth of silicide on the region is inhibited.

The gate electrode 14 and the nMOSF
The above n + to be a source / drain diffusion layer of the ET region 12
The surface of the ion implantation region 12a and the pMOSF
The above p + serving as a source / drain diffusion layer of the ET region 13
On the surface of the ion implantation region 13a, a silicide film (layer) 15 is provided by salicide technology.

Further, the nMOSFET region 12 and the pMOSFET region 13 are provided with contacts 16 connected to the respective source / drain diffusion layers via the silicide film 15.

In the case of such a configuration, for example, FIG.
(A) and (b), as shown in FIG.
At the time of forming the a and p + ion implantation regions 13a,
Depending on the positions of the resist masks 21 and 22, the n + ion implantation region 12a and the p + ion in the gate electrode 14 correspond to a predetermined interval X provided between the n + ion implantation region 12a and the p + ion implantation region 13a. It is possible to form a region Y in which both the n + type impurity and the p + type impurity do not exist (or exist at a low concentration) at the boundary with the implantation region 13a.

As described above, neither the n + type impurity nor the p + type impurity exists in the gate electrode 14 (or
By forming the region Y (existing at a low concentration), for example, as shown in FIG. 3, the rate of the silicidation reaction on the gate electrode 14 during the deposition of the silicide film 15 is made substantially uniform (n + type impurity). And the speed of the silicidation reaction can be prevented from decreasing in a region where both p + -type impurities are present. Therefore, it is possible to improve the thickness of the silicide film 15 at the boundary between the n + ion implantation region 12a and the p + ion implantation region 13a.

Next, with reference to FIGS. 4 to 11, a description will be given of a process of manufacturing a logic circuit using the CMOS having the above configuration.

First, as shown in FIG.
Is selectively formed on the surface of the STI (S
An element isolation region 31 having a “Hallow Trench Isolation” structure is formed.

Next, as shown in FIG. 5, a p-type well region (Pwell) 32 and an n-type well region (Nwell) 33 are formed in the surface region of the semiconductor substrate 11 in which the element isolation regions 31 are formed. I do.

Next, as shown in FIG. 6, a gate electrode 14 made of polysilicon or polysilicon germanium is formed on the surface of the semiconductor substrate 11 with a gate oxide film 34 interposed therebetween.

Next, as shown in FIG. 7, the surface of the p-type well region 32 and the n-type well region 33 are self-aligned with the gate electrode 14 by extension of the source / drain diffusion layer. The portions 35 are respectively formed.

Next, in order to prevent a short circuit between the source / drain diffusion layer and the gate electrode 14, after an insulating film is deposited on the entire surface, the insulating film is dry-etched without a mask (remaining side walls). Thus, as shown in FIG. 8, the side wall insulating films 36 are formed on both side wall portions of the gate electrode 14.

FIGS. 7 and 8 correspond to, for example, sections taken along line 6a-6a in FIG. 6, for example.

Next, as shown in FIG. 9A, the photoresist is patterned by a lithography technique to form a resist mask 21 in a predetermined region on the semiconductor substrate 11. And 40 keV, 5 × 10 ¹⁵ c
Under the condition of m ⁻² , As + is ion-implanted to form an n + ion-implanted region 12 a in a self-aligned manner. Thus,
As shown in FIG. 9B, the source / drain diffusion layer (first diffusion layer of the first conductivity type) 3 in the nMOSFET region 12
7 is formed.

FIG. 9B shows, for example, FIG.
This corresponds to a cross section along line 9a-9a in FIG.

Next, as shown in FIG. 10A, after the resist mask 21 is removed, a photoresist is patterned again by lithography to form a resist mask 22 on a predetermined region on the semiconductor substrate 11. Form. Then, under the conditions of 3 keV and 4 × 10 ¹⁵ cm ⁻² , B + is ion-implanted into the p + ion-implanted region 1.
3a is formed in a self-aligned manner. Thus, FIG.
As shown in FIG. 6, a source / drain diffusion layer (second conductivity type second diffusion layer) 38 in the pMOSFET region 13 is formed.

FIG. 10B shows, for example, FIG.
This corresponds to a cross section along line 10a-10a in (a).

As described above, the source / drain diffusion layer 37 of the nMOSFET region 12 and the pMOSFE
In forming the source / drain diffusion layers 38 in the T region 13, a predetermined distance X between the n + ion implanted region 12a and the p + ion implanted region 13a is determined based on a design rule at the time of creating a layout pattern by CAD processing, for example. So that the resist mask 2 is provided.
1 and 22 are formed.

The n + ion implanted regions 12a and p
When there are a large number of adjacent portions of the + ion implantation region 13a in the chip, a layout pattern is generated so that a predetermined interval X is provided for each boundary portion.

As a result, a portion where doping is not performed on the gate electrode 14 is secured, and as a result, As + (n + type impurity) and B + (p +
(Or source impurities)
A region Y is formed in which impurity ions implanted at the time of forming the extension portion 35 of the drain diffusion layer exist at a low concentration.

After the resist mask 22 is removed, as shown in FIGS. 11A and 11B, the gate electrode 14 is removed.
Above, the surface of the source / drain diffusion layer 37 of the nMOSFET region 12, and the pMOSFET region 1
The silicide film 15 is formed on the surface of the third source / drain diffusion layer 38 by, for example, a salicide technique using Co. At this time, the n + ion implantation region 12a and the p + ion implantation region 1 are formed on the gate electrode 14.
Since the low-concentration region Y exists at the boundary with 3a, the silicide film 15 having a uniform thickness can be formed without hindering the growth of the silicide film at that portion.

Therefore, as a result of improving the heat resistance, it is possible to prevent the breakage of the silicide film 15 by a subsequent heat process, and to prevent the silicide film 1 from being broken.
It is possible to eliminate the occurrence of a failure mode in which a voltage is not applied to the gate electrode 14 due to the abnormal increase in the resistance of the gate electrode 5.

FIG. 11B shows, for example, FIG.
(A) corresponds to a section taken along line 11a-11a and line 11b-11b, respectively.

As described above, it is possible to suppress the rate of the silicidation reaction from becoming non-uniform in sticking the silicide onto the gate electrode.

That is, a low-concentration region in which the n + type impurity and the p + type impurity are not doped is formed at the boundary between the n + ion implantation region and the p + ion implantation region on the gate electrode. Thereby, it is possible to prevent the silicide film from being partially thinned and the cohesion resistance from being deteriorated in the subsequent heating step. Therefore, it is possible to prevent the film formation failure of the silicide film, and to improve the disconnection and the abnormal increase of the resistance to cause the malfunction of the circuit.

In the above embodiment, when forming the source / drain diffusion layers, a region where the impurity is not doped is formed at the boundary between the n + ion implantation region and the p + ion implantation region on the gate electrode. However, the present invention is not limited to this.
The same can be applied when forming the extension portion of the drain diffusion layer. That is, when the extension portion is formed, the n-type ion-implanted region and the p-type
It is also possible to provide a space (predetermined interval X) between the region and the mold ion implantation region so as to prevent overlapping portions (overlap).

The present invention can be applied not only to a logic circuit using CMOS but also to an SRAM as shown in FIG. 12, for example. FIG. 1A is a plan view showing the layout of the SRAM, and FIG. 1B is a corresponding circuit diagram.

In FIG. 12, the load element pMO
The drain electrode of the active region AA of the SFET (Qp1) is connected via a contact Ca, the drain electrode of an nMOSFET (Qn1) as a driver element is connected via a contact Cb, and the pMOS as a load element is connected.
FET (Qp2) and nMOSF as driver element
The common gate electrode of ET (Qn3) is connected to an upper layer wiring (M1) (not shown) via a contact Cc.

In such a configuration, the pMOSF
Between the ET (Qp1) and the nMOSFET (Qn1), and between the pMOSFET (Qp2) and the nMOS
With a predetermined interval X between the FET and the FET (Qn3), p
+ / N + ion implantation regions are provided,
The pMOSFET (Qp2) and the nMOSFE
T (Qn3) common gate electrode GC and pM
The OSFET (Qp2) and the nMOSFET (Qn
3) are in common contact with each drain electrode,
The pMOSFET (Qp1) and the nMOSFET
A desired silicide film can be formed with a uniform thickness on the common gate electrode GC with (Qn1).

In addition, the present invention is not limited to the above-described embodiments, and can be variously modified in an implementation stage without departing from the scope of the invention. Furthermore, the (each) embodiment includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example,
Even if some components are deleted from all the components shown in the embodiments, at least one of the problems described in the section of the problem to be solved by the invention can be solved, and the effects of the invention can be solved. (At least one of the effects described in the section)
Is obtained, a configuration from which the configuration requirement is deleted can be extracted as an invention.

[0043]

As described above in detail, according to the present invention, it is possible to prevent a film formation defect of a silicide film, and to prevent a disconnection or an abnormal increase in resistance to cause a malfunction of a circuit. And a method of manufacturing a semiconductor device that can perform the method.

[Brief description of the drawings]

FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a main part showing a method for forming an n + ion implantation region and a p + ion implantation region in the semiconductor device.

FIG. 3 is a schematic cross-sectional view showing a gate electrode structure in the semiconductor device.

FIG. 4 is a process sectional view similarly illustrating the method for manufacturing the semiconductor device;

FIG. 5 is a process sectional view similarly illustrating the method for manufacturing the semiconductor device;

FIG. 6 is a process sectional view similarly illustrating the method for manufacturing the semiconductor device;

FIG. 7 is a process sectional view similarly illustrating the method for manufacturing the semiconductor device;

FIG. 8 is a process sectional view similarly illustrating the method for manufacturing the semiconductor device;

FIG. 9 is a process sectional view similarly illustrating the method for manufacturing the semiconductor device;

FIG. 10 is a process sectional view similarly illustrating the method for manufacturing the semiconductor device;

FIG. 11 is a process sectional view similarly illustrating the method for manufacturing the semiconductor device;

FIG. 12 is a schematic diagram showing another configuration example of the present invention.

FIG. 13 is a schematic plan view of a semiconductor device shown to explain a conventional technique and its problems.

FIG. 14 is a schematic cross-sectional view of a main part showing a method for forming an n + ion implantation region and a p + ion implantation region in a conventional semiconductor device.

FIG. 15 is a schematic cross-sectional view showing a gate electrode structure in a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12 ... nMOSFET area 12a ... n + ion implantation area 13 ... pMOSFET area 13a ... p + ion implantation area 14 ... Gate electrode 15 ... Silicide film 16 ... Contact 21, 22 ... Resist mask 31 ... Element isolation area 32 ... p-type Well region 33 ... n-type well region 34 ... gate oxide film 35 ... extension part 36 ... side wall insulating film 37 ... source / drain diffusion layer (nMOSFET region) 38 ... source / drain diffusion layer (pMOSFET region) X ... predetermined interval Y …region

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 BB01 BB20 BB36 BB40 CC05 DD02 DD04 DD56 DD78 DD84 EE09 FF14 GG10 HH16 5F048 AB01 AB03 AC03 BA01 BB06 BB07 BB08 BC06 BE03 BG13 DA25

Claims (8)

[Claims] A step of forming a gate electrode on a semiconductor substrate via an insulating film; and a step of forming ions in a first surface region on the semiconductor substrate including the gate electrode in a self-aligned manner with respect to the gate electrode. Implanting to form a first diffusion layer of a first conductivity type; and forming a second diffusion layer adjacent to the first surface region on the semiconductor substrate including the gate electrode at a predetermined interval. Forming a second conductivity type second diffusion layer by performing ion implantation in the surface region of the gate electrode in a self-aligned manner; and forming a silicide layer at least on the upper surface of the gate electrode. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the predetermined interval is set to be equal to or larger than a grain size of a gate electrode material forming the gate electrode. 3. The predetermined interval is set in consideration of misalignment of respective resist masks for forming the first diffusion layer of the first conductivity type and the second diffusion layer of the second conductivity type, respectively. 3. The method according to claim 2, wherein the gate electrode material is set to be equal to or larger than a grain size of the gate electrode material. 4. The method according to claim 2, wherein the gate electrode material is polysilicon or polysilicon germanium. 5. The method according to claim 1, wherein the predetermined interval is determined according to a design rule when a layout pattern is created. 6. The method according to claim 1, wherein the layout pattern is created by CAD.
The method according to claim 5, wherein the method is performed using (Computer Aided Design). 7. After the step of forming the gate electrode, ion implantation is performed in a self-aligned manner on the gate electrode in the first surface region to form a first conductive type first diffusion layer. Forming an extension portion; and performing ion implantation in the second surface region on the gate electrode in a self-aligned manner to form an extension portion of a second diffusion layer of the second conductivity type. The method according to claim 1, further comprising: 8. The method according to claim 1, wherein the first surface region and the second surface region have a predetermined interval at all positions adjacent to each other.