JP2002110784A - Manufacturing method of multi-layer wiring structure, and its structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-layer wiring structure which connects upper layer wiring layer and lower layer wiring layer with a via contact having a large aspect ratio. SOLUTION: A process for forming the via contact of the multi-layer wiring structure comprises an electroless plating process, in which a catalyst layer is provided on the bottom face of a via hole, a plating metal layer is grown upward of the via hole on the catalyst layer, and the via hole is filled with the plating metal layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer wiring structure and a method of manufacturing the same, and more particularly, to a via contact structure for connecting an upper wiring layer and a lower wiring layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view of a general multilayer wiring structure 20. In such a multilayer wiring structure 20, an insulating film 2 and a lower wiring layer 3 are formed on a semiconductor substrate 1 on which elements such as transistors (not shown) are formed. The lower wiring layer 3 is connected to an element (not shown) formed on the semiconductor substrate 1. In FIG. 4, the lower wiring layer 3 extends in a direction perpendicular to the paper surface. An interlayer insulating film 4 is formed on the insulating film 2, and, for example, a via hole having a substantially circular cross section is provided at a position on the lower wiring layer 3. In the via hole, a barrier metal layer 5 and a plating layer 7 are sequentially formed, and a via contact is formed. Further, on the interlayer insulating film 4, an upper wiring layer 8 electrically connected to the via contact is formed.
Is formed. In FIG. 4, the upper wiring layer 8 extends in a direction parallel to the paper surface. In this way, the lower wiring layer 3 and the upper wiring layer 8 are electrically connected via the via contact, and the multilayer wiring structure 20 is formed.

FIG. 5 shows a process of manufacturing a conventional multilayer wiring structure using an electrolytic plating method. First, as shown in step (a), an insulating film 2 and a lower wiring layer 3 are formed on a semiconductor substrate 1 using a general method, and an interlayer insulating film 4 is formed thereon.

Next, as shown in step (b), for example, a via hole 8 having a substantially circular cross section is formed in the interlayer insulating film 4 on the lower wiring layer 3 and a barrier metal layer 5 is formed on the inner wall thereof. In the steps after the step (b), the semiconductor substrate 1 is omitted.

Next, as shown in a step (c), a seed layer 6 to be used in an electrolytic plating method to be performed later is formed by a sputtering method.

Finally, as shown in a step (d), a plating layer 7 is formed on the seed layer 6 by using an electrolytic plating method, a via hole 8 is buried, and a via contact is formed.

[0007] Seed layer 6 and plating layer 7 on interlayer insulating film 4
Is removed by a CMP method or the like, and an upper wiring layer (not shown) is formed so as to be electrically connected to the via contact. Through these steps, the multilayer wiring structure 20 shown in FIG. 4 is formed.

[0008]

However, the aspect ratio (depth / diameter) of a via hole of a multilayer wiring structure used in a circuit increases with the increase in the degree of integration and miniaturization of the circuit.
The uniformity of the thickness of the seed layer 6 formed by sputtering is deteriorated. In particular, as shown in FIG. 5C, on the side surface of the via hole 8, the thickness of the seed layer 6 is partially reduced, or the seed layer 6 is not partially formed. As a result, in the electroplating process using the seed layer 6, the plating layer 7 is not sufficiently formed on the side surface of the thin via hole of the seed layer 6, and the void 12 as shown in FIG. This causes the via contact to have a high resistance and a disconnection.

On the other hand, in recent years, a method of forming a via contact using an electroless plating method has been proposed. FIG.
Is a manufacturing process of a multilayer wiring structure using an electroless plating method. 6A, a via hole 8 whose surface is covered with the barrier metal layer 5 is formed in the interlayer insulating film 4, as shown in FIG. 6A. FIG.
1A to 1C, the semiconductor substrate 1 is omitted.

Next, as shown in FIG. 6B, on the surface of the interlayer insulating film 4 and on the bottom and side surfaces of the via hole 8,
A noble metal catalyst layer 9 having a substantially uniform thickness is formed by a wet method.

Finally, an electroless plating layer 10 is grown on the catalyst layer 9 by using an electroless plating method. In general, in the electroless plating method, since the catalytic reaction occurs substantially uniformly on the entire surface of the catalyst layer 9, the plating layer 1 having a substantially uniform thickness over the entire surface.
0 can be formed. However, when the aspect ratio of the via hole 8 increases, the supply of the plating solution into the via hole 8 becomes insufficient, and the deposition rate of the plating layer 10 decreases near the bottom surface of the via hole 8. As a result, voids as indicated by reference numeral 12 in FIG. 6C were generated, and even when the electroless plating method was used, the via contact had a high resistance or a disconnection occurred.

Accordingly, the present invention provides a multilayer wiring structure in which a via contact having a high aspect ratio is buried by using an electroless plating method to form a via contact in a highly integrated and miniaturized circuit. Aim.

[0013]

SUMMARY OF THE INVENTION The present invention relates to a method for manufacturing a multilayer wiring structure in which wiring layers are provided so as to sandwich an interlayer insulating film, and the wiring layers are connected by via contacts. Forming a lower wiring layer on the substrate, forming an interlayer insulating film to cover the lower wiring layer, penetrating the interlayer insulating film on the lower wiring layer, Forming a via hole so as to be exposed; burying a plating metal layer in the via hole so as to be electrically connected to the lower wiring layer; forming a via contact as a via contact; and electrically connecting to the via contact. Forming an upper wiring layer on the interlayer insulating film so as to make a connection, wherein the via contact forming step includes providing a catalyst layer on a bottom surface of the via hole, and forming a catalyst layer on the catalyst layer above the via hole. Toward The Kki metal layer is grown, a method for manufacturing a multilayer interconnection structure, characterized in that in the plated metal layer is an electroless plating step of filling the via hole.
In this manufacturing method, since the plating layer is deposited from the bottom surface of the via hole toward the opening, the via hole can be filled with the plating layer without forming a void generated by the conventional method. As a result, it is possible to prevent the via contact from having a high resistance and disconnection due to the generation of voids.

In the present invention, the step of forming the via contact preferably includes a step of forming the catalyst layer having a substantially uniform thickness on the bottom surface and the side surface of the via hole; Removing and leaving the catalyst layer on the bottom surface;
Embedding the via hole with the plated metal layer by an electroless plating method using the catalyst layer. Thus, by forming the catalyst layer on the bottom surface of the via hole, it is possible to prevent generation of voids in the electroless plating process using the catalyst layer.

The step of removing the catalyst layer on the side wall is preferably a step using substrate bias sputtering.

The catalyst layer may be formed by a catalytic metal colloid adsorption method.

Further, in the present invention, the via contact forming step may be performed by a dry process so that the film thickness on the bottom surface and the side surface of the via hole is larger on the bottom surface than on the side surface. A step of forming a catalyst layer, a step of removing the catalyst layer by wet etching and leaving the catalyst layer on the bottom surface, and forming the via hole by the electroless plating method using the catalyst layer. And a step of embedding in the method. Thus, by forming the catalyst layer on the bottom surface of the via hole, it is possible to prevent generation of voids in the electroless plating process using the catalyst layer.

The thickness of the catalyst layer is preferably at least twice as large on the bottom surface as on the side surface. This is because only the catalyst layer on the side surface of the via hole can be selectively removed by using the wet etching process.

The step of removing the catalyst layer on the side surface may be a wet etching step using an etchant having a viscosity adjusted to 10 centipoise or more. Suppress the supply of the etchant to the catalyst layer on the bottom of the via hole,
This is because only the catalyst layer on the side surface can be selectively removed.

[0020] The catalyst layer may be provided continuously on the bottom surface of the via hole and on the side surface near the bottom surface.

In the present invention, the step of forming a via contact preferably includes the step of forming a photoresist layer on the interlayer insulating film so as to fill the via hole, and the step of forming the via hole in the photoresist layer in the via hole. Forming a hole so that a part of the bottom surface is exposed; forming the catalyst layer on the exposed bottom surface; removing the photoresist layer; Embedding the via hole with the plating metal layer by an electrolytic plating method.
As described above, by forming the catalyst layer on a part of the bottom surface of the via hole, it is possible to prevent generation of voids in the electroless plating step using the catalyst layer.

The catalyst layer is preferably made of one metal selected from the group consisting of palladium, platinum, ruthenium, rhodium, iridium and gold.

The plating metal layer is preferably made of one metal selected from the group consisting of copper, aluminum and silver.

According to the present invention, there is provided a multilayer wiring structure in which wirings provided with an interlayer insulating film interposed therebetween are connected by via contacts. An interlayer insulating film provided to cover the lower wiring layer and a via hole penetrating the interlayer insulating film,
A via contact electrically connected to the lower wiring layer,
An upper wiring layer provided on the interlayer insulating film and electrically connected to the via contact, wherein the via contact is formed on the bottom surface of the via hole and formed using the catalyst layer and the catalyst layer; And a plated wiring layer. In such a multilayer wiring structure, since the via hole is buried with the plating layer without forming a void, the resistance of the via contact can be increased and the disconnection can be prevented. For this reason, a highly reliable and high performance multilayer wiring structure can be obtained.

[0025] The catalyst layer may be a catalyst layer provided continuously on the bottom surface of the via hole and on the side surface of the via hole near the bottom surface.

The catalyst layer may be formed only on a part of the via hole on the bottom surface.

[0027] The catalyst layer is preferably made of one metal selected from the group consisting of palladium, platinum, ruthenium, rhodium, iridium and gold.

The plating metal layer is preferably made of one metal selected from the group consisting of copper, aluminum and silver.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a cross-sectional view of a manufacturing process of the multilayer wiring structure according to the present embodiment.
In this method, first, as shown in FIG. 1A, a semiconductor substrate 1 is prepared. As the semiconductor substrate 1, for example, a silicon substrate is used. On the semiconductor substrate 1, a semiconductor element such as a transistor is formed using a general manufacturing process.

On a semiconductor substrate 1, an insulating film 2 made of, for example, silicon oxide and a lower wiring layer 3 made of, for example, copper
Is formed. The lower wiring layer 3 is connected to a transistor (not shown) formed on the semiconductor substrate 1 and the like. In FIG. 1A, the lower wiring layer 3 extends in a direction perpendicular to the paper surface.

Subsequently, an interlayer insulating film 4 made of, for example, silicon oxide is formed on the entire surface of the insulating film 2 and the lower wiring layer 3. The via hole 8 is formed on the lower wiring layer 3 of the interlayer insulating film 4 by using a general lithography process and an etching process.
Is formed. The via hole 8 has, for example, a circular cross section, and the surface of the lower wiring layer 3 is exposed at the bottom.

Subsequently, a barrier metal layer 5 such as Ta, TaN, TiN, or WN is formed by a sputtering method so as to cover the bottom and side surfaces of the via hole 8.
The barrier metal layer 5 prevents copper embedded in the via hole 8 from diffusing into the interlayer insulating film 4 in a later step. The barrier metal layer 5 may not be provided depending on the type of metal to be embedded in the via hole 8.

Next, as shown in FIG. 1 (b), a catalyst layer 9 used for electroless plating is formed by using a catalytic metal colloid adsorption method. Specifically, for example, after tin is adsorbed on the inner surface of the via hole 8 and on the interlayer insulating film 4 using an aqueous tin chloride solution, tin is replaced with palladium using an aqueous palladium chloride solution, and is made of a palladium colloid. The catalyst layer 9 is formed. The thickness of the catalyst layer 9 is set to 10 so that the electrical resistance of the via contact does not increase.
nm or less. In FIGS. 1A to 1E, the substrate 1 is omitted.

Next, as shown in FIG.
_{2. The} catalyst layer 9 is removed by sputtering using a plasma such as NH ₃ so that the catalyst layer 9 remains only on the bottom surface of the via hole 8 and on the side surface near the bottom surface. In this case, the catalyst layer 9 on the side surface of the via hole 8 adheres again near the bottom surface of the via hole 8 after being sputtered. In such sputtering, for example, a high-frequency bias is applied to the semiconductor substrate 1 so that a directional ion beam is applied to the semiconductor substrate 1.
Can be illuminated above. In order to prevent the catalyst layer 6 on the bottom of the via hole 8 from being sputtered,
00 mTorr or more, and the applied high frequency bias is 30
It is preferable that sputtering is performed under the condition of 0 V or less. In FIG. 1C, the catalyst layer 9 is also left on the side surface of the via hole 8, but the catalyst layer 9 on the side surface may be entirely removed and left only on the bottom surface.

Next, as shown in FIG. 1D, an electroless plating layer 10 of copper is formed on the catalyst layer 9 by an electroless plating method using a catalyst layer 9 made of palladium. In this case, the electroless plating layer 10 is deposited from the surface of the catalyst layer 9 toward above the via hole 8. For this reason, since the via holes 8 are buried from below to above, the generation of the voids 12 generated by the conventional electroless plating method as shown in FIG. 6C can be prevented. Finally, as shown in FIG.
Is completed with the electroless plating layer 10 ending the electroless plating step.

Finally, as shown in FIG.
The electroless plating layer 10 projecting upward from the surface of the interlayer insulating film 4 is removed by a method or the like, and an upper wiring layer 11 made of, for example, copper is formed thereon. In FIG. 1E, the upper wiring layer 11 extends in a direction parallel to the paper. Through the above steps, a multilayer wiring structure in which the lower wiring layer 3 and the upper wiring layer 11 are connected by the via contact including the electroless plating layer 10 is formed.

Embodiment 2 FIG. 2 is a cross-sectional view of a step of manufacturing another multilayer wiring structure according to the present embodiment. In this method, first, a via hole 8 provided with the barrier metal layer 5 shown in FIG. 2A is formed by a process similar to the above-described process of FIG. In FIGS. 2A to 2E, the substrate 1 is omitted.

Next, as shown in FIG. 2B, a catalyst layer 6 made of, for example, palladium is formed so as to cover the bottom and side surfaces of the via hole. For forming the catalyst layer 6, for example, a dry process such as an ionization sputtering method, an ion beam evaporation method, an arc discharge deposition method, and a cluster ion beam evaporation method is used. In such a dry process, the catalyst layer 6 is deposited with anisotropy. That is, in the via hole 8, the catalyst layer 6 is formed to be thicker on the bottom surface than on the side surfaces. In particular, it is preferable that the thickness of the catalyst layer 6 on the bottom surface is twice or more the thickness of the catalyst layer 6 on the side surface. Note that the thickness of the catalyst layer 6 is preferably 10 nm or less so as not to increase the electric resistance of the via contact.

Next, as shown in FIG. 2C, the catalyst layer 6 on the interlayer insulating film 4 is removed by the CMP method.

Next, as shown in FIG. 2D, the catalyst layer 6 on the side surface of the via hole 8 is selectively removed by wet etching, and the catalyst layer 6 is formed only on the bottom surface of the via hole 8. leave. As described above, since the film thickness of the catalyst layer 6 is thicker on the bottom surface than on the side surfaces, it is possible to selectively remove the catalyst layer 6 on the side surfaces by performing normal isotropic etching. it can. As an etching solution, a mixed solution of hydrochloric acid, nitric acid and acetic acid, a mixed solution of hydrochloric acid and nitric acid, and the like can be used.

On the other hand, by adjusting the viscosity of the etchant, selective etching can be performed while suppressing the supply of the etchant to the bottom surface of the via hole 8. That is, when the aspect ratio of the via hole is large, if the viscosity of the etchant is increased, the etchant is less likely to enter the via hole, and only the catalyst layer 6 near the opening of the via hole can be selectively etched. With this method, it is possible to selectively remove only the catalyst layer 6 on the side surface while leaving the catalyst layer 6 at the bottom of the via hole 8. Further, it is possible to omit the CMP step performed in the step of FIG. 2C and to remove the catalyst layer 6 on the interlayer insulating film 4 simultaneously with the catalyst layer 6 on the side surface of the via hole 8.

In FIG. 2D, the catalyst layer 6 is left only on the bottom surface of the via hole 8, but as shown in FIG.
The catalyst layer 6 may be left on the side surface near the bottom surface.

Next, as shown in FIG. 2E, the electroless plating layer 1 made of copper is formed on the catalyst layer 6 by the electroless plating method.
0 is deposited. The electroless plating layer 10 is deposited so as to fill the via hole 8, thereby forming a via contact. The plating layer 10 is deposited so as to fill the via hole 8 from below to above the via hole 8. Therefore, no void is generated in the plating layer 10. Finally, the electroless plating layer 10 on the interlayer insulating film 4 is
After removal by the MP method, an upper wiring layer 11 made of, for example, copper is formed. Through such steps, a multilayer wiring structure can be obtained.

Embodiment 3 FIG. FIG. 3 is a cross-sectional view showing a step of manufacturing another multilayer wiring structure according to the present embodiment. In this method, first, a via hole 8 provided with the barrier metal layer 5 shown in FIG. 3A is formed by a process similar to the above-described process of FIG. It should be noted that the substrate 1 is also omitted in the steps of FIGS.

Next, as shown in FIG. 2B, a photoresist layer 11 is formed on the interlayer insulating film 4 so as to fill the via holes 8. Further, a hole having a diameter smaller than the diameter of the via hole 8 is provided in the photoresist layer 11 inside the via hole 8 by using a general photolithography process. At the bottom surface of the hole, the barrier metal layer 5 provided in the via hole 8 is exposed.

Next, as shown in FIG. 3C, a catalyst layer 9 is formed on the bottom surface of the hole using, for example, a catalytic metal colloid adsorption method.

Next, as shown in FIG. 3D, the catalyst layer 6 can be formed on a part of the bottom surface of the via hole 8 by removing the photoresist layer 11. In addition,
In the step of FIG. 3C, the catalyst layer 6 is formed, for example, by a dry process on the top of the photoresist layer 11 and the bottom of the hole, and in the step of FIG. The catalyst layer 6 on the layer 11 may be formed by lift-off.

Next, as shown in FIG. 3E, the electroless plating layer 1 made of copper is formed on the catalyst layer 6 by the electroless plating method.
0 is deposited. The electroless plating layer 10 is deposited so as to fill the via hole 8, thereby forming a via contact. Also in this case, since the plating layer 10 is deposited upward from below the via hole 8, no void is generated in the plating layer 10. Finally, the interlayer insulating film 4
The upper electroless plating layer 10 is removed by a CMP method, and an upper wiring layer 11 made of, for example, copper is formed. Through such steps, a multilayer wiring structure can be obtained.

In the first to third embodiments, the case where palladium is used for the catalyst layer 6 and copper is embedded as the electroless plating layer 10 has been described. , Rhodium, iridium,
Gold or the like can also be used. In addition, the electroless plating layer 10
In addition to copper, aluminum, silver and the like can also be used.

[0050]

As is apparent from the above description, in the method for manufacturing a multilayer wiring structure according to the present invention, the plating layer is deposited from the bottom surface of the via hole toward the opening, so that the via hole is formed without generating a void. Can be embedded in the plating layer. As a result, it is possible to prevent an increase in the resistance of the via contact, disconnection, and the like due to the generation of a void.

In the multilayer wiring structure according to the present invention,
Since the occurrence of voids in the via contact is prevented,
A highly reliable multilayer wiring structure can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a step of manufacturing a multilayer wiring structure according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process of a multilayer wiring structure according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a manufacturing step of a multilayer wiring structure according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view of a conventional multilayer wiring structure.

FIG. 5 is a cross-sectional view of a manufacturing process of a conventional multilayer wiring structure.

FIG. 6 is a cross-sectional view of a manufacturing process of a conventional multilayer wiring structure.

[Explanation of symbols]

1 ... semiconductor substrate, 2 ... insulating film, 3 ... lower wiring layer,
4 interlayer insulating film, 5 barrier metal layer, 6 seed layer, 7 plating layer, 8 via hole, 9 catalyst layer,
10 ... plating layer, 11 ... upper wiring layer, 12 ... void, 20 ... multilayer wiring structure.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroyuki Sakagami 3-802 F.T. EA03 4M104 AA01 BB04 BB17 BB30 BB32 BB33 CC01 DD06 DD16 DD22 DD28 DD37 DD53 DD75 FF13 FF17 FF18 FF22 GG13 HH13 HH15 HH20 5F033 HH08 HH11 HH14 JJ08 JJ11 JJ14 JJ21 Q14 XXX15 XX04 XX09

Claims (16)

[Claims] 1. A wiring layer is provided so as to sandwich an interlayer insulating film,
A method of manufacturing a multilayer wiring structure for connecting said wiring layers by via contacts, comprising: preparing a substrate; forming a lower wiring layer on said substrate; and forming an interlayer insulating film so as to cover said lower wiring layer. Forming a via hole so as to penetrate the interlayer insulating film on the lower wiring layer and expose the lower wiring layer; and forming a via hole so as to be electrically connected to the lower wiring layer. A via contact forming step of burying a plated metal layer in the via hole to form a via contact; and forming an upper wiring layer on the interlayer insulating film so as to be electrically connected to the via contact. Forming a catalyst layer on the bottom surface of the via hole, growing the plating metal layer on the catalyst layer toward the upper side of the via hole, and filling the via hole with the plating metal layer. A method for manufacturing a multilayer wiring structure, characterized by comprising a step of: A step of forming the catalyst layer having a substantially uniform thickness on the bottom surface and the side surface of the via hole; removing the catalyst layer on the side wall; The method according to claim 1, further comprising: a step of leaving the catalyst layer on the bottom surface; and a step of filling the via hole with the plating metal layer by an electroless plating method using the catalyst layer. 3. The method according to claim 2, wherein the step of removing the catalyst layer on the side wall is a step using substrate bias sputtering. 4. The method according to claim 2, wherein the catalyst layer is formed by a catalytic metal colloid adsorption method. 5. The catalyst layer is formed on the bottom surface and the side surface of the via hole by a dry process such that the thickness of the catalyst layer is greater on the bottom surface than on the side surface. Removing the catalyst layer by wet etching to leave the catalyst layer on the bottom surface, and embedding the via hole with the plating metal layer by an electroless plating method using the catalyst layer. The method according to claim 1, further comprising: 6. The method according to claim 5, wherein the thickness of the catalyst layer is at least twice as large on the bottom surface as on the bottom surface. 7. The method according to claim 2, wherein the step of removing the catalyst layer on the side wall is a wet etching step using an etchant having a viscosity adjusted to 10 centipoise or more. The manufacturing method as described. 8. The production method according to claim 1, wherein the catalyst layer is provided continuously on the bottom surface of the via hole and on the side surface near the bottom surface. Method. 9. The step of forming a via-contact, the step of forming a photoresist layer on the interlayer insulating film so as to fill the via-hole, and the step of forming a bottom surface of the via-hole on the photoresist layer in the via-hole. Forming a hole so that the portion is exposed; forming the catalyst layer on the exposed bottom surface; removing the photoresist layer; and electroless plating using the catalyst layer. Burying the via hole with the plating metal layer. 10. The method according to claim 1, wherein the catalyst layer is made of one metal selected from the group consisting of palladium, platinum, ruthenium, rhodium, iridium and gold.
10. The production method according to any one of items 9 to 9. 11. The method according to claim 1, wherein the plating metal layer is made of one metal selected from the group consisting of copper, aluminum and silver. 12. A multilayer wiring structure in which wiring provided with an interlayer insulating film interposed therebetween is connected by a via contact, comprising: a substrate; a lower wiring layer provided on the substrate; An interlayer insulating film provided so as to cover, a via contact embedded in a via hole penetrating the interlayer insulating film, and electrically connected to the lower wiring layer; and a via contact provided on the interlayer insulating film; An upper wiring layer electrically connected to the via hole, wherein the via contact includes a catalyst layer provided on the bottom surface of the via hole, and an electroless plating metal layer formed using the catalyst layer. Characteristic multilayer wiring structure. 13. The catalyst layer according to claim 1, wherein the catalyst layer is provided continuously on the bottom surface of the via hole and on a side surface of the via hole near the bottom surface.
3. The multilayer wiring structure according to 2. 14. The multilayer wiring structure according to claim 12, wherein said catalyst layer is formed only on a part of said via hole on said bottom surface. 15. The method according to claim 1, wherein the catalyst layer is made of one metal selected from the group consisting of palladium, platinum, ruthenium, rhodium, iridium and gold.
15. The multilayer wiring structure according to any one of 2 to 14. 16. The multilayer wiring structure according to claim 12, wherein said plating metal layer is made of one metal selected from the group consisting of copper, aluminum, and silver.