JP2002110500A - Semiconductor device with alignment marks and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having alignment marks and its manufacturing method which allows the alignment marks to be accurately measured, even if a layer insulation film is planarized. SOLUTION: A layer insulation film 3 is formed on a mark layer 2a forming alignment marks 2b and has openings 3b just above the alignment marks 2b. The distance L1 between the side wall of the opening 3b and the side wall of the alignment mark 2b nearest to that side wall is H×20+50 μm or more where the distance between the top face of the mark layer 2a and the top face of the layer insulation film 3 is H.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an alignment mark and a method of manufacturing the same, and more specifically, to a semiconductor device having an alignment mark used for overlaying a wafer and a mask and a method of manufacturing the same. It is about.

[0002]

2. Description of the Related Art When a wiring layer is formed in a semiconductor manufacturing process, it is necessary to align a mask for forming an upper wiring layer with a lower wiring layer. When aligning the mask, there are a method of detecting a step on the upper surface of the interlayer insulating film covering the alignment mark formed on the semiconductor wafer, and a method of detecting the step of the alignment mark by opening the interlayer insulating film.

FIG. 24 is a schematic sectional view of an alignment mark forming region of a type for detecting a step on the upper surface of an interlayer insulating film. Referring to FIG. 24, a plurality of alignment marks 102a formed separately from the same layer as the lower wiring layer (not shown) are formed on the surface of semiconductor substrate 101. An interlayer insulating film 103 is formed so as to cover the lower wiring layer and the alignment mark 102a.

On the upper surface of the interlayer insulating film 103, a step appears which reflects the step between the alignment mark 102a and the surface of the semiconductor substrate 101. Therefore, by detecting the step on the upper surface of the interlayer insulating film 103, the position of the alignment mark 102a can be indirectly detected. Thus, the upper wiring layer 105 can be patterned by performing mask alignment on the lower wiring layer.

By the way, LSI (Large Scale Integrat)
With the increase in the number of wiring layers in an ed circuit, a new technique for planarizing an interlayer insulating film has been developed.
icalMechanical Polishing) is drawing attention. This C
MP is a technology in which slurry (abrasive) is supplied onto a wafer and the surface is mechanically polished with a pad (polishing cloth). Flatness and shape control in the vertical direction are compared with conventional planarization technology. It is much better in sex.

However, if this CMP is applied to the conventional process as it is, the interlayer insulating film 10 shown in FIG.
3 becomes flat. For this reason, the position of the alignment mark 102a cannot be detected from the step on the upper surface of the interlayer insulating film 103, and subsequent mask alignment becomes impossible. Therefore, as described above, a method is employed in which the interlayer insulating film is opened and the level difference of the alignment mark is directly detected.

Referring to FIG. 25, in this method, an opening 103a for exposing alignment mark 102a is formed in interlayer insulating film 103. This allows
Even if the upper surface of the interlayer insulating film 103 is planarized by CMP, the alignment mark 102a is formed through the opening 103a.
Can be detected. Therefore, it is possible to perform alignment of a mask for patterning the upper wiring layer 105.

[0008]

However, FIG.
As described above, the type in which the opening 103a is provided in the interlayer insulating film 103 also has a problem that the alignment accuracy is significantly deteriorated. Hereinafter, this will be described in detail.

For example, when a plug layer is formed in a contact hole before forming upper wiring layer 105, referring to FIG. 26, after a conductive layer 104 for filling a contact hole is formed over the entire surface, a CMP polishing cloth is formed. Polished at 10.
Thus, the conductive layer 103 on the interlayer insulating film 103 is entirely removed, and the conductive layer 104 is left in the contact hole to form a plug layer.

In this case, the upper surface of the conductive layer 104 is somewhat polished by bending the CMP polishing cloth 110 in the opening 103a. However, as shown in FIG. 27, the conductive layer 104 on the plurality of alignment marks 102a is not polished uniformly. Therefore, a step appearing on the upper surface of the upper wiring layer covering the conductive layer 104 also becomes an asymmetric step.
It does not accurately reflect the step due to the alignment mark 102a. Therefore, the alignment accuracy in the alignment of the patterning mask on the upper wiring layer is significantly deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having good alignment accuracy even when an interlayer insulating film is flattened, and a method of manufacturing the same.

[0012]

A semiconductor device having an alignment mark according to one aspect of the present invention includes a semiconductor substrate, an alignment mark, and an insulating layer. The semiconductor substrate has a main surface. The alignment mark includes a mark layer formed on the main surface of the semiconductor substrate. The insulating layer is formed on the main surface of the semiconductor substrate and has an opening reaching the alignment mark. When the distance between a part of the side wall of the insulating layer to be the opening and the side wall of the alignment mark closest to the part of the side wall is H, the distance between the upper end of the alignment mark and the upper surface of the insulating layer is H In addition, it is H × 20 + 50 μm or more.

[0013] In the semiconductor device having the alignment mark according to one aspect of the present invention, the space between the side wall of the opening and the alignment mark is ensured sufficiently large in consideration of the bending of the polishing pad of the CMP. Therefore, even when the contact hole filling conductive layer is polished by CMP to form a plug layer in the contact hole, the contact hole filling conductive layer right above the alignment mark is polished with a CMP polishing cloth uniformly and flatly. Can be performed. Therefore, it is possible to accurately perform alignment in overlaying a mask for patterning the upper wiring layer formed on the conductive layer for filling contact holes.

A semiconductor device having an alignment mark according to another aspect of the present invention includes a semiconductor substrate, an alignment mark, and an insulating layer. The semiconductor substrate has a main surface. The alignment mark includes a mark layer formed on the main surface of the semiconductor substrate. The insulating layer is formed on the main surface of the semiconductor substrate and has an opening reaching the alignment mark. The opening has an opening diameter portion of H × 20 μm or less, where H is the distance between the upper end of the alignment mark and the upper surface of the insulating layer.

In the semiconductor device having the alignment mark according to another aspect of the present invention, the diameter of the opening is set small so that the CMP polishing cloth does not contact the conductive layer for filling the contact hole directly above the alignment mark. . Therefore, the conductive layer for embedding the contact hole on the alignment mark is not polished by the CMP polishing cloth. Therefore, it is possible to accurately perform alignment in overlaying a mask for patterning the upper wiring layer formed on the contact hole filling conductive layer.

In another aspect, the alignment mark preferably extends in a direction orthogonal to the opening in a plane.

This makes it possible to perform alignment with high accuracy. A method for manufacturing a semiconductor device having an alignment mark according to one aspect of the present invention includes the following steps.

First, a mark layer constituting an alignment mark is formed on a main surface of a semiconductor substrate. Then, an insulating layer is formed on the main surface of the semiconductor substrate so as to have an opening reaching the alignment mark. Then, a covering layer is formed so as to cover the insulating layer and the alignment mark. And by a chemical mechanical polishing method using a polishing cloth,
The covering layer on the insulating layer is removed. Then, an opening is formed in the insulating layer by a chemical mechanical polishing method so as to have an opening diameter such that the coating layer immediately above the alignment mark can be uniformly and flatly polished.

In the method of manufacturing a semiconductor device having an alignment mark according to one aspect of the present invention, the opening has an opening diameter such that the CMP polishing cloth can uniformly and flatly polish the coating layer directly above the alignment mark. Therefore, the step on the upper surface of the coating layer accurately reflects the step formed by the alignment mark and the surface of the semiconductor substrate. Therefore, alignment can be performed with high accuracy in overlaying a mask for patterning the upper wiring layer formed on the covering layer.

A method of manufacturing a semiconductor device having an alignment mark according to another aspect of the present invention includes the following steps.

First, a mark layer constituting an alignment mark is formed on a main surface of a semiconductor substrate. Then, an insulating layer is formed on the main surface of the semiconductor substrate so as to have an opening reaching the alignment mark. Then, a covering layer is formed so as to cover the insulating layer and the alignment mark. And by a chemical mechanical polishing method using a polishing cloth,
The covering layer on the insulating layer is removed. Then, an opening is formed in the insulating layer so as to have an opening diameter such that the coating layer immediately above the alignment mark is not polished by the chemical mechanical polishing method.

In the method of manufacturing a semiconductor device having an alignment mark according to another aspect of the present invention, the opening has an opening diameter such that the CMP polishing pad does not polish the coating layer immediately above the alignment mark. Therefore, the step on the upper surface of the coating layer on the alignment mark accurately reflects the step formed by the alignment mark and the surface of the semiconductor substrate. Therefore, alignment can be performed with high accuracy in overlaying a mask for patterning the upper wiring layer formed on the cover layer.

In another aspect, the alignment mark and the insulating layer are preferably formed so as to extend in the direction perpendicular to the plane of the alignment mark opening.

This makes it possible to perform alignment with high accuracy. Preferably, in the above other aspect, a signal at an edge portion of the opening generated at the time of alignment mark measurement is removed, and only a signal of the alignment mark is extracted.

This makes it possible to accurately detect the position of the alignment mark.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view schematically showing a configuration of a semiconductor device having an alignment mark according to Embodiment 1 of the present invention, and FIG.
It is a schematic sectional drawing which follows the II line.

Referring to FIGS. 1 and 2, on the surface of silicon substrate 1, lower wiring layer 2 and mark layer 2a are formed separately from the same layer by patterning. The mark layer 2a is provided with a plurality of concave alignment marks 2b, forming an image recognition type FIA mark. An interlayer insulating film 3 is formed on lower wiring layer 2 and mark layer 2a, and the upper surface of interlayer insulating film 3 is planarized by, for example, CMP.

The interlayer insulating film 3 is provided with, for example, a contact hole 3a reaching the lower wiring layer 2 and an opening 3b reaching a plurality of alignment marks 2b.
The plug hole 4 is filled in the contact hole 3a, and the conductive layer 4 for filling the contact hole is filled in the opening 3b.
Remains. An upper wiring layer 5 is formed on the interlayer insulating film 3, and is electrically connected to the lower wiring layer 4 via a plug layer 4.

In this configuration, the side wall of the opening 3b
The distance L ₁ between the side wall of the alignment mark 2 b located closest to the side wall of the opening 3 b is H × H, where H is the distance between the upper surface of the mark layer 2 a and the upper surface of the interlayer insulating film 3.
The size is set to 20 + 50 μm or more.

The distance L ₁ is, for example, 80 μm when the distance H between the upper surface of the mark layer 2 a and the upper surface of the interlayer insulating film 3 is about 700 nm. In this case, the total length of the opening 3b in the horizontal direction in FIG. 1 is about 260 μm.

Next, the manufacturing method of the present embodiment will be described. 3 and 4 are schematic sectional views showing a method of manufacturing a semiconductor device having an alignment mark according to the first embodiment of the present invention in the order of steps. Referring to FIG. 3, a conductive layer is formed on the surface of silicon substrate 1, and is patterned by ordinary photolithography and etching. Thereby, the lower wiring layer 2 and the mark layer 2a constituting the concave alignment mark 2b are formed from the conductive layer. Interlayer insulating film 3 is formed so as to cover lower wiring layer 2 and mark layer 2a. The upper surface of interlayer insulating film 3 is planarized by, for example, CMP. After this,
A contact hole 3a and an opening 3b are formed in the interlayer insulating film 3 by ordinary photolithography and etching. At this time, the interval L ₁ is H × 20 + 50 μm
The opening 3b is formed as described above. Thereafter, a conductive layer 4 for filling a contact hole is formed on the entire surface so as to fill the contact hole 3a.

Referring to FIG. 4, conductive layer 4 for filling contact holes on interlayer insulating film 3 is formed by polishing pad 10 of CMP.
Is removed, plug layer 4 is formed in contact hole 3a, and conductive layer 4 remains in opening 3b. During the CMP, the conductive layer 4 on the plurality of alignment marks 2b in the opening 3b is somewhat removed by the bending of the polishing pad 10.

Thereafter, after a conductive layer for an upper wiring layer is formed on the entire surface, a photoresist is applied on the conductive layer for the upper wiring layer. This photoresist is patterned by exposure and development. The exposure of the photoresist is performed by irradiating the photoresist with light through a mask (reticle) aligned with the lower wiring layer 2 based on the position detection signals of the plurality of alignment marks 2b. By etching the conductive layer for the upper wiring layer using the patterned photoresist as a mask, the upper wiring layer 5 shown in FIGS. 1 and 2 is formed. Thereafter, the resist pattern is removed by ashing or the like, and a semiconductor device having the alignment marks shown in FIGS. 1 and 2 is completed.

The concave alignment mark 2b shown in FIGS. 1 and 2 is, for example, an image recognition type FIA mark formed with a groove type mark. Here, the image recognition type is a method in which there are scanning lines in the horizontal direction, the scanning lines are detected one by one, and they are added and averaged, and the center position is measured from the waveform. The Y direction is measured separately. The FIA mark method is a method in which one image data is taken in the scanning line direction and one data is obtained by averaging a plurality of image data.

According to this method, if the mark portion (step) is asymmetric with respect to the horizontal direction in FIG. 1, the waveform of the mark is affected, but the influence is small in the vertical direction in FIG. Therefore, drawing vertical spacing L ₂ between the side wall of the alignment marks 2b and the opening 3b in FIG. 1, the distance L ₁
It is not necessary to secure a large size as in the above. However, as long as minimize the effect of the mark waveform by asymmetry of the mark portion (stepped portion), interval L ₂ also comparable to the interval L ₁ in the vertical direction in the drawing (= H × 20 + 50μm or more) is preferably set to.

In this embodiment, the groove type mark structure has been described. However, the present invention can be similarly applied to a plateau type structure as shown in FIG. Referring to FIG. 5, in the mark structure of the plateau-remaining type, alignment mark 2c is formed in a convex shape by a mark layer. The distance L between the side wall of the opening 3b and the side surface of the convex alignment mark 2c closest to the side wall.
₁ is set so as to be H × 20 + 50 μm or more when the distance between the upper end of the alignment mark 2c and the upper surface of the interlayer insulating film 3 is H.

The remaining structure is almost the same as that of the first embodiment, and therefore the same members are denoted by the same reference characters and description thereof will not be repeated.

Although the number of alignment marks has been described as seven, the number is not limited to seven and may be one or more.

[0040] In this embodiment, the distance L ₁ between the sidewall and the alignment marks 2b of the opening portion 3b (2c) is secured sufficiently large in consideration of the deflection of the polishing cloth 10 of the CMP. For this reason, in FIG.
(2c) The upper conductive layer 4 is polished uniformly and flat by the polishing pad 10 of CMP. Therefore, the steps of the conductive layer 4 on the alignment marks 2b accurately reflect the steps formed by the alignment marks 2b and the surface of the silicon substrate 1. Therefore, alignment can be performed with high accuracy in overlaying a mask for patterning the upper wiring layer 5.

(Embodiment 2) FIG. 6 is a plan view schematically showing a configuration of a semiconductor device having an alignment mark according to Embodiment 2 of the present invention, and FIG. 7 is a VII of FIG.
It is a schematic sectional drawing which follows the VII line.

Referring to FIGS. 6 and 7, on the surface of silicon substrate 1, wiring layer 2 and mark layer 2a are formed separately from the same layer by patterning. The mark layer 2a is provided with a plurality of concave alignment make-ups 2b to form an image recognition type FIA mark. An interlayer insulating film 3 is formed on lower wiring layer 2 and mark layer 2a, and the upper surface of interlayer insulating film 3 is planarized by, for example, CMP.

The interlayer insulating film 3 is provided with, for example, a contact hole 3a reaching the lower wiring layer 2 and an opening 3b reaching the alignment mark 2b. The plug layer 4 is filled in the contact hole 3a,
The conductive layer 4 for embedding a contact hole remains in the opening 3b. An upper wiring layer 5 is formed on the interlayer insulating film 3, and is electrically connected to the lower wiring layer 2 via a plug layer 4.

In this configuration, when the distance between the upper surface of the mark layer 2a and the upper surface of the interlayer insulating film 3 is H, the opening 3b has an opening diameter portion of H × 20 μm or less.

Next, the manufacturing method of the present embodiment will be described. 8 and 9 are schematic sectional views showing a method of manufacturing a semiconductor device having an alignment mark according to the second embodiment of the present invention in the order of steps. Referring to FIG. 8, a conductive layer is formed on the surface of silicon substrate 1, and is patterned by ordinary photolithography and etching. Thereby, the lower wiring layer 2 and the mark layer 2a constituting the concave alignment mark 2b are formed from the conductive layer. Interlayer insulating film 3 is formed so as to cover lower wiring layer 2 and mark layer 2a. The upper surface of interlayer insulating film 3 is planarized by, for example, CMP. After this,
A contact hole 3a and a plurality of openings 3b are formed in the interlayer insulating film 3 by ordinary photolithography and etching techniques. At this time, the opening 3b has the opening diameter L
₃ (H × 20 μm or less). Thereafter, a conductive layer 4 for filling a contact hole is formed on the entire surface so as to fill the contact hole 3a.

Referring to FIG. 9, conductive layer 4 for embedding contact holes on interlayer insulating film 3 is formed by polishing pad 10 of CMP.
Is removed, plug layer 4 is formed in contact hole 3a, and conductive layer 4 remains in opening 3b. In this CMP, the polishing pad 10 does not contact the conductive layer 4 directly above the alignment mark 2b.

Thereafter, a conductive layer for the upper wiring layer is formed on the entire surface, and a photoresist is applied on the conductive layer for the upper wiring layer. The mask is an alignment mark 2b
Is positioned with respect to the lower wiring layer 2 based on the position detection signal. After the photoresist is exposed through this mask, it is developed and patterned. By etching the conductive layer for the upper wiring layer using this resist pattern as a mask, upper wiring layer 5 shown in FIGS. 6 and 7 is formed.

In the above-described image recognition type alignment method, as shown in FIG. 10, the signal of the edge of the opening 3b and the signal of the alignment mark 2b appear simultaneously. Therefore, alignment measurement is performed by extracting only the signal of the alignment mark 2b by signal analysis.

In this embodiment, the groove type mark structure has been described. However, the present invention can be applied to a plateau type structure as shown in FIG. Referring to FIG. 11, in the plateau-remaining type structure, alignment mark 2c is formed in a convex shape by a mark layer. The opening 3b at this time is also set to have the same opening diameter L ₃ (H × 20 μm or less) as described above.

The remaining structure is almost the same as the structure shown in FIGS. 6 and 7, and the same members are denoted by the same reference characters and description thereof will be omitted.

In the present embodiment, as shown in FIG.
The diameter of the opening 3b is set small so that the P polishing cloth 10 does not polish the conductive layer 4 directly above the alignment mark 2b. Therefore, the step on the upper surface of the conductive layer 4 on the alignment mark 2b accurately reflects the step formed by the alignment mark 2b and the surface of the silicon substrate 1. Therefore, alignment can be performed with high accuracy in overlaying a mask for patterning the upper wiring layer 5.

(Embodiment 3) FIG. 12 is a plan view schematically showing a configuration of a semiconductor device having an alignment mark according to Embodiment 3 of the present invention, and FIG. 13 is taken along line XIII-XIII of FIG. It is an outline sectional view.

Referring to FIGS. 12 and 13, the present embodiment differs from the second embodiment in the method of alignment marks. That is, in the second embodiment, the image recognition type FIA mark system has been described, but the alignment mark of the present embodiment is a diffracted light detection type LSA mark system. That is, when the laser scanning direction is the direction of arrow A in FIG. 12, a plurality of alignment marks 2b are arranged in a direction orthogonal to the laser scanning direction. The plurality of alignment marks 2b arranged in the vertical direction in FIG. 12 are arranged in one opening 3b.

The remaining structure is almost the same as that of FIGS. 6 and 7 described above, and the same members are denoted by the same reference characters and description thereof will be omitted.

Here, the diffracted light detection type is based on the principle that when a laser beam is moved in the scanning direction, a diffracted light is generated in a direction perpendicular to the scanning direction when passing over a dot mark of 8 μm pitch. Means to detect the position of the mark. LSA refers to a sensor for detecting a position of an alignment mark by scanning a mark on a wafer with a laser beam. Here, when the LSA laser beam and the LSA mark formed on the wafer overlap, a diffracted light is generated, and the accurate position of the LSA mark can be obtained from the intensity waveform of the generated diffracted light.

In the alignment system of the diffracted light detection type, as shown in FIG. 14, no diffracted light is generated from the edge of the opening 3b, and only the diffracted light from the alignment mark 2b is obtained. Therefore, a good signal is obtained, and alignment measurement can be performed with high accuracy.

Although the groove type mark structure has been described in the present embodiment, the present invention can be applied to a plateau type structure as shown in FIG. Referring to FIG. 15, in the structure of the plateau-remaining type, alignment mark 2c is formed in a convex shape by a mark layer.

The remaining structure is almost the same as the structure shown in FIGS. 12 and 13 described above. Therefore, the same members are denoted by the same reference numerals and description thereof will be omitted.

In this embodiment, as in the above-described second embodiment, the diameter of the opening 3b is set small so that the polishing pad 10 of CMP does not polish the conductive layer 4 directly above the alignment mark. Therefore, alignment mark 2
b on the upper surface of the conductive layer 4
The step shape formed by b and the surface of the silicon substrate 1 is accurately reflected. Therefore, alignment can be performed with high accuracy in overlaying a mask for patterning the upper wiring layer 5.

(Fourth Embodiment) FIG. 16 is a plan view schematically showing a configuration of a semiconductor device having an alignment mark according to a fourth embodiment of the present invention.
8 is the XVII-XVII line and XVIII-
It is a schematic sectional drawing which follows the XVIII line.

Referring to FIGS. 16 to 18, on the surface of silicon substrate 1, lower wiring layer 2 and mark layer 2a are formed separately from the same layer by patterning. A concave alignment mark 2b is formed on the mark layer 2a to form an image recognition type FIA mark. An interlayer insulating film 3 is formed on lower wiring layer 2 and mark layer 2a, and the upper surface of interlayer insulating film 3 is planarized by, for example, CMP.

A contact hole 3a reaching the lower wiring layer 2 and a plurality of alignment marks 2b are formed in the interlayer insulating film 3.
The opening 3b is formed. This opening 3
b and the alignment mark 2b are arranged so as to be orthogonal to each other in a plane.

The plug layer 4 is filled in the contact hole 3a, and the conductive layer 4 for filling the contact hole remains in the opening 3b. An upper wiring layer 5 is formed on the interlayer insulating film 3, and is electrically connected to the lower wiring layer 2 via a plug layer 4.

[0064] In this configuration, the opening portion 3b, the distance between the upper surface and the upper surface of the interlayer insulating film 3 of the mark layer 2a is taken as H, and a opening diameter L ₃ parts: H × 20 [mu] m ( (FIG. 18).

Next, the manufacturing method of the present embodiment will be described. 19 and 20 are schematic sectional views showing a method of manufacturing a semiconductor device having an alignment mark according to the fourth embodiment of the present invention in the order of steps. Referring to FIG. 19, a conductive layer is formed on the surface of silicon substrate 1, and is patterned by ordinary photolithography and etching. Thereby, the lower wiring layer 2 and the mark layer 2a constituting the concave alignment mark 2b are formed from the conductive layer. Interlayer insulating film 3 is formed so as to cover lower wiring layer 2 and mark layer 2a. The upper surface of interlayer insulating film 3 is planarized by, for example, CMP. Thereafter, the contact hole 3a and the opening 3b are formed in the interlayer insulating film 3 by ordinary photolithography and etching techniques.
Is formed. At this time, the opening 3b has the opening diameter L
₃ (H × 20 μm or less). Thereafter, a conductive layer 4 for embedding a contact hole is formed on the entire surface so as to embed the inside of the contact hole 3a.

Referring to FIG. 20, the contact hole burying conductive layer 4 on interlayer insulating film 3 is removed by CMP polishing cloth 10, whereby plug layer 4 is formed in contact hole 3a. Part of the conductive layer 4 remains in the opening 3b. During this CMP, the polishing pad 10 does not contact the conductive layer 4 directly above the alignment mark 72b.

Thereafter, a conductive layer for the upper wiring layer is formed on the entire surface, and a photoresist is applied on the conductive layer for the upper wiring layer. The mask is an alignment mark 2b
Is positioned with respect to the lower wiring layer 2 based on the position detection signal. After the photoresist is exposed through this mask, it is developed and patterned. By etching the conductive layer for the upper wiring layer using this resist pattern as a mask, upper wiring layer 5 shown in FIGS. 16 and 17 is obtained.

In this embodiment, the alignment mark 2
b is provided so as to be orthogonal to the opening 3b,
A good signal clearly indicating the alignment mark 2b as shown in FIG. 21 is obtained, and alignment measurement can be performed with high accuracy.

Although the groove type mark structure has been described in the present embodiment, the present invention can also be applied to the plateau-remaining type mark structure shown in FIGS. 22 and 23. FIG. 22 shows XVII- in FIG.
FIG. 23 corresponds to the section taken along line XVII of FIG.
It corresponds to a cross section taken along line I-XVIII.

Referring to FIG. 15, FIG. 22 and FIG.
In the mark structure of the plateau leaving type, the alignment mark 2c is formed in a convex shape by the mark layer.

The remaining structure is substantially the same as that of FIGS. 16 to 18 described above, and the same members are denoted by the same reference characters and description thereof will be omitted.

Also in this embodiment, the diameter of the opening 3b is set to be small so that the polishing pad 10 of CMP does not polish the conductive layer 4 just above the alignment mark, as in the second embodiment. Therefore, alignment mark 2
b on the upper surface of the conductive layer 4
The step shape formed by b and the surface of the silicon substrate 1 is accurately reflected. Therefore, alignment can be performed with high accuracy in overlaying a mask for patterning the upper wiring layer 5.

In the second embodiment, the alignment mark 2a (or 2b) extends in a direction parallel to the direction in which the opening 3b extends in a plan view. In the image-recognition type alignment mark in this case, diffracted light is also generated from the edge of the opening 3b as shown in FIG. For this reason, the signal at the edge of the opening 3b is removed by removing the signal at the edge of the opening 3b to extract only the signal of the alignment mark. There is a need to avoid signals.

On the other hand, in the present embodiment,
As shown in FIG. 16, the alignment mark 2b (or 2)
c) extends in a direction orthogonal to the direction in which the opening 3b extends in a plan view. In this case, the image recognition type alignment mark also recognizes the edge of the opening 3b, but the alignment mark 2b (or 2c) produces a stronger waveform due to the waveform processing, and therefore the alignment mark 2b (or 2c). Can be aligned only for In the case of a diffraction light detection type alignment mark,
Since only the diffracted light generated at a certain angle is measured by the detector, the diffracted light exceeding the detection range is not detected. By utilizing this, the pitch of the openings 3b is formed in a dense pattern, so that diffracted light generated from the openings 3b is excluded.
Alignment can be performed only on the alignment mark.

The first, second and fourth embodiments described above
In the above, description has been made by taking an example of an FIA mark that is an image recognition type, but the present invention is not limited to this, and the present invention can be applied to any other image recognition type mark. In the third embodiment, the LSA mark of the diffracted light detection type has been described as an example. However, the present invention is not limited to this, and the present invention can be applied to any other types of diffracted light detection type marks.

In the first to fourth embodiments, the material of the lower wiring layer 2, the mark layer 2a, the upper wiring layer 5, and the plug layer 4 may be a conductive material, and may be polycrystalline silicon (doped) doped with impurities. Polysilicon), tungsten silicide (WSi), titanium silicide (TiSi),
Polycide composed of silicide such as cobalt silicide (CoSi), tantalum silicide (TaSi), and molybdenum silicide (MoSi) may be used, or aluminum (Al), aluminum / copper (AlC)
u), aluminum, silicon, copper (AlSiCu),
Tungsten (W), cobalt (Co), titanium (T
i), copper (Cu), platinum (Pt), ruthenium (Ru)
Metal materials such as titanium nitride (TiN), tantalum oxide (TiO), ruthenium oxide (RuO ₂ ), BST
(BaSrTiO ₃ ), strontium titanate (Sr
High dielectric constant materials such as TiO ₃ ) and lead zirconate titanate (PZT) may be used.

The material of the interlayer insulating film 3 may be any insulating material, and may be a transparent film such as silicon oxide (SiO ₂ ), a low dielectric constant interlayer film, a translucent film, or an opaque film.

The polishing cloth 10 in the first to fourth embodiments is, for example, a polishing cloth having a hardness (ASKER-C) of 95, but is not limited to this.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0080]

In the semiconductor device having the alignment mark according to one aspect of the present invention, the distance between the side wall of the opening and the alignment mark is sufficiently large in consideration of the bending of the polishing pad of the CMP. Therefore, even when the contact hole filling conductive layer is polished by CMP to form a plug layer in the contact hole, the contact hole filling conductive layer immediately above the alignment mark is uniformly and flatly polished with a CMP polishing cloth. Can be performed. Therefore, it is possible to accurately perform alignment in overlaying a mask for patterning the upper wiring layer formed on the conductive layer for filling contact holes.

In the semiconductor device having the alignment mark according to another aspect of the present invention, the diameter of the opening is set small so that the CMP polishing cloth does not contact the conductive layer for filling the contact hole directly above the alignment mark. . Therefore, the conductive layer for embedding the contact hole on the alignment mark is not polished by the CMP polishing cloth. Therefore, it is possible to accurately perform alignment in overlaying a mask for patterning the upper wiring layer formed on the contact hole filling conductive layer.

In the above other aspect, preferably, a part of the side wall of the alignment mark forms a wall surface which is continuous with a part of the side wall of the insulating layer to be an opening. This allows
Alignment can be performed with high accuracy.

In the method of manufacturing a semiconductor device having an alignment mark according to one aspect of the present invention, the opening has an opening diameter such that the CMP polishing cloth can uniformly and flatly polish the coating layer directly above the alignment mark. Therefore, the step on the upper surface of the coating layer accurately reflects the step formed by the alignment mark and the surface of the semiconductor substrate. Therefore, alignment can be performed with high accuracy in overlaying a mask for patterning the upper wiring layer formed on the covering layer.

In the method of manufacturing a semiconductor device having an alignment mark according to another aspect of the present invention, the opening has an opening diameter such that the CMP polishing pad does not polish the coating layer immediately above the alignment mark. Therefore, the step on the upper surface of the coating layer on the alignment mark accurately reflects the step formed by the alignment mark and the surface of the semiconductor substrate. Therefore, alignment can be performed with high accuracy in overlaying a mask for patterning the upper wiring layer formed on the cover layer.

In the above other aspect, preferably, the alignment mark and the insulating layer are formed so as to extend in a direction orthogonal to the plane of the alignment mark opening.
Thereby, alignment can be performed with high accuracy.

In the above other aspect, preferably, the signal at the edge of the opening, which is generated at the time of alignment mark measurement, is removed, and only the signal of the alignment mark is extracted. This makes it possible to accurately detect only the alignment mark signal.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a configuration of a semiconductor device having an alignment mark according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view taken along line II-II in FIG.

FIG. 3 is a schematic cross-sectional view showing a first step of a method for manufacturing a semiconductor device having an alignment mark according to the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a second step of the method for manufacturing a semiconductor device having an alignment mark according to the first embodiment of the present invention.

FIG. 5 is a schematic sectional view showing a configuration of a semiconductor device having a plateau-type alignment mark according to the first embodiment of the present invention;

FIG. 6 is a plan view schematically showing a configuration of a semiconductor device having an alignment mark according to a second embodiment of the present invention.

FIG. 7 is a schematic sectional view taken along the line VII-VII in FIG.

FIG. 8 is a schematic sectional view showing a first step of a method for manufacturing a semiconductor device having an alignment mark according to the second embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing a second step of the method for manufacturing a semiconductor device having an alignment mark according to the second embodiment of the present invention.

FIG. 10 is a diagram showing an alignment signal of a semiconductor device having an alignment mark according to the second embodiment of the present invention.

FIG. 11 is a schematic sectional view showing a configuration of a semiconductor device having a plateau-type alignment mark according to a second embodiment of the present invention;

FIG. 12 is a plan view schematically showing a configuration of a semiconductor device having an alignment mark according to a third embodiment of the present invention.

FIG. 13 is a schematic sectional view taken along line XIII-XIII of FIG.

FIG. 14 is a diagram showing an alignment signal of a semiconductor device having an alignment mark according to the third embodiment of the present invention.

FIG. 15 is a cross sectional view schematically showing a configuration of a semiconductor device having a plateau-type alignment mark according to a third embodiment of the present invention.

FIG. 16 is a plan view schematically showing a configuration of a semiconductor device having an alignment mark according to a fourth embodiment of the present invention.

FIG. 17 is a schematic sectional view taken along the line XVII-XVII in FIG. 16;

FIG. 18 is a schematic sectional view taken along line XVIII-XVIII in FIG.

FIG. 19 is a schematic cross-sectional view showing a first step of a method for manufacturing a semiconductor device having an alignment mark according to the fourth embodiment of the present invention.

FIG. 20 is a schematic cross-sectional view showing a second step of the method for manufacturing a semiconductor device having an alignment mark according to the fourth embodiment of the present invention.

FIG. 21 is a diagram showing an alignment signal of a semiconductor device having an alignment mark according to the fourth embodiment of the present invention.

FIG. 22 is a cross sectional view schematically showing a configuration of a semiconductor device having a plateau-type alignment mark according to a fourth embodiment of the present invention.

FIG. 23 is a sectional view schematically showing a configuration of a semiconductor device having a plateau-type alignment mark according to a fourth embodiment of the present invention;

FIG. 24 is a schematic cross-sectional view showing a configuration near an alignment mark when a conventional interlayer insulating film is not flattened.

FIG. 25 is a schematic cross-sectional view showing a configuration near an alignment mark when the interlayer insulating film is flattened.

FIG. 26 is a schematic cross-sectional view showing how CMP is performed in the configuration of FIG. 25;

FIG. 27 is a schematic cross-sectional view showing a state where a step is asymmetrically polished by CMP.

[Explanation of symbols]

1 silicon substrate, 2 lower wiring layer, 2a mark layer,
2b, 2c alignment mark, 3 interlayer insulating film, 3
a contact hole, conductive layer for filling contact hole, 5 upper wiring layer.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akihiro Nakae 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (72) Inventor Tadashi Shimizu 1-1-1, Sachicho, Takatsuki-shi, Osaka Matsushita Electronics Industry Co., Ltd. (72) Inventor Takashi Watanabe 1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. F-term (reference) 5F046 EA03 EA09 EA12 EA13 EA18 EA22 EB01 EB05

Claims (7)

[Claims] A semiconductor substrate having a main surface; an alignment mark including a mark layer formed on the main surface of the semiconductor substrate; and an alignment mark formed on the main surface of the semiconductor substrate and reaching the alignment mark. An insulating layer having an opening, wherein a distance between a part of a side wall of the insulating layer to be the opening and a side wall of the alignment mark closest to a part of the side wall is an upper end of the alignment mark. H × 20 + 50, where H is the distance between the substrate and the upper surface of the insulating layer.
A semiconductor device having an alignment mark, which is not less than μm. A semiconductor substrate having a main surface; an alignment mark formed of a mark layer formed on the main surface of the semiconductor substrate; and an alignment mark formed on the main surface of the semiconductor substrate and reaching the alignment mark. An insulating layer having an opening, wherein the opening has an opening diameter portion of H × 20 μm or less when an interval between an upper end of the alignment mark and an upper surface of the insulating layer is H. Semiconductor device having an alignment mark. 3. A part of a side wall of the alignment mark extends in a direction perpendicular to the opening in a plane.
A semiconductor device having the alignment mark according to claim 2. 4. A step of forming a mark layer constituting an alignment mark on a main surface of a semiconductor substrate, and forming an insulating layer on the main surface of the semiconductor substrate so as to have an opening reaching the alignment mark. A step of forming a coating layer so as to cover the insulating layer and the alignment mark; anda step of removing the coating layer on the insulating layer by a chemical mechanical polishing method using a polishing cloth. An alignment mark, wherein the opening is formed in the insulating layer so as to have an opening diameter such that the coating layer immediately above the alignment mark can be uniformly and flatly polished by the chemical mechanical polishing method. A method for manufacturing a semiconductor device. 5. A step of forming a mark layer constituting an alignment mark on a main surface of a semiconductor substrate, and forming an insulating layer on the main surface of the semiconductor substrate so as to have an opening reaching the alignment mark. A step of forming a coating layer so as to cover the insulating layer and the alignment mark; anda step of removing the coating layer on the insulating layer by a chemical mechanical polishing method using a polishing cloth. Manufacturing a semiconductor device having an alignment mark, wherein the opening is formed in the insulating layer so as to have an opening diameter such that the coating layer immediately above the alignment mark is not polished by the chemical mechanical polishing method. Method. 6. The method of manufacturing a semiconductor device having an alignment mark according to claim 5, wherein said alignment mark and said insulating layer are formed such that said alignment mark extends in a direction orthogonal to said opening in a plane. . 7. The method for manufacturing a semiconductor device having an alignment mark according to claim 5, wherein a signal generated at the time of measuring the alignment mark at an edge portion of the opening is removed, and only a signal of the alignment mark is extracted.