JP3019839B2 - Semiconductor device having overlay measurement mark and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a mark for measuring overlay accuracy with a base in a pattern forming step, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been increasingly miniaturized as the degree of integration has increased. One of the most important technologies in miniaturization is an exposure technology (photolithography technology). Hereinafter, an example of manufacturing a semiconductor device using the photolithography technique will be described.

First, a first conductive layer is formed on a substrate on which a pattern is to be formed. A photoresist is applied, exposed, and a pattern is formed by development. Thereafter, a base pattern is formed by etching. Further, an insulating interlayer film is formed on the substrate having the base pattern formed by the etching or the like. Next, alignment is performed on the base pattern already formed to form a contact hole pattern. This forming method is ordinary photo etching.

Further, a second conductive layer is formed. In recent years, a burying step with tungsten is often performed in this step. After this embedding step, for example, an aluminum alloy is formed as a second conductive layer by a sputtering method. Next, a photoresist is applied, and exposure and development are performed to form a pattern with the photoresist on the second conductive layer.

As described above, when the resist pattern is superimposed on the contact hole pattern which is the underlying pattern, it is most preferable that the two patterns be superimposed without displacement, and even if there is a displacement, the amount of the displacement is limited. It must be less than the fixed amount. Therefore, such overlay deviation is measured using a predetermined mark. Conventionally, a box-in-box mark as shown in FIG. 7 is generally used as this mark.

FIG. 7A is a plan view showing a conventional overlay measurement mark, and FIG. 7B is a cross-sectional view taken along line 6b-6b shown in FIG. 7A. The overlay measurement mark is provided in a scribe line area of the wafer (an area for finally separating as a chip). The overlay measurement mark includes an outer box mark 11 and an inner box mark 12. One mark, for example, the outer box mark 11 is created at the same time as the formation of the contact hole as the base pattern,
2 is formed by a photoresist pattern.

That is, as shown in FIG. 7B, an interlayer film 23 is formed on the first conductive layer 21 and the interlayer film 2 is formed.
In 3, a contact hole (not shown) for connecting the first conductive layer 21 and a second conductive layer 25 described later is formed, and at the same time, an opening 23 a having a pattern area larger than the contact hole is formed. The opening 23a becomes the outer box mark 11. Next, after tungsten (not shown) is embedded in the contact hole, a second conductive layer (aluminum wiring layer) 25 is deposited in the opening 23a and on the interlayer film 23. Next, a photoresist pattern is formed on the wiring layer 25. Of these patterns, the pattern 27 formed on the opening 23a becomes the inner box mark 12.

[0008] By measuring the displacement of the two box marks 11 and 12, that is, by performing the overlay measurement, the displacement between the contact hole pattern and the aluminum wiring pattern can be measured. The center of the pattern of the inner box mark 12 is the outer box mark 1
The case where the pattern mark coincides with the center of the pattern No. 1 is a state where there is no displacement between the two box marks 11 and 12.

The purpose of such overlay measurement is to confirm that the shift amount is within a predetermined range, and to correct the overlay shift by feeding back the measurement result of the shift amount to an exposure apparatus. And so on.

[0010]

The step of embedding tungsten in the contact hole is performed by depositing a tungsten layer in the contact hole, in the opening 23a and on the interlayer film 23, and then etching back this layer. Tungsten is buried in the contact hole (etch back method of tungsten). When this etch back is performed, the pattern area of the opening 23a forming the outer box mark 11 is larger than the pattern area of the contact hole, so that tungsten in the opening 23a is not sufficiently etched back. . Specifically, the pattern shape of the opening 23a is 25 μm on one side.
The contact hole has a rectangular shape with a side of 2.5 μm to 10 μm. Therefore, as shown in FIG. 7, the tungsten residue 13 remains on the inner wall (outside box mark) of the opening 23a in a sidewall shape. Thus, even when the overlay measurement for optically observing the overlay measurement mark is performed in a state where the tungsten residue 13 remains, it is difficult to perform an accurate measurement.

That is, in this overlay measurement, FIG.
Light is irradiated from above (in the direction perpendicular to the paper surface) the overlay measurement mark shown in FIG. 7A, and the reflected light is detected to capture the mark. The pattern of the box marks 11 and 12 is obtained from the captured data. The position is recognized, and the deviation amount between the center of the outer box mark 11 and the center of the inner box mark 12 is measured. When the overlay measurement mark is imaged, the outer box mark (i.e., the inner wall of the opening) 11 is rough due to the tungsten residue 13, so that the pattern shape of the outer box mark 11 (i.e., the inner wall of the opening) is obtained. ) Cannot be detected accurately. Therefore, the accuracy and reproducibility of the overlay measurement are reduced.

FIG. 8 is a waveform diagram when the overlay measuring mark shown in FIG. 7 is observed by an optical measuring device. FIG.
7 indicate the outer box mark 11 shown in FIG. 7, and the two inner waves 35 and 37 shown in FIG. 8 correspond to the inner box mark 12 shown in FIG.
It is shown. Wave 3 outside this optical measurement
The reason why 1, 33 is not smooth is that the outer box mark 11 is rough due to the tungsten residue 13 as described above. Thus the outer wave 3
If 1, 33 is not smooth, the outer box mark 11 cannot be accurately detected.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device having an overlay measurement mark capable of improving the accuracy and reproducibility of overlay measurement, and a semiconductor device having the same. It is to provide a manufacturing method.

[0014]

In order to solve the above-mentioned problems, a semiconductor device having an overlay measurement mark according to the present invention is provided with a mark for measuring overlay of a first pattern and a second pattern. It is characterized in that it is formed by an outer box mark and an inner box mark, and at least one of the two box marks is formed in a square by rectangular or circular dots.

Further, the present invention is characterized in that a conductive material is embedded in a rectangular box mark with rectangular or circular dots. Further, the semiconductor device having the overlay measurement mark of the present invention includes a pattern formed by the first conductive layer, a pattern formed by the second conductive layer, a pattern formed by the first conductive layer, and a pattern formed by the second conductive layer. An insulating layer for insulation, having an opening in the insulating layer to electrically connect the pattern of the first conductive layer and the pattern of the second conductive layer, wherein the opening and the second conductive layer The mark for measuring the superposition of the patterns is characterized by being formed in a rectangular shape by rectangular or circular dots.

According to the present invention, a rectangular or circular dot is formed in a square by the above configuration, whereby the side wall of the pattern becomes optically smooth, and the overlay measurement accuracy and measurement reproducibility can be improved. It is.

The method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film on a first conductive layer, and forming the first conductive layer and a second conductive layer described later on the interlayer insulating film. And a plane pattern formed of a plurality of openings is a frame-shaped or square first box mark, and the pattern area of each opening is equal to that of the connection hole. A step of forming a first box mark that is 5 times or more and 2 times or less, a step of embedding a filling material in the connection hole and the opening by an etch-back method, and A step of forming a second conductive layer and a step of forming a photoresist pattern on the second conductive layer, wherein a plane located on the second conductive layer and above the first box mark Square pattern Forming a photoresist pattern having a second box mark, and optically observing the first and second box marks to determine the positions of the first and second box marks. The overlay of the connection hole pattern and the photoresist pattern is measured by detecting a shift.

In the method of manufacturing a semiconductor device, a plurality of openings having a pattern area of 0.5 to 2 times the pattern area of the connection hole are formed in the interlayer insulating film, and the openings are formed in the first box mark. Used as For this reason, the embedding material to be embedded in the connection hole by the etch back method is completely embedded in the opening. Thereby, when the first and second box marks are optically observed, a smooth optical measurement waveform diagram can be obtained, and the positions of both box marks can be detected with high accuracy. As a result, the accuracy and reproducibility of the overlay measurement can be improved.

According to the present invention, there is provided a semiconductor device having an overlay measurement mark, comprising: an interlayer insulating film formed on a first conductive layer; and a planar pattern comprising a plurality of openings formed in the interlayer insulating film. Is a frame-shaped or square first box mark, and an embedding material embedded in the opening,
A second conductive layer formed on the interlayer insulating film, and a second box mark formed on the first box mark and having a rectangular planar pattern formed by a part of the second conductive layer. And characterized in that:

In the interlayer insulating film, a connection hole for electrically connecting the second conductive layer and the first conductive layer is formed, and the opening has a pattern area of the connection hole. The filling material may be formed to be 0.5 times or more and 2 times or less of that of the above, and the filling material may be buried in the connection hole.

In the second box mark, a photoresist pattern formed of a box pattern located on the second conductive layer and above the first box mark is transferred to the second conductive layer. Preferably, it is

Further, the first box mark and the box pattern are optically observed to detect a displacement between the first box mark and the box pattern, thereby obtaining a pattern of the connection hole. It is preferable to measure the overlap between the photoresist pattern and the photoresist pattern.

Preferably, the planar shape of the opening is rectangular or circular.

Further, it is preferable that the filling material is a conductive material. This conductive material may be, for example, tungsten.

The opening has a diameter of 0.3 μm.
It is preferably a rectangle or a circle having a size of 1 μm or less.
The opening has a diameter of 0.5 μm or more and 0.6 μm or more.
More preferably, it is a rectangle or a circle of m or less.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing an overlay measurement mark used in the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a sectional view taken along line 22-22 shown in FIG. The overlay measurement mark is provided on the scribe line area of the wafer or on the semiconductor chip.

The outer box mark 1 shown in FIG. 1 is created by an embedding process using, for example, an etch-back method of tungsten. The outer box mark 1 is formed of a tungsten material embedded in the plurality of openings 4a. In the openings 4a, the dot-shaped openings 4a are arranged in a rectangular frame as a whole. Each opening 4a is formed in a square pattern. The whole of the plurality of openings 4a constitutes the outer box mark 1. The outer box mark 1 has a square shape of 25 μm on a side as a whole, and each opening (ie, each dot) 4a has a square shape of 0.5 μm on a side.

The inner box mark 2 is formed of a resist pattern 2a for patterning a layer to be overlapped (ie, the second conductive layer 5). The inner box mark 2 has a square pattern with a plane shape of 10 μm on a side.

In the step of burying the outer box mark 1 in the interlayer film 4 between the first conductive layer 3 and the second conductive layer 5 shown in FIG. 2, tungsten is buried. That is, as shown in FIG. 2, an interlayer film 4 is formed on the first conductive layer 3 and the first conductive layer 3
At the same time, a plurality of openings 4a having the same pattern area as the contact hole are formed. Next, tungsten 19 is buried in the contact hole and the opening 4a. The tungsten 19 buried in the plurality of openings 4a becomes the outer box mark 1. Thereafter, a second conductive layer 5 is deposited on the interlayer film 4, and a photoresist pattern is formed on the second conductive layer 5. Of these patterns, the pattern 2a formed on the outer box mark 1 becomes the inner box mark 2.

However, after patterning the second conductive layer 5 using the photoresist pattern, an inner box mark is transferred to the patterned second conductive layer.

Although the present embodiment shows an example of the dot arrangement (the arrangement of the openings 4a), the arrangement is not limited to this, and it goes without saying that the dot arrangement can be changed as appropriate.

Next, overlay measurement is performed by optically observing the overlay measurement mark (in the state shown in FIG. 1) using an overlay measurement apparatus. That is, light is irradiated from above the overlay measurement mark shown in FIG. 1 (in a direction perpendicular to the paper surface), the reflected light is detected, and the mark is imaged. Recognizing the pattern position, the shift amount between the center of the outer box mark 1 and the center of the inner box mark 2 is detected.

FIG. 3 is a diagram showing an optical measurement waveform when the overlay measurement mark shown in FIG. 1 is measured by an optical measurement device (overlay measurement device). The two outer waves 15, 16 shown in FIG. 3 indicate the outer box mark 1 shown in FIG. 1, and the two inner waves 17, 16 shown in FIG.
Reference numeral 18 denotes the inner box mark 2 shown in FIG. The shift amount between the outer box mark 1 and the inner box mark 2 is detected using such a waveform diagram. At this time, unlike the waveform diagram obtained by observing the conventional overlay measurement mark, the waves 15 and 16 indicating the outer box mark 1 are smooth. Therefore, the pattern position of the outer box mark 1 can be accurately detected.

Next, a method of forming an overlay measurement mark according to the present embodiment will be described with reference to FIG. 4A to 4E are cross-sectional views showing a method for manufacturing a semiconductor device having the overlay measurement mark shown in FIG.

First, as shown in FIG. 4A, a first conductive layer having a thickness of, for example, 300 n is formed on a silicon substrate 14.
m of polysilicon layer 6 is deposited.
Is patterned using a known photo-etching method.

Next, as shown in FIG. 4B, for example, an oxide film 7 as a first insulating layer is formed on the polysilicon layer (first conductive layer) 6 and the silicon substrate 14 by a known atmospheric pressure CVD.
(Chemical Vapor Deposition) method and heat flow.

Thereafter, as shown in FIG. 4C, a contact hole 8 and a plurality of openings 4a for connecting the first conductive layer 6 and a second conductive layer 9 described later are formed in the oxide film 7. Is formed using a known photo-etching method. Each opening 4
a is formed to have a size equal to or close to the contact hole 8 used in the actual device. Specifically, the pattern area of each opening 4a is desirably about 0.5 to 2 times the pattern area of the contact hole 8. The planar pattern shape of each opening 4a is a square dot.

Next, as shown in FIG. 4D, a step of embedding a conductive material in the contact hole 8 and the opening 4a is performed. As the filling step, for example, a well-known tungsten etch-back method is used. At this time, since the size of each opening 4a is equal to or close to that of the contact hole 8, tungsten 19 is completely buried in each opening 4a as in the contact hole 8. The tungsten 19 embedded in the opening 4a in this manner becomes the outer box mark 1. At this time, the edge portion of the buried tungsten 19 constituting the outer box mark 1 is smooth.

Thereafter, as shown in FIG. 4E, for example, an aluminum alloy film 9 is formed as a second conductive layer on the oxide film 7 and the buried tungsten 19. A pattern of a photoresist film 10 is formed on the aluminum alloy film 9. Of these patterns, a pattern 2a formed at the center on the outer box mark 1 becomes the inner box mark 2. If the pattern of the photoresist film 10 is not displaced from the pattern of the contact hole 8, the center of the inner box mark 2 matches the center of the outer box mark 1.

According to the first embodiment, the interlayer film 4
Then, a plurality of openings 4a having a size equal to or close to the contact hole 8 used in the actual element are formed, and this is used as the outer box mark 1. Therefore, the tungsten buried in the contact hole 8 is completely buried also in the opening 4a. Therefore, unlike the conventional overlay measurement mark, tungsten residue does not remain on the outer box mark, so that a smooth optical measurement waveform diagram can be obtained as shown in FIG. The position can be detected with high accuracy. As a result, the accuracy and reproducibility of the overlay measurement can be improved.

Further, since the plurality of openings 4a are arranged in three rows in a rectangular frame to form the outer box mark 1, an optical measurement waveform having higher sensitivity than the conventional outer box mark can be obtained. Obtainable. That is, when the apertures are arranged in three rows and optically observed using an overlay measuring device, the peaks obtained from the apertures in each row are mutually emphasized, and the sensitivity is higher than that in the aperture in one row. Can be improved.

In the first embodiment, each opening 4a is formed in a square pattern. However, the present invention is not limited to the square pattern. For example, each opening may be formed in a circular pattern. It is possible.

The outer box mark 1 is formed by arranging the dot-shaped openings 4a as a whole in a rectangular frame shape, and as shown in FIG.
The outer box mark 1 is formed such that there are no corners (that is, a square is formed by four bars, but the four corners of the square are arranged so that the bars are not connected). It is also possible.

FIG. 6 is a sectional view showing an overlay measurement mark used in the semiconductor device according to the second embodiment of the present invention. The same parts as those in FIG. explain.

The tungsten 19 buried in the plurality of openings 4a becomes the inner box mark 1. A photoresist pattern is formed on the second conductive layer 5, and a pattern 2 a formed on the inner box mark 1 in the pattern becomes the outer box mark 2. That is, in the present embodiment, both box marks are reversed from those in the first embodiment.

The same effects as in the first embodiment can be obtained in the second embodiment.

In the second embodiment, the inner box marks are formed by arranging the plurality of openings 4a for embedding the tungsten 19 so that the plane pattern is a rectangular frame. It is also possible to form the inner box mark by arranging the openings 4a so that the plane pattern is square.

[0049]

As is apparent from the above description, according to the present invention, at least one box mark of the overlay measurement mark composed of the outer box mark and the inner box mark is formed into a square by a rectangular or circular dot. By completely embedding the embedding metal, the side walls of the pattern can be made optically smooth, and the overlay measurement accuracy and measurement reproducibility can be improved.

Further, according to the present invention, a plurality of openings having a pattern area of 0.5 to 2 times the pattern area of the connection hole are formed in the interlayer insulating film, and this is formed as a first box mark. Used as Accordingly, it is possible to provide a semiconductor device having an overlay measurement mark capable of improving the accuracy and reproducibility of overlay measurement, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a plan view showing an overlay measurement mark used for a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line 22-22 shown in FIG.

FIG. 3 is a waveform diagram when the overlay measurement mark shown in FIG. 1 is observed by an optical measurement device.

4A to 4E are cross-sectional views illustrating a method for manufacturing a semiconductor device having the overlay measurement mark shown in FIG.

FIG. 5 is a plan view showing a modification of the overlay measurement mark shown in FIG.

FIG. 6 is a cross-sectional view showing an overlay measurement mark used in a semiconductor device according to a second embodiment of the present invention.

7 (a) is a plan view showing a conventional overlay measurement mark, and FIG. 7 (b) is a cross-sectional view along line 6b-6b shown in FIG. 7 (a). .

8 is a waveform chart when the overlay measurement mark shown in FIG. 7 is observed by an optical measurement device.

[Explanation of symbols]

1 Outer box mark 2
Inner box mark 2a Pattern 3
First conductive layer 4 Interlayer film 4a
Opening 5 Second conductive layer 6
Polysilicon 7 oxide film 8
Contact hole 9 Aluminum alloy 10
Wiring pattern 11 Outer box mark 12
Inner box mark 13 Tungsten residue 14
Silicon substrate 15, 16 Outer wave 1
7, 18 Inner wave 19 Tungsten 21
First conductive layer 23 Interlayer film 23
a Opening 25 Wiring layer 27
Patterns 31, 33 Waveforms showing box marks outside 35, 37 Waveforms showing box marks inside

Claims (12)

(57) [Claims] 1. A mark for measuring the superposition of a first pattern and a second pattern, wherein the mark for measuring the superposition is formed by the first pattern and the second pattern. A semiconductor device having an overlay measurement mark, comprising an outer box mark and an inner box mark to be formed, wherein at least one of the two box marks is formed in a rectangular shape by rectangular or circular dots. 2. A pattern formed by a first conductive layer, a pattern formed by a second conductive layer, an insulating layer for insulating a pattern formed by the first conductive layer and a pattern formed by a second conductive layer, A layer having an opening for electrically connecting the pattern by the first conductive layer and the pattern by the second conductive layer, for measuring the overlap of the opening and the pattern by the second conductive layer; A semiconductor device having an overlay measurement mark, wherein the mark is formed in a rectangular shape by rectangular or circular dots. 3. The semiconductor device having an overlay measurement mark according to claim 1, wherein a conductive material is buried in the dot portion. 4. The overlay measurement mark according to claim 1, wherein the dot diameter of the overlay measurement mark is 0.3 to 1 μm.
A semiconductor device having the overlay measurement mark according to any one of 2 and 3. 5. A step of forming an interlayer insulating film on a first conductive layer, and a connection for electrically connecting the first conductive layer and a second conductive layer to be described later to the interlayer insulating film. The hole and the plane pattern formed by the plurality of openings are frame-shaped or square first box marks, and the pattern area of each opening is 0.5 times or more and 2 times or less that of the connection hole. A step of forming one box mark; a step of embedding a filling material in the connection hole and the opening by an etch-back method; and a step of forming a second conductive layer on the filling material and the interlayer insulating film. Forming a photoresist pattern on the second conductive layer, wherein the planar shape located on the second conductive layer and above the first box mark is a square pattern. With box mark Forming a photoresist pattern, and optically observing the first and second box marks to detect a positional shift between the first box mark and the second box mark, A method for manufacturing a semiconductor device, comprising: measuring a superposition of a pattern of a connection hole and the photoresist pattern. 6. An interlayer insulating film formed on a first conductive layer, and a first box mark formed in the interlayer insulating film and having a frame pattern or a rectangular plane pattern including a plurality of openings, An embedding material embedded in the opening; a second conductive layer formed on the interlayer insulating film; and a part of the second conductive layer formed on the first box mark. And a second box mark having a rectangular planar pattern. 7. A connection hole for electrically connecting the second conductive layer and the first conductive layer is formed in the interlayer insulating film, and the opening has a pattern area of the connection hole. Formed to be 0.5 times or more and 2 times or less of that of
7. The semiconductor device having an overlay measurement mark according to claim 6, wherein the burying material is buried in the connection hole. 8. The second box mark, wherein a photoresist pattern formed of a box pattern located on the second conductive layer and above the first box mark is transferred to the second conductive layer. 8. A semiconductor device having an overlay measurement mark according to claim 7, wherein: 9. The pattern of the connection hole is obtained by optically observing the first box mark and the box pattern to detect a displacement between the first box mark and the box pattern. 9. The semiconductor device having an overlay measurement mark according to claim 8, wherein the overlay measurement is performed on the overlay between the photoresist pattern and the photoresist pattern. 10. The semiconductor device having an overlay measurement mark according to claim 6, wherein a planar shape of the opening is rectangular or circular. 11. The semiconductor device having an overlay measurement mark according to claim 6, wherein the filling material is a conductive material. 12. The overlay measurement mark according to claim 6, wherein the opening has a rectangular or circular shape having a diameter of 0.3 μm or more and 1 μm or less. Semiconductor device.