JP2002094367A - Level conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level conversion circuit that can prevent deterioration in jitter characteristics due to fluctuations in an output voltage level of a full differential amplifier circuit being a component of the level conversion circuit caused by fluctuations in the frequency or amplitude of an input signal. SOLUTION: The level conversion circuit consists of the full differential amplifier circuit comprising a couple of PMOSTs 1, 2 connected between a pair of level shift circuits 200, 300 and comprising three NMOSTs 3-5, of a limiter circuit comprising a couple of NMOSTs 6, 7 connected to an output side of the full differential amplifier circuit, of a common source ground circuit, comprising 4 pairs of PMOSTs 8-11 and NMOSTs 12-15 and of a couple of inverter circuits 100, 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit which receives a balanced input type ECL (emitter coupled logic) level input signal and converts it into a CMOS (complementary MOS) level output signal.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit (IC), as one technique for enabling high-speed operation, internal circuit operation is performed at an ECL level, and only interface output is performed by a CM.
It is common to convert to OS level. At this time, E
A level conversion circuit is used to convert from the CL level to the CMOS level.

[0003] Such a conventional level conversion circuit is disclosed in, for example, "Level Conversion Circuit" of Japanese Patent Application Laid-Open No. Hei 5-212433. FIG. 3 shows a conventional balanced input type ECL.
FIG. 2 is a circuit diagram showing, as a block, an example of a level conversion circuit for converting a level input signal into a CMOS level output signal.

The level conversion circuit shown in FIG. 3 has a positive-phase (or non-inverted) input terminal 16, a negative-phase (or inverted) input terminal 17, a positive-phase output terminal 18, a negative-phase output terminal 19, a power supply terminal 20, a ground ( GND) terminal 21, first level shift circuit 200,
Second level shift circuit 300, first inverter circuit 10
0 and a second inverter circuit 101. Further, the first and second level shift circuits 200, 3
Two P-channel MOS transistors (hereinafter referred to as
1, 2 and 3 N-channel MOs
It has a fully differential amplifier composed of S transistors (hereinafter referred to as NMOST) 3 to 5. In addition, a grounded source circuit including four pairs of PMOSTs 8 to 11 and NMOSTs 12 to 15 is provided between the fully differential amplifier and the pair of inverter circuits 100 and 101.

Here, the in-phase input terminal 16 is connected to the NMOST
3 and the input terminal 2 of the level shift circuit 200
02. On the other hand, the negative phase input terminal 17
The gate of ST4 and the input terminal 302 of the level shift circuit 300 are connected. The gate of the PMOST1 is connected to the output terminal 201 of the level shift circuit 200, and the drain is set to N.
The drain of the MOST3 and the source are connected to the power supply terminal 20.
Connected to. On the other hand, the gate of the PMOST2 is connected to the output terminal 301 of the level shift circuit 300, and the drain is connected to the NMO.
The drain and the source of ST4 are connected to the power supply terminal 20. In addition, the sources of the NMOSTs 3 and 4 are connected to the drain of the NMOST5 forming a bias circuit. Further, the gate of the NMOST 5 is connected to the bias terminal 22 and the source is connected to the GND terminal 21.

[0006] Next, four pairs of P
The MOSTs 8 to 11 and the NMOSs 12 to 15 will be described. The sources of the PMOSTs 8 to 11 are connected to the power supply terminal 2
Connected to 0. The gates of PMOSTs 8 and 11 are
PMOST1, the first output node 31 of the fully differential amplifier
And the drain of NMOST3. The gates of the PMOSTs 9 and 10 are connected to the second output node 41 of the fully differential amplifier, PMOST2 and NMOT.
Commonly connected to the drain of ST4. On the other hand, NMOST
Sources 12 to 15 are commonly connected to a GND terminal 21. The gates of NMOSTs 12 and 13 are interconnected, and these gates are connected to the drain of PMOST8 along with the drain of NMOST12. NMOST
13 and the drain of PMOST9 are connected to a node 5 commonly connected to the input terminal of the inverter circuit 100.
It becomes 1. The gates of the NMOSTs 14 and 15 are interconnected, and these gates are further connected to the drain of the PMOST10 together with the drain of the NMOST14.
On the other hand, the drain of the NMOST15 and the PMOST11
Becomes a node 61 commonly connected to the input terminal of the inverter circuit 101. The outputs of the inverter circuits 100 and 101 are connected to output terminals 18 and 19, respectively.

Next, the operation of the level conversion circuit shown in FIG. 3 will be described. Here, the output of the first level shift circuit 200 is 201, and the output of the second level shift circuit 300 is 3
01, and the outputs of the fully differential amplifier composed of the PMOSTs 1 and 2 and the NMOSTs 3 to 5 are 31 and 41, respectively. In addition, PMOST9, NMOST13 and PMT13
The outputs of the source ground circuit constituted by the OST 11 and the NMOST 15 are denoted by 51 and 61, respectively.

A normal phase input terminal 16 and a negative phase input terminal 17
When the ECL level balance signal is input to the input terminal, the output 201 of the first level shift circuit 200
6 is a waveform obtained by level-shifting the waveform input to 6. Similarly, the output 301 of the second level shift circuit 300 is a waveform obtained by level-shifting the waveform input to the antiphase input terminal 17. When a positive-phase input signal is input to the gates of the PMOST1 and the NMOST3, respectively, and a negative-phase input signal is input to the gates of the PMOST2 and the NMOST4, the outputs 31 and 41 of the fully differential amplifier become positive-phase input terminals. 16. A negative-phase output and a normal-phase output are output in a form in which the waveform input to the negative-phase input terminal 17 is amplified. When a positive-phase output signal 41 of the fully differential amplifier is input, the output 51 of the source ground circuit constituted by the PMOST 9 and the NMOST 13 outputs a signal of the opposite phase obtained by amplifying the output signal 41 and inverting the output signal 41. . The output 61 of the source grounding circuit composed of the PMOST 11 and the NMOST 15 receives the inverted signal output 31 of the full differential amplifier, and amplifies the output signal 31 and inverts the inverted signal. Output. The source ground circuit outputs 51 and 61 are amplified to the CMOS level by the inverter circuits 100 and 101, and the positive-phase output signal is output from the positive-phase output terminal 18 and the negative-phase output signal is output from the negative-phase output terminal 19, respectively.

FIG. 4 shows an operation waveform diagram (or timing chart) of the level conversion circuit shown in FIG.
(A) shows the input signals of the input terminals 16 and 17 and the signal voltage waveforms of the output nodes 201 and 301 of the level shift circuits 200 and 300 when a low frequency signal is input. (B) shows the input signals of the input terminals 16 and 17 and the output nodes 201 and 301 of the level shift circuits 200 and 300 when a high-frequency signal is input.
5 shows a signal voltage waveform of the first embodiment. (C) shows the signal waveforms at the output nodes 31 and 41 of the above-described fully differential amplifier. (D)
Shows a signal waveform at the input node 51 of the inverter circuit 100. FIG. 4E is a diagram for explaining jitter generation which is a problem of the level conversion circuit shown in FIG.

[0010]

However, the above-mentioned conventional level conversion circuit has the following problems. That is, the output voltage level of the fully differential amplifier fluctuates due to the frequency and amplitude fluctuations of the input signal, and the jitter characteristics deteriorate. The reason will be described with reference to the operation waveform diagram of FIG. In the waveform diagram of FIG. 4, a solid line indicates a circuit operation when a high frequency signal is input, and a broken line indicates a circuit operation when a low frequency signal is input. The positive and negative phase input signals are input from the positive and negative phase input terminals 16 and 17 to the NMOSTs 3 and 4 and the input terminals 202 and 302 of the level shift circuits 200 and 300, respectively. At the same time, level shift circuits 2
The positive-phase and negative-phase input signals, which are lower than 00 and 300 by a certain level, are input from nodes 201 and 301. For example, when the input signal has a low frequency, the levels of the output nodes 31 and 41 of the fully differential amplifier composed of the NMOSTs 3 to 5 and the PMOSTs 1 and 2 become the maximum operable output voltage level. However, when the input signal has a high frequency, the levels of the output nodes 31 and 41 of the above-described fully differential amplifier operate at a level that does not reach the maximum operable output voltage level.

As described above, when the input signal is at a low frequency and at a high frequency, the operation output voltage level of the fully differential amplifier fluctuates, and the output node 51 of the grounded source circuit constituted by the next stage PMOST9 and NMOST13. In addition, the response time of the positive-phase output of the inverter circuit 100 also varies. Therefore, an output signal whose response time fluctuates is output to the positive-phase and negative-phase output terminals due to the frequency fluctuation of the input signal, and jitter occurs. In order to prevent this jitter from occurring, it is necessary to increase the amplification factor of the fully differential amplifier to increase the response speed, and to always keep the output of the fully differential amplifier at the maximum operation output level. However, in order to increase the response speed by this method, it is necessary to increase the drain current of the biasing NMOS T5, which causes another problem that power consumption increases. In addition, even when the amplitude of the input signal fluctuates, the response speed of the fully differential amplifier fluctuates, so that the same problem as described above occurs.

[0012]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a level conversion circuit capable of eliminating or reducing the occurrence of the above-mentioned jitter without increasing power consumption.

[0013]

SUMMARY OF THE INVENTION A level conversion circuit according to the present invention is connected between a pair of level shift circuits connected between a power supply terminal and a GND terminal, and is provided with a total difference to which a balanced input type ECL input signal is inputted. And a grounded source circuit connected between the output terminal of the fully differential amplifier and the pair of inverter circuits.
A circuit for obtaining an output converted to an S level, comprising a pair of limiter circuits connected between an output side of a fully differential amplifier and an input side of a common source circuit.

According to a preferred embodiment of the level conversion circuit of the present invention, the limiter circuit is constituted by a pair of N-channel MOS transistors (NMOST) connected between the output node of the fully differential amplifier and the power supply terminal. You. The pair of NMOSTs constituting the limiter circuit have a source connected to the output node of the fully differential amplifier, and a drain and a gate connected to a power supply terminal. The fully differential amplifier is a pair of NMOS
T and a bias NMOS whose drain is connected to the source of the NMOST and whose source is connected to the GND terminal.
T, a P-channel MOS transistor having a drain connected to a drain of a pair of NMOSTs and a source connected to a power supply terminal
And a transistor (PMOST). The above-mentioned common source circuit is constituted by four pairs of PMOST and NMOST.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction and operation of a preferred embodiment of a level conversion circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a preferred embodiment of a level conversion circuit according to the present invention. For convenience of explanation,
The same reference numerals are used for the components corresponding to the above-described related art. This level conversion circuit includes a positive-phase input terminal 16, a negative-phase input terminal 17, and a positive-phase output terminal 1.
8, a negative-phase output terminal 19, a power supply terminal 20, and a GND (ground) terminal 21. Also, the first level shift circuit 2
00, a second level shift circuit 300, a fully differential amplifier connected between the level shift circuits 200 and 300,
First inverter circuit 100, second level shift circuit 10
1 and fully differential amplifier and inverter circuits 100 and 101
It is composed of a transistor circuit connected between them.

First, a fully differential amplifier is composed of a pair of PMOSTs 1, 2 and 3
3-5. The positive-phase input terminal 16 is connected to the gate of the NMOST3 constituting the fully differential amplifier and the input terminal 202 of the first level shift circuit 200. On the other hand, the anti-phase input terminal 17 is connected to the NM
The gate of the OST 4 and the input terminal 302 of the second level shift circuit 300 are connected. The gate of the PMOST1 is connected to the output terminal 201 of the first level shift circuit 200. On the other hand, the gate of the PMOST2 is connected to the output terminal 301 of the second level shift circuit 300. PM
The drain of the OST1 is connected to the drain of the NMOST3 and forms a node 31. On the other hand, the drain of the PMOST4 and the drain of the NMOST2 are interconnected to form a node 41. Finally, NMOST3, 4
Is connected to the drain of NMOST5, and NM
The gate of the OST 5 is connected to the bias terminal 22, and the source is connected to the GND terminal 21.

Next, the fully differential amplifier and the inverter circuit 10
0, 101, the transistor circuit is NMO
ST6, 7, 12-15 and PMOST8-11. The drains and gates of NMPOSTs 6 and 7 and the sources of PMOSTs 8 to 11 are connected to power supply terminal 2
Connected to 0. Source of NMOST6, PMOST9
And 11 have their gates connected to node 31 of the fully differential amplifier described above. On the other hand, the source of NMOST7 and PM
The gates of OSTs 8 and 10 are connected to node 41 of the fully differential amplifier. On the other hand, the sources of the NMOSTs 12 to 15 are connected to the GND terminal 21. The drain of NMOST12 is connected to the gates of NMOST12 and 13 and PMT.
Connected to the drain of OST8. Also, NMOST1
3 is connected to the drain of PMOST9,
The node 51 is connected to the input terminal of the first inverter circuit 100. The drain of NMOST14 is NMOS
Connected to the gates of T14 and T15 and the drain of PMOST10. Further, the drain of the NMOST 15 is a node 61 connected to the drain of the PMOST 11 and connected to the input terminal of the second inverter circuit 101. The above-described positive-phase output terminal 18 and negative-phase output terminal 19 are connected to the output terminals of the pair of inverter circuits 100 and 101, respectively.

The level conversion circuit of the present invention shown in FIG. 1 is, as apparent from the comparison with the conventional level conversion circuit shown in FIG. 3, fully-differential amplifier constituted by PMOSTs 1, 2 and NMOSTs 3 to 5 and four pairs of the same. PMOST8 ~ 11
And the common source circuit constituted by NMOSTs 12 to 15 are the same. Therefore, the difference is that the fully differential amplifier and the PMOSTs 8 to 11 and the NMOSTs 12 to 1
And NMOST between the common source circuit constituted by
6 and 7 are added.

Next, the operation of the level conversion circuit shown in FIG. 1 will be described. Here, the output of the first level shift circuit 200 is 201, and the output of the second level shift circuit 300 is 3
01. PMOST1,2 and NMOST3-5
Are output as 31 and 41, respectively. The outputs of the source ground circuit constituted by the PMOST9 and the NMOST13 and the PMOST11 and the NMOST15 are denoted by 51 and 61, respectively.

Normal phase input terminal 16 and negative phase input terminal 17
When an ECL level balanced input signal is input to the input terminal, a level-shifted waveform of the waveform input to the in-phase input terminal 16 is output to the output 201 of the level shift circuit 200. Similarly, as the output 301 of the level shift circuit 300, a waveform obtained by level-shifting the waveform input to the antiphase input terminal 17 is output. PMOST1 and NMOST3
Signals of the positive phase input are input to the gates of
When a signal of the opposite phase input is input to the gates of the OST2 and the NMOST4, the outputs 31 and 41 of the fully differential amplifier are output.
Output a negative-phase output and a normal-phase output in a form in which the waveforms input to the positive-phase input terminal 16 and the negative-phase input terminal 17 are amplified. At this time, the output voltage levels of the outputs 31 and 41 of the fully differential amplifier are changed by the drain current of the NMOS T5.
The current equations (1) and (2) for the following MOS transistors
Is determined by Id = K * (Vgs-Vt) 2 (1) where K and Vt are constants.

Next, by transforming the above equation (1), the following equation (2) is obtained. Vgs = SEQ (Id / K) -Vt (2) Here, Id in the equation (2) is a drain current, and Vgs is a gate-source voltage. In the level conversion circuit of the present invention, Id is a current flowing through the NMOS T5, and Vg
s is the voltage between the power supply terminal 20 of the NMOSTs 6 and 7 and the output nodes 31 and 41 of the fully differential amplifier.

Here, PMOST1 and NMOST3
Signals of the positive phase input are input to the gates of
When an inverted-phase input signal is input to the gates of the OST2 and the NMOST4, the NMOST3 is turned on (conducting), and the NM2 is turned on.
OST4 is turned off (non-conductive). At this time, the current flowing through the fully differential amplifier is PMOST1 and NMOST6.
Is determined by the drain current. Since the drain current of PMOST1 is constant determined by the above equation (1), NMOST6
Is the difference between the current set in the NMOST5 and the drain current flowing in the PMOST1.
Further, if the drain current flowing through the NMOS T6 is determined by the above equation (2), Vgs of the NMOS T6 is determined, and the output voltage level of the fully differential amplifier is determined. Next, P
The output 51 of the source ground circuit composed of the MOST 9 and the NMOST 13 is a positive-phase output signal 4 of the fully differential amplifier.
When 1 is input, the output signal 41 is amplified and inverted to output a signal of the opposite phase.

Further, PMOST11 and NMOST1
The output 61 of the source grounding circuit composed of the differential signal 5 is supplied with the output signal 3 when the signal output 31 of the opposite phase of the fully differential amplifier is inputted.
1 is amplified and inverted to output a positive-phase signal. The common source outputs 51 and 61 are amplified to the CMOS level by the inverter circuits 100 and 101, and the positive-phase output signal is output from the positive-phase output terminal 18 and the negative-phase output signal is output from the negative-phase output terminal 19.

The level conversion circuit of the present invention can set the output voltage level of the fully differential amplifier to an arbitrary level by adjusting the drain current of the NMOS T5.
That is, by setting the output voltage level of the fully differential amplifier to the operation output voltage level when the input signal is at a high frequency, the operation output voltage level is always the same even when the input signal is at a low frequency and at a high frequency. As a result, there is no change in the response time of the fully differential amplifier due to the change in the frequency of the input signal.
No jitter occurs in the output signal. Even when the amplitude of the input signal fluctuates, the same result as described above can be obtained by setting the operation output voltage level of the differential amplifier to the operation output voltage level when the amplitude is minimum, and no jitter occurs.

Next, a description will be given with reference to the operation waveform diagram of FIG. FIGS. 2A to 2E show the above-described FIGS.
(E). That is, it shows the circuit operation due to the frequency fluctuation of the input signal. In FIG. 2, a solid line indicates a circuit operation when a high frequency signal is input, and a broken line indicates a circuit operation when a low frequency signal is input. Normal phase and negative phase input terminal 1
The positive and negative phase input signals from NMOS transistors 6 and 17 are NMOST3,
4 and a pair of level shift circuits 200 and 300 are input to input terminals 202 and 302. At the same time, PMOST
1. The positive and negative phase input signals 201, 30 of which the level shift circuits 200, 300 have been lowered by a certain level
1 is input. When input signal is high frequency, NMOS
The output voltage levels of the output nodes 31 and 41 of the fully differential amplifier composed of T3 to T5 and PMOSTs 1 and 2 are NM
The output voltage level is determined by the drain currents of the OSTs 6, 7 and the NMOS T5.
The operating voltage levels of the output nodes 31 and 41 of the fully differential amplifier operate at the same output voltage level as the low frequency signal.

Therefore, the operation is performed without the output voltage level fluctuation of the fully differential amplifier due to the frequency fluctuation of the input signal. Therefore, the next-stage PMOST9 and NMOST13, PM
The response time does not fluctuate also in the common source circuit and the inverter circuits 100 and 101 constituted by the OST11 and the NMOST15. Therefore, no jitter occurs because the response time due to the input frequency fluctuation does not fluctuate in the positive and negative phase output signals.

The configuration and operation of the preferred embodiment of the level conversion circuit according to the present invention have been described above in detail. However, it should be noted that such an embodiment is merely an example of the present invention and does not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made in accordance with the particular application without departing from the spirit of the invention.

[0029]

As is apparent from the above description, the level conversion circuit according to the present invention has the following remarkable practical effects. That is, the characteristics and performance of the circuit can be improved. The reason is that the provision of the limiter circuit at the output of the fully differential amplifier circuit constituting the level conversion circuit makes it possible to always keep the operation output voltage level constant. Therefore, it is possible to prevent the jitter characteristic from deteriorating due to the fluctuation of the operation output voltage level of the fully differential amplifier based on the fluctuation of the frequency and the amplitude.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a preferred embodiment of a level conversion circuit according to the present invention, which is shown by one block.

FIG. 2 is a waveform diagram for explaining the operation of the preferred embodiment of the level conversion circuit shown in FIG. 1;

FIG. 3 is a circuit diagram of a conventional level conversion circuit.

FIG. 4 is a waveform diagram for explaining the operation of the conventional level conversion circuit shown in FIG. 3;

[Description of Signs] 1, 2, 8 to 11 P-channel MOS transistor (PMOST) 3 to 7, 12 to 15 N-channel MOS transistor (NMOST) 16 Normal-phase input terminal 17 Negative-phase input terminal 18 Normal-phase output terminal 19 Reverse Phase output terminal 20 Power supply terminal 21 GND terminal 22 Bias terminal 100, 101 Inverter circuit 200, 300 Level shift circuit

Claims (5)

[Claims] A balun input type EC connected between a pair of level shift circuits connected between a power supply terminal and a GND terminal;
A differential amplifier to which an L input signal is input, and a source ground circuit connected between an output terminal of the differential amplifier and a pair of inverter circuits, and convert the pair of inverter circuits to a CMOS level A level conversion circuit for obtaining a corrected output, comprising: a pair of limiter circuits connected between an output side of the full differential amplifier and an input side of the common source circuit. 2. The semiconductor device according to claim 1, wherein said limiter circuit comprises a pair of N-channel MOS transistors (NMOST) connected between an output node of said fully differential amplifier and said power supply terminal. Level conversion circuit as described. 3. A pair of NMOSs constituting said limiter circuit
3. The level conversion circuit according to claim 2, wherein T has a source connected to an output node of the full differential amplifier, and a drain and a gate connected to the power supply terminal. 4. A fully differential amplifier comprising a pair of NMOSTs.
And a bias NMOS whose drain is connected to the source of the NMOST and whose source is connected to the GND terminal.
4. The transistor according to claim 1, wherein the transistor is constituted by T and a P-channel MOS transistor (PMOST) having a drain connected to a drain of the pair of NMOSTs and a source connected to the power supply terminal. Level conversion circuit as described. 5. The common source circuit comprises four pairs of PMOSTs.
5. The level conversion circuit according to claim 1, wherein the level conversion circuit comprises: