JP2002076863A - Digital phase comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital phase comparator by which measurement accuracy can be enhanced. SOLUTION: The digital phase comparator is provided with an analog phase comparator 1, a clock oscillator 5 that generates clocks of two kinds or more, a 1st digital counter 2 that counts up a period when an output of the analog phase comparator 1 is active on the basis of a 1st clock outputted from the clock oscillator 5, a 2nd digital counter 3 that counts up a period when the output of the analog phase comparator 1 is active on the basis of a 2nd clock different from the 1st clock and outputted from the clock oscillator 5, and a digital adder 4 that provides an output of a sum of an output of the 1st digital counter 2 and an output of the 2nd digital counter 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital phase comparator for detecting a phase difference between two input signals.

[0002]

2. Description of the Related Art In order to detect a phase difference between two input signals, a digital phase comparator which counts an analog phase difference between two input signals by a clock and outputs a digital phase difference is known.

FIG. 5 is a block diagram of a conventional digital phase comparator. In FIG. 5, reference numeral 1 denotes an analog phase comparator which detects a phase difference e from a reference point of a first input signal to a reference point of a second input signal. 9 is a clock oscillator. Reference numeral 10 denotes a digital counter which receives as input the phase difference e of the analog phase comparator 1 and the clock n generated by the clock oscillator 9 and counts up with the clock n only during the period when the analog phase comparator 1 is active. The phase difference p is output.

The operation of the digital phase comparator constructed as described above will be described below.

FIG. 6 is an explanatory diagram of the operation of the digital phase comparator of FIG. a is a first input signal, which is input to the analog phase comparator 1. b is a second input signal, which is similarly input to the analog phase comparator 1. The phase difference e is the first
, From the reference point of the input signal a to the reference point of the second input signal b, and is output from the analog phase comparator 1. n is a clock signal used for counting up by a digital counter of 10.

Next, the operation will be described along the flow of signals. The analog phase comparator 1 detects a phase difference e from the reference point of the first input signal a to the reference point of the second input signal b, and outputs it as a pulse wave. The phase difference e output from the analog phase comparator 1 is counted up by a clock n generated from nine oscillators, and the count value is output as a digital phase difference p from a ten digital counter.

[0007]

In such a digital phase comparator, the accuracy of the phase difference output depends on the frequency of the clock used for counting, and depends on the measurement time when the phase difference is stationary. I do.

FIG. 7 is an explanatory diagram of the clock frequency, the measurement time, and the phase difference measurement accuracy of FIG. FIG. 7A shows FIG.
FIG. 5 is an explanatory diagram of clock frequency and digital phase difference measurement accuracy. From FIG. 7A, the output of the analog phase comparator can be the maximum emax and the minimum emin for the count value p. Accordingly, if the frequency of the clock used for counting is f, the difference between emax and emin is Δ = 2 × (1 / f), and the phase difference output accuracy of the digital phase comparator is determined by counting the phase difference output of the analog phase comparator. It depends on the frequency of the clock.

FIG. 7B is an explanatory diagram of the measurement time and the digital phase difference measurement accuracy of FIG. 7B, when the phase difference is stationary, the count values p1 and p2, which are digital phase difference outputs, are proportional to the measurement time t1 and the measurement time t2, and p2 = t2 / t1 × p1 The measurement time t1 The ratio of the phase error to the digital phase difference output value in the case of is Δ / digital phase error output value p1 = Δ / p1 The ratio of the phase error to the digital phase difference output value when the measurement time is t2 is Δ / digital phase Error output value p2 = Δ / p2 = Δ / (t
2 / t1 × p1) Therefore, the digital phase error output accuracy also depends on the measurement time.

An object of the present invention is to provide a digital phase comparator capable of improving the above-mentioned conventional problems and improving the measurement accuracy.

[0011]

In order to solve this problem, a digital phase comparator according to the present invention comprises an analog phase detector for detecting a phase difference from a reference point of a first input signal to a reference point of a second input signal. A phase comparator, a clock oscillator that generates two or more types of clocks, and an output of the analog phase comparator and a first clock among a plurality of clocks output by the clock oscillator. A first digital counter that counts up with the first clock only during a period in which the output of the comparator is active, an output of the analog phase comparator, and a first clock among a plurality of clocks output by the clock oscillator. A different second clock is input, and counting is performed with the second clock only while the output of the analog phase comparator is active. And second digital counter, the first
And a digital adder that receives the output of the digital counter and the output of the second digital counter as inputs, and outputs the sum of the output value of the first digital counter and the output value of the second digital counter. The configuration is as follows.

Thus, by adding the count values counted independently for the different first and second clocks, the phase difference is increased by a frequency higher than the actual frequency of each of the first and second clocks. This has the same effect as measuring, and has the effect of improving the accuracy of digital phase difference measurement.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention comprises an analog phase comparator for detecting a phase difference from a reference point of a first input signal to a reference point of a second input signal; A clock oscillator that generates more than two kinds of clocks, and an output of the analog phase comparator and a first clock of a plurality of clocks output by the clock oscillator are input, and the output of the analog phase comparator is active. A first digital counter that counts up with the first clock only during a period, and a second clock that is different from the first clock among the plurality of clocks output from the analog phase comparator and the plurality of clocks output from the clock oscillator. And input
A second digital counter that counts up with the second clock only during an active period of the output of the analog phase comparator, and an output of the first digital counter and an output of the second digital counter as inputs; A digital adder for outputting a sum of an output value of the first digital counter and an output value of the second digital counter, wherein The addition of the count values independently counted by the first and second clocks has the same effect as measuring the phase difference at a higher frequency than the actual frequency of each of the first and second clocks. Thus, the effect of improving the digital phase difference measurement accuracy can be obtained.

According to a second aspect of the present invention, an analog phase comparator for detecting a phase difference from a reference point of a first input signal to a reference point of a second input signal, and three or more clocks are generated. A clock oscillator, an output of the analog phase comparator and one different clock of a plurality of clocks output by the clock oscillator are input, and the input clock is used only during a period in which the output of the analog phase comparator is active. A plurality of digital counters for counting up, the number of which is not less than three and the number of output clocks of the clock oscillator, and a digital addition for receiving outputs of the plurality of digital counters as inputs and outputting a sum of output values of the plurality of digital counters And a digital phase comparator characterized by having three or more clocks. By adding the count value, 3
It has the same effect as measuring the phase difference at a higher frequency than the actual frequency of each type of individual clock,
The effect of improving the digital phase difference measurement accuracy is obtained.

According to a third aspect of the present invention, in the clock oscillator, the plurality of clocks to be output have the same frequency, and the phase difference between the plurality of clocks is a value obtained by dividing 360 degrees by the number of the digital counters. 3. A digital phase comparator according to claim 1, wherein the digital phase comparator is a clock oscillator that oscillates a clock having a frequency equal to that of the digital counter. Counting is performed by a clock that equally divides 360 degrees by the number, and by adding the outputs of the plurality of digital counters, the same effect as when counting at the frequency of the number of digital counters with respect to the frequency of each clock is obtained. The effect of improving the measurement accuracy is obtained, and the effect of improving the measurement accuracy is obtained.

An embodiment of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 1 is a block diagram of a digital phase comparator according to a first embodiment of the present invention.
In FIG. 1, components denoted by the same reference numerals as those in FIG. 5 have the same functions and description thereof will be omitted. Reference numeral 5 denotes a clock oscillator which can generate two or more types of clocks. 2 is a first digital counter, and the phase difference e of the analog phase comparator 1
And the first clock c generated by the clock oscillator 5 as an input, and counts up by the first clock c only during a period in which the analog phase comparator 1 is active, and the count value f
Is output. Reference numeral 3 denotes a second digital counter which receives as input the phase difference e of the analog phase comparator 1 and the second clock d generated by the clock oscillator 5, and outputs the second clock only during a period in which the analog phase comparator 1 is active. Count up with d and output count value g. Reference numeral 4 denotes a digital adder, which is a count value f of the first digital counter 2.
And the count value g of the second digital counter 3 is added to output a digital phase difference h.

The operation of the digital phase comparator configured as described above will be described below. FIG. 2 is an explanatory diagram of the operation of the digital phase comparator of FIG. In FIG. 2, signals denoted by the same reference numerals as those in FIG. 6 are the same kind of signals, and the description thereof is omitted. c is a first clock, which is used for counting up by the first digital counter 2. d is
The second clock is used by the second digital counter 3 to count up.

Next, the operation will be described along the flow of signals. The phase difference from the reference point of the first input signal a to the reference point of the second input signal b is detected by the analog phase comparator 1 and output as a phase difference e which is a pulse wave. A phase difference e output from the analog phase comparator 1 is counted up by a first clock c generated by a clock oscillator 5, and a count value f is output from a first digital counter 2; Output phase difference e
With the second clock d generated by the clock oscillator 5
The second digital counter 3 outputs the count value g that has been counted up in step (1). The count value f of the first digital counter 2 and the count value g of the second digital counter 3 are added, and the result is output from the adder 4 as a digital phase difference h.

As described above, according to the present embodiment, the values independently counted by two types of clocks are added,
The number of clocks for counting the phase difference output of the analog phase comparator increases, and the same effect as increasing the clock frequency can be obtained.

(Embodiment 2) FIG. 3 is a block diagram of a digital phase comparator according to a second embodiment of the present invention. In FIG. 3, the same reference numerals as those in FIGS. 1 and 5 denote the same function or the same kind of signal, and a description thereof will be omitted. Reference numeral 6 denotes a clock oscillator for generating a first clock j and a second clock k. The frequencies of the first clock j and the second clock k are the same, and the phase difference between the clocks is a value obtained by dividing 360 degrees by the number of digital counters. In the present embodiment, the number of digital counters is “2”, which is the total number of the first digital counter 2 and the second digital counter 3, and the phase difference between the first clock j and the second clock k is 180. Set to degree.
Similar to the two outputs of the clock oscillator 5 of FIG. 1, the first clock j is input to the first digital counter 2 and the second clock k is input to the second digital counter 3.

As for the signal flow, the first input signal a and the second
Is output as the phase difference e. The first digital counter 2 converts the phase difference e into a first clock j
The second digital counter 3 outputs a count value g obtained by counting up the phase difference e by the first clock k. Count value f,
The digital phase difference h added by the count value g and the adder 4
Is output as

As described above, according to this embodiment, the clock oscillator 6 has the same frequency and the phase difference of each clock is 18
By outputting two types of clocks at 0 degrees and adding the independently counted values, the same effect as when counting at twice the clock frequency is obtained, and the effect of improving the measurement accuracy is obtained.

Therefore, the phase difference output of the analog phase comparator is added to the values independently counted by the two types of clocks, the first clock j and the second clock k, and
The phase difference output of the analog phase comparator has the same effect as the case of counting by increasing the clock frequency, and the effect of improving the measurement accuracy is obtained.

[0025]

As described above, according to the present invention, the phase difference output pulse width of the analog phase comparator is added to the values counted independently by a plurality of clocks, and the added value is converted to the digital phase difference. By providing the output, the accuracy of the phase difference output has the same effect as increasing the frequency of the clock to be counted, without depending on the frequency of the clock used for counting, and is advantageous in that the accuracy of the phase difference measurement is improved. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital phase comparator according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of the operation of the digital phase comparator of FIG. 1;

FIG. 3 is a block diagram of a digital phase comparator according to a second embodiment of the present invention;

FIG. 4 is an explanatory diagram of the operation of the digital phase comparator.

FIG. 5 is a block diagram of a conventional digital phase comparator.

FIG. 6 is an explanatory diagram of the operation of the digital phase comparator.

FIG. 7 is an explanatory diagram of clock frequency, measurement time, and phase difference measurement accuracy of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Analog phase comparator 2 1st digital counter 3 2nd digital counter 4 Digital adder 5 Clock oscillator 6 Clock oscillator

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yoshihisa Fujimori 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. (Reference)

Claims (3)

[Claims] An analog phase comparator for detecting a phase difference between a reference point of a first input signal and a reference point of a second input signal; a clock oscillator for generating two or more types of clocks; A first clock which receives an output of a comparator and a first clock among a plurality of clocks output by the clock oscillator, and counts up with the first clock only during an active period of the output of the analog phase comparator; A digital counter, an output of the analog phase comparator, and a second clock different from a first clock among a plurality of clocks output from the clock oscillator are input, and the output of the analog phase comparator is active. A second digital counter that counts up with the second clock only during a period, and an output of the first digital counter and the second digital counter. A digital adder which receives an output of a digital counter and outputs a sum of an output value of the first digital counter and an output value of the second digital counter. . 2. An analog phase comparator for detecting a phase difference from a reference point of a first input signal to a reference point of a second input signal; a clock oscillator for generating three or more types of clocks; An output of a comparator and one of different clocks among a plurality of clocks output by the clock oscillator are input, and the count is increased by the input clock only during an active period of the output of the analog phase comparator. And a plurality of digital counters equal to or less than the number of output clocks of the clock oscillator, and a digital adder that receives outputs of the plurality of digital counters and outputs a sum of output values of the plurality of digital counters. Digital phase comparator. 3. The clock generator according to claim 1, wherein the clock oscillator outputs a plurality of clocks having the same frequency, and generates a clock having a phase difference of 360 ° divided by the number of the digital counters. 3. The digital phase comparator according to claim 1, wherein the digital phase comparator is an oscillator.