JP2002075819A - Reference marker for designating position in semiconducor chip and its forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily aim at equipment. SOLUTION: A plurality of semiconductor chips 12 partitioned by scribe lines 14 are laid out on a silicon wafer 10. Reference markers 30 are formed on the scribe lines 14 corresponding to each semiconductor chip 12. The reference markers 30 have matching patterns 36. The matching patterns 36 are formed on orthogonal straight lines 38 and 40, and formed in a cross shape at positions containing origins O as the intersections of the straight lines 38 and 40. In the reference markers 30, square-shaped dummy patterns are formed in the proximity of the matching patterns 36 in each of four regions partitioned by the straight lines 38 and 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference point indicating a reference point indicating a pattern position in a semiconductor chip, and more particularly to a reference point for specifying a position in a semiconductor chip used for pattern inspection after a pattern forming step of the semiconductor chip. It relates to a label and a forming method.

[0002]

2. Description of the Related Art A semiconductor chip in which a large number of elements are integrated is
It is manufactured by repeating a process of forming a conductive film or an insulating film on a semiconductor substrate such as silicon and a process of etching these films to form a predetermined pattern a plurality of times. Each time the pattern formation process by etching is completed, a scanning electron microscope (Scanning Electron Mi) called a length measuring SEM is used.
The inspection is performed to determine whether or not the size of the contact hole, the width of the wiring pattern, and the like are formed as prescribed by using a crossscope (SEM).

FIG. 13 is an explanatory view of a conventional method for designating a pattern to be inspected. Referring to FIG. 13, a silicon wafer 10 has a large number of chip regions (semiconductor chips) 12 to be semiconductor chips. These semiconductor chips 12 are separated from each other by scribe lines 14, and after forming elements and wirings on the semiconductor chips 12, the silicon wafer 10 is cut along the scribe lines 14 and divided. The scribe line 14 includes each semiconductor chip 12
L-shaped mask alignment marks corresponding to a pair of corners 16 on the diagonal line (for example, upper left corner 16a and lower right corner 16c or upper right corner 16b and lower left corner 16d of semiconductor chip 12). 18 (18a, 18b) are provided.

The mask alignment mark 18 is provided when a pattern is formed on the semiconductor chip 12, and is formed, for example, on a projection when a wiring pattern is formed.
When a hole such as a contact hole is formed, it is formed as a concave portion. Then, the mask alignment mark 18 is used for alignment of an enlarged mask (reticle) so as not to cause a pattern shift when a pattern is formed on the semiconductor chip 12 in the next step. In addition, the semiconductor chip 1
The position of a pattern to be inspected (for example, a contact hole or a wiring) in the mask alignment mark 18 (for example,
It is specified by the XY coordinate position with the origin at the outer bent portion of the mask alignment mark 18b). Then, in the inspection process after the pattern formation, the cross-shaped aim (cursor) 20 of the SEM is aligned with the line outside the mask alignment mark 18b, and the coordinate position specified by using the intersection of the aim 20 as the origin is obtained. .

[0005]

However, the conventional mask alignment mark 18 used for dimensional inspection during the manufacturing process of a semiconductor chip is formed in an L-shape,
The EM cross-shaped aim 20 is aligned with the L-shaped mask alignment mark 18.
It is slightly difficult to match because it is aligned with the outside line or inside line. In addition, the conventional mask alignment mark 18 is always formed in the same position, the same size, and the same shape even when the pattern forming process is changed, such as the process of forming the gate electrode and the process of forming the contact hole and the via hole provided in the insulating layer. Is done. For this purpose, as shown in FIG. 14, a silicon oxide film (SiO ₂ film) 24 constituting an insulating layer is deposited on a silicon substrate 22 which is, for example, the silicon wafer 10, and a contact not shown is formed on the silicon oxide film 24. In the step of forming a hole, after forming a mask alignment mark 18A composed of a concave portion in the silicon oxide film 24,
When a metal film for forming a wiring pattern is formed, the concave mask alignment mark 18A is not sufficiently filled with the metal film, and the shape of the edge portion 26 of the mask alignment pattern 18B formed by the metal film is formed. May collapse and become unclear. Therefore, SEM aiming 2
Accurate alignment of 0s becomes difficult, and it takes time to find the target pattern or the pattern cannot be found. In addition, the semiconductor chip 12 has a multi-layer wiring structure, and the mask alignment marks 18 formed as recesses are formed.
When the mask alignment marks formed previously are misaligned, the previously formed mask alignment mark and the currently formed mask alignment mark are misaligned, and the shape of the upper mask alignment mark often collapses and becomes unclear.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to make it possible to easily aim a device. Another object of the present invention is to provide a clear marker. Another object of the present invention is to make it possible to easily find a specified pattern in a semiconductor chip.

[0007]

In order to achieve the above object, a position designation mark in a semiconductor chip according to the present invention is a base point mark for designating a position in a semiconductor chip, and is orthogonal to the mark. It is characterized by having a matching pattern provided on each of the two straight lines and located on both sides of the intersection of the two straight lines and overlapping the aiming of the device.

[0008] That is, the position designation marker according to the present invention is provided on two orthogonal straight lines and has an alignment pattern located on both sides of the intersection of the two straight lines, and substantially corresponds to the aiming of the device. Since it is formed in a cross shape, it is possible to easily and accurately superimpose the devices even if the edge portion is not sharp, and it is possible to easily find a specified pattern to be inspected.

The alignment pattern may be formed in a cross shape at a position including the intersection. When the alignment pattern is formed in a cross shape, it becomes easier to aim the device. The cross-shaped alignment pattern may be formed as a projection. When a gate electrode, a wiring pattern, or the like is formed, unnecessary portions are removed by etching, and the alignment pattern is also formed as a convex portion, so that the alignment pattern can be easily formed without an extra step. When the matching pattern is formed as a cross-shaped convex portion, a convex dummy pattern may be formed in each of the four regions defined by two orthogonal straight lines in the vicinity of the matching pattern. When a small convex portion is formed in a part of a wide area, the pattern is often excessively etched, and the pattern may be smaller than a target size. By providing a dummy pattern, such a phenomenon is prevented, and a predetermined size is provided. An alignment pattern can be formed.

[0010] The cross-shaped alignment pattern can be formed as a concave portion. When a contact hole or the like is formed in the insulating layer, by forming the cross-shaped alignment pattern as a concave portion, the alignment pattern can be easily formed without adding an extra step. Further, the alignment pattern can be formed at a position separated from the intersection of two orthogonal straight lines. Also in this case, since the matching pattern is provided on the two straight lines at positions separated from the intersection on both sides of the intersection of the two straight lines, the matching pattern is substantially the same as that formed in a cross shape. The effect is obtained. The alignment pattern formed at a position separated from the intersection may be formed as a concave portion. When the alignment pattern is formed as a convex portion, it is desirable to provide a dummy pattern in the vicinity. However, when the alignment pattern is formed as a concave portion, a pattern having a predetermined size is easily formed without being excessively etched without providing a dummy pattern. be able to.

When the alignment pattern is formed as a concave portion, it is desirable that the width thereof is smaller than the width of the alignment pattern formed as a convex portion. By reducing the width of the alignment pattern formed by the concave portions, for example, in the subsequent wiring forming step, the concave portions can be reliably filled with the metal forming the wiring, and the shape of the next alignment pattern is sharpened. Can be. Further, even if the recess is not filled with the wiring material, the shape of the projection formed by the wiring material is clear because the width of the projection formed by the wiring material is wider than that of the projection formed by the recess. Makes it easy to aim the equipment,
Can be stacked reliably.

The method for forming a base point marker for designating a position in a semiconductor chip according to the present invention is a method for forming a base point marker for designating a position in a semiconductor chip. Wherein, on both sides of the intersection of the two orthogonal straight lines, a registration pattern for superimposing a device is formed as a recess in the pattern forming step of the semiconductor chip, and is formed at a different position for each different pattern forming step. It is characterized by.

As described above, when the alignment pattern composed of the concave portions is formed at a different position for each semiconductor chip pattern forming process, the alignment patterns composed of the concave portions can be prevented from being continuously formed at the same position and overlapping. It is possible to prevent a phenomenon in which a misalignment occurs between the upper and lower patterns and the shape of the alignment pattern is distorted, and it is easy to aim the device on the alignment pattern.

The different positions at which the alignment pattern composed of the concave portions is formed may be a central position including the intersection of the two straight lines and a separated position apart from the intersection. The alignment pattern may be alternately formed at the center position and the separation position.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a method of forming a base point marker for specifying a position in a semiconductor chip and a method of forming the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is an explanatory view of a reference mark for specifying a position in a semiconductor chip according to a first embodiment of the present invention. In order to form an active region (field) in a semiconductor chip 12, a silicon nitride film is formed. FIG. 9 shows a base point marker for specifying a position in a semiconductor chip formed in an etching process of a (Si ₃ N ₄ film). FIG. 1A is a partial plan view of the silicon wafer, and FIG. 1B is a partial cross-sectional view taken along line AA of FIG. In this embodiment,
A case where a MOS transistor is formed on a semiconductor chip will be described as an example.

In FIG. 1A, a silicon wafer 10
In FIG. 1, a large number of square or rectangular semiconductor chips (chip forming regions) 12 are partitioned by scribe lines 14. The scribe line 14 is provided with mask alignment marks 18a and 18b for reticle alignment (not shown) corresponding to a pair of corners located on a diagonal line of each semiconductor chip 12. further,
A base mark 30 is formed on the scribe line 14 corresponding to each semiconductor chip 12. This base point marker 30
Are the mask alignment marks 18 of the semiconductor chip 12, for example.
Are provided at corners where no is provided (in the case of the embodiment, the lower left corner of the semiconductor chip 12). However, the base marker 3
The position at which 0 is provided may be arbitrarily set within the semiconductor chip 12, but if provided at a position close to a corner of the semiconductor chip 12, the base mark 30 can be easily found.

The base point marker 30 according to the first embodiment includes:
In a plurality of silicon nitride films 32 (32 _aa , 32 _ab ,..., 32 _nn ) formed in the semiconductor chip 12, a position P of a central portion of a predetermined silicon nitride film 32, for example, a silicon nitride film 32 _{bb. 1} is for the origin and O (0,0) is a base point for specifying the (x _1, y _1).

The silicon nitride film 32 is formed on the silicon wafer 1
0 is formed on the entire upper surface of the silicon substrate 34 constituting
After being deposited by the method described above, the film is etched so as to remain only in a portion where an active region is to be formed, and is divided into a plurality as shown in FIG. Then, the silicon wafer 10 having the silicon nitride film 32 is heated in an oxidizing atmosphere, and the exposed portion where the silicon nitride film 32 is not present is oxidized to form an element isolation region, and then the silicon nitride film 32 is removed. You.

On the other hand, the reference mark 30 is made of a silicon nitride film, and is formed simultaneously when the silicon nitride film 32 is etched and divided. The base point marker 30 has a matching pattern 36 formed in a cross shape. As shown in detail in FIG. 2A, the matching pattern 36 exists on two orthogonal straight lines 38 and 40 indicated by alternate long and short dash lines.
At the center position including the zero intersection point 42, both sides of the intersection point 42 are provided extending along the straight lines 38 and 40.
The length of the cross-shaped matching pattern 36 is SE
M is shorter than the length of the cross-shaped aim (cursor) 20 so that the aim 20 can be easily overlapped with the alignment pattern 36.

The orthogonal straight lines 38 and 40 are the X coordinate axis and the Y coordinate axis in the rectangular coordinate system.
2 is an origin O for specifying a position in the semiconductor chip 12. In addition, 4 divided by straight lines 38 and 40
In each of the four regions, that is, the first to fourth quadrants, a square dummy pattern 44 (44a to 44d) is provided near the matching pattern 36 to prevent the matching pattern 36 from being excessively etched. are doing. Then, the matching pattern 36 and the dummy pattern 44
2 is formed as a convex portion on the silicon substrate 34 as shown in FIG.

The thus formed base according to the first embodiment
The point marker 30 has a cross-shaped alignment pattern 36.
Therefore, the aim 20 of the SEM is easily aligned with the pattern 30
It is possible to superimpose on the designation in the semiconductor chip 12.
The position, eg P₁ (X ₁ , Y₁ Easy to find
The size of the pattern made of the silicon nitride film 32
Legal inspections and the like can be performed quickly and reliably.

As shown in FIG. 3, after a device isolation region 46 is formed on the silicon substrate 34, a silicon dioxide film is formed on the surface of the active region 48 which is a field defined by the device isolation region 46. A gate oxide film 50 of (silicon oxide film) is formed. Thereafter, a conductive film such as polycrystalline silicon is deposited on the silicon substrate 43 by CVD or the like, and this is etched to form the gate electrode 52. At this time, a reference mark for inspecting the width of the gate electrode 52 and the like is formed simultaneously with the gate electrode 52 by using polycrystalline silicon. This base point marker
By etching the polycrystalline silicon deposited on the silicon wafer 10, it is formed in the same position and the same size and the same shape as the base mark 30 shown in the first embodiment.

That is, as shown in FIG. 4A, a base point mark 54 formed of polycrystalline silicon is composed of a cross-shaped matching pattern 56 and four dummy patterns 58 (58a to 58d). I have. And
The cross-shaped alignment pattern 56 and the dummy pattern 58 have the same size as the alignment pattern 36 of the base point marker 30 and the dummy pattern 44 described above. In addition, as shown in FIG. 4B, the base mark 54 is formed in a convex shape on the gate oxide film 50 by using polycrystalline silicon, similarly to the base mark 30.

FIG. 5 shows a base point marker according to the second embodiment. The base point marker 60 according to this embodiment includes:
It is formed by a cross-shaped matching pattern 62. As in the first embodiment, the alignment pattern 62 extends along both sides of the origin O along the straight lines 38 and 40 at the center position including the origin O, which is the intersection of the two orthogonal straight lines 38 and 40. It is provided. However, the base point marker 60 does not have a dummy pattern adjacent to the cross-shaped alignment pattern 62.

The details of the matching pattern 62 are shown in FIG.
As shown in FIG. 5, the width of the alignment pattern 56 is narrower than that of the alignment pattern 56 made of polycrystalline silicon, and the length thereof is
It is shorter. However, the width of the alignment pattern 62 is wider than the width of the aim 20 so that the cross-shaped aim 20 of the SEM can be easily measured. Further, as shown in FIG. 6B, the alignment pattern 62 is formed as a cross-shaped hole, that is, a concave portion, and is formed, for example, when forming a hole such as a contact hole in an insulating film. That is, in the case of the present embodiment, the matching pattern 62 is formed in the insulating layer 72 covering the MOS transistor 70 shown in FIG.
b,...) are formed.

FIG. 7 shows a cross section of an n-channel MOS transistor 70, for example. In the MOS transistor 70, a gate electrode 52 made of polysilicon is provided on an active region 48 via a gate oxide film 50. Also, on one side of the gate electrode 52, a source 76 composed of n ⁺ diffusion region is provided, with each other is provided with a drain 78 made on the other side of the gate electrode 52 from the n ⁺ diffusion region,
A region between the source 76 and the drain 78 is a channel region 80 composed of a p-diffusion region. The MOS transistor 70 is covered with an insulating layer 72 made of silicon dioxide.

The base point marker 60 shown in FIGS.
It is provided as a concave portion when forming a contact hole 74 penetrating through the insulating layer 72 and the gate oxide film 56, and is used as an origin of coordinates for specifying the position of the contact hole 74 whose diameter is to be measured. The contact hole 74
Are the source 76, the drain 78 and the gate electrode 52
Is electrically connected to a wiring provided on the insulating layer 72.

The base marker 60 according to the second embodiment is
Since the width of the alignment pattern 62 formed as the concave portion is smaller than the width of the alignment pattern 36 of the base mark 30 and the alignment pattern 56 of the base mark 54, the width of the alignment pattern 62 depends on the wiring material in the next step of forming the wiring on the semiconductor chip 12. It is surely buried, and it is possible to prevent the shape of the reference mark formed in the wiring forming step from being collapsed.

In the manufacturing process of the semiconductor chip 12,
After the formation of the contact hole 74 shown in FIG. 7, a metal layer (a wiring material) made of aluminum or the like is deposited by sputtering or CVD while filling the contact hole 74 and covering the insulating layer 72. Then, the metal layer is etched so as to have a predetermined pattern, and as shown in FIG. 8, a wiring 82 (electrically connected to a source 76, a drain 78, a gate electrode 52, and the like via a contact hole 74). 82a, 82b,...).
Further, when the wiring 82 is formed by etching, a base point marker (not shown) for inspecting a dimension or the like of the wiring 82 at a predetermined position is formed on the scribe line 14 of the silicon wafer 10.

The base mark provided in the step of forming the wiring 82 is formed in a convex shape by the metal constituting the wiring 82, and is formed at the same position and the same size as the base mark 30 according to the first embodiment. It is composed of the formed cross-shaped pattern and the dummy pattern. Therefore, since the cross-shaped alignment pattern is larger than the alignment pattern 62 formed as the concave portion, even if the metal layer does not completely fill the alignment pattern 62,
It is possible to reliably form a convex cross-shaped alignment pattern made of a metal that does not lose its shape, to easily and surely overlap the sights 20, and to easily and quickly find the position of the designated wiring 82. Can be.

After the formation of the wiring 82, as shown in FIG. 9, an interlayer insulating layer 84 is provided so as to cover the wiring 82, and via holes 86 (86a, 86b,...) Are formed in the interlayer insulating layer 84. At this time, the base point marker 90 according to the third embodiment shown in FIG. 10 is formed at the same time. The base point marker 90 has a matching pattern 92 (92a to 92d). As shown in detail in FIG. 11A, these matching patterns 92 are provided at positions overlapping the cross-shaped matching pattern 94 of the base point marker formed together with the wiring 82. The width of the alignment pattern 92 is the width of the alignment pattern 9.
4 is smaller than the width.

The alignment patterns 92a and 92b are located on the straight line 38 which is the X axis. The matching pattern 92a is located on one side of the origin O (the right side of the origin O in FIG. 11A), which is the intersection of the straight lines 38 and 40, and is located at a distance away from the origin O. It is provided outside the alignment pattern 62 formed together with the contact hole 74. The alignment pattern 92b is provided on the other side of the origin O and away from the origin O, that is, outside the alignment pattern 62. On the other hand, the matching patterns 92c and 92d are located on the straight line 40 serving as the Y axis and are provided outside the matching pattern 62 separated from the origin O, and the matching pattern 92c is located on one side of the origin O (FIG. 11A). , The alignment pattern 92d is located on the other side of the origin O. And
As shown in FIG. 11B, these matching patterns 92 are formed in the interlayer insulating layer 84 as holes serving as concave portions. The width of the alignment pattern 92 is larger than the width of the aim 20 (not shown in the figure), as in the case of the alignment pattern 62.

The base point marker 90 according to the third embodiment thus formed is provided with the alignment patterns 92a to 92 located on the two orthogonal straight lines 38 and 40 and on both sides of the origin O.
Since it has 2d, it is possible to obtain substantially the same effect as when it is formed in a cross shape. In addition, since the alignment patterns 62 and 92 are formed at positions different from those of the previously formed concave alignment patterns 62, when the alignment patterns 62 and 92 are formed in an overlapping manner, it may occur when there is a positional shift (pattern shift) between the two. It is possible to eliminate the collapse of a simple shape and form a clear matching pattern 92. Therefore, the aim 20 can be easily and reliably overlapped with the alignment pattern 92.

As shown in FIG. 12, when a wiring 96 (96a, 96b,...) Is formed on the interlayer insulating layer 84, a base mark (not shown) formed together with the wiring 96 The same shape and the same size as the base marker 30 according to the first embodiment are formed at the same positions as the base marker 30. Further, an insulating layer 98 is provided to cover the wiring 96, and the insulating layer 98 is provided with a via hole 100 (100a, 100a).
00b,...) Are formed in the same position and the same size as the base marker 60 of the second embodiment shown in FIG. You. When an upper wiring (not shown) is provided on the insulating layer 98, the base marker (not shown) formed at this time is located at the same position as the base marker 30 according to the first embodiment. The same shape and the same size are formed. Then, in the case of further providing a base mark including the next concave portion, at the same position as the base mark 90 according to the third embodiment shown in FIG.
The same size is formed. That is, when the base point marker is formed as a concave portion, the base point marker is formed alternately at a central position including the intersection (origin O) of the straight lines 38 and 40 and at a separated position away from the intersection.

[0036]

As described above, according to the present invention, there is provided an alignment pattern provided on two orthogonal straight lines and located on both sides of the intersection of the two straight lines, thereby substantially aiming the equipment. Therefore, even if the edge portion is not sharp, it is possible to easily and accurately superimpose the devices, and it is possible to easily find a specified pattern to be inspected.

According to the method of manufacturing the reference mark according to the present invention, since the alignment pattern including the concave portion is formed at a different position for each semiconductor chip pattern forming process, the alignment pattern including the concave portion is continuously formed at the same position. This can prevent the pattern from being overlapped by being formed on the upper and lower surfaces, preventing a phenomenon in which a positional shift occurs between the upper and lower patterns and causing the shape of the alignment pattern to collapse, and making it easy to aim the device on the alignment pattern.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a base point marker according to a first embodiment of the present invention, wherein (1) is a partial plan view of a semiconductor wafer, and (2) is a cross-sectional view taken along line AA of (1). It is.

FIG. 2 is a detailed explanatory view of a position designation base point marker in the semiconductor chip according to the first embodiment, wherein (1) is a plan view,
(2) is a cross-sectional view along the line BB of (1).

FIG. 3 is an explanatory diagram of a step of forming a gate electrode of a MOS transistor.

FIGS. 4A and 4B are explanatory views of a base point marker according to an embodiment formed simultaneously with a gate electrode, wherein FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along line CC of FIG. .

FIG. 5 is an explanatory diagram of a position designation base point marker in a semiconductor chip according to a second embodiment of the present invention.

FIG. 6 is a detailed explanatory view of a base point marker according to the second embodiment, wherein (1) is a plan view, and (2) is a cross-sectional view along the line DD of (1).

FIG. 7 is a diagram illustrating a step of forming a contact hole in an insulating layer provided over the MOS transistor.

FIG. 8 is an explanatory diagram of a step of forming a wiring on an insulating layer.

FIG. 9 is an explanatory diagram of a step of forming a via hole in an interlayer insulating layer formed to cover a wiring.

FIG. 10 is an explanatory diagram of a base point marker according to a third embodiment.

FIG. 11 is a detailed explanatory view of a base point marker according to the third embodiment, in which (1) is a plan view and (2) is a cross-sectional view along line EE of (1).

FIG. 12 is an explanatory diagram of a step of providing a wiring and an insulating layer on an interlayer insulating layer.

FIG. 13 is an explanatory diagram of a conventional method of designating a pattern to be inspected.

FIG. 14 is a diagram illustrating an example of a conventional reason why a mask alignment mark serving as a reference for designating a position of a pattern to be inspected becomes unclear.

[Explanation of symbols]

10 Silicon wafer 12 Semiconductor chip 14 Scribe line 30, 54, 60 Base mark 32 _{aa to} 32 _nn 32 32 Pattern (silicon nitride film, gate electrode) 34 ... silicon substrate 36, 56, 62 ... matching pattern 38, 40 ... straight line 42 ... intersections 44a to 44d, 58a to 58d ... dummy pattern 74a, 74b, 82a, 82b ... pattern (contact Holes and wirings) 90... Origin markers 92a to 92d, 94... Matching patterns 86a, 86b... Patterns (via holes)

Claims (10)

[Claims] 1. A base point marker for designating a position in a semiconductor chip, provided on each of two orthogonal straight lines, located on both sides of an intersection of the two straight lines, and aiming at a device. A base point marker for specifying a position in a semiconductor chip, having a matching pattern. 2. The position mark in a semiconductor chip according to claim 1, wherein the alignment pattern is formed in a cross shape at a position including the intersection. Designation base indicator. 3. The base point marker for position designation in a semiconductor chip according to claim 2, wherein the alignment pattern is formed as a projection. 4. The base point marker for position designation in a semiconductor chip according to claim 3, wherein each of the four regions defined by the two orthogonal straight lines has a convex dummy pattern proximate to the matching pattern. A base point marker for specifying a position in a semiconductor chip, wherein a base mark is formed. 5. The base point marker for position designation in a semiconductor chip according to claim 2, wherein the matching pattern is formed as a concave portion. 6. The semiconductor device according to claim 1, wherein the alignment pattern is formed at a position separated from an intersection of the two orthogonal straight lines. The base point indicator for specifying the location within the. 7. The base point marker for position designation in a semiconductor chip according to claim 6, wherein the alignment pattern is formed as a concave portion. 8. The alignment mark formed as the concave portion according to claim 3, wherein the alignment pattern formed as the concave portion has a width of the alignment pattern formed as the convex portion according to claim 3. A base point marker for specifying a position in a semiconductor chip, wherein the base point marker is narrower. 9. A method of forming a base point marker for designating a position in a semiconductor chip, the method comprising: forming a base point marker on each of two orthogonal straight lines and at both sides of an intersection of the two orthogonal straight lines. An alignment pattern for aiming is formed as a recess in the pattern forming step of the semiconductor chip,
A method for forming a reference mark for position designation in a semiconductor chip, wherein the reference mark is formed at a different position for each different pattern forming step. 10. The method according to claim 9, wherein the different positions at which the matching pattern is formed are separated from a center portion including an intersection of the two straight lines and from the intersection. Separated position,
A method of forming a base point mark for designating a position in a semiconductor chip, wherein the alignment pattern is alternately formed at the center position and the separated position for each pattern forming step of the semiconductor chip.