JP2002073005A - Graphic processor and graphic processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a graphic processor and graphic processing method by which the memory utilizing efficiency of a parameter RAM part can be improved and a variety of graphic displays can be displayed, by adding character array information which is information about character arrays to a conventional parameter RAM part, and setting the optimum character array in a parameter RAM part. SOLUTION: An image memory address operation part 6 receives control information, a parameter RAM address correspondent to the sprite number outputted from the parameter RAM part 2, X origin coordinate value, Y origin coordinate value, sprite X size Nsx, sprite Y size Nsy, graphic data ROM address Ad (ROM), and character array information Arr or the like, generates an upper address of graphic data ROM and a lower address of graphic data ROM, and then reads character data stored in a graphic data ROM 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic processing apparatus and a graphic processing method, and more particularly to a graphic processing capable of registering more graphic data by efficiently using a memory capacity for registering a display graphic. The present invention relates to an apparatus and a graphic processing method.

[0002]

2. Description of the Related Art In recent years, a graphic processing apparatus has been required to cope with complicated and sophisticated graphic display on a screen and to further improve the processing speed of the graphic. A conventional graphic processing apparatus will be described with reference to FIGS.

FIG. 19 is a block diagram showing a conventional graphic processing apparatus, and FIG. 20 is a detailed block diagram of the image memory address calculating section 196 of FIG.

The graphic processing apparatus shown in FIG. 19 includes a CPU 198 for controlling the entire graphic processing apparatus and a graphic processing section 19 for performing a graphic drawing process in accordance with a command issued from the CPU 198.
00, a graphic data ROM 199 that outputs character data corresponding to a graphic data ROM address output from an image memory address calculation unit 196 included in the graphic processing unit 1900, and a display device 1910 such as a liquid crystal display device or a CRT. Have.

The graphic processing unit 1900 includes a CPU 198
A graphic control unit 191 for decoding each instruction and controlling each circuit block constituting the graphic processing unit 1900, X and Y coordinate values for determining the position of the graphic in the screen display area, the size of the graphic, and the graphic data ROM 199 to be referred to A parameter RAM unit 192 in which parameters such as a graphic data ROM address as address information are stored, and whether or not a graphic is in a screen display area is determined.
And a hit judging section 193 for outputting the graphic data ROM address stored in the AM section 192.

Further, the graphic processing unit 1900 refers to the hit information, outputs a graphic information of a graphic in a screen display area, a counter control unit 194, a display graphic buffer memory 195 for storing the graphic information, and FIG. As shown in the figure, the control information from the graphic control unit 191 and the sprite number output from the parameter RAM unit 192, (sprite X
The size Nsx-1), the scanning line value, and the Y origin coordinate value are input, and a drawing end signal, an image memory address operation unit 196 for generating a graphic data ROM upper address and a graphic data ROM lower address, and the graphic data ROM 199 are taken out. And an image data modification operation unit 197 that performs modification processing such as texture on the obtained character data.

Next, the operation of the conventional graphic processing apparatus shown in FIG. 19 will be described.

The graphic control unit 191 decodes an instruction from the CPU 198 and sets graphic parameters in the parameter RAM unit 192. As shown in FIG. 21, the configuration of the parameter RAM 192 is such that, for each address of the parameter RAM 192, an X origin coordinate value, a Y origin coordinate value, a sprite X size Nsx, a sprite Y size Nsy,
It is configured to include each information of the graphic data ROM address.

As shown in FIG. 22, when two display figures 222 and 223 exist in the screen display area 221, the upper left corner of the screen display area 221 is set to the screen display area 221.
, The X-coordinate value, the Y-coordinate value (Xm, Ym), and (Xn,
Yn) is defined as the X origin coordinate value and the Y origin coordinate value of the display graphics 222 and 223, respectively.

In the X direction and Y direction of the display figures 222 and 223,
The length in the direction is expressed in units of pixels in the display figures 222 and 22.
3 as sprite X size Nsx and sprite Y size Nsy.

Next, the hit judging section 193 includes the graphic control section 1
Reference is made to the graphic parameters stored in the parameter RAM unit 192 based on the control information output from the controller 91, and whether or not the graphic stored in the parameter RAM unit 192 exists in the screen display area 221 shown in FIG. Is determined, and the hit information activated for the graphic displayed on the screen display area is determined by the counter control unit 19.
4 is output.

The counter control section 194 is provided with a hit judging section 19.
When the hit information is activated with reference to the hit information output from No. 3, the sprite number corresponding to the hit information is stored in the display graphic buffer memory 195.

Next, the image memory address operation unit 196
In response to the control information, the graphic parameter corresponding to the sprite number stored in the display graphic buffer memory 195 is read from the parameter RAM unit 192, and the graphic data RO storing the character data constituting the display graphic is stored.
A figure data ROM address for reading character data from M199 is calculated, and the figure data ROM 199 is read.
Output the graphic data ROM address.

Next, the image data modification operation unit 197 receives the control information, inputs the character data to be displayed from the graphic data ROM 199, and performs image data modification processing such as translucent processing such as texture, enlargement / reduction, and alpha blending. Then, the image signal is output to the display device 1910 for displaying the image signal on the screen.

Recently, various functions have been demanded of the graphic processing apparatus. One of such functions is an animation display function.

Next, an explanation will be given of a case where an animation figure generated by synthesizing a plurality of figures called sprites by using the above-described conventional figure processing apparatus is continuously displayed for animation display.

An example of a sprite will be described with reference to FIG. 24. FIG. 24A shows a sprite SP1 having triangular opaque data, and FIG.
FIG. 24C shows a sprite SP2 having rectangular fill data generated by extracting a part of P1.

FIG. 24D shows a sprite SP4 in a case where the sprite SP2 and the sprite SP3 are combined and the sprite SP2 and the sprite SP3 are made opaque, with the sprite SP2 facing the front and the sprite SP3 facing the back.

The sprites SP1 to SP4 are 8 pixels × 8 pixels or 16 pixels ×
It is composed of unit graphics stored in a graphics data ROM 199 of 16 pixels.

Characters are stored in the graphic data ROM 199 in the order of consecutive addresses as shown in FIG. 23A. When a sprite is formed from these characters, as shown in FIG. And a method of sequentially arranging characters in the horizontal (X) direction, and FIG.
As shown in FIG. 3C, there is a method of sequentially arranging characters in the vertical (Y) direction.

Here, CH1 to CH16 represent character numbers. 23 (b) and FIG. 23 (c) have the same image data of the characters CH1 to CH16, and the arrangement of the characters CH1 to CH16 is different, so that FIG. 23 (b) and FIG. The displayed image data differs.

In FIGS. 23 (b) and 23 (c), the character X
The size Xc and the character Y size Yc represent the size of the character in the X and Y directions in pixel units.
CH and YCH are parameters representing the horizontal and vertical positions of the character. For example, in FIG. 23B, XCH = 1 and YCH = 2 represent the character CH10.

Further, the sprite X size Nsx and the sprite Y size Nsy, which are obtained by adding 1 to the maximum values of XCH and YCH, respectively, represent the number of horizontal and vertical characters constituting the sprite, that is, the sprite size.

As described above, the sprite is configured by arranging characters stored in the graphic data ROM 199 in the horizontal and vertical directions.
Graphic data ROM address Ad (ROM) shown in FIG.
Is displayed by reading character data from the graphic data ROM 199 with reference to FIG.

Next, sprites SP1 and SP shown in FIG.
An example of generating an animation using SP3 and SP4 will be described with reference to FIG.

As shown in FIGS. 25 (a), 25 (b) and 25 (c), reference numerals 251 to 253 denote animation figures.
1, SP4 and SP3 are animation figures 251 to 25
3 is a sprite. The animation figures 251 to 253 are continuously displayed on the screen display area to generate an animation.

Assuming that the character arrangement of the sprite SP1 is FIG. 25 (a) 'and the character arrangement of the sprite SP3 is FIG. 25 (c)', the character arrangement of the sprite SP4 is as shown in FIG. 25 (b) '. Become.

Next, the image memory address calculation section 196 constituting the conventional image processing apparatus will be described with reference to FIG.

A conventional image memory address calculation unit 196
Is composed of a character count section 201, a subtraction circuit 202, an address separation section 203, addition circuits 204 and 206, and a multiplication circuit 205.

Next, the operation of the above circuit will be described.
The description will be made assuming that the character arrangement is the horizontal (X) direction shown in FIG. 23B, and that the drawing process proceeds from the left to the right, that is, in the positive direction in the X direction.

The subtraction circuit 202 subtracts the Y origin coordinate value, which is the Y coordinate of the upper left corner of the sprite, from the scanning line value corresponding to the scanning line number in the display screen area, and obtains a value obtained by subtracting the value.
Output to 3.

The address separating unit 203 counts the characters constituting the sprite from the character at the top (closest to the Y axis), and indicates the Y-direction character address YCH indicating the character and the scanning line. A figure data ROM lower address indicating the number in the positive direction in the Y direction from the uppermost scanning line constituting the character is calculated.

On the other hand, the character counting section 201 performs a counting operation in synchronization with the control information, and outputs a character count value which is an array number of the character in the X direction.

The adder 206 has a sprite X size N
The product of sx and the Y-direction character address YCH, the sprite number which is a sprite-specific number, and the character count value are added to generate a graphic data ROM upper address indicating a higher address for the graphic data ROM 199. Here, all addresses for the graphic data ROM 199 are constituted by the graphic data ROM upper address and the graphic data ROM lower address described above.

The character counting section 201 is provided in FIG.
As shown in (b), the character count value is incremented in order from 0 to the last character in the X direction constituting the sprite, and a drawing end signal indicating that drawing of all the characters constituting the sprite has been completed lastly. Output.

When the above operation for one sprite is completed, the same processing is performed for the next sprite, and the same processing is repeated for all sprites in the screen display area, so that all images composed of sprites are processed. Perform data display.

[0037]

When the conventional graphic processing apparatus described above is focused on the sprite SP3 shown in FIG. 25 (b), the character arrangement is limited to the horizontal (X) direction. The character numbers in the third column are discontinuous.

Therefore, the parameter RAM section 192 has
Four figures, that is, characters CH2 and CH3, characters CH6 and CH7, and characters CH10 and CH
11 and the characters CH14 and CH15 must be stored independently.

For this reason, the memory use efficiency of the parameter RAM unit 192 decreases, the number of figures that can be stored in the parameter RAM unit 192 decreases, and it becomes difficult to perform various displays using more figures.

Conversely, if the memory capacity of the parameter RAM unit 192 is increased to store all the required graphics, there is a problem that the cost of the graphics processing apparatus increases.

Further, when the figures stored in the parameter RAM section 192 increase, the figures to be controlled from the CPU 198 in FIG. 19 via the figure control section 191 increase, so that the processing time increases and the processing speed of the entire figure processing apparatus decreases. There is a disadvantage of doing so.

Therefore, an object of the present invention is to add character arrangement information, which is information relating to character arrangement, to a conventional parameter RAM section, and to set an optimum character arrangement based on the character arrangement information in the parameter RAM section. An object of the present invention is to provide a graphic processing device and a graphic processing method in which the memory use efficiency of the parameter RAM unit is improved.

Further, the object of the present invention is to provide a common image memory address calculation unit, which allows a character image arrangement in the horizontal (X) direction and a character arrangement in the vertical (Y) direction to coexist in the parameter RAM unit. Data ROM
It is an object of the present invention to provide a graphic processing device and a graphic processing method capable of generating an address for reading character data from a graphic.

Another object of the present invention is to provide a parameter RAM.
In addition to the horizontal and vertical directions and the method of mixing the horizontal and vertical directions, the diagonal direction or the array direction is defined by a function, and the parameter RAM
It is an object of the present invention to provide a graphic processing device and a graphic processing method capable of displaying various animations without significantly increasing the memory capacity of a section.

[0045]

Therefore, a graphic processing apparatus according to the present invention displays a sprite in which characters composed of a plurality of pixel data are arranged in a matrix in an X direction and a Y direction in a screen display area. A parameter RAM unit that includes character arrangement information that is information relating to the arrangement of the characters, and stores sprite graphic information that is graphic information of the sprite;
A graphic data ROM for storing character data which is image data of the character; and a graphic data ROM address which is address information for the graphic data ROM for reading out the character data by referring to the graphic information and the character arrangement information. And an image data modification operation unit that receives the character data and generates an image signal for display on a display device.

The graphic processing method according to the present invention is a graphic processing method for displaying, in a screen display area, a sprite in which characters composed of a plurality of pixel data are arranged in a matrix in the X and Y directions. A first step of sequentially incrementing a character count value representing an order in the X direction, which is a scanning line direction of the character, and a scan indicating a Y direction number of a scanning line scanning in the X direction of the screen display area. From the linear value, the Y
A second step of subtracting the origin coordinate value and calculating an in-character scanning line value that is a scanning line value in the character; and calculating the in-character scanning line value in the Y direction of the pixel data constituting the character. Divided by the number of arrays, the Y direction character address indicating the character order of the character in the Y direction, which is the quotient, and the lower address of the address information of the graphic data ROM for storing the character data as the image data of the character. A third step of outputting a certain figure data ROM address lower address, and, when the character arrangement is in the X direction, multiplying the sprite X size, which is the size of the sprite in the X direction, by the Y direction character address; And a fourth step of holding the character count value, and the character array is Y A fifth step of holding the Y-direction character address and multiplying the sprite Y size, which is the size of the sprite in the Y direction, by the character count value; A sixth step of calculating a graphic data ROM address upper address, which is an upper address of the graphic data ROM address, by referring to each multiplication result calculated in step 5.

[0047]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a graphic processing apparatus according to the present invention, and FIG. 2 is a block diagram showing an image memory address calculator 6 shown in FIG.
It is a detailed block diagram of.

The graphic processing apparatus shown in FIG. 1 includes a CPU 8 for controlling the entire graphic processing apparatus, a graphic processing section 100 for performing a graphic drawing process in accordance with a command issued from the CPU 8, and an image memory constituting the graphic processing section 100. A graphic data ROM 9 for outputting character data corresponding to a graphic data ROM address output from the address calculation unit 6 and a display device 10 such as a liquid crystal display device or a CRT are provided.

The graphic processing unit 100 decodes an instruction from the CPU 8 and controls each circuit block constituting the graphic processing unit 100, and X and Y coordinate values for determining the position of the graphic in the screen display area. , The size of the figure, and the figure data RO which is the address information of the figure data ROM 9 to be referred to.
A parameter RAM unit 2 in which parameters such as an M address and character arrangement information as character arrangement information of a sprite are stored, and whether or not a figure is present in a screen display area is determined. And a hit judging section 3 for outputting a graphic data ROM address stored in the ROM.

The graphic processing unit 100 further stores a display sprite number storage unit 11 for storing the number of all sprites to be displayed in one screen display area, and counts the number of sprites to be displayed by referring to activated hit information. FIG. 2 shows a sprite number calculation unit 12 to be increased, a counter control unit 4 that outputs graphic information of a sprite in a screen display area with reference to hit information, a display graphic buffer memory 5 that stores this graphic information, As shown, the character count control signal from the graphic control unit 1 and the sprite number, Y origin coordinate value output from the parameter RAM unit 2, (sprite X size Nsx-1), (sprite Y size Ns)
y-1), the character array information Arr and the like are input, and an image memory address calculation unit 6 for generating a drawing end signal, a graphic data ROM upper address and a graphic data ROM lower address, and character data extracted from the graphic data ROM 9 And an image data modification operation unit 7 for performing modification processing such as texture.

Next, the operation of the graphic processing apparatus of the present invention shown in FIG. 1 will be described.

The graphic controller 1 decodes an instruction from the CPU 8 and sets graphic parameters in the parameter RAM 2.

As shown in FIG. 3, the configuration of the parameter RAM 2 is such that, for each address corresponding to each sprite in the screen display area, as shown in FIG. 22, the X coordinate of the reference origin (upper left corner) of the sprite X origin coordinate value P which is the value
x, Y origin coordinate value Py which is the Y coordinate value of the reference origin of the sprite, sprite X size Nsx which is the sprite X size calculated in character units, and sprite Y direction size calculated in character units It is configured to include a certain sprite Y size Nsy, a graphic data ROM address Ad (ROM) used for reading a character from the graphic data ROM 9, character arrangement information Arr for determining the character arrangement direction, and the like.

The graphic control unit 1 extracts sprite graphic information from the parameter RAM unit 2 in the order of processing, and outputs this information to the hit determination unit.

Next, the hit judging section 3 refers to the graphic information stored in the parameter RAM 2 based on the control information output from the graphic control section 1 and displays the graphic stored in the parameter RAM section 2 on the screen display area shown in FIG. 221, that is, whether or not to display this graphic,
The hit information activated for the graphic displayed on the screen display area and the address of the parameter RAM unit 2 are output to the counter control unit 4.

The counter control unit 4 refers to the hit information output from the hit judging unit 3, and when the hit information is activated, stores the sprite number of the sprite corresponding to the hit information in the display graphic buffer memory 5. . At this time, the counter control unit 4 refers to the number of all sprites displayed in one screen display area stored in the display sprite number storage unit 11 and the number of sprites calculated by the sprite number calculation unit 12, It operates to output the sprite number corresponding to the activated hit information to the display graphic buffer memory 5.

When the hit judging section 3 completes the hit judgment for all sprites, the graphic control section 1 reads out the stored sprite number from the display graphic buffer memory 5. Then, the graphic information relating to the sprite to be displayed is read from the parameter RAM unit 2 with reference to the read sprite number. The graphic information of the sprite graphic thus read is output to the image memory address operation unit 6 and the image data modification operation unit 7.

Next, the image memory address operation unit 6 receives the control information, refers to the graphic information corresponding to the sprite number stored in the display graphic buffer memory 5, and stores the character data constituting the sprite. A figure data ROM address for reading character data is calculated from the figure data ROM 9, and the figure data ROM
9 to output the graphic data ROM address.

The image data modification operation unit 7 receives the control information, inputs the character data to be displayed from the graphic data ROM 9, and performs image data modification processing such as texture, enlargement / reduction, and translucent processing such as alpha blending. Display device 1 for displaying an image signal on a screen
Output to 0.

Next, a case will be described in which an animation graphic using a plurality of sprites shown in FIG. 4 is continuously displayed and an animation is displayed using the graphic processing apparatus of the present invention described above.

First, the sprites SP1 to SP4 will be described. SP1 is a sprite having opaque triangular data as shown in FIG.
As shown in FIG. 4B, the sprite is generated by extracting a part of the sprite SP1, SP3 is a sprite having rectangular fill data as shown in FIG. 4C, and SP4 is a sprite having rectangular fill data as shown in FIG. Sprite SP as shown in)
2 is a sprite in which the sprite SP2 and the sprite SP3 are combined and the sprite SP2 is opaque and the sprite SP2 and the sprite SP3 are combined. Here, the characteristic point is that, unlike the character arrangement of FIG. 25A ′, the sprite SP1 has characters arranged in the vertical direction.

The character array information Arr shown in FIG.
(B) (b indicates binary data) indicates that the character array is in the horizontal (X) direction, and when the character array information Arr is 1 (b), the character array is vertical (Y) Indicates a direction.

As described above, the graphic processing apparatus according to the present invention
The character array information Arr is provided in the parameter RAM unit 2, and the image memory address calculation unit 6 generates the graphic data ROM address with reference to the character array information Arr, so that FIG. 4 (a) 'and (b)' , (C) '
As shown in (1), characters constituting the sprite can be arranged in any combination of the horizontal direction and the vertical direction. Thus, various figures can be stored in the parameter RAM unit 2 without increasing the memory capacity of the parameter RAM unit 2.
, And a complicated animation display can be performed.

Here, the memory structure of the animation figure shown in FIGS. 25 (b) and (b) 'in the conventional parameter RAM section 192 and FIGS. 4 (b) and (b)' in the parameter RAM section 2 of the present invention. A description will be given while comparing with the memory structure of the animation figure shown.

FIG. 5A shows a conventional parameter RAM 1.
25 shows a memory configuration corresponding to the animation figure of FIGS. 25 (b) and (b) ′, and the first line of the sprite SP2 has characters CH2 and CH3 arranged therein and is composed of these characters CH2 and CH3. X origin coordinate value and Y origin coordinate value of the figure
0. The sprite X size Nsx and the sprite Y size Nsy are 2 and 1, respectively.

In the second line of the sprite SP2, characters CH6 and CH7 are arranged. The X origin coordinate value of the figure composed of these characters CH6 and CH7 is not changed from the X origin coordinate value X0. 1 character
With a configuration of 6 pixels × 16 pixels, since the Y origin coordinate value moves 16 pixels in the positive Y direction, Y0 +
It becomes 16. The sprite X size Nsx and the sprite Y size Nsy are 2 and 1, respectively, as in the first row.

Similarly, the third and fourth rows of the sprite SP2 are as shown in FIG.

As for the sprite SP3 which is synthesized with the sprite SP2, the X origin coordinate value is
16 pixels smaller than the X origin coordinate value of X2, X0
−16, and the Y origin coordinate value is the above-mentioned sprite SP2.
Is the same as the Y origin coordinate value Y0.

The sprite X size Nsx and the sprite Y size Nsy of the sprite SP3 are both 4.

On the other hand, FIG. 5B shows a parameter R of the present invention.
FIG. 5B shows a memory configuration corresponding to the animation figure of FIGS. 4B and 4B ′ in AM2. As can be seen from FIG.
(B), which indicates that the character array is in the vertical direction. The sprite X size Nsx and the sprite Y size Nsy are 2 and 4, respectively. The sprite SP3 is the same as that in FIG.

As described above, in the conventional parameter RAM unit 192, a memory capacity of five rows is required to represent the animation graphic shown in FIG.
Parameter RAM unit 2 constituting the graphic processing apparatus of the present invention
In this case, only two rows of memory capacity are required to represent the animation graphic of FIG. 4B, so that the memory capacity can be significantly reduced.

Next, the image memory address calculating section 6 constituting the graphic processing apparatus of the present invention will be described with reference to FIGS. 2 (a) and 2 (b).
A brief description will be given using.

As shown in FIG. 2A, the image memory address calculation unit 6 according to the present embodiment includes a character count control signal, which is a part of control information output from the graphic control unit 1, and a sprite X size. A value obtained by subtracting 1 from Nsx is input, and the character count unit 21 that increments the character count value in synchronization with the character count unit control signal, and the number of the scanning line from the top scanning line (closest to the Y origin) From the scanning line value indicating whether the scanning line
A subtraction circuit 22 for subtracting the origin coordinate value, and the output data of the subtraction circuit 22 are divided by the number of pixels in the vertical direction constituting the character, and the result of the division is YCH representing the character address in the Y direction, which is a quotient, and the remainder. The address separation unit 23 for calculating the lower address of the graphic data ROM, the AND gate 27 for inputting the character arrangement information and the value obtained by subtracting 1 from the sprite Y size Nsy, and subtracting 1 from the character arrangement information and the sprite X size Nsx And an AND gate 28 for inputting a value.

Further, the image memory address calculator 6 according to the present embodiment includes an adder circuit 29 for adding 1 to the output data from the AND gate 27 and an adder circuit 24 for adding 1 to the output data from the AND gate 28. , A multiplication circuit 25A that multiplies the character count value by the output data of the addition circuit 29, and Y output from the address separation unit 23.
A multiplication circuit 25B for multiplying the output data of the addition circuit 24 by the YCH representing the character address in the direction, a sprite number and the output data of the multiplication circuits 25A and 25B are added, and the character data stored in the graphic data ROM 9 is added. And an adder circuit 26 for generating a graphic data ROM upper address which is an upper address of the graphic data ROM address for reading the data.

If the character arrangement is a horizontal arrangement, the character arrangement information is 0 (b),
When the character arrangement is a vertical arrangement, the character arrangement information is 1 (b).

When the character arrangement information is 0 (b), A
By the ND gate 27 (sprite Y size Nsy-
1) is masked, and 0 is output from the AND gate 27. Then, 1 is added by the addition circuit 29, and the multiplication circuit 25A outputs the character count value to the addition circuit 26 as it is.

On the other hand, the AND gate 28 is connected to the (sprite X
The size Nsx-1) is output, and the adding circuit 24 outputs a sprite X size Nsx. The multiplication circuit 25B multiplies the sprite X size Nsx by the character address in the Y direction, and outputs the multiplication result to the addition circuit 26.

On the other hand, when the character arrangement information is 1 (b), the AND gate 28 (sprite X size Ns
x-1) is masked, and 0 is output from the AND gate 28. Then, 1 is added by the addition circuit 24, and the multiplication circuit 25B outputs the character address YCH in the Y direction as it is to the addition circuit 26.

On the other hand, the AND gate 27 is connected to the (sprite Y
Then, the adder circuit 29 outputs a sprite Y size Nsy. The multiplication circuit 25A multiplies the sprite Y size Nsy by the character count value, and outputs the multiplication result to the addition circuit 26.

As described above, the image memory address calculation unit 6 according to the present embodiment transmits the sprite number, the character count unit control signal, and the (sprite X size Nsx
-1), (sprite Y size Nsy-1), character array information, scanning line value, and Y origin coordinate value, and the graphic data ROM upper address and the graphic data ROM are input.
Generate the lower address.

FIG. 2B shows a timing chart of the image memory address calculating section 6 shown in FIG.

The character count section control signal generates a pulse signal prior to the drawing processing of the character data CH1 to CHn, and the character count section forms a sprite from 0 in synchronization with the pulse signal (number of characters -1). When the drawing of all the characters constituting the sprite is completed, a drawing end signal is output.

Referring to FIGS. 6 and 7, the operation of image memory address calculating section 6 according to the present embodiment when the character arrangement is the horizontal arrangement shown in FIG. Will be described.

In FIG. 6A, the characters CH1 to CH16 constituting the sprite SP6 are arranged four by four in the horizontal direction and the vertical direction, and the number of pixels in each character in the vertical direction, that is, the number of scanning lines is 16. Here, the scanning line for each character is set to l in the positive direction of Y.
1 to 116, the scanning line (first scanning line) closest to the origin of the screen display area is defined as L1, and L2 is sequentially set in the positive Y direction.
L3... L16, L17, L18. That is, L1, L2... Represent the absolute number of the scanning line, and l
0 to 115 represent relative scanning line numbers for each character.

To simplify the description, the coordinate value of the Y origin of the sprite SP6 is set to 0, that is, the sprite SP6
The description will be made assuming that the upper left corner of the mark coincides with the origin of the screen display area.

Now, the scanning lines are characters CH5, 6, 7,
Consider the fourth scanning line of No. 8, ie, the memory address in the case of 14 (L20).

FIG. 6B shows the character arrangement of the graphic data ROM 9 of the characters CH1 to CH16 constituting the sprite SP6, and the graphic data ROM upper address which is the upper address in the graphic data ROM 9 of the characters CH1 to CH16 is 0 to 0. 15 is shown. As can be seen from FIG. 6B, the character CH5
The graphic data ROM upper addresses of .about.CH8 are 4-7.

The scanning line L20 includes the characters CH5 to CH5.
Corresponding to the scanning line 14 of CH8 and the graphic data RO
This indicates that the M lower address is 4. Therefore, the graphic data ROM
The character number of the character 9 is uniquely determined, and the scanning line position in the character is determined by the graphic data ROM lower address.

That is, by specifying the graphic data ROM upper address and the graphic data ROM lower address, character data to be drawn can be read from the graphic data ROM 9 for each scanning line.

FIG. 6C shows the character number, graphic data ROM upper address and graphic data R described above.
The relationship between the OM lower addresses is shown.

Next, the operation of the image memory address calculation unit 6 in the case shown in FIG. 6 will be described with reference to FIG.

As can be seen from FIG. 6A, since the Y origin coordinate value and the scanning line value are 0 and 20, respectively, and the sprite X size Nsx and the sprite Y size Nsy are respectively 4, (sprite X size Nsx-1),
(Sprite Y size Nsy-1) is 3, and the character arrangement information is 0.

The subtraction circuit 22 subtracts the Y origin coordinate value (= 0) from the scanning line value (= 20) and outputs 20 to the address separation section 23. The address separating unit 23 converts the input data 20 into the number of vertical pixels 16 constituting a character.
Then, YCH representing the character address in the Y direction, which is the quotient, is set to 1 from the result of the division, and the same value as the graphic data ROM lower address shown in FIG.

The output of the AND gate 27 becomes 0 because the character arrangement information is 0, and the addition circuit 29 outputs the 0
Multiplication circuit 25A generated by adding 1 and a constant 1
Output to Also, the output of the AND gate 28 becomes 3, and
The addition circuit 24 outputs 4 generated by adding 3 to the constant 1 to the multiplication circuit 25B.

The multiplication circuit 25B multiplies the character address YCH (= 1) in the Y direction by 4 output from the addition circuit 24, and outputs 4 generated to the addition circuit 26.

The character counting section 21 multiplies output data from 0 to (sprite X size Nsx-1) = 3, that is, 0 → 1 → 2 → 3 output data in synchronization with the character counting section control signal. Output to 25A. Therefore, the multiplication circuit 25A outputs 0 → 1 → 2 → 3 data to the addition circuit 26.

Assuming that the sprite number is 0,
The adder circuit 26 stores the graphic data ROM shown in FIG.
4 to 7 that are the same as the upper address are generated.

Next, with reference to FIGS. 8 and 9, the operation of the image memory address calculating section 6 according to the present embodiment when the character arrangement is the vertical arrangement shown in FIG. Will be described.

In FIG. 8 (a), the characters CH1 to CH16 constituting the sprite SP8 are arranged four by four in the horizontal and vertical directions, and the number of pixels of each character in the vertical direction, that is, the number of scanning lines is 16. Here, the scanning line for each character is set to l in the positive direction of Y.
1 to 116, the scanning line (first scanning line) closest to the origin of the screen display area is defined as L1, and L2 is sequentially set in the positive Y direction.
L3... L16, L17, L18. That is, L1, L2... Represent the absolute number of the scanning line, and l
0 to 115 represent relative scanning line numbers for each character.

To simplify the description, the coordinate value of the Y origin of the sprite SP8 is set to 0, that is, the sprite SP8
The description will be made assuming that the upper left corner of the mark coincides with the origin of the screen display area.

Now, the scanning lines are characters CH2, 6, 1
Consider the fourth scanning line of 0,14, that is, the memory address in the case of l4 (L20).

FIG. 8B shows the character arrangement of the graphic data ROM 9 of the characters CH1 to CH16 constituting the sprite SP8, and the graphic data ROM upper address which is the upper address in the graphic data ROM 9 of the characters CH1 to CH16 is 0 to 0. 15 is shown. As can be seen from FIG. 8B, the character CH
The figure data ROM upper addresses of 2, 6, 10, and 14 are 1, 5, 9, and 13, respectively.

The scanning line L20 is composed of the characters CH2 and CH2.
It corresponds to 6, 10, and 14 scanning lines 14 and indicates that the lower address of the graphic data ROM is 4.
Therefore, the character number constituting the graphic data ROM 9 is uniquely determined by the graphic data ROM upper address, and the scanning line position in the character is determined by the graphic data ROM lower address.

That is, by specifying the graphic data ROM upper address and the graphic data ROM lower address, character data to be drawn can be read from the graphic data ROM 9 for each scanning line.

FIG. 8C shows the character number, graphic data ROM upper address and graphic data R described above.
The relationship between the OM lower addresses is shown.

Next, the operation of the image memory address calculation unit 6 in the case shown in FIG. 8 will be described with reference to FIG.

As can be seen from FIG. 8A, the Y origin coordinate value and the scanning line value are 0 and 20, respectively, and the sprite X size Nsx and the sprite Y size Nsy are 4 respectively. Nsx-1),
(Sprite Y size Nsy-1) is 3, and the character arrangement information is 1.

The subtraction circuit 22 subtracts the Y origin coordinate value (= 0) from the scanning line value (= 20) and outputs 20 to the address separation section 23. The address separating unit 23 converts the input data 20 into the number of vertical pixels 16 constituting a character.
The character address YCH in the Y direction, which is the quotient, is set to 1 from the result of the division, and the same value as the graphic data ROM lower address shown in FIG.

The output of the AND gate 28 becomes 0 because the character arrangement information is 1, and the addition circuit 24 outputs the 0
Multiplication circuit 25B generated by adding 1 and a constant 1
Output to Also, the output of the AND gate 27 becomes 3, and
The addition circuit 29 outputs 4 generated by adding 3 to a constant 1 to the multiplication circuit 25A.

The multiplying circuit 25B multiplies the character address YCH (= 1) in the Y direction by 1 output from the adding circuit 24 and outputs 1 to the adding circuit 26.

The character counting section 21 outputs 0 → 1 → 2 → 3 data to the adding circuit 26 in synchronization with the character counting section control signal, as described above.

Assuming that the sprite number is 0,
The adder circuit 26 stores the graphic data ROM shown in FIG.
The same 1, 5, 9, 13 as the upper address is generated.

As described above, the image memory address calculation section 6 constituting the image processing apparatus of the present invention uses the character array information corresponding to the case where the character array is in the horizontal direction and the vertical direction to determine whether the character array is in the horizontal direction or in the horizontal direction. 6 (c) or 8 (c) regardless of the vertical direction.
The graphic data ROM upper address and the graphic data ROM lower address shown in FIG.

Next, a graphic processing method using the graphic processing apparatus of the present invention will be described with reference to the drawings.

FIG. 10 is a flowchart showing the processing method of the image memory address calculating section 6 of the present invention shown in FIG. 2. In step ST1, the graphic control section 1 determines whether or not the image processing has been completed. When it is determined that the process has been completed, the character counting unit 21 shown in FIG. 2 is reset by the character counting unit control signal in step ST11, and performs the process of step ST12. Step S
At T12, the hit determination unit 3 determines whether a sprite to be drawn next exists in the screen display area. If it is determined that a sprite to be drawn next does not exist in the screen display area, the hit determination unit 3 determines in step ST13. The drawing process for the entire screen display area is completed, and the drawing processing for the screen display area of the next frame is performed.

If it is determined in step ST12 that there is a sprite to be drawn next, the process of step ST1 is performed.

When it is determined in step ST1 that the image processing has not been completed, in step ST2, the character counting section 21 increments the character count value.

Subsequently, in step ST3, the relative scanning line number based on the Y origin coordinate value of the character is calculated by subtracting the Y origin coordinate value from the scanning line value.

Next, in step ST4, the address separating section 23 generates the YCH representing the character address in the Y direction and the lower address of the graphic data ROM, and the image memory address calculating section 6 determines in step ST5 that the character arrangement information is in the horizontal direction. When the information that the character arrangement information is vertical is received, the process of step ST9 is performed.

If it is determined in step ST5 that the character arrangement information is in the horizontal direction, the process proceeds to step S5.
At T6, the multiplication circuit 25B multiplies the sprite X size Nsx output from the addition circuit 24 by the character address YCH in the Y direction output from the address separation unit 23, and outputs the multiplication result to the addition circuit 26. Then, in step ST7, the character counting section 21 keeps holding the character count value without incrementing it.

On the other hand, if it is determined in step ST5 that the character arrangement information is in the vertical direction, the process in the next step ST10 is performed while holding the character address YCH in the Y direction in step ST9. In step ST10, the multiplication circuit 25A multiplies the sprite Y size Nsy output from the addition circuit 29 by the character count value output from the character counting section 21, and outputs the multiplication result to the addition circuit 26.

Finally, the addition circuit 26 is provided with a multiplication circuit 25A,
The multiplication result from 25B and the sprite number are respectively added to generate a graphic data ROM upper address.

Next, the image memory address calculator 6 of the present invention
The second embodiment will be described with reference to FIGS. Note that components common to FIG. 2 are denoted by common reference characters / numbers.

FIG. 11 is a block diagram showing a second embodiment of the image memory address calculating section 6 of the present invention.
Reference numeral 2 denotes a character array generated by the image memory address calculator 6 shown in FIG.

As shown in FIG. 12, the character array generated by the image memory address calculation unit 62 according to the present embodiment is arranged from the upper right (X is positive and Y is negative) to the lower left (X is negative and Y (Characters are in the positive direction). Such an arrangement is effective when deforming a figure.

The image memory address calculator 6 according to the present embodiment calculates the character count value in synchronization with the character count control signal which is a part of the control information output from the graphic controller 1 as shown in FIG. It comprises a character counting section 21 for incrementing, and a subtraction circuit 22 for subtracting the Y origin coordinate value from the scanning line value.

The image memory address calculator 6 according to the present embodiment divides the output data of the subtraction circuit 22 by the number of pixels in the vertical direction constituting the character, and calculates the quotient of the character address in the Y direction from the result of the division. An address separating unit 23 for calculating the YCH to be represented and the remainder of the figure data ROM lower address, and a character address YCH in the Y direction are input and controlled by character arrangement information, and output data is output to the multiplication circuit 25B 1 (h). A fixed circuit unit 117 and a cumulative addition circuit 114 for cumulatively adding the character address YCH in the Y direction are provided.

Further, the image memory address calculator 6 according to the present embodiment receives the output data of the accumulator 114 and (sprite X size Nsx-1), and sets the character array information to 0, that is, the character array in the horizontal direction. If the character arrangement information is 1, that is, if the character arrangement is in an oblique direction, the selection means 115 outputs the output data of the accumulative addition circuit 114; An adder circuit 116 for adding 1 to the output data from the means 115 and a multiplying circuit 25B for multiplying the output data from the adder circuit 116 and the output data from the 1 (h) fixed circuit section 117 are provided.

The image memory address calculating section 6 according to the present embodiment comprises a character count value and a cumulative addition circuit 1.
14, an addition circuit 111 for adding the output data from the register 112 to the output data from the register 112, and outputting the addition result to the register 112; a register 112 for inputting the addition result from the addition circuit 111 and the sprite number;
The character count value is output when the character array information is 0, that is, in the horizontal direction, and the output of the register 112 is output when the character array information is 0, that is, in the oblique direction. Selection means 113 for outputting data.

Here, if the character arrangement information is 0, the 1 (h) fixed circuit section 117 outputs the character address YCH in the Y direction as it is, and if the character arrangement information is 1,
, The character address YCH is fixed at 1 (h). The character count value is sequentially cumulatively added by the addition circuit 111 and the register 112.

By performing the above operation, if the character arrangement information is 0, the character
The graphic data ROM is arranged in an array as shown in FIG.
When an address is generated and the character array information is 1, the graphic data ROM address is generated so that the characters are arranged as shown in FIG.

Next, the image memory address calculator 6 of the present invention
A second embodiment of the graphic processing method using the second embodiment will be described.

FIG. 13 is a flowchart showing a processing method of the image memory address calculating section 62 of the present invention shown in FIG. 11, and corresponds to step ST in the processing flowchart of FIG.
9 and 10 correspond to steps ST1 in FIG.
4 and 15 are different. Step ST
At 14, the character address YCH input to the cumulative addition circuit 114 is sequentially cumulatively added. Further, the cumulative addition value output from the cumulative addition circuit 114 is added by 1 through the selection means 115 in the addition circuit.

Subsequently, in step ST15, the character count value is cumulatively added by the addition circuit 111 and the register 112.

According to such a processing flow, when the character arrangement information is 0, the graphic data ROM address is generated so that the characters are arranged as shown in FIG. 6A, while the character arrangement information is 1 In the case of, the graphic data ROM address is generated such that the characters are arranged as shown in FIG.

Next, the image memory address calculation unit 6 of the present invention
The third embodiment will be described with reference to FIGS. Note that components common to those in FIG. 11 are denoted by common reference characters / numbers.

FIG. 14 is a block diagram showing a third embodiment of the image memory address calculating section 63 of the present invention. FIG. 15 shows a character array generated by the image memory address calculating section 63.

As shown in FIG. 15, the character array generated by the image memory address calculation unit 63 according to the present embodiment is arranged from the lower left (X is negative and Y is positive) to the upper right (X is positive and Y is Y). Characters are sequentially arranged in the direction of () is a negative direction), which is opposite to the direction of the character arrangement shown in FIG. Such an array is
Similar to the arrangement in FIG. 12, this is effective when deforming a figure.

The image memory address operation unit 63 of the present invention shown in FIG. 14 is different from the adder circuit 111 constituting the image memory address operation unit 62 shown in FIG.
Provided with an addition circuit 141 for adding 1 to
The difference from the image memory address calculation unit 62 shown in FIG. 11 is that a NAND gate 142 is newly provided.

Here, when the character arrangement information is 1, the NAND gate 142 operates so as to mask the cumulative addition value output from the cumulative addition circuit 114 so as not to add 1 further.

By performing the above operation, if the character arrangement information is 0, the character
The graphic data ROM is arranged in an array as shown in FIG.
When an address is generated and the character array information is 1, the graphic data ROM address is generated so that the characters are arranged as shown in FIG.

Next, the image memory address calculator 6 of the present invention
A third embodiment of the graphic processing method using the twenty-third embodiment will be described.

FIG. 16 is a flow chart showing the processing method of the image memory address calculating section 63 of the present invention shown in FIG. 14, and corresponds to step ST1 in the processing flow chart of FIG.
4 and 15 correspond to steps ST1 in FIG.
6 and 17 are different. Step ST
At 16, the character address YCH input to the accumulation circuit 114 is sequentially accumulated.

On the other hand, in step ST 17, the character count value is cumulatively added by the adding circuit 141 and the register 112, and the added value obtained by adding 1 is output to the selecting means 113.

According to such a processing flow, when the character arrangement information is 0, the graphic data ROM address is generated so that the characters are arranged as shown in FIG. 6A, while the character arrangement information is 1 In the case of, the graphic data ROM address is generated such that the characters are arranged as shown in FIG.

Next, the image memory address calculator 6 of the present invention
The fourth embodiment will be described with reference to FIG. Components common to those in FIG. 14 are denoted by common reference characters / numbers.

FIG. 17 is a block diagram showing a fourth embodiment of the image memory address operation unit 64 of the present invention.

The image memory address operation unit 64 of the present invention shown in FIG. 17 is different from the image memory address operation unit 63 shown in FIG. 14 is different from the image memory address calculation unit 63 shown in FIG. 14 in that the calculation function unit 171 is provided and a vertical character calculation function unit 172 is provided in place of the accumulation circuit 114.

Here, the horizontal character operation function unit 17
In step 1, for each character count value, a predefined function is executed on the calculation result from the vertical character calculation function unit, and this execution result is output to the selection unit 113. Y
A predetermined function is executed for the character address YCH in the direction, and the execution result is output to the selection unit 115 and the horizontal direction character operation function unit 171.

Thus, the image memory address operation unit 64
Is a graphic corresponding to the horizontal direction as shown in FIG. 6A, the vertical direction as shown in FIG. 8A, the diagonal direction as shown in FIG. 12 or FIG. It is possible to generate a data ROM address.

Next, the image memory address calculator 6 of the present invention
A fourth embodiment of the graphic processing method using the fourth embodiment will be described.

FIG. 18 is a flow chart showing the processing method of the image memory address calculating section 64 of the present invention shown in FIG. 17, and corresponds to step ST1 in the processing flow chart of FIG.
4 and 15 correspond to steps ST1 in FIG.
8 and 19 are different.

In step ST18, the vertical direction character operation function unit 172 performs a simple cumulative addition on the input Y-direction character address YCH, and also executes a more complicated operation set in the vertical direction character operation function unit 172. And outputs the result to the horizontal character calculation function unit 171 and the selection unit 115.

In step ST19, the horizontal character calculation function unit 171 performs a simple cumulative addition to the input character count value, and performs a more complicated calculation set in the horizontal character calculation function unit 171. The processing is performed and output to the selection unit 113.

According to such a processing flow, when the character arrangement information is in the horizontal direction, the character
The graphic data ROM is arranged in an array as shown in FIG.
If an address is generated and the character arrangement information is in the vertical direction, the graphic data ROM address is generated so that the characters are arranged as shown in FIG.

[0157] Further, the character is changed to that shown in FIG.
It is possible to generate a more complicated graphic data ROM address corresponding to an oblique direction as shown in FIG.

In FIG. 4, the screen display area 41 has been described as having one sprite SP1, SP4, and SP3, but a single scene display area may have a plurality of sprites.

The size of the sprites SP1, SP4, SP3 may match the size of the screen display area. In this case, both the X origin coordinate value and the Y origin coordinate value are 0.
Becomes

Further, in FIG.
As shown in FIG. 22, the X origin coordinate value Px, which is the X coordinate value of the reference origin (upper left corner) of the sprite, and the sprite of the sprite are assigned to each address corresponding to each sprite in the screen display area. The Y origin coordinate value Py which is the Y coordinate value of the reference origin, the sprite X size Nsx which is the sprite X size calculated in character units, and the sprite Y size which is the sprite Y direction size calculated in character units Although the description has been made as including Nsy, graphic data ROM address Ad (ROM) used when reading characters from the graphic data ROM 9, character arrangement information Arr that determines the arrangement direction of characters, etc., sprites are arranged in the X direction. X sprite composed of characters that have been set, and Y sprite composed of characters arranged in the Y direction If configured not contain a site,
The parameters defined above are the X sprite and Y
It is defined for each sprite.

[0161]

As described above, the graphic processing apparatus and the graphic processing method according to the present invention add character arrangement information, which is information relating to character arrangement, to the conventional parameter RAM section, and store the character arrangement information in the parameter RAM section. By setting a more optimal character arrangement, the memory use efficiency of the parameter RAM unit can be improved. Thus, if the memory capacity of the parameter RAM is constant, more graphics can be registered in the parameter RAM.

When displaying a plurality of character arrays, the number of graphics controlled by the CPU in the parameter RAM is reduced, so that the processing speed can be improved.

Further, even if the character arrangement in the horizontal (X) direction and the character arrangement in the vertical (Y) direction in the parameter RAM section are mixed, the character data is transferred from the graphic data ROM section by the common image memory address operation section. An address for reading data can be generated, and the number of circuit elements can be further reduced.

In addition to the method of mixing the character arrangement of the parameter RAM section in the horizontal direction, the vertical direction, and the horizontal and vertical directions, the oblique direction or the arrangement direction is defined by a function, and the memory capacity of the parameter RAM section is greatly increased. Various animations can be displayed without increasing the number of animations.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a graphic processing apparatus according to the present invention.

FIGS. 2A and 2B are a block diagram and a timing chart showing a first embodiment of an image memory address calculator 6 constituting the graphic processing device of the present invention.

FIG. 3 shows a parameter R constituting the graphic processing apparatus of the present invention.
FIG. 3 is a diagram illustrating a memory configuration of an AM unit 2.

FIG. 4 is a diagram for explaining an animation graphic generated by using the graphic processing device of the present invention and an arrangement of characters constituting the animation graphic.

FIG. 5 shows a conventional parameter RAMA2 in FIG.
(B), the memory configuration corresponding to the animation figure of (b) ′ and FIG. 4 in the parameter RAM 2 of the present invention.
It is a figure showing the memory structure corresponding to the animation figure of (b) and (b) '.

FIG. 6 is a diagram for explaining scanning lines when the character arrangement is a horizontal arrangement, and a sprite SP6.
Data R of characters CH1 to CH16 constituting
A diagram showing a character array of the OM9, a character number, a graphic data ROM upper address, and graphic data R.
FIG. 9 is a diagram illustrating a relationship between OM lower addresses.

FIG. 7 is a diagram showing an image memory address calculating unit 61 constituting the graphic processing device of the present invention when the character array is in the horizontal direction.
It is a figure for explaining the concrete operation of.

FIG. 8 is a diagram for explaining scanning lines when the character arrangement is a vertical arrangement, and a sprite SP8.
Data R of characters CH1 to CH16 constituting
A diagram showing a character array of the OM9, a character number, a graphic data ROM upper address, and graphic data R.
FIG. 9 is a diagram illustrating a relationship between OM lower addresses.

FIG. 9 is a diagram showing an image memory address calculating unit 61 constituting the graphic processing device of the present invention when the character array is in the vertical direction.
It is a figure for explaining the concrete operation of.

FIG. 10 is a flowchart showing a processing method of the image memory address calculation unit 61 of the present invention shown in FIG.

FIG. 11 is a block diagram showing a second embodiment of the image memory address calculation unit 6 constituting the graphic processing device of the present invention.

12 is an image memory address calculation unit 62 shown in FIG.
FIG. 4 is a diagram of a sprite in which characters are arranged in an oblique direction according to a graphic data ROM address generated by (1).

FIG. 13 is a flowchart showing a processing method of the image memory address calculation unit 62 of the present invention shown in FIG.

FIG. 14 is a block diagram showing a third embodiment of the image memory address calculation unit 6 constituting the graphic processing device of the present invention.

15 is an image memory address calculation unit 63 shown in FIG.
FIG. 4 is a diagram of a sprite in which characters are arranged in an oblique direction according to a graphic data ROM address generated by (1).

FIG. 16 is a flowchart showing a processing method of the image memory address calculation unit 63 of the present invention shown in FIG.

FIG. 17 is a block diagram showing a fourth embodiment of the image memory address calculating section 6 constituting the graphic processing device of the present invention.

18 is a flowchart showing a processing method of the image memory address calculation unit 64 of the present invention shown in FIG.

FIG. 19 is a block diagram showing a conventional graphic processing device.

FIG. 20 is a block diagram and a timing chart showing an image memory address calculation unit 196 included in a conventional graphic processing apparatus.

FIG. 21 shows a parameter R constituting a conventional graphic processing apparatus.
FIG. 3 is a diagram illustrating a memory configuration of an AM unit 192.

FIG. 22 is an explanatory diagram for describing a screen display area and sprites included therein.

FIG. 23 shows sprites in which characters are arranged in the X (horizontal) direction and the Y (vertical) direction, and a graphic data ROM.
FIG. 3 is a diagram for explaining a character arrangement in FIG.

FIG. 24 is a diagram for explaining sprites SP1 to SP4.

FIG. 25 is a diagram showing a configuration of animation figures 251 to 253 and a character configuration of sprites SP1 to SP3 constituting the animation figures 251 to 253, respectively.

[Explanation of symbols]

1,191 graphic control unit 2,192 parameter RAM unit 3,193 hit determination unit 4,194 counter control unit 5,195 display graphic buffer memory 6,61,62,63,64,196 image memory address calculation unit 7,197 Image data modification operation unit 8,198 CPU 9,199 Graphic data ROM 10,1910 Display device 11 Display sprite number storage unit 12 Sprite number calculation unit 21,201 Character count unit 22,202 Subtraction circuit 23,203 Address separation unit 24, 26, 29, 111, 116, 141, 204,
206 Addition circuit 25A, 25B, 205 Multiplication circuit 27, 28 AND gate 100, 1900 Graphic processing unit 112 Register 113, 115 Selection means 114 Cumulative addition circuit 117 1 1 (h) fixed circuit unit 142 NAND gate 171 Horizontal character operation function unit 172 Vertical character operation function part

Continued on the front page F term (reference) 2C001 BA06 BC08 CB01 CB02 CB04 CC02 CC03 5B050 BA07 BA08 BA11 EA24 FA02 5C082 AA06 BA43 BB32 CB01 DA22 DA35 MM02

Claims (10)

[Claims] 1. A graphic processing apparatus for displaying, on a screen display area, a sprite in which characters composed of a plurality of pixel data are arranged in a matrix in an X direction and a Y direction, the character being information relating to the arrangement of the characters. A parameter RAM unit that stores arrangement information and stores sprite graphic information that is graphic information of the sprite, a graphic data ROM that stores character data that is image data of the character, and refers to the graphic information and the character arrangement information. The graphic data RO, which is address information for the graphic data ROM for reading out the character data,
A graphic processing apparatus, comprising: an image memory address operation unit that generates an M address; and an image data modification operation unit that receives the character data and generates an image signal to be displayed on a display device. 2. The sprite includes an X sprite composed of the characters arranged in the X direction and a Y sprite composed of the characters arranged in the Y direction, and the character arrangement information corresponds to the X sprite. X character array information and Y corresponding to the Y sprite
Character array information, and wherein the image memory address calculation unit generates the graphic data ROM address corresponding to the X character array information and the graphic data ROM address corresponding to the Y character array information, respectively. 2. The graphic processing device according to claim 1, wherein: 3. The sprite includes the characters arranged diagonally, the character arrangement information includes diagonal character arrangement information corresponding to the characters arranged diagonally, and the image memory address calculation unit 2. The graphic processing apparatus according to claim 1, wherein said graphic data ROM address corresponding to said oblique character array information is generated. 4. A hit determination for inputting the sprite graphic information, determining whether to display the sprite in the screen display area, and outputting hit information to be activated when determining to display the sprite in the screen display area. And a display graphic buffer memory for storing a sprite number that is the number of the sprite corresponding to the activated hit information. The image memory address calculation unit is configured to store the sprite number in the display graphic buffer memory. Referring to the sprite number,
2. The graphic processing apparatus according to claim 1, wherein said graphic data ROM address is generated. 5. The X-sprite graphic information includes an X-origin coordinate value and a Y-origin coordinate value, which are coordinate values in the X and Y directions of respective reference origins of the X sprite and the Y sprite. 3. The graphic processing apparatus according to claim 2, further comprising a sprite X size that is a size of the Y sprite in the X direction, and a sprite Y size that is a size of the X sprite and the Y sprite in the Y direction. 6. A subtraction circuit for subtracting the Y origin coordinate value from a scanning line value indicating a number of a scanning line scanned in the X direction of the screen display area in the Y direction, the image memory address computing unit; The subtraction result output from the circuit is divided by the number of arrangements of the pixel data constituting the character in the Y direction, and a Y direction character address indicating the character order of the character in the Y direction, which is a quotient, and the graphic data RO
An address separating unit for outputting a figure data ROM address lower address which is a lower address of the M address; (the sprite X size -1) and (the sprite Y
When the size-1) and the character arrangement information are input, and when the character arrangement information is input when the character arrangement is in the X direction (the sprite X size-1)
Is output, and when the character arrangement information is input when the character arrangement is in the Y direction (the sprite Y
Selecting means for outputting (size-1); (sprite X size-1) and (sprite Y size-1) output from the selecting means are each 1
First and second addition circuits, a first multiplication circuit for multiplying the addition result from the first addition circuit by the Y-direction character address, and an X-direction of the character constituting the sprite. A second multiplication circuit for multiplying a character count value representing the order of the above by the addition result from the second addition circuit; and output data from the first and second multiplication circuits,
A third adder circuit for adding a sprite number which is a sprite number in the screen display area and outputting a result of the addition as a graphic data ROM address upper address which is an upper address of the graphic data ROM address. The graphic processing device according to claim 5, wherein: 7. A subtraction circuit for subtracting the Y origin coordinate value from a scanning line value indicating a number of a scanning line scanning in the X direction of the screen display area in the Y direction, the image memory address computing unit; The subtraction result output from the circuit is divided by the number of arrangements of the pixel data constituting the character in the Y direction, and a Y direction character address indicating the character order of the character in the Y direction, which is a quotient, and the graphic data RO
An address separating unit for outputting a figure data ROM address lower address which is a lower address of the M address, a first accumulator circuit for accumulatively adding the Y-direction character addresses in order, (the sprite X size -1) When the first cumulative addition result output from the first cumulative addition circuit and the character arrangement information are input, and when the character arrangement information is input when the character arrangement is in the X direction, (the sprite X size- 1) outputting the first cumulative addition result when the character arrangement information is input when the character arrangement is in an oblique direction; and the first selection means for outputting the first cumulative addition result. (The above Sprite X
A first addition circuit for adding 1 to the size-1) and the first cumulative addition result; and outputting the Y-direction character address when the character arrangement information when the character arrangement is in the X direction is input. When the character arrangement information is input when the character arrangement is in an oblique direction, 1 is output.
(H) a fixed circuit unit; a multiplication circuit that multiplies the addition result of the first adder circuit with the output data from the 1 (h) fixed circuit unit; and an order of the characters forming the sprite in the X direction. A second cumulative addition circuit that inputs a character count value representing the following and the first cumulative addition result, performs cumulative addition on the character count value, and outputs a second cumulative addition result; When the second cumulative addition result and the character arrangement information are input, the character count value is output when the character arrangement information is input when the character arrangement is in the X direction, and when the character arrangement is in an oblique direction. Output the second cumulative addition result when the character arrangement information is input.
Selecting means for adding the output data of the multiplying circuit, the output data from the second selecting means, and the sprite number which is the number of the sprite in the screen display area. Graphic data R as upper address
6. The graphic processing apparatus according to claim 5, further comprising: a third adder circuit for outputting as an OM address upper address. 8. A subtraction circuit for subtracting the Y origin coordinate value from a scan line value indicating a number in the Y direction of a scan line scanned in the X direction of the screen display area, the image memory address operation unit; The subtraction result output from the circuit is divided by the number of arrangements of the pixel data constituting the character in the Y direction, and a Y direction character address indicating the character order of the character in the Y direction, which is a quotient, and the graphic data RO
An address separating unit for outputting a figure data ROM address lower address which is a lower address of the M address, a first accumulator circuit for accumulatively adding the Y-direction character addresses in order, (the sprite X size -1) When the first cumulative addition result output from the first cumulative addition circuit and the character arrangement information are input, and when the character arrangement information is input when the character arrangement is in the X direction, (the sprite X size- 1) outputting the first cumulative addition result when the character arrangement information is input when the character arrangement is in an oblique direction; and the first selection means for outputting the first cumulative addition result. (The above Sprite X
When the character arrangement information is input when the character arrangement is in the X direction, 1 is added to the size-1) and the first cumulative addition result, and the character arrangement information when the character arrangement is in the oblique direction is added. A first addition circuit that adds 0 when the character array is input, and outputs the Y-direction character address when the character array information is input when the character array is in the X direction, and the character array is in an oblique direction. When the character arrangement information at the time of is input, 1 is output.
(H) a fixed circuit unit; a multiplication circuit that multiplies the addition result of the first adder circuit with the output data from the 1 (h) fixed circuit unit; and an order of the characters forming the sprite in the X direction. A second cumulative addition circuit that inputs a character count value representing the following and the first cumulative addition result, performs a cumulative addition on the character count value, and outputs a second cumulative addition result of adding 1. Inputting a character count value, the second cumulative addition result, and the character array information, and outputting the character count value when the character array information is input when the character array is in the X direction; Output the second cumulative addition result when the character arrangement information is input when is in the oblique direction.
Selecting means for adding the output data of the multiplying circuit, the output data from the second selecting means, and the sprite number which is the number of the sprite in the screen display area. Graphic data R as upper address
6. The graphic processing apparatus according to claim 5, further comprising: a third adder circuit for outputting as an OM address upper address. 9. A subtraction circuit for subtracting the Y origin coordinate value from a scan line value indicating a number in the Y direction of a scan line scanned in the X direction of the screen display area, the image memory address operation unit; The result of the subtraction output from the circuit is divided by the number of arrangements of the pixel data constituting the character in the Y direction, and a Y direction character address indicating the character order of the character in the Y direction, which is a quotient, and the graphic data RO
An address separating section for outputting a figure data ROM address lower address which is a lower address of the M address; inputting the Y-direction character address to perform a predetermined operation on the Y-direction character address to obtain a first operation result; A first operation function section to be output, (the sprite X size −1), the first operation result, and the character array information are input, and the character array information when the character array is in the X direction is input. First selecting means for outputting (the sprite X size -1) when the input is performed, and outputting the first calculation result when the character array information is input when the character array is not in the X direction; Output from the first selecting means (the sprite X
When the character array information when the character array is in the X direction is input, 1 is added to the size-1) and the first calculation result, and the character array information when the character array is not in the X direction is added. A first adding circuit that adds 0 when input, and outputs the Y direction character address when the character array information is input when the character array is in the X direction, and the character array is not in the X direction. When the character arrangement information is input, 1 is output.
(H) a fixed circuit unit; a multiplication circuit that multiplies the addition result of the first adder circuit with the output data from the 1 (h) fixed circuit unit; and an order of the characters forming the sprite in the X direction. A second calculation function for inputting a character count value representing the following and the first calculation result, performing a predetermined calculation on the first calculation result for each of the character count values, and outputting a second calculation result Part, input the character count value, the second calculation result and the character array information, and output the character count value when the character array information is input when the character array is in the X direction; A second selecting means for outputting the second operation result when the character arrangement information is input when the character arrangement is not in the X direction; and an output data of the multiplication circuit. Data and the output data from the second selecting means and a sprite number which is a sprite number in the screen display area, and the addition result is represented by graphic data R which is an upper address of the graphic data ROM address.
The graphic processing apparatus according to claim 5, further comprising a second adder circuit that outputs the OM address as an upper address. 10. A graphic processing method for displaying a sprite in which a character composed of a plurality of pixel data is arranged in a matrix in an X direction and a Y direction in a screen display area, wherein the scanning of the character constituting the sprite is performed. A first step of sequentially incrementing a character count value representing an order in the X direction, which is a line direction; and a Y origin coordinate based on a scanning line value indicating a number of a scanning line scanned in the X direction of the screen display area. A second step of subtracting a value to calculate a scanning line value within the character which is a scanning line value within the character; and calculating the scanning line value within the character by the number of arrays of pixel data constituting the character in the Y direction. And a character address in the Y direction representing the character order of the character in the Y direction, which is a quotient, Graphic data R, which is the lower address of the address information of the graphic data ROM for storing the character data which is the image data of
A third step of outputting an OM address lower address, and when the character array is in the X direction, multiplying a sprite X size, which is a size of the sprite in the X direction, by the Y direction character address; A fourth step of holding a count value; and when the character arrangement is in the Y direction, holding the Y direction character address, and determining the sprite Y size, which is the size of the sprite in the Y direction, and the character count value. A fifth step of multiplying, and a figure data ROM address upper address which is an upper address of the figure data ROM address is calculated with reference to each multiplication result calculated in the fourth step and the fifth step. And a sixth step.