JP2002072228A - Method of manufacturing tft panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make reducible plasma damage to a TFT(thin film transistor) under a pixel electrode even if the pixel electrode is formed by dry etching, when a TFT panel having a structure where the pixel electrode consisting of ITO is positioned on the tip side of the TFT is manufactured. SOLUTION: A large sized substrate 11 having a size corresponding to the size of the plural TFT panels and consisting of glass or the like is provided with nine TFT panel forming regions 12 in total consisting of three rows and three columns. In this case, a TFT panel non-forming region has width D1 of 2 cm (or more) and width D2 of 1 cm (or more). And, no resist pattern is formed on the upper surface of the TFT panel non-forming region of an ITO layer 36 formed on the entire surface of the large sized substrate 11. Thereby, the ITO etching total area becomes relatively large and amounts to 50% or more of the surface area of the substrate. Thus, the plasma damage to the TFT under the pixel electrode can be reduced even if the dry etching is performed using an RIE device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a TFT (thin film transistor) panel.

[0002]

2. Description of the Related Art For example, an active matrix type liquid crystal display device has a structure in which a pixel electrode made of ITO (indium-tin oxide) is positioned on the top side of a TFT serving as a switching element, that is, TOP-ITO. What is called a structure is being developed. When manufacturing a TFT panel having a pixel electrode, a TFT, and the like in a liquid crystal display device having such a structure, an alignment film may be formed, but the formation of the pixel electrode is the last.

On the other hand, scanning signal lines, data signal lines, and the like are formed of Al (aluminum) -based metal on a TFT panel substrate, and an ITO layer is formed with a connection pad formed at one end thereof being exposed. Is patterned by wet etching to form a pixel electrode,
The exposed connection pads react with the etching solution of ITO and are easily dissolved. Also, the Al-based metal layer and the I
When the TO layer and the etchant of ITO coexist in contact, A
The l-based metal layer is oxidized and the ITO layer is reduced (Al-ITO battery reaction), and both are severely corroded.

[0004]

As described above, TOP-
In the case of an ITO-structured TFT panel, the exposed connection pads made of Al-based metal react with the ITO etchant to easily dissolve, or the Al-ITO battery reaction causes Al to be dissolved.
Since both the base metal layer and the ITO layer are severely corroded, it is important to take some measures. Further, in the case of wet etching, there is a limit to high definition. Thus, it is conceivable to form a pixel electrode by patterning the ITO layer by dry etching. However, in the case of dry etching, the characteristics of the TFT below the pixel electrode fluctuate due to plasma damage. An object of the present invention is to reduce plasma damage to a TFT below a pixel electrode even when the pixel electrode is formed by dry etching.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor device including a TFT formed on a large-sized substrate having a size corresponding to a plurality of TFT panels and an insulating film formed on the large-sized substrate. When the formed ITO layer is dry-etched to form a pixel electrode, the ITO layer in a region where a TFT panel is not formed is dry-etched. According to a second aspect of the present invention, in the first aspect, the total area of the ITO etching is 50% of the substrate area.
% Or more. According to a third aspect of the present invention, in the second aspect of the present invention, the width of the TFT panel non-forming region in the peripheral portion of the large substrate is 2 cm.
This is what has been described above. According to a fourth aspect of the present invention, in the first aspect of the present invention, a dielectric is disposed around a lower electrode disposed in the reaction chamber for dry etching. According to a fifth aspect of the present invention, in the first aspect of the present invention, the surface of the lower electrode disposed in the reaction chamber for dry etching is covered with a dielectric. According to a sixth aspect of the present invention, in the invention of the fourth or fifth aspect, the width of the TFT panel non-formed region in the peripheral portion of the large-sized substrate is 1 cm or less. Claim 7
The dry etching is performed by reactive ion etching using a mixed gas of a hydrogen halide gas and an inert gas in the invention according to any one of claims 1 to 8. It is. According to the first aspect of the invention, when the ITO layer is dry-etched to form a pixel electrode, the ITO layer in the TFT panel non-formation region is dry-etched.
The total area of the ITO etching becomes relatively large, so that even if the pixel electrode is formed by dry etching,
Plasma damage to the TFT below the pixel electrode can be reduced.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a view for explaining a method of manufacturing a TFT panel according to a first embodiment of the present invention, and is a schematic configuration diagram of an ITO layer dry etching apparatus, that is, an RIE (reactive ion etching) apparatus. It is shown. This RIE apparatus is of a cathode coupling type and includes a reaction vessel 1. A lower electrode (cathode) 2 is provided at a lower portion in the reaction vessel 1, and an upper electrode (anode) 3 is provided at an upper portion. The lower electrode 2 is connected to an RF power supply 5 via a blocking capacitor 4.
The upper electrode 3 is grounded. A gas inlet 6 is provided at a predetermined location on the upper part of the reaction vessel 1, and a gas outlet 7 is provided at a predetermined location on the lower part. The gas inlet 6 is
It is connected to gas supply means (not shown) for supplying a mixed gas of hydrogen iodide gas (hydrogen halide gas) and helium gas (inert gas).

On the lower electrode 2, a large substrate 11 made of glass or the like having a size corresponding to a plurality of TFT panels is mounted. The large-sized substrate 11 includes a total of nine TFT panel formation regions 12 in three rows and three columns, as shown by a dashed line in FIG. 2, for example. in this case,
The width D1 of the TFT panel non-forming region in the peripheral portion of the large substrate 11 is 2 cm (or more), and the width D2 of the TFT panel non-forming region between the TFT panel forming regions 12 is 1c.
m (or more). A region indicated by a two-dot chain line in the TFT panel formation region 12 is a display region 13.
It is. Although not shown, the large substrate 11
After being bonded to a common electrode substrate having the same size as that of the display region 13 by a frame-shaped sealing material formed corresponding to the display region 13, the substrate is cut along the outer peripheral edge of each TFT panel formation region 12,
Liquid crystal is injected from the sealing holes formed in each sealing material to obtain individual TFT panels.

Next, a part of an example of a specific structure on the large substrate 11 will be described with reference to FIG. A gate electrode 21 made of Al-based metal or chromium, a scanning signal line (not shown), and the like are formed at predetermined locations on the upper surface of the display area 13 of the large substrate 11. T of large substrate 11
A scanning signal lower connection pad 22 made of Al-based metal or chromium is formed at a predetermined location on the upper surface of the non-display area in the FT panel formation area 12. A gate insulating film 23 is formed on the entire upper surface of the large substrate 11 including the gate electrode 21 and the like.

The gate insulating film 2 on the gate electrode 21
A semiconductor thin film 24 made of intrinsic amorphous silicon is formed at a predetermined position on the upper surface of the substrate 3. Semiconductor thin film 2
A channel protective film 25 is formed at the center of the upper surface of the substrate 4. Ohmic contacts 26 and 27 made of n-type amorphous silicon are formed on both sides of the upper surface of the channel protective film 25 and on each upper surface of the semiconductor thin film 24 on both sides thereof. A is provided on the upper surfaces of the ohmic contacts 26 and 27.
A source electrode 28 and a drain electrode 29 made of l-based metal or chromium are formed. And the gate electrode 2
1. A TFT 30 is constituted by 1, a gate insulating film 23, a semiconductor thin film 24, a channel protective film 25, ohmic contacts 26 and 27, a source electrode 28 and a drain electrode 29.

A data signal lower connection pad 31 is formed at a predetermined location on the upper surface of the non-display area in the TFT panel formation area 12 of the gate insulating film 23. In this case, the data signal lower connection pad 31 has a three-layer structure of an intrinsic amorphous silicon layer, an n-type amorphous silicon layer, and a metal layer made of Al-based metal or chromium. Also,
Although not shown, a data signal line formed at a predetermined position on the upper surface of the gate insulating film 23 has a similar three-layer structure.

An overcoat film 32 is formed on the entire upper surface of the gate insulating film 23 including the TFT 30 and the like. Contact holes 33 and 34 are formed in portions of the overcoat film 32 corresponding to the source electrodes 28 and portions corresponding to the lower connection pads 31 for data signals. A contact hole 35 is formed in a portion of the overcoat film 32 and the gate insulating film 23 corresponding to the scanning signal connection pad 22. Contact hole 33,
An ITO layer 36 is formed on the entire upper surface of the overcoat film 32 including the layers 34 and 35. Resist patterns 37a, 37b, 37 are formed at predetermined locations on the upper surface of the ITO layer 36.
c is formed. In this case, the resist pattern 37
a is for forming a pixel electrode, a resist pattern 37b is for forming an upper connection pad for a data signal, and a resist pattern 37c is for forming an upper connection pad for a scanning signal. .

Next, a case where the ITO layer 36 of the large substrate 11 is dry-etched using the RIE apparatus shown in FIG. 1 to form pixel electrodes and the like will be described. First, the gas in the reaction vessel 1 is discharged from the gas discharge port 7 to evacuate the inside of the reaction vessel 1, and then a mixed gas of hydrogen iodide gas and helium gas supplied from gas supply means is supplied to the gas inlet port. 6 and introduced into the reaction vessel 1. Then, resist patterns 37a, 37b, 37c are formed by reactive ion etching using a mixed gas of hydrogen iodide gas and helium gas.
Is used as a mask to dry-etch ITO layer 36.

As a result, as shown in FIG. 4, a pixel electrode 38 made of an ITO layer is formed below the resist pattern 37a by being connected to the source electrode 28 through the contact hole 33, and is formed below the resist pattern 37b from the ITO layer. The data signal upper connection pad 39 is connected to the data signal lower connection pad 31 via the contact hole 34, and the scanning signal upper connection pad 40 made of an ITO layer is formed under the resist pattern 37c. It is formed so as to be connected to the lower connection pad 22 for the scanning signal via the same. After that, the resist patterns 37a, 3
When 7b and 37c are peeled off, they become as shown in FIG.

Here, in the case of this embodiment, no resist pattern was formed on the upper surface of the ITO layer 36 where the TFT panel was not formed in FIG. 2 (hereinafter, referred to as a product of this embodiment). On the other hand, for comparison, in FIG.
A product in which a resist pattern was formed on the upper surface of the O layer 36 where the TFT panel was not formed was prepared (hereinafter, referred to as a comparative product). The flow rate of the hydrogen iodide gas was set to 200 ccm, the flow rate of the helium gas was set to 25 ccm, and the reaction vessel 1
The pressure inside is set to 5 Pa, and 13.56 MH from RF power source 6
A 2.5 kW RF power was applied.

In the case of the product of this embodiment, since the resist pattern is not formed on the upper surface of the TFT panel non-formed region of the ITO layer 36 in FIG. 2, the ITO layer 36 in the TFT panel non-formed region is dry. Etched. On the other hand, in the case of the comparative product, in FIG.
Since the resist pattern is formed on the upper surface of the non-TFT panel area of the TO layer 36, the ITO layer 36 in the non-TFT panel area is not dry-etched.

The TF of the present embodiment and the comparative product
When the VG (gate voltage) -ID (drain current) characteristics of T30 were examined, the result shown in FIG. 6 was obtained in the case of the product of the present embodiment, and the result shown in FIG. 7 was obtained in the case of the comparative product. In the case of the comparative product shown in FIG. 7, the off region (sub-threshold region) is deteriorated, but in the case of the product of this embodiment shown in FIG. 6, such deterioration is not seen.

Considering this, the hydrogen iodide gas introduced into the reaction vessel 1 is dissociated in the plasma, and the charged particles generated by the plasma potential and the negative self-bias of the large substrate 11 in the plasma seeds. Irradiated on the ITO layer 36 after being accelerated. The irradiated charged particles react with the surface particles of the ITO layer 36 due to the kinetic energy at this time, and the by-product InIx generated thereby is discharged from the gas discharge port 7, whereby the dry etching proceeds.

However, in the case of the comparative product, in FIG.
Since the resist pattern is formed on the upper surface of the ITO layer 36 where the TFT panel is not formed, the total area of the ITO etching is relatively small, about 30% of the substrate area. For this reason, the charged particles concentrate on and attack the ITO layer 36 having a relatively small area, and the density of the charged particles is deviated during the plasma seeding, and the etched portion of the ITO layer 36 (particularly, the peripheral surface of the pixel electrode 38). The charged particles are excessively concentrated on the portion where the charge is applied, and the TFT 30 is charged with electric charge via the ITO layer 36. As a result, the TFT 3 under the pixel electrode 38
0 undergoes plasma damage, and the off region deteriorates as shown in FIG.

On the other hand, in the case of the product of this embodiment, FIG.
Since the resist pattern is not formed on the upper surface of the TFT panel non-formed area of the ITO layer 36,
The total etching area is relatively large, at least 50% of the substrate area. For this reason, the charged particles have a relatively large area of ITO.
The dispersed particles attack the layer 36, the charged particle density in the plasma seeds is averaged, and the charged particles are excessively concentrated on the etched portion of the ITO layer 36 (particularly, on the peripheral surface of the pixel electrode 38). And T via the ITO layer 36
It is difficult for the FT 30 to be charged. As a result, the TFT 30 below the pixel electrode 38 is less susceptible to plasma damage, and the off region is improved as shown in FIG.

Conventionally, when a pixel electrode is formed by patterning an ITO layer by wet etching, the widths D1 and D2 shown in FIG. 2 are set to about 1 cm. This is to reduce the area of the TFT non-forming region in the large substrate as much as possible and to improve the yield. In the case of this conventional large substrate, for example, in FIG. 2, even if a resist pattern is not formed on the upper surface of the TFT panel non-formed region of the ITO layer 36, the total area of the ITO etching is less than 50% of the substrate area. . For this reason,
In the case of dry etching, the characteristics of the TFT below the pixel electrode fluctuate due to plasma damage. In view of the above, the present inventor has determined the critical condition of the total area of the ITO etching with respect to the substrate area. When the total area of the ITO etching is 50% or more of the substrate area, the characteristics as shown in FIG. It was confirmed that a TFT having good was obtained, and when it was less than that, the TFT exhibited deteriorated characteristics as shown in FIG.

On the other hand, in the case of the above embodiment, since the width D1 shown in FIG. 2 is 2 cm (or more),
Although the area of the TFT non-forming region occupying the large substrate 11 increases, plasma damage to the TFT 30 below the pixel electrode 38 can be reduced, but this is not preferable in terms of yield. Then, next, a case where the area of the TFT non-formation region in the large substrate can be reduced will be described.

FIG. 8 shows T in the second embodiment of the present invention.
It is shown to explain the method of manufacturing the FT panel,
FIG. 9 shows a schematic configuration diagram of the IE device, and FIG. 9 shows a partial plan view thereof. In this RIE apparatus, the lower electrode 1
Around one is disposed four dielectrics 41 made of mica, alumina, ceramic or the like. In this case, the dielectric 41
Have the same potential as the lower electrode 11.

Therefore, in this RIE apparatus, a part of the charged particles in the plasma seed is guided to the dielectric 41 around the large substrate 11, and the etched portion of the ITO layer on the large substrate 11 (particularly, around the pixel electrode). Surface part)
Thus, the charged particles are not excessively concentrated, and plasma damage to the TFT below the pixel electrode can be reduced. As a result, for example, the widths D1 and D2 shown in FIG.
cm (or less). In this case, the charged particles in the plasma seed are dispersed over a wider area than the ITO layer forming region on the large-sized substrate 11, so that the etch rate uniformity can be improved.

Meanwhile, in the case of a general RIE apparatus, a deposition preventing plate made of quartz or the like is arranged around the lower electrode in order to prevent by-products generated during etching from adhering to the inner wall of the reaction vessel. Have been. However, in the case of an anti-adhesion plate made of quartz or the like, the charged particles in the plasma seeds are excessively concentrated on the etched portion of the ITO layer on the large-sized substrate 11 (particularly, on the peripheral surface of the pixel electrode). It cannot be avoided and plasma damage to the TFT below the pixel electrode cannot be reduced.

FIG. 10 is a view for explaining a method of manufacturing a TFT panel according to a third embodiment of the present invention. FIG. 10 is a schematic structural view of an RIE apparatus, and FIG. It is shown. In this RIE device,
The surface of the slightly larger lower electrode 11 is coated with a dielectric 42 made of mica, alumina, ceramic, or the like.

Therefore, also in this RIE apparatus, a part of the charged particles in the plasma seed is guided to the dielectric 42 around the large substrate 11, and the etched portion of the ITO layer on the large substrate 11 (particularly, around the pixel electrode). Surface part)
Thus, the charged particles are not excessively concentrated, and plasma damage to the TFT below the pixel electrode can be reduced. As a result, for example, the widths D1 and D2 shown in FIG.
cm (or less). Also in this case, the charged particles in the plasma seed are
Since the dispersion is performed over a wider range than the upper ITO layer formation region, the etch rate uniformity can be improved.

In the above embodiment, the upper connection pad for the scanning signal and the upper connection pad for the data signal are made of ITO.
Although the case of forming with layers has been described, the present invention is not limited to this, and one of the upper connection pads or both of the upper connection pads may not be formed. In particular, when the lower connection pad for a scanning signal is formed of an aluminum-based metal, the contact resistance increases when the ITO layer is stacked, so that the ITO layer may be omitted. in this case,
Although a natural oxide film is formed on the surface of the aluminum-based metal, it has been confirmed that a reliable contact can be obtained when the driver IC is directly face-down bonded on the scanning signal upper connection pad. In addition, since the source / drain electrodes are connected to the pixel electrodes, it is preferable that the source / drain electrodes be formed of a metal other than an aluminum-based metal such as chromium, instead of an aluminum-based metal on which a natural oxide film is easily formed on the surface. In this case, even if an ITO layer is stacked on the drain electrode, the contact resistance does not increase, so that the ITO layer may be formed.
Further, in the above embodiment, the case where the cathode coupling type RIE apparatus is used has been described. However, the present invention is not limited to this, and a microwave high density plasma etching apparatus or an anode coupling type plasma etching apparatus may be used. .

[0028]

As described above, according to the present invention, when the ITO layer is dry-etched to form a pixel electrode, the ITO layer in the TFT panel non-formed area is dry-etched. The total area is relatively large, so that even if the pixel electrode is formed by dry etching, plasma damage to the TFT below the pixel electrode can be reduced.

[Brief description of the drawings]

FIG. 1 is a view schematically illustrating a method of manufacturing a TFT panel according to a first embodiment of the present invention, which is a schematic configuration diagram of an ITO layer dry etching apparatus, that is, an RIE apparatus.

FIG. 2 is a plan view of a large substrate or the like having a size corresponding to a plurality of TFT panels.

FIG. 3 is a partial IT example of a specific structure on a large substrate;
Sectional drawing in the state before O layer etching.

FIG. 4 is a sectional view of a step following FIG. 3;

FIG. 5 is a sectional view of a step following FIG. 4;

FIG. 6 is a VG-ID characteristic diagram in the case of the product of the present embodiment.

FIG. 7 is a VG-ID characteristic diagram in the case of a comparative product.

FIG. 8 is a schematic configuration diagram of an RIE apparatus for explaining a method of manufacturing a TFT panel according to a second embodiment of the present invention.

FIG. 9 is a plan view of a part of the RIE apparatus shown in FIG. 8;

FIG. 10 is a view schematically illustrating a method for manufacturing a TFT panel according to a third embodiment of the present invention, and is a schematic configuration diagram of an RIE apparatus.

11 is a plan view of a part of the RIE apparatus shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reaction container 2 Lower electrode 3 Upper electrode 6 Gas inlet 7 Gas outlet 11 Large substrate 12 TFT panel formation area 13 Display area 36 ITO layer

Continued on the front page F term (reference) 2H092 HA04 JA24 JB22 JB31 JB56 MA15 MA18 NA11 NA27 NA29 5F004 AA06 BA04 BB13 DA00 DA20 DA22 DA23 DB31 EA40 5F110 AA26 BB01 CC07 DD02 EE03 EE04 GG02 GG15 GG16 NN03 HK03 HK16 NN03

Claims (7)

[Claims] 1. A pixel electrode is formed by dry-etching an ITO layer formed on a large-sized substrate including a TFT formed on a large-sized substrate corresponding to a plurality of TFT panels via an insulating film. A step of dry-etching the ITO layer in a region where no TFT panel is formed. 2. The method according to claim 1, wherein the ITO is used.
A method for manufacturing a TFT panel, wherein a total etching area is 50% or more of a substrate area. 3. The method of manufacturing a TFT panel according to claim 2, wherein a width of a TFT panel non-forming region in a peripheral portion of the large-sized substrate is 2 cm or more. 4. The method according to claim 1, wherein a dielectric is disposed around the lower electrode disposed in the reaction chamber for dry etching. 5. The method according to claim 1, wherein a surface of the lower electrode disposed in the reaction vessel for dry etching is coated with a dielectric. 6. The method of manufacturing a TFT panel according to claim 4, wherein a width of a TFT panel non-formation area in a peripheral portion of the large-sized substrate is 1 cm or less. 7. The invention according to claim 1, wherein the dry etching is performed by reactive ion etching using a mixed gas of a hydrogen halide gas and an inert gas. Manufacturing method of TFT panel.