JP2002057228A - Semiconductor memory integrated circuit and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory integrated circuit for preventing characteristics changes due to capacitance coupling between floating gates, and to provide a method for manufacturing the same. SOLUTION: Non-volatile memory transistors, each having the floating gate 5a formed on a silicon substrate 1 via a gate insulating film 4 and a control gate 7a formed on the gate 5a via an inter-gate insulating film 6, are formed integrally. A silicon oxide film 20 is formed in a state isolated from the gate 5a, in between the adjacent memory transistors in the channel longitudinal direction, and the gate 5a is filled in a self-aligned manner between the films 20. Thus, the gate 7a is extended, from the upper surface of the gate 5a to the side face, and the capacity coupling between the adjacent gates 5a is shielded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory integrated circuit using a nonvolatile memory transistor having a stacked structure of a floating gate and a control gate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art An electrically rewritable nonvolatile semiconductor memory (EE) which has a small unit cell area and is suitable for large capacity.
Some PROMs use NAND cells. FIG. 24 shows an equivalent circuit of the memory cell array.
FIG. 25 shows a sectional structure of the memory cell array in the bit line direction.

A plurality (for example, 16) of non-volatile memory transistors (memory cells) MT are connected in series so that adjacent sources share a source and a drain, and one end thereof is connected to a bit line BL via a selection transistor ST0.
The other end is connected to the common source line SS via the selection transistor ST1. The memory transistor MT has a stacked structure of a floating gate FG and a control gate CG, and the control gate CG is continuously patterned in one direction to become a word line WL. The select transistors ST0 and ST1 have the same gate structure as the memory transistor MT, but the floating gate is not separated, and the select gate lines SL0 and SL1 run in parallel with the word lines WL by the double-layer polycrystalline silicon film.
Is formed.

In the channel length direction of the NAND type cell, the control gate CG and the floating gate FG are etched in a self-aligned manner. At this time, the control gate CG
(That is, the pitch of the word lines WL) becomes the minimum processing dimension. For this reason, as miniaturization progresses, capacitive coupling between floating gates of adjacent memory transistors has become so large that it cannot be ignored.

[0005]

The above-described capacitive coupling between floating gates adversely affects memory characteristics. For example, consider a memory transistor of interest and a memory transistor adjacent thereto. The adjacent memory transistor changes from an erased state (a state in which electrons in the floating gate are released) to a write state (a state in which electrons are injected into the floating gate),
When the potential of the floating gate decreases, the potential of the floating gate of the memory transistor of interest decreases due to capacitive coupling, and the threshold value increases. That is, even if the distribution of the threshold value of the memory transistor is suppressed to a certain range by the verify operation after the writing, the threshold value fluctuates due to the writing of the adjacent memory transistor.

FIG. 26 shows the manner in which the threshold value changes in the case of a binary memory. The threshold distributions of the binary data "0" and "1" deviate from the desired state shown by the solid line as shown by the broken line. This leads to deterioration of read performance. Specifically, when reading is performed with the selected word line set to 0 V, “0” that is originally conductive is performed.
A situation occurs in which the data memory transistor does not conduct, or a situation occurs in which sufficient conduction cannot be obtained when a pass voltage is applied to a non-selected word line in the NAND cell to make it conductive.

FIG. 27 shows a case of a multi-valued memory (storage data has four values of "0", "1", "2", "3"). In the case of a multilevel memory, it is necessary to narrow the threshold range of each memory transistor to a narrower range than in the case of a binary memory. Therefore, the influence of the threshold variation due to capacitive coupling is greater than in the case of binary.

Specific numerical examples will be given. Note that the channel is in the accumulation state in the writing state and the channel is in the inversion state in the pair of specification castles, and the capacitance between the floating gate and the channel portion is simplified to that of a gate insulating film capacitor. Actually, when the channel is depleted, the capacitance between the floating gate and the channel is the series capacitance of the gate insulating film and the depletion layer. Therefore, the above assumption assumes that the capacitance between the floating gate and the channel is large. Therefore, it is assumed that the effect in question here is weakened.

Under the above assumption, if a memory cell is formed according to the 0.2 μm rule, the capacitance between the floating gate and the channel is 0.14 fF. The capacitance between the floating gate and the control gate is also about the same. In general, the width of the floating gate in the word line direction is about 1.5 times the minimum design rule in order to secure a large capacitive coupling between the control gate and the floating gate, and is about 0.3 μm. . Assuming that the thickness of the polycrystalline silicon constituting the floating gate is 0.1 μm, the capacitance between the floating gates adjacent in the channel length direction is
It becomes about 0.0052 fF.

Assuming that the threshold value of a memory transistor in an erased state is -3 V and the threshold value becomes 2 V after writing, a change in threshold value due to capacitive coupling in a memory transistor adjacent to this memory transistor is expressed as follows: -3│ + 2) × 0.14 / (0.14 + 0.1)
4) Δ × 0.0052 / (0.14 + 0.14) = 0.
046 [V].

When the design rule is 0.1 μm, the capacitance between the floating gate and the channel, the capacitance between the floating gate and the control gate, and the capacitance between the floating gates in the channel length direction are 0.035 fF, 0.035 fF, and 0.035 fF, respectively. 0.052
fF. At this time, when there is a threshold change due to writing similar to the above example, the threshold change in the adjacent memory transistor is ｛(│−3│ + 2) × 0.035 / (0.035 + 0.
035)｝ × 0.0052 / (0.035 + 0.03)
5) = 0.19 [V].

Further, when the design rule becomes 0.08 μm, the capacitance between the floating gate and the channel, the capacitance between the floating gate and the control gate, and the capacitance between the floating gates in the channel length direction are 0.022 fF and 0.022 fF, respectively. , 0.
052 fF. At this time, when there is a threshold change due to writing similar to the above example, the threshold change in the adjacent memory transistor is 、 (│−3│ + 2) × 0.022 / (0.022 + 0.
022)｝ × 0.0052 / (0.022 + 0.02)
2) = 0.30 [V].

In LSI miniaturization, although the planar size is reduced, various film thicknesses are not generally reduced due to securing of a withstand voltage, securing of a low resistance value, electromigration resistance and the like. Therefore, the capacitance between the floating gates does not change even if the design rule is reduced, whereas the capacitance between the floating gate and the channel portion, and the capacitance between the control gate and the floating gate are reduced by the square as the planar size is reduced. Become. As a result, as exemplified above, the variation in the threshold value due to the capacitive coupling between the floating gates increases with miniaturization and has a significant effect.

A numerical example in the case of a multi-value will be described. For example, 4
For the values, a threshold distribution as shown in FIG. 27 is determined. The threshold value of the highest write state, that is, the data "3" state in FIG.
The threshold value of the data “0” state of No. 7 is -3V. When the design rule is 0.2 μm, for a certain memory transistor, when the state is changed from the erased state to the maximum written state, the threshold value change in the adjacent memory transistor is ｛(│−3│ + 4) × 0.14 / (0.14 + 0.1
4) Δ × 0.0052 / (0.14 + 0.14) = 0.
064 [V].

When the design rule is 0.1 μm, the change in the upper threshold value is as follows: ｛(│−3│ + 4) × 0.035 / (0.035 + 0.
035)｝ × 0.0052 / (0.035 + 0.03)
5) = 0.27 [V]. Further, when the design rule is 0.08 μm,
The upper threshold change is: 、 (│−3│ + 4) × 0.022 / (0.022 + 0.
022)｝ × 0.0052 / (0.022 + 0.02)
2) = 0.42 [V]. Even if the gap (guard band) of the threshold distribution between the data shown in FIG. 27 is set to 0.5 V, the guard band may exceed the guard band due to the capacitive coupling between the floating gates.

In the case of a NAND flash EEPROM, data is erased collectively in block units.
Capacitance coupling between floating gates due to data erasure of an adjacent memory transistor in a NAND cell does not matter. However, in the case of a method in which data is erased in units of one word line range (one page), the threshold value fluctuation of the memory transistor adjacent to the erased memory transistor is changed.
It becomes a problem as in the case of writing.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor memory integrated circuit capable of preventing a characteristic variation due to capacitive coupling between floating gates and a method of manufacturing the same.

[0018]

According to the present invention, there is provided a semiconductor substrate, a floating gate formed on the semiconductor substrate via a first gate insulating film, and a second gate insulating film on the floating gate. In a semiconductor memory integrated circuit in which a non-volatile memory transistor having a control gate formed via a gate is integrated, capacitive coupling between floating gates of memory transistors adjacent in the channel length direction extends from the upper surface of the floating gate to the side surface. It is characterized by being shielded by a control gate provided.

According to the present invention, in the channel length direction of the memory transistor, by extending a part of the control gate to the side surface of the floating gate, the capacitive coupling between the adjacent floating gates is shielded, and the memory transistor is miniaturized. Characteristic fluctuation due to capacitive coupling between floating gates of the memory transistor at the time can be prevented.

In a method of manufacturing a semiconductor memory integrated circuit according to the present invention, a step of forming a floating gate on a semiconductor substrate while being covered with a first insulating film via a first gate insulating film; Forming a second insulating film selectively on the side wall of the stacked structure of the first and second insulating films; and forming a third insulating material different from the first and second insulating films between adjacent floating gates. A step of embedding a film, a step of peeling off the first and second insulating films, a step of forming a second gate insulating film on the upper surface and side surfaces of the floating gate, and depositing and etching an electrode material film And embedding a control gate facing the upper surface and the side surface of the floating gate in a state of being self-aligned with the third insulating film.

According to the method of manufacturing a semiconductor memory integrated circuit of the present invention, a step of forming an element isolation insulating film for partitioning a stripe-shaped element formation region in which a plurality of memory transistors are formed on a semiconductor substrate; Depositing a first electrode material film via a gate insulating film on
Forming a slit on the element isolation insulating film in the first electrode material film, embedding a first insulating film in the slit, and masking the first electrode material film with a second insulating film Forming a plurality of floating gates arranged at a predetermined pitch on the element formation region by etching using a pattern; and selectively forming a third insulating film on a side wall of the stacked structure of the floating gate and the second insulating film. Forming a film, forming source and drain diffusion layers in a self-aligned manner on the floating gate, and forming a fourth insulating material different from the first to third insulating films between the adjacent floating gates. A step of embedding a film, a step of peeling off the first to third insulating films,
Forming an inter-gate insulating film on the upper surface and side surfaces of the floating gate, and depositing and etching a second electrode material film to form the floating gate in a self-aligned state with the fourth insulating film. Burying a control gate facing the upper surface and the side surface.

According to the manufacturing method of the present invention, the control gate structure for shielding the capacitive coupling between the floating gates can be formed in a self-aligned manner by utilizing the damascene method.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG.
FIG. 2A, FIG. 2B, and FIG. 2C are cross-sectional views taken along lines AA ′, BB ′, and CC ′ of FIG. 1, respectively.

The silicon substrate 1 has, for example, a double well structure, and the memory cell array region is a p-type well. This substrate 1 is provided with STI (Shallow Trench).
The element isolation insulating film 2 is buried by an (hIsolation) method, and a stripe-shaped element formation region 3 is partitioned. Channel ion implantation is performed on the element formation region 3 as necessary. On such a substrate 1, a floating gate 5a is formed by a first layer polycrystalline silicon film via a gate insulating film 4, and a second layer polycrystalline silicon film is formed on the floating gate 5a via an intergate insulating film 6. Control gate line 7a is formed. Source / drain diffusion layers 8 are formed on control gate line 7a in a self-aligned manner to form a nonvolatile memory transistor.

As shown in FIGS. 1 and 2B, the floating gate 5a is separated for each memory transistor in the direction of the word line WL. The control gate line 7a is formed continuously and becomes a word line WL. Regarding the select transistors formed at both ends of the NAND type cell, the first layer polycrystalline silicon film 5a is formed continuously in parallel with the word line WL, and together with the second layer polycrystalline silicon film 7b laminated thereon. , Select gate lines SL0 and SL1.

Although the gate insulating film 4 in the memory transistor region is not distinguished from the gate insulating film 4 in the select transistor region in the drawing, a thin tunnel insulating film is actually used in the memory transistor region, and a thicker gate insulating film is used in the select transistor region. Is used. Also, select gate lines SL0,
The first polycrystalline silicon film 5b and the second polycrystalline silicon film 7b of SL1 are short-circuited at an appropriate interval.

As shown in FIG. 2A, a floating gate 5a is provided between adjacent memory transistors in the channel length direction.
Is formed, a silicon oxide film 20 is buried as an insulating film so as to partition between the floating gates 5a, leaving a gap between the silicon oxide film 20 and the floating gates 5a. The control gate 7a is self-aligned and embedded between these silicon oxide films 20. As a result, the control gate line 7a also enters the gap between the floating gate 5a and the silicon oxide film 20, and extends from the upper surface of the floating gate 5a symmetrically to the source and drain sides to both sides. Formed into a state. Thus, the control gate 7
As a result, the floating gate 5a is self-aligned with the floating gate 5a, symmetrically overlaps with the source and drain sides of the transistor, and the portions extending on both side surfaces of the floating gate 5a are adjacent to the floating gate 5a in the channel length direction. It will act as a shield to prevent capacitive coupling between them.

The same structure is provided between a select gate transistor and a memory transistor, and between select gate transistors adjacent to each other with a bit line contact interposed therebetween. That is,
Second layer polycrystalline silicon film 7b which is a gate electrode of a select gate transistor and becomes select gate lines SL0 and SL1
Thus, the select gate line is also buried so as to extend from the upper surface to the side surface of the first-layer polycrystalline silicon film 5b, similarly to the control gate 7a.

In this embodiment, the memory transistors arranged in the word line WL direction have the same structure. That is, as shown in FIG. 2B, a silicon oxide film 21 as an insulating film that partitions between the floating gates 5a is left on the element isolation insulating film 2 between the adjacent memory transistors, with a gap left between the floating gates 5a. Embedded with The control gate lines 7a are continuously patterned while being self-aligned and embedded between the silicon oxide films 21.

The surface on which the memory transistor and the select transistor are formed is covered with an interlayer insulating film 9. A contact plug 10 is buried in the interlayer insulating film 9, and a bit line (BL) 11 connected to the diffusion layer 8 via the contact plug 10 is formed. The bit line 11 is further covered with an interlayer insulating film 12, on which a necessary metal wiring is formed (not shown).

The manufacturing process of the memory cell array region according to this embodiment will now be described with reference to FIGS. 3A to 3C. 3A to 3C respectively correspond to FIG.
2 to FIG. 2C. The same applies to the subsequent process sectional views. 3A to 3C show a state where a first-layer polycrystalline silicon film 5 as an electrode material film is deposited via a gate insulating film 4 on a substrate 1 which has been subjected to element isolation according to a normal process.

Next, as shown in FIGS. 4A to 4C, in order to separate the floating gate in the word line WL direction, a slit is formed on the first layer polycrystalline silicon film 5 by lithography and RIE on the element isolation insulating film 2. Process 30. Subsequently, a silicon nitride film 31 is deposited as an insulating film material that can be removed with a solvent different from the silicon oxide film or the polycrystalline silicon film, and this is entirely etched and left only on the side wall of the slit 30.

Next, as shown in FIGS. 5A to 5C, a silicon oxide film 21 is deposited on the entire surface. The silicon oxide film 21 is flattened by CMP to obtain
As shown in C, it is embedded in the slit 30.

Next, as shown in FIGS. 7A to 7C, a silicon nitride film 33 of the same material as the material left on the slit side wall is deposited on the entire surface. And lithography and RIE
As a result, as shown in FIG. 8A to FIG. 8C, the silicon nitride film 33 is turned into a word line WL and select gate lines SL0 and S0.
The mask pattern is formed to be continuous in the L1 direction. At this time, the silicon oxide film 21 and the silicon nitride film 31 remaining on the side walls are also etched away in the slit portion on the element isolation region. Then, using the patterned silicon nitride film 33 as a mask, the first layer polycrystalline silicon film 5 is etched to form floating gates 5a arranged at a predetermined pitch in the channel length direction and lower wirings 5b of select gate lines SL0 and SL1. And are formed. The lower wiring 5b is not slit-processed and continues in the direction of the select gate lines SL0 and SL1.

Further, by depositing a silicon nitride film 34 and etching the entire surface, the silicon nitride film 34 is left on the side wall of the floating gate 5a covered with the silicon nitride film 33, as shown in FIG. 8A. As described above, the source and drain diffusion layers 8 are formed by implanting impurity ions while the silicon nitride film 34 is formed on the side wall of the floating gate 5a. The step of forming the source / drain diffusion layer 8 is as follows.
This can be performed before forming the silicon nitride film 34 on the side wall.

After that, as shown in FIGS. 9A to 9C, a silicon oxide film 20 is deposited, and the silicon oxide film 20 is buried flat in the gap between the floating gates 5a by CMP or whole surface etching. Then, using a solvent capable of isotropically and selectively etching the silicon nitride film, for example, hot phosphoric acid, the silicon nitride film 33 covering the floating gate 5a and the silicon nitride films 34 and 31 formed on the side walls of the floating gate 5a are removed. Etch. As a result, FIG.
As shown in FIGS. 10A to 10C, partitioning silicon oxide films 20 and 21 are provided between the floating gates 5a adjacent to each other in the channel length direction and the word line direction orthogonal thereto. A state where the gap is left is obtained.

It should be noted here that, in the channel length direction, the upper surface of the silicon oxide film 20 formed between the floating gates 5a is higher than the upper surface of the floating gate 5a (FIG. 1).
0A), the silicon oxide film 21 left in the isolation region of the floating gate 5a on the element isolation region has substantially the same upper surface as the upper surface of the floating gate 5a (see FIG. 10B).

Thereafter, after the inter-gate insulating film 6 is formed,
The floating gate 5 is formed in the channel length direction by the damascene process.
A polycrystalline silicon film is buried between the silicon oxide films 20 partitioning between a. That is, as shown in FIG. 11A to FIG. 11C, as the inter-gate insulating film 6, for example, a silicon oxide film / silicon nitride film / silicon oxide film (ONO
After forming the film, a second-layer polycrystalline silicon film 7 serving as a gate electrode material film of the control gate and the select transistor is deposited. Then, the polycrystalline silicon film 7 is entirely etched until the upper surface of the silicon oxide film 20 is exposed.
As shown in FIGS. 2A to 12C, a control gate line (word line WL) 7a of a memory transistor and a select gate line (SL0, SL1) 7b, which is a gate electrode of a select transistor, separated by a silicon oxide film 20 are formed.

Control gate 7a and select gate line 7b
In the channel length direction, as shown in FIG. 12A, the silicon oxide film 20 enters the gap between the floating gate 5a and the silicon oxide film 20 so as to extend from the upper surface to the side surface. Also in the word line direction, as shown in FIG. 12B, the control gate 7a enters the gap between the floating gate 5a and the silicon oxide film 21 so as to extend from the upper surface to the side surface. Thereafter, as shown in FIGS. 2A to 2C, an interlayer insulating film 9 is deposited according to a normal process, a contact plug 10 is buried, and a bit line 11 is formed.

According to this embodiment, the control gate 7a
Extend from the upper surface to the side surface of the floating gate 5a in both the channel length direction and the direction orthogonal to the channel length direction. In particular, in the channel length direction, the control gate 7a is self-aligned with the floating gate 5a, and is formed to extend symmetrically from the upper surface of the floating gate 5a to the source and drain sides. The control gate portion extending to the side surface of the floating gate serves as a shield for preventing capacitive coupling between the floating gates. As a result, interference due to writing in an adjacent memory transistor is prevented. Therefore, the NAND type EEPR
This prevents deterioration of characteristics due to interference between adjacent memory transistors when the OM is miniaturized.

In the case of this embodiment, the control gate 7
Since a faces not only the upper surface of the floating gate 5a but also the four side surfaces, the coupling capacitance between the control gate and the floating gate is increased, and excellent write characteristics are obtained. Further, since the process for extending the control gate 7a to the side surface of the floating gate 5a is performed in a self-aligned manner by using the damascene process, the increase in the cell size can be suppressed.

Next, a NAND cell type EEPROM according to another embodiment will be described. The layout of the memory cell array is the same as that of the previous embodiment shown in FIG. In the following drawings, parts corresponding to those in the above embodiment are denoted by the same reference numerals. In the case of this embodiment, AA ', B in FIG.
13A, 13B and 13C are sectional views taken along the lines -B 'and CC', respectively.

As in the previous embodiment, in the channel length direction, as shown in FIG. 13A, a silicon oxide film 20 is arranged between adjacent floating gates 5A. The control gate 7a is formed in an aligned state. Therefore, the control gate 7a is embedded so as to extend from the upper surface to the side surface of the floating gate 5a. However, in the above embodiment, as shown in FIG. 2B, the silicon oxide film 21 is arranged on the element isolation insulating film 2 between the floating gates 5a arranged in the word line direction, but in this embodiment, FIG. This silicon oxide film 21 does not exist as shown in FIG.

The specific manufacturing steps are shown in FIG.
FIG. 14 showing cross sections A ′, BB ′ and CC ′
A description will be given with reference to the process sectional views of FIGS. FIGS. 14A to 14C show a state in which a first-layer polycrystalline silicon film 5 as an electrode material film is deposited via a gate insulating film 4 on a substrate 1 which has been subjected to element isolation according to a normal process.

Next, as shown in FIGS. 15A to 15C,
In order to separate the floating gate in the word line WL direction, a slit 30 is formed in the first layer polycrystalline silicon film 5 on the element isolation insulating film 2 by lithography and RIE. continue,
As shown in FIGS. 16A to 16C, a silicon nitride film 41 is deposited as an insulating film material that can be separated with a solvent different from a silicon oxide film or a polycrystalline silicon film. Then, the silicon nitride film 41 is etched by CMP processing or the entire surface, and as shown in FIGS. 17A to 17C,
It is embedded flat in the slit 30.

Next, as shown in FIGS. 18A to 18C,
A silicon nitride film 33 made of the same material as the material embedded in the slit is deposited on the entire surface. And lithography and R
19A to 19C, the silicon nitride film 33 is converted into a word line WL and a select gate line S as shown in FIGS.
The mask pattern is formed to be continuous in the L0 and SL1 directions. At this time, at the same time, the silicon nitride film 41 is also etched away in the slit portion on the element isolation region. Then, using the patterned silicon nitride film 33 as a mask, the first layer polycrystalline silicon film 5 is etched to form floating gates 5a arranged at a predetermined pitch in the channel length direction.
And the lower wiring 5b of the select gate lines SL0 and SL1 are formed. The lower wiring 5b is not slit-processed and continues in the direction of the select gate lines SL0 and SL1.

Further, by depositing a silicon nitride film 34 and etching the entire surface, the silicon nitride film 34 is left on the side wall of the floating gate 5a covered with the silicon nitride film 33, as shown in FIG. 19A. As described above, the source and drain diffusion layers 8 are formed by implanting impurity ions while the silicon nitride film 34 is formed on the side wall of the floating gate 5a. Note that the step of forming the source / drain diffusion layers 8 may be performed before forming the silicon nitride film 34 on the side walls.

Thereafter, as shown in FIGS. 20A to 20C, a silicon oxide film 20 is deposited, and is etched by CMP or the whole surface to bury the silicon oxide film 20 in the gap between the floating gates 5a flat. And a solvent capable of isotropically and selectively etching the silicon nitride film;
The silicon nitride film 33 covering the floating gate 5a and the silicon nitride films 34 and 41 formed on the side walls of the floating gate 5a are etched using, for example, hot phosphoric acid. This allows
As shown in FIGS. 21A to 21C, a state in which a silicon oxide film 20 serving as a partition is arranged between each floating gate 5a adjacent in the channel length direction with a gap left between the floating gate 5a and the floating gate 5a. can get.

Here, in the channel length direction, the upper surface of the silicon oxide film 20 formed between the floating gates 5a is higher than the upper surface of the floating gate 5a (see FIG. 21A). Thereafter, after the inter-gate insulating film 6 is formed, a polycrystalline silicon film is buried between the silicon oxide films 20 separating the floating gates 5a in the channel length direction by a damascene process. That is, as shown in FIGS. 22A to 22C, for example, after a laminated structure film (ONO film) of a silicon oxide film / silicon nitride film / silicon oxide film is formed as the inter-gate insulating film 6, the gate of the control gate and the gate of the select transistor are formed. A second-layer polycrystalline silicon film 7 serving as an electrode material film is deposited. Then, the polycrystalline silicon film 7 is entirely etched until the upper surface of the silicon oxide film 20 is exposed.
As shown in FIG. 3C, the control gate line (word line WL) of the memory transistor separated by the silicon oxide film 20
7a and select gate lines (SL0, SL1) 7b which are gate electrodes of the select transistors are formed.

Control gate 7a and select gate line 7b
In the channel length direction, as shown in FIG. 23A, the silicon oxide film is self-aligned with the floating gate 5a and symmetrically extends from the upper surface of the floating gate 5a to the source and drain sides to the side surfaces. 20 and into the gap. Also in the word line direction, as shown in FIG. 23B, the control gate 7a is embedded in the slit so as to face the side surface from the upper surface of the floating gate 5a. Thereafter, as shown in FIGS. 2A to 2C, an interlayer insulating film 9 is deposited according to a normal process, a contact plug 10 is buried, and a bit line 1 is formed.
1 is formed.

According to this embodiment, as in the previous embodiment, interference due to capacitive coupling between adjacent floating gates can be prevented. Further, since the control gate faces not only the upper surface of the floating gate but also the four side surfaces, the coupling capacitance between the control gate and the floating gate is increased, and excellent writing characteristics are obtained. Furthermore, since the process for extending the control gate to the side surface of the floating gate is performed in a self-aligned manner by using a damascene process, an increase in cell size can be suppressed. Unlike the previous embodiment, a control gate is buried without a silicon oxide film serving as a partition between floating gates adjacent in the word line direction. Therefore, an effect equivalent to that of the above embodiment can be obtained with a simpler process than that of the above embodiment.

Up to this point, EE using NAND cells has been described.
Although the PROM has been described, the present invention is not limited to this. EEPRO such as DINOR type, AND type, NOR type
Even in the case of M, when the memory transistor has a stacked structure of the floating gate and the control gate and has a structure in which there is no contact between the floating gates of the adjacent memory transistors, the same effect is obtained by applying the present invention. Is obtained.

[0053]

As described above, according to the present invention, by forming the control gate so as to cover the side surface of the floating gate, interference due to capacitive coupling between the floating gates of adjacent memory transistors can be prevented. In particular, the performance of miniaturized memories and multi-value memories can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layout of a memory cell array according to an embodiment of the present invention.

FIG. 2A is a sectional view taken along line A-A 'of FIG.

FIG. 2B is a sectional view taken along line B-B 'of FIG.

FIG. 2C is a sectional view taken along the line C-C 'of FIG.

FIG. 3A is a diagram showing a first embodiment of a polycrystalline silicon film deposition process.
It is A 'sectional drawing.

FIG. 3B is a sectional view taken along the line B-B 'showing the same step.

FIG. 3C is a sectional view along a line C-C 'showing the same step.

FIG. 4A is a cross-sectional view along the line AA ′ showing a step of forming a slit in the first-layer polycrystalline silicon film.

FIG. 4B is a sectional view taken along the line B-B 'showing the same step.

FIG. 4C is a cross-sectional view along the line C-C 'showing the same step.

FIG. 5A is an AA ′ sectional view showing a silicon oxide film depositing step.

FIG. 5B is a sectional view taken along the line B-B 'showing the same step.

FIG. 5C is a cross-sectional view along the line C-C 'showing the same step.

FIG. 6A is a cross-sectional view along the line AA 'showing a step of embedding a slit in a silicon oxide film.

FIG. 6B is a B-B ′ sectional view showing the same step.

FIG. 6C is a sectional view along a line C-C 'showing the same step.

FIG. 7A is an AA ′ sectional view showing a silicon nitride film depositing step.

FIG. 7B is a B-B ′ sectional view showing the same step.

FIG. 7C is a cross-sectional view along the line C-C 'showing the same step.

FIG. 8A is a cross-sectional view along the line AA 'showing a floating gate patterning step using a silicon nitride film mask.

FIG. 8B is a sectional view taken along the line B-B 'showing the same step.

FIG. 8C is a sectional view along a line C-C 'showing the same step.

FIG. 9A is a sectional view along AA 'showing a step of embedding a silicon oxide film between floating gates.

FIG. 9B is a sectional view taken along the line B-B 'showing the same step.

FIG. 9C is a cross-sectional view along the line C-C 'showing the same step.

FIG. 10A is an AA ′ showing a step of removing a silicon nitride film;
It is sectional drawing.

FIG. 10B is a B-B ′ sectional view showing the same step.

FIG. 10C is a sectional view along a line C-C 'showing the same step.

FIG. 11A is a view showing a step of depositing a second-layer polycrystalline silicon film.
It is -A 'sectional drawing.

FIG. 11B is a B-B ′ sectional view showing the same step.

FIG. 11C is a cross-sectional view along the line C-C 'showing the same step.

FIG. 12A is a sectional view taken along the line AA ′ showing a step of etching a second-layer polycrystalline silicon film to bury a control gate.

FIG. 12B is a sectional view taken along the line B-B 'showing the same step.

FIG. 12C is a sectional view along a line C-C 'showing the same step.

FIG. 13A is a sectional view of the memory cell array taken along line AA ′ of FIG. 1 according to another embodiment;

FIG. 13B is a sectional view taken along the line B-B ′.

FIG. 13C is a sectional view taken along the line C-C ′.

FIG. 14A is a sectional view along AA 'showing a step of depositing a first-layer polycrystalline silicon film according to the embodiment.

FIG. 14B is a sectional view taken along the line B-B ′ of the same step.

FIG. 14C is a sectional view taken along the line C-C ′ in the same step.

FIG. 15A is a sectional view taken along the line AA ′ showing a step of forming a slit of the first-layer polycrystalline silicon film.

FIG. 15B is a B-B ′ sectional view showing the same step.

FIG. 15C is a sectional view along a C-C ′ line showing the same step.

FIG. 16A is a sectional view taken along the line AA ′ showing a silicon nitride film depositing step.

FIG. 16B is a sectional view taken along the line B-B ′ showing the same step.

FIG. 16C is a sectional view along a line C-C ′ showing the same step.

FIG. 17A is a sectional view taken along the line AA ′ showing a step of embedding a slit in a silicon nitride film.

FIG. 17B is a B-B ′ sectional view showing the same step.

FIG. 17C is a sectional view along a line C-C 'showing the same step.

FIG. 18A is a sectional view along AA 'showing a silicon nitride film depositing step.

FIG. 18B is a sectional view along a B-B ′ line showing the same step.

FIG. 18C is a cross-sectional view along the line C-C 'showing the same step.

FIG. 19A is a sectional view taken along the line AA ′ showing a floating gate patterning step using a silicon nitride film mask.

FIG. 19B is a B-B ′ sectional view showing the same step.

FIG. 19C is a cross-sectional view along the line C-C 'showing the same step.

FIG. 20A is a sectional view taken along the line AA ′ showing a step of embedding a silicon oxide film between floating gates.

FIG. 20B is a B-B ′ sectional view showing the same step.

FIG. 20C is a cross-sectional view along the line C-C 'showing the same step.

FIG. 21A is an AA ′ showing a step of removing a silicon nitride film;
It is sectional drawing.

FIG. 21B is a B-B ′ sectional view showing the same step.

FIG. 21C is a cross-sectional view along the line C-C 'showing the same step.

FIG. 22A is a view showing a step of depositing a second-layer polycrystalline silicon film.
It is -A 'sectional drawing.

FIG. 22B is a sectional view taken along the line B-B ′ showing the same step.

FIG. 22C is a sectional view along a C-C ′ line showing the same step.

FIG. 23A is a sectional view along AA ′ showing a step of etching a second-layer polycrystalline silicon film to bury a control gate.

FIG. 23B is a B-B ′ sectional view showing the same step.

FIG. 23C is a cross-sectional view along the line C-C 'showing the same step.

FIG. 24 is an equivalent circuit of a memory cell array of a NAND type EEPROM.

FIG. 25 is a sectional view of the memory cell array in a bit line direction.

FIG. 26 is a diagram showing data and threshold distribution in the case of binary storage.

FIG. 27 is a diagram showing data and threshold distribution in the case of multi-value storage.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation insulating film, 3 ... Element formation region, 4 ... Gate insulating film, 5 ... First-layer polycrystalline silicon film, 5a ... Floating gate, 5b ... Select gate line, 6 ... Intergate insulation Film, 7: second-layer polycrystalline silicon film, 7a: control gate (word line), 7b: selection gate line, 8: source and drain diffusion layers, 9: interlayer insulating film, 10: contact plug, 11: bit line , 20, 21 ... silicon oxide film.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 27/115 29/417 F term (Reference) 4M104 AA01 BB01 CC05 DD02 DD04 DD16 DD17 FF06 GG16 HH20 5F001 AA25 AA43 AA63 AB02 AD41 AD60 AD61 AF20 AG07 5F033 HH04 MM17 MM20 QQ08 QQ09 QQ19 QQ25 QQ31 QQ48 RR04 VV03 VV06 XX23 5F083 EP02 EP27 EP33 EP34 EP55 EP76 GA13 JA04 NA01 PR06 PR29 PR40 PR44 PR54 ZA21

Claims (6)

[Claims] A nonvolatile memory having a semiconductor substrate, a floating gate formed on the semiconductor substrate via a gate insulating film, and a control gate formed on the floating gate via an inter-gate insulating film. In a semiconductor memory integrated circuit in which transistors are integratedly formed, capacitive coupling between floating gates of memory transistors adjacent in the channel length direction is shielded by a control gate extending from the upper surface to the side surface of the floating gate. Semiconductor memory integrated circuit. 2. An insulating film is disposed between memory transistors adjacent in a channel length direction at a predetermined distance from a floating gate of the memory transistor, and a control gate is embedded in the insulating film in a self-aligned manner. 2. The semiconductor memory integrated circuit according to claim 1, wherein: 3. The semiconductor memory integrated circuit according to claim 1, wherein said control gate extends symmetrically from the upper surface of said floating gate to the source and drain sides in a self-aligned manner with said floating gate. . 4. The semiconductor memory integrated circuit according to claim 1, wherein a plurality of memory transistors adjacent to each other in a channel length direction share a source / drain diffusion layer to form a NAND type cell. . 5. A semiconductor device, comprising:
Forming a floating gate in a state of being covered with the insulating film, and selectively forming a second insulating film on a side wall of a stacked structure of the floating gate and the first insulating film; Embedding a third insulating film of a material different from that of the first and second insulating films, separating the first and second insulating films, and forming a gate on the upper surface and side surfaces of the floating gate Forming an inter-insulating film, and embedding a control gate facing the upper surface and side surfaces of the floating gate in a state of being self-aligned with the third insulating film by depositing and etching an electrode material film. A method for manufacturing a semiconductor memory integrated circuit, comprising: 6. A step of forming an element isolation insulating film for partitioning a stripe-shaped element formation region where a plurality of memory transistors are formed on a semiconductor substrate; and a first electrode material on the semiconductor substrate via a gate insulating film. Depositing a film, forming a slit in the first electrode material film on the element isolation insulating film, embedding a first insulating film in the slit, and depositing the first electrode material film. Etching using a mask pattern of a second insulating film to form a plurality of floating gates arranged at a predetermined pitch on the element formation region; and forming a plurality of floating gates on a sidewall of a stacked structure of the floating gate and the second insulating film. Selectively forming a third insulating film; forming self-aligned source and drain diffusion layers on the floating gate; and forming the first to third insulating layers between adjacent floating gates. A step of embedding a fourth insulating film of a material different from the above, a step of separating the first to third insulating films, a step of forming an inter-gate insulating film on the upper surface and side surfaces of the floating gate, Embedding a control gate facing the upper surface and side surfaces of the floating gate in a state of being self-aligned with the fourth insulating film by depositing and etching an electrode material film. An integrated circuit manufacturing method.