KR100833448B1 - Non-volatile memory device, and method of manufacturing thereof, and method of programming thereof - Google Patents

Abstract

A non volatile memory device, a manufacturing method thereof and a programming method thereof are provided to prevent variation of threshold voltage of a memory cell by preventing transfer of hot carrier into the memory cell, and simultaneously minimizing the capacitance coupling between a word line and a select line. A second insulating layer(218) is formed on a semiconductor substrate(200) including a conductive shielding line(216p). A contact hole is formed on the second insulating layer so as to expose a part of a drain(212d), the conductive shielding line and a source contact plug(216s). A drain contact plug(220d) is formed within the contact hole above the drain. At this time, an upper part contact plug(220) is formed in the contact hole above the conductive shielding line and the source contact plug.

Description

Non-volatile memory device, method of manufacturing the same and program method thereof Non-volatile memory device, and method of manufacturing, and method of programming

1 is a cross-sectional view illustrating a change of a threshold voltage in a memory cell adjacent to a select transistor during a program operation according to the related art.

2A through 2E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

3 is a circuit diagram illustrating a program method of a nonvolatile memory device according to a first embodiment of the present invention.

4 is a circuit diagram illustrating a program method of a nonvolatile memory device according to a second exemplary embodiment of the present invention.

FIG. 5 is a timing diagram illustrating a bias applied in the program method of FIG. 4.

<Explanation of symbols for the main parts of the drawings>

100, 200: semiconductor substrate 105: channel region

110, 212d: Drain 115, 212s: Source

202: tunnel insulating film 204: electron storage film

206: dielectric film 208: control gate

210: hard mask 212j: junction area

214: first insulating film 216s: source contact plug

216p: conductive shielding line 218: second insulating film

220: upper contact plug 220d: drain contact plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, a method of manufacturing the same, and a program method thereof, and more particularly, to a nonvolatile memory device for minimizing a change in threshold voltage of a memory cell that is not programmed during a program operation. will be.

The nonvolatile memory device has a characteristic that stored data is not erased even when power supply is interrupted. A typical nonvolatile memory device is a flash memory device, which can be classified into a NOR flash memory device and a NAND flash memory device according to the structure of a memory cell array.

In the NAND type flash memory device, a memory cell array is divided into block units, and each block includes a plurality of strings. Here, the string includes a select transistor and a memory cell. Specifically, the string includes a drain select transistor connected to a bit line, a source select transistor connected to a common source, and a plurality of memories connected in series between the drain select transistor and the source select transistor. The gate of the drain select transistor is connected to the gates of the drain select transistors included in another string, and the connected gates become a drain select line. The gate of the source select transistor is connected to the gates of source select transistors included in another string, and the connected gates become source select lines. Gates of the memory cells are connected to gates of memory cells included in other strings, respectively, and the connected gates become word lines.

The NAND flash memory device including the string stores data in a program operation of injecting electrons into the floating gate. All memory cells are erased before the program operation is performed. That is, all the electrons injected into the floating gate by the erase operation before the program operation are released to make the memory cells erase. Thereafter, a program operation is performed. In all memory program operations, a high program voltage of 15V to 20V is applied to a selected word line, and a pass voltage of 9V to 10V is applied to other word lines to turn on a memory cell. Meanwhile, not all memory cells connected to the word line are programmed, but some memory cells must be erased according to data to be stored. Therefore, 0 V is applied to the bit line connected to the string including the memory cell to be programmed and the program disturb voltage is applied to the bit line connected to the string including the memory cell to maintain the erase state. (E.g., Vcc) is applied. When the program disturb voltage is applied, even if a high program voltage is applied to the word line, the program operation is not performed because the program voltage is transferred to the channel region and the voltage difference is reduced. However, in a memory cell adjacent to the select transistor, a threshold voltage is changed due to hot carrier injection. This will be described in detail as follows.

1 is a cross-sectional view illustrating a change of a threshold voltage in a memory cell adjacent to a select transistor during a program operation according to the related art. The power source voltage Vcc is applied to the drain 110 and the source 115 of the string including the memory cell that must maintain the erase state during the program operation through the bit line BL0 and the common source line CSL. The power supply voltage Vcc is applied to the drain select line DSL, and the ground voltage 0V is applied to the source select line SSL. In this state, channel boosting occurs on the surface of the semiconductor substrate 100 due to the high bias applied to the word lines WL0 to WL31 during the program operation. In addition, the GIDL current is generated by the high junction potential at the edge portion A where the junction of the source select transistor SST adjacent to the memory cell M0 connected to the selected word line WL0 is shared. (2), hot carriers of electron-hole pairs are also generated by the strong corner field due to the channel boosting potential. Hot election of the hot carrier moves into the cell string by the side electric field due to the channel boosting potential. In detail, a hot carrier is generated in the channel region 105 under the memory cell MO connected to the word line WL0 to which the program voltage 18V is applied, and high is generated by the program voltage 18V. Hot election hot electrons generated in the channel region 105 under the word line WLO are injected into the floating gate 130 of the memory cell M0 by the vertical electric field.

In such a mechanism, the electrons formed in the edge portion A in which the junction of the source select transistor SST and the memory cell M0 connected to the word line WL0 adjacent to the source select transistor SST are shared. The channel boosting potential is accelerated by moving from the source select transistor SST toward the adjacent word line WL0 to have hot electron characteristics enough to program the word line WL0. As a result, during the program operation, the threshold voltage Vth of the flash memory cell M0 connected to the word line WL0 adjacent to the source select transistor SST changes. In addition, a similar phenomenon may occur in the memory cell M31 connected to the word line WL31 adjacent to the drain select transistor DST to change the threshold voltage Vth.

In addition, a parasitic capacitor C100 exists between the word line and the select line (particularly, the drain select line), and the threshold voltage Vth also changes in the select transistor and the memory cell due to capacitance coupling of the parasitic capacitor C100. Problems arise.

As described above, as the threshold voltage of the memory cell to maintain the erase state during the program operation is changed by hot carrier injection or capacitance coupling between the word line and the select line, the data stored in the memory cell is changed.

In contrast, the nonvolatile memory device, a method of manufacturing the same, and a program method thereof according to the present invention form an electrode isolated from a semiconductor substrate between a select line and a word line, and apply a bias during a program operation to move a hot carrier to a memory cell. By minimizing the capacitance coupling between the word line and the select line at the same time, it is possible to prevent the threshold voltage of the memory cell, which must maintain the erase state during the program operation, from changing.

A nonvolatile memory device according to an embodiment of the present invention includes a plurality of select lines and a plurality of word lines formed on a semiconductor substrate, a contact plug formed between the select lines, and a semiconductor substrate between the select line and the word line. And a conductive shielding line provided to be isolated.

In the above, the select line is a source select line or a drain select line. The select line may include a source select line and a drain select line, and a conductive shielding line may be provided to be isolated from the semiconductor substrate, respectively, between the drain select line and the word line, and between the source select line and the word line. The semiconductor device may further include a junction region formed on the semiconductor substrate between the select lines and the word lines. And an insulating film for electrically isolating the conductive shielding line from the select lines and the word lines.

A method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention includes providing a semiconductor substrate having a plurality of select lines and a plurality of word lines, and forming a first insulating layer on the semiconductor substrate including the select lines and the word lines. Forming a conductive film, removing the first insulating film between the select line, forming a conductive shielding line on the first insulating film between the select line and the word line, and forming a conductive shielding line on the semiconductor substrate including the conductive shielding line. Forming a contact hole by forming a second insulating film, etching the second insulating film to expose the semiconductor substrate and the conductive shielding line between the select lines, and forming a contact plug inside the contact hole.

In the above, the method may further include forming a junction region in the semiconductor substrate between the select lines and the word lines before forming the first insulating layer. A conductive shielding line may be formed between the source select line and the word line among the select lines. A conductive shielding line may be formed between the drain select line and the word line among the select lines. The select line includes a source select line and a drain select line, and a conductive shielding line may be formed between the drain select line and the word line and on the first insulating layer between the source select line and the word line, respectively. When forming the conductive shielding line, source contact plugs may be formed together on the semiconductor substrate between the source select lines.

In the method of programming a nonvolatile memory device according to the first embodiment of the present invention, a plurality of word lines and a plurality of select lines are formed on a semiconductor substrate, and a conductive shielding line is isolated from the semiconductor substrate between the word lines and the select line. And providing a nonvolatile memory device provided thereon, and performing a program operation while applying a negative potential bias to the conductive shielding line.

In the above, the select line includes a source select line and a drain select line, and a conductive shielding line is provided between the source select line and the word line. A conductive shielding line may be provided between the drain select line and the word line. A conductive shielding line may be provided between the source select line and the word line and between the drain select line and the word line, respectively. A negative potential bias of -1V to -5V is applied to the conductive shielding line.

In the method of programming a nonvolatile memory device according to a second embodiment of the present invention, a plurality of word lines and a plurality of select lines are formed on a semiconductor substrate, and a first conductive shield is isolated from the semiconductor substrate between the word lines and the select line. Providing a nonvolatile memory device having a line, and performing a program operation while applying a positive potential bias to the conductive shielding line.

In the above, the positive potential bias is applied at the same timing or earlier than the bias applied to the word lines which are not selected during the program operation among the word lines. The select line includes a source select line and a drain select line, and a first conductive shielding line is provided between the drain select line and the word line. In the program operation, a positive potential bias higher than a bias applied to the drain select line and lower than 5V is applied to the first conductive shielding line. A second conductive shielding line is further provided between the source select line and the word line, and a negative potential bias may be applied to the second conductive shielding line during the program operation. A negative potential bias of -1 V to -5 V is applied to the second conductive shielding line.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

2A through 2E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a plurality of select lines DSL and SSL and word lines WL0 to WLn are formed on the semiconductor substrate 200, and a junction region 212j, a drain 212d, and a source (between) are formed therebetween. 212s) is formed. In detail, a plurality of word lines WL0 to WLn are formed between the drain select line DSL and the source select line SSL. A drain 212d to be connected to the bit line is formed in the semiconductor substrate 200 between the drain select line DSL, and a source 212s is formed in the semiconductor substrate 200 between the source select line SSL. Meanwhile, the select lines DSL and SSL and the word lines WL0 to WLn may form the tunnel insulating layer 202, the electron storage layer 204, the dielectric layer 206, the control gate 208, and the hard mask 210. Include. In this case, a portion of the dielectric layer 206 is removed from the select lines DSL and SSL so that the electron storage layer 204 is connected to the control gate 208. In the above, the drain select line DSL, the source select line SSL, and the word lines WL0 to WLn formed therebetween form one string.

Meanwhile, the spacing between the select lines is wider than the spacing between word lines. The gap between the select line and the word line is wider than the gap between the word lines and smaller than the gap between the select lines.

Referring to FIG. 2B, the first insulating layer 214 is formed on the semiconductor substrate 200 including the select lines DSL and SSL and the word lines WL0 to WLn. The first insulating film 214 may be formed of an oxide film or a nitride film, or may be formed in a stacked structure of an oxide film and a nitride film.

On the other hand, the first insulating layer 214 is formed to a thickness that is completely filled between the word lines, and only partially filled between the select lines and between the select line and the word line. In detail, since the gap between the word lines is the smallest, the first insulating layer 214 is formed to be thick so that the word insulating layers 214 are filled with the first insulating layer 214. Since the gap between the select lines is widest, the first insulating layer 214 is formed thin. On the other hand, between the select line and the adjacent word line is narrower than the interval of the select lines and wider than the interval of the word lines. Accordingly, the first insulating layer 214 is formed thicker than the first insulating layer 214 between the select lines and the adjacent word line. However, the gap between the select line and the adjacent word line is not completely filled with the first insulating layer 214 as between word lines.

Referring to FIG. 2C, an etching process is performed such that a part of the drain 212d and the source 212s are exposed. In detail, since the first insulating layer 214 is formed to have a different thickness according to the distance between the select line and the word line, the target etching thickness is set based on the thickness of the first insulating layer 214 formed between the select lines. Carry out an etching process.

As a result, the first insulating layer 214 is formed in the form of a spacer only on opposite sidewalls of the select line while the first insulating layer 214 on the source 212s or the drain 212d is removed between the select lines. As a result, the source 212s and the drain 212d are exposed. Since the first insulating layer 214 is thickest and filled between the word lines, the first insulating layer 214 remains between the word lines even after the etching process. Meanwhile, since the first insulating layer 214 is formed thicker than the first insulating layer 214 between the select line and the adjacent word line, the semiconductor substrate 200 is etched only so that the semiconductor substrate 200 is not exposed. That is, only the thickness becomes thinner and remains along the surface of the select line, the word line and the semiconductor substrate.

Referring to FIG. 2D, a contact plug 216s and a conductive shielding line 216p are formed by filling a conductive material between the select lines and between the select line and the word line. Specifically, a conductive layer is formed on the semiconductor substrate 200 so as to fill between the source select lines SSL and between the select lines DSL and SSL and the word lines WL0 and WLn. Subsequently, a patterning process is performed such that the conductive layer remains only between the source select lines SSL and between the select lines DSL and SSL and the word lines WL0 and WLn. The patterning process can be performed by a chemical mechanical polishing process using the first insulating film 214 as a polishing stop film. In addition, the patterning process may be performed by applying a photoresist on the conductive layer, forming a photoresist pattern through an exposure and development process, and then etching the conductive layer by an etching process using the photoresist pattern. When the patterning process is carried out in the latter manner, the conductive layer can be patterned so that the upper width is wider than the lower width.

As a result, source contact plugs 216s are formed between the source select lines SSL. The source contact plug 216s may be formed in a line form between the source select line SSL. Similarly, a conductive shielding line 216p is formed between the source select line SSL and the word line WL0, and between the drain select line DSL and the word line WLn, and the conductive shielding line 216p is also formed. A line is formed between the line SSL and the word line WL0 and between the drain select line DSL and the word line WLn, respectively. The source contact plug 216s and the conductive shielding line 216p may be formed of a metal material such as tungsten or polysilicon.

Referring to FIG. 2E, the second insulating layer 218 is formed on the semiconductor substrate 200 including the conductive shielding line 216p. Subsequently, a contact hole is formed in the second insulating layer 218 to expose a portion of the source contact plug 216s, the conductive shielding line 216p, and the drain 212d. A drain contact plug 220d is formed in the contact hole above the drain 212d. In this case, an upper contact plug 220 is formed in the contact hole above the source contact plug 216s and the conductive shielding line 216p.

Subsequently, although not shown in the drawing, a conductive material layer is formed on the second insulating film 218 including the plugs 220 and 220d and then patterned to form bit lines (not shown) and metal wires (not shown). .

Although the conductive shielding line 216p is formed between the source select line SSL and the word line WL0 and between the drain select line DSL and the word line WLn, only one of the conductive shielding lines (216p) is formed. 216p) may be formed. That is, when it is desired to interfere with the movement of the hot carrier, the conductive shielding line 216p may be formed only between the source select line SSL and the word line WL0, and between the drain select line DSL and the word line WLn. When removing the capacitance coupling of the conductive shielding line 216p may be formed only between the drain select line DSL and the word line WLn.

Hereinafter, a method of preventing the threshold voltage of the memory cell adjacent to the select transistor from changing by applying a bias to the conductive shielding line 216p during the program operation to prevent the movement of the hot carrier or to remove the capacitance coupling.

3 is a circuit diagram illustrating a program method of a nonvolatile memory device according to a first embodiment of the present invention.

Referring to FIG. 3, a high program voltage Vpgm of 15V to 20V is applied to a selected word line (eg, WL1) during a program operation. In this case, the program voltage Vpgm is applied while increasing the level by the ISPP method, and since such a method is widely known, a detailed description thereof will be omitted. The pass voltage Vpass is applied to unselected word lines (eg, WL0, WL2 to WLn) so that the memory cells are turned on unconditionally. A bias of about 1.5 V is applied to the drain select line DSL, and a ground voltage (0 V) is applied to the source select line SSL. The power source voltage Vcc is applied to the common source line CSL. In addition, a ground voltage 0V is applied to the bit line BL0 connected to the string including the memory cell C1 to be programmed, and a bit line BL1 connected to the string including the memory cell C0 not to be programmed. ), A disturbance voltage (eg, Vcc) is applied to interrupt the program.

In addition, a voltage of -1V to -5V is applied to the conductive shielding lines Line1 and Line2 formed between the select line and the word line, and preferably a voltage of -3V. Although the conductive shielding lines Line1 and Line2 are formed between the drain select line DSL and the word line WLn and between the source select line SSL and the word line WL0, only one of the conductive lines is formed. This may be formed.

When the program operation is performed under the above conditions, since the electric field formed by the bias of the negative potential applied to the conductive line Line1 is transmitted to the semiconductor substrate, the electric field transmitted to the semiconductor substrate is generated at the junction region of the select transistor. The carrier (see Fig. 1) prevents the movement in the memory cell direction. That is, since the hot carrier is prevented from moving to the memory cell connected to the word line adjacent to the select line, the hot carrier is prevented from being injected into the floating gate. Therefore, it is possible to prevent the threshold voltage of the memory cell adjacent to the select line from changing.

4 is a circuit diagram illustrating a program method of a nonvolatile memory device according to a second exemplary embodiment of the present invention. FIG. 5 is a timing diagram illustrating a bias applied in the program method of FIG. 4.

4 and 5, the bit lines BL0 and BL1, the drain select line DSL, the source select line SSL, the word lines WL0 to WLn, and the common source line, as in the condition described with reference to FIG. 3. A bias for the program operation is applied to the CSL. In addition, a bias higher than the voltage applied to the drain select line DSL and lower than 5V is applied to the conductive shielding line Line1. Preferably, 3V is applied to the conductive shielding line Line1. A positive potential bias is applied to the conductive shielding line Line1 between the drain select line DSL and the word line WLn to minimize capacitance coupling between the drain select line DSL and the word line WLn. Accordingly, it is possible to prevent the voltage boosting level of the channel region from being lowered in order to prevent program operation.

When the voltage boosting level of the channel region decreases, the voltage difference between the word line and the channel region increases, so that the threshold voltage of the memory cells may change as the memory cell is abnormally programmed. However, as described above, the memory cell is prevented from applying a positive potential bias to the conductive shielding line Line1 between the drain select line DSL and the word line WLn to prevent the voltage boosting level of the channel region from being lowered. The threshold voltage of can be prevented from changing.

Meanwhile, the boosting level of the channel region may be lowered by the bias of the positive potential applied to the conductive shielding line Line1. For example, if the bias of the positive potential is applied later than the pass voltage Vpass applied to the unselected word lines, the boosting level of the channel region may be lowered because the channel region is prevented from being precharged. Therefore, it is desirable to adjust the timing of applying the positive potential bias to the conductive shielding line Line1. Specifically, it is preferable to apply a bias of positive potential to the conductive shielding line Line1 at least equal to or faster than the pass voltage Vpass applied to the unselected word lines.

In the above, a program method for preventing hot carriers from being injected into a floating gate of a memory cell and a program method for preventing a boosting level of a channel region from being lowered have been described. However, in order to prevent both of them at the same time, a positive potential bias is applied to the conductive shielding line Line1 between the drain select line DSL and the word line WLn, and the source select line SSL and the word line ( Negative potential bias may be applied to the conductive shielding line Line2 between WL0.

As described above, the present invention forms an electrode isolated from the semiconductor substrate between the select line and the word line and applies a bias during the program operation to prevent hot carriers from moving to the memory cell and at the same time between the word line and the select line. By minimizing the capacitance coupling, it is possible to prevent the threshold voltage of the memory cell from maintaining the erase state during the program operation.

Claims (23)

A plurality of select lines and a plurality of word lines formed on the semiconductor substrate; A contact plug formed between the select lines; And a conductive shielding line provided between the select line and the word line so as to be isolated from the semiconductor substrate. The method of claim 1, And a select line is a source select line. The method of claim 1, And the select line is a drain select line. The method of claim 1, The select line includes a source select line and a drain select line, and the conductive shielding line is provided to be isolated from the semiconductor substrate between the drain select line and the word line, and between the source select line and the word line, respectively. Nonvolatile Memory Device. The method of claim 1, And a junction region formed in the semiconductor substrate between the select lines and the word lines. The method of claim 1, And an insulating film for electrically insulating the conductive shielding line from the select lines and the word lines. Providing a semiconductor substrate on which a plurality of select lines and a plurality of word lines are formed; Forming a first insulating film on the semiconductor substrate including the select lines and the word lines; Removing the first insulating film between the select lines; Forming a conductive shielding line on the first insulating film between the select line and the word line; Forming a second insulating film on the semiconductor substrate including the conductive shielding line; Etching the second insulating layer to expose the semiconductor substrate and the conductive shielding line between the select line to form a contact hole; And And forming a contact plug in the contact hole. 8. The method of claim 7, before forming the first insulating film, And forming a junction region in the semiconductor substrate between the select lines and the word lines. The method of claim 7, wherein And the conductive shielding line is formed between a source select line and the word line among the select lines. The method of claim 7, wherein And a conductive shielding line is formed between the drain select line and the word line among the select lines. The method of claim 7, wherein The select line includes a source select line and a drain select line, and the conductive shielding line is formed on the first insulating layer between the drain select line and the word line, and between the source select line and the word line, respectively Method of manufacturing nonvolatile memory device. The method of claim 9, And forming a source contact plug on the semiconductor substrate between the source select lines when forming the conductive shielding line. Providing a nonvolatile memory device having a plurality of word lines and a plurality of select lines formed on a semiconductor substrate, and a conductive shielding line separated from the semiconductor substrate between the word lines and the select lines; And And performing a program operation while applying a negative potential bias to the conductive shielding line. The method of claim 13, And the select line comprises a source select line and a drain select line, and the conductive shielding line is provided between the source select line and the word line. The method of claim 13, And the select line comprises a source select line and a drain select line, and the conductive shielding line is provided between the drain select line and the word line. The method of claim 13, The select line includes a source select line and a drain select line, and the conductive shielding line is provided between the source select line and the word line and between the drain select line and the word line, respectively. . The method of claim 13, And a negative potential bias of -1V to -5V is applied to the conductive shielding line. Providing a nonvolatile memory device having a plurality of word lines and a plurality of select lines formed on a semiconductor substrate, and having a first conductive shielding line separated from the semiconductor substrate between the word lines and the select lines; And And performing a program operation while applying a positive potential bias to the conductive shielding line. The method of claim 18, And the positive potential bias is applied at the same timing or earlier than the bias applied to the word lines which are not selected during the program operation of the word lines. The method of claim 18, And the select line includes a source select line and a drain select line, and the first conductive shielding line is provided between the drain select line and the word line. The method of claim 20, And a positive potential bias higher than a bias applied to the drain select line and lower than 5V during the program operation is applied to the first conductive shielding line. The method of claim 20, A second conductive shielding line is further provided between the source select line and the word line, and a negative potential bias is applied to the second conductive shielding line during the program operation. The method of claim 22, And a negative potential bias of -1 V to -5 V is applied to the second conductive shielding line.

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