JP2002057213A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2002057213A
JP2002057213A JP2000241359A JP2000241359A JP2002057213A JP 2002057213 A JP2002057213 A JP 2002057213A JP 2000241359 A JP2000241359 A JP 2000241359A JP 2000241359 A JP2000241359 A JP 2000241359A JP 2002057213 A JP2002057213 A JP 2002057213A
Authority
JP
Japan
Prior art keywords
resist
etching
sulfuric acid
insulating film
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000241359A
Other languages
Japanese (ja)
Inventor
Hirobumi Kobayashi
博文 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2000241359A priority Critical patent/JP2002057213A/en
Publication of JP2002057213A publication Critical patent/JP2002057213A/en
Withdrawn legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device for improving adhesibility between a BPSG film and a resist, suppressing penetration of etchant into an interface and eliminating etching defects. SOLUTION: A BPSG film 2 as an inter-planarized insulating film is used on a metal wiring 11 in a Si wafer WF, as shown in Fig. (a). Then, although a system moves to a lithographic process, where a contact part with the metal wiring of an upper layer is formed. A cleaning process by a mixed liquid of sulfuric acid and hydrogen peroxide water, whose of specific gravity of sulfuric acid is 1.6 to 1.75 with respect to the PGSG film 12, as a pretreatment is inputted. Then, isotropic wet etching shown in Fig. (b) and dry etching as anisotropic etching shown in Fig.(c) are performed through the application of resist 13 and the formation of a resist pattern PTN.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置製造に
係り、特に平坦化層間絶縁膜表面へのレジスト塗布の前
処理に適用される半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device which is applied to a pre-treatment for applying a resist to the surface of a planarized interlayer insulating film.

【0002】[0002]

【従来の技術】近年、半導体装置の大規模集積化、デザ
インルールの縮小化が著しい。これに伴い、LSIプロ
セスにおいて金属配線の微細化が進められ、上層の金属
配線とのコンタクト部は狭まる一方である。このような
コンタクト部の形成にはリソグラフィ技術が不可欠であ
る。そこで、レジスト塗布工程におけるレジストの密着
性についても、微細パターン実現のため重要視されてい
る。
2. Description of the Related Art In recent years, large-scale integration of semiconductor devices and reduction of design rules have been remarkable. Along with this, the miniaturization of the metal wiring is promoted in the LSI process, and the contact portion with the upper metal wiring is being narrowed. A lithography technique is indispensable for forming such a contact portion. Therefore, the adhesion of the resist in the resist coating process is also regarded as important for realizing a fine pattern.

【0003】例えば、LSIプロセスでは、アルミニウ
ム配線など金属配線層間の平坦化層間絶縁膜としてBP
SG膜が用いられる。BPSG膜は、B(ボロン)とP
(リン)の酸化物であるB23 とP25 (P2
3 )を添加したSiO2 膜である。BPSG膜は、高温
で熱処理することで流動させ、下地段差を緩和し得るこ
とが知られている(リフロー法)。
For example, in an LSI process, BP is used as a planarizing interlayer insulating film between metal wiring layers such as aluminum wiring.
An SG film is used. BPSG film consists of B (boron) and P
B 2 O 3 and P 2 O 5 (P 2 O
This is a SiO 2 film to which 3 ) is added. It is known that the BPSG film can be made to flow by heat treatment at a high temperature, thereby reducing the level difference of the base (reflow method).

【0004】図4は、半導体ウェハ上に設けられる配線
のコンタクト部を形成する従来技術を示す断面図であ
る。金属配線41上に平坦化されたBPSG膜42が設
けられている。この下層の金属配線41に繋がるコンタ
クト部を形成する際、まず、BPSG膜42上にレジス
ト43を塗布し、レジストパターンPTNを形成する。
その後、レジストパターンPTNに従ってウェットエッ
チングにより等法的にエッチングする。その後、破線の
ようにさらに、レジストパターンPTNに従ってドライ
エッチングを施し異方性エッチングする。
FIG. 4 is a sectional view showing a conventional technique for forming a contact portion of a wiring provided on a semiconductor wafer. A flattened BPSG film 42 is provided on the metal wiring 41. When forming a contact portion connected to the lower metal wiring 41, first, a resist 43 is applied on the BPSG film 42 to form a resist pattern PTN.
After that, etching is performed in accordance with the resist pattern PTN by wet etching. Thereafter, as indicated by a broken line, dry etching is further performed according to the resist pattern PTN to perform anisotropic etching.

【0005】上記ウェットエッチングは、コンタクト部
の段差を予め緩和するために施される。仮にドライエッ
チングによる異方性エッチングだけを施すと、コンタク
ト部の段差が破線のように急峻になる。従って、後に形
成する図示しない上層の金属配線の被覆性が悪くなるの
で好ましくない。すなわち、ウェットエッチングは、上
層の金属配線(図示せず)の被覆性を考慮しての方策で
ある。
[0005] The wet etching is performed in order to relieve the step of the contact portion in advance. If only anisotropic etching by dry etching is performed, the step of the contact portion becomes steep as shown by the broken line. Therefore, the coverage of the upper metal wiring (not shown) formed later is deteriorated, which is not preferable. That is, wet etching is a measure taking into account the coverage of the upper metal wiring (not shown).

【0006】[0006]

【発明が解決しようとする課題】一般にBPSG膜とレ
ジストの密着性は必ずしも良いとはいえず、上記図4に
示すように、ウェットエッチングの際、BPSG膜42
とレジスト43の界面にエッチング液が染み込む。BP
SG膜等の酸化膜はウェットのエッチングレートが小さ
くそれに応じた時間がかかる。このため、上記界面への
染み込みの度合いも大きく、ウェット比(A/B)が大
きくなる。この結果、高密度なパターンにおけるコンタ
クト部の配列間では配線ショートなどの不具合が生じる
恐れがあり、エッチング不良として扱われることにな
る。
Generally, the adhesion between the BPSG film and the resist is not always good, and as shown in FIG.
The etchant permeates the interface between the substrate and the resist 43. BP
An oxide film such as an SG film has a small wet etching rate and takes a corresponding time. For this reason, the degree of penetration into the interface is large, and the wet ratio (A / B) is large. As a result, there is a possibility that a problem such as a wiring short-circuit may occur between the arrangement of the contact portions in the high-density pattern, and this is treated as an etching defect.

【0007】本発明は、上記のような事情を考慮してな
されたもので、BPSG膜とレジストの密着性を良くし
て、界面へのエッチング液の染み込みを抑え、エッチン
グ不良をなくする半導体装置の製造方法を提供しようと
するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor device that improves the adhesion between a BPSG film and a resist, suppresses the penetration of an etchant into an interface, and eliminates etching defects. It is intended to provide a method for producing the same.

【0008】[0008]

【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、半導体ウェハに設けられた平坦化層間絶
縁膜を選択的にエッチングして下層の配線層とのコンタ
クト部を形成する方法であって、前記平坦化層間絶縁膜
上にレジストを塗布しレジストパターンを形成する工程
と、前記レジストパターンに従って露出した前記平坦化
層間絶縁膜を部分的にウェットエッチングする等法性エ
ッチング工程と、前記等法性エッチング工程後に前記レ
ジストパターンに従って前記平坦化層間絶縁膜を下層の
配線層が露出するまでドライエッチングする異方性エッ
チング工程とを具備し、前記平坦化層間絶縁膜上へのレ
ジスト塗布前処理として硫酸比重が1.60より大き
く、1.75より小さい硫酸−過酸化水素水混合液によ
る洗浄を行うことを特徴とする。
A method of manufacturing a semiconductor device according to the present invention is a method of forming a contact portion with a lower wiring layer by selectively etching a planarized interlayer insulating film provided on a semiconductor wafer. A step of applying a resist on the planarized interlayer insulating film to form a resist pattern, and an isotropic etching step of partially wet-etching the planarized interlayer insulating film exposed according to the resist pattern, Anisotropically etching the flattened interlayer insulating film according to the resist pattern after the isotropic etching process until the underlying wiring layer is exposed, and applying a resist on the planarized interlayer insulating film. As a pretreatment, washing with a mixed solution of sulfuric acid and hydrogen peroxide having a specific gravity of sulfuric acid larger than 1.60 and smaller than 1.75 is required. And butterflies.

【0009】本発明に係る半導体装置の製造方法によれ
ば、上記比重の範囲の硫酸−過酸化水素水混合液による
洗浄によって、平坦化層間絶縁膜上の汚染物質を除去し
得ると共に平坦化層間絶縁膜の親水性を向上させる。こ
れによりレジストの密着性を向上させる。
According to the method of manufacturing a semiconductor device of the present invention, it is possible to remove contaminants on the planarized interlayer insulating film and clean the planarized interlayer insulating film by cleaning with a mixed solution of sulfuric acid and hydrogen peroxide having the above specific gravity. Improves the hydrophilicity of the insulating film. This improves the adhesion of the resist.

【0010】[0010]

【発明の実施の形態】図1(a)〜(c)は、それぞれ
本発明の一実施形態に係る半導体装置の製造方法の要部
であり、ウェハに対する洗浄工程及びリソグラフィ工程
の一部を示す断面図である。
1 (a) to 1 (c) are main parts of a method of manufacturing a semiconductor device according to an embodiment of the present invention, and show a part of a cleaning step and a lithography step for a wafer. It is sectional drawing.

【0011】図1(a)に示すように、SiウェハWF
において、図示しない集積回路形成のためのトランジス
タ素子等、さらにそれらに応じた少なくとも1層以上の
金属配線11の形成がなされる。この金属配線11上に
平坦化層間絶縁膜としてBPSG膜12が用いられる。
BPSG膜12は、高温で熱処理することで流動させ、
下地段差を緩和する(リフロー法)。
As shown in FIG. 1A, a Si wafer WF
In step (1), a transistor element for forming an integrated circuit (not shown) and the like, and at least one or more metal wirings 11 corresponding thereto are formed. On this metal wiring 11, a BPSG film 12 is used as a planarizing interlayer insulating film.
The BPSG film 12 is made to flow by heat treatment at a high temperature,
Relieve the step on the base (reflow method).

【0012】次に、上層の金属配線とのコンタクト部を
形成するリソグラフィ工程に移行するが、その前処理と
してBPSG膜12の洗浄工程を入れる。このBPSG
膜12の洗浄には、硫酸−過酸化水素水混合液(SP
M:sulfuric acid /hydrogenperoxide /water mix
)による洗浄、いわゆるSPM洗浄が適当である。こ
れにより、BPSG膜12上の汚染物質(有機物及び金
属汚染)が除去される。
Next, the process shifts to a lithography process for forming a contact portion with a metal wiring of an upper layer, and a cleaning process of the BPSG film 12 is provided as a pretreatment. This BPSG
For cleaning the membrane 12, a mixed solution of sulfuric acid and hydrogen peroxide (SP)
M: sulfuric acid / hydrogenperoxide / water mix
), So-called SPM cleaning is suitable. Thus, contaminants (organic matter and metal contamination) on the BPSG film 12 are removed.

【0013】上記BPSG膜12に対するSPM洗浄を
利用し、係る本発明では、レジストの密着性を向上させ
る。SPM洗浄において、硫酸比重が1.60より大き
く、1.75より小さい硫酸−過酸化水素水混合液を用
いるのである。処理温度については120℃程度であ
り、処理時間は10分程度である。これにより、BPS
G膜12上の汚染物質(有機物及び金属汚染)が除去さ
れるのはもとより、BPSG膜12上の平坦化層間絶縁
膜の親水性を向上させる。この結果、レジストの密着性
が大幅に向上する。
In the present invention, the SPM cleaning of the BPSG film 12 is used to improve the adhesiveness of the resist. In the SPM cleaning, a mixed solution of sulfuric acid and hydrogen peroxide having a specific gravity of sulfuric acid larger than 1.60 and smaller than 1.75 is used. The processing temperature is about 120 ° C., and the processing time is about 10 minutes. With this, BPS
In addition to removing contaminants (organic matter and metal contamination) on the G film 12, the hydrophilicity of the planarized interlayer insulating film on the BPSG film 12 is improved. As a result, the adhesion of the resist is greatly improved.

【0014】次に、図1(b)に示すように、レジスト
13の塗布及びレジストパターンPTNの形成を経る。
その後、レジストパターンPTNに従って、露出したB
PSG膜12を部分的にウェットエッチする。BPSG
膜12とレジスト13の密着性は良好に保たれるので、
界面におけるエッチング液の染み込みはかなり抑えられ
る。これにより、図中A/Bで表せるウェット比は大き
くなり過ぎることなく、微細パターンを保証する等法性
エッチングが達成できる。
Next, as shown in FIG. 1B, application of a resist 13 and formation of a resist pattern PTN are performed.
Then, according to the resist pattern PTN, the exposed B
The PSG film 12 is partially wet-etched. BPSG
Since the adhesion between the film 12 and the resist 13 is kept good,
The penetration of the etching solution at the interface is considerably suppressed. As a result, the wet ratio represented by A / B in the figure does not become too large, and the isotropic etching that guarantees a fine pattern can be achieved.

【0015】次に、図1(c)に示すように、等法性エ
ッチング工程後、同じレジストパターンPTNに従っ
て、上記BPSG膜12を下層の配線層11が露出する
までドライエッチにより異方性エッチングする。
Next, as shown in FIG. 1C, after the isotropic etching step, the BPSG film 12 is anisotropically etched by dry etching according to the same resist pattern PTN until the underlying wiring layer 11 is exposed. I do.

【0016】図2は、上記図1のBPSG膜12に対す
るSPM洗浄において、硫酸比重の違いに影響するレジ
ストに従ったウェット比を表す図である。図3は、図2
におけるSPM洗浄液による処理バッチ数に対する硫酸
比重推移を示す特性図である。
FIG. 2 is a view showing the wet ratio according to the resist which affects the difference in the specific gravity of sulfuric acid in the SPM cleaning of the BPSG film 12 shown in FIG. FIG. 3 shows FIG.
FIG. 6 is a characteristic diagram showing a change in specific gravity of sulfuric acid with respect to the number of batches treated with the SPM cleaning liquid in FIG.

【0017】図2において、SPM洗浄液交換前の96
回目、100回目洗浄処理平均と、SPM洗浄液交換後
の1回目、8回目洗浄処理平均とで、その後パターン形
成したレジストに従ったウェットエッチングを比較す
る。図示しないウェハ面内の任意位置5箇所におけるウ
ェット比(すなわち図1(b)に示すA/B)の検査結
果は、前者のSPM洗浄液交換前の方が良好である。ま
た、この結果は、ウェットエッチング液の交換前、交換
後にほとんど影響されないことがわかる。
In FIG. 2, 96 before the SPM cleaning liquid is replaced.
The average of the first and eighth cleaning treatments and the average of the first and eighth cleaning treatments after the replacement of the SPM cleaning liquid are compared with each other after the wet etching according to the patterned resist. The inspection results of the wet ratio (that is, A / B shown in FIG. 1B) at five arbitrary positions in the wafer surface (not shown) are better before the former SPM cleaning liquid replacement. Further, it can be seen that this result is hardly affected before and after the replacement of the wet etching solution.

【0018】図3に示すように、上記SPM洗浄液は、
処理数が多くなるにつれて硫酸がウェハ表面に付いて持
ち出される分、また、過酸化水素水の補充もあって、徐
々に硫酸比重が小さくなる。斜線は過酸化水素水を補充
した場合の誤差範囲を示している。少なくともバッチ数
60を過ぎたあたりから硫酸比重1.75を下回り、液
交換までに硫酸比重は1.65を下回る場合もある。
As shown in FIG. 3, the SPM cleaning solution is
As the number of treatments increases, the specific gravity of sulfuric acid gradually decreases due to the amount of sulfuric acid carried on the wafer surface and the replenishment of hydrogen peroxide. The hatched lines indicate the error range when hydrogen peroxide solution is replenished. The specific gravity of sulfuric acid may fall below 1.75 at least after the number of batches exceeds 60, and may fall below 1.65 by the time of liquid exchange.

【0019】すなわち、上記図2のSPM洗浄液交換前
の96回目、100回目洗浄処理は、少なくとも硫酸比
重1.75より小さいSPM洗浄液での処理といえる。
また、SPM洗浄液交換後の1回目、8回目洗浄処理
は、硫酸比重1.75より大きいSPM洗浄液での処理
といえる。
In other words, the 96th and 100th cleaning processes before the replacement of the SPM cleaning solution shown in FIG. 2 can be said to be at least processes using an SPM cleaning solution having a sulfuric acid specific gravity smaller than 1.75.
Further, the first and eighth cleaning processes after the replacement of the SPM cleaning solution can be said to be processes using an SPM cleaning solution having a sulfuric acid specific gravity of more than 1.75.

【0020】上記図2、図3から、SPM洗浄液交換後
あまり処理数が嵩んでいないときの方がウェット比の劣
化がみられること、及び洗浄効果を考慮すると、上述の
ように、SPM洗浄においては硫酸比重が1.60より
大きく、1.75より小さい硫酸−過酸化水素水混合液
を用いることが好ましい。さらに好ましくは硫酸比重を
1.7前後に保つSPM洗浄を実施すればよい。このよ
うな硫酸比重を有する硫酸−過酸化水素水混合液による
洗浄により、汚染物質除去と共にBPSG膜のレジスト
の密着性を向上させ、ウェット比を良好にする。
From FIG. 2 and FIG. 3, when the number of treatments is not so large after the replacement of the SPM cleaning liquid, the deterioration of the wet ratio is observed, and the cleaning effect is taken into consideration. It is preferable to use a mixed solution of sulfuric acid and hydrogen peroxide having a specific gravity of sulfuric acid larger than 1.60 and smaller than 1.75. More preferably, SPM cleaning in which the specific gravity of sulfuric acid is maintained at around 1.7 may be performed. By cleaning with a mixed solution of sulfuric acid and hydrogen peroxide having such a specific gravity of sulfuric acid, contaminants are removed and the adhesion of the resist of the BPSG film is improved, and the wet ratio is improved.

【0021】上記実施形態の方法によれば、SPM洗浄
によって、BPSG膜の親水性を高め、レジストとの密
着性を向上させることができる。これにより、レジスト
パターンによるウェットエッチングの際、BPSG膜と
レジストの界面へのエッチング液の染み込みを大幅に低
減できる。
According to the method of the above embodiment, the hydrophilicity of the BPSG film can be increased by SPM cleaning, and the adhesion to the resist can be improved. Thereby, at the time of wet etching using the resist pattern, the penetration of the etching solution into the interface between the BPSG film and the resist can be significantly reduced.

【0022】一般にBPSG膜はウェットのエッチング
レートが小さくそれに応じた時間がかかる。上記界面へ
の染み込みを抑えることによって、予定した等方性エッ
チングが達成され、高密度なパターンにおけるコンタク
ト部の配列間にも対応できる段差緩和部が形成できる。
In general, the BPSG film has a low wet etching rate and takes a corresponding time. By suppressing the permeation into the interface, a predetermined isotropic etching is achieved, and a step relief portion that can cope with the arrangement of the contact portions in the high-density pattern can be formed.

【0023】[0023]

【発明の効果】以上説明したように、本発明に係る半導
体装置の製造方法によれば、BPSG膜の洗浄工程とし
て、少なくとも硫酸比重が1.60より大きく、1.7
5より小さい硫酸−過酸化水素水混合液を用いる。これ
により、汚染物質除去と共にBPSG膜のレジストの密
着性を向上させ、ウェット比を良好にする。この結果、
BPSG膜とレジストの界面へのエッチング液の染み込
みを抑え、エッチング不良をなくし、高密度な微細パタ
ーンが実現できる高信頼性の半導体装置の製造方法を提
供することができる。
As described above, according to the method of manufacturing a semiconductor device according to the present invention, at least the specific gravity of sulfuric acid is larger than 1.60 and 1.7 in the step of cleaning the BPSG film.
Use a sulfuric acid-hydrogen peroxide mixture less than 5. As a result, the contaminant is removed, the adhesion of the BPSG film to the resist is improved, and the wet ratio is improved. As a result,
It is possible to provide a method for manufacturing a highly reliable semiconductor device capable of suppressing penetration of an etching solution into an interface between a BPSG film and a resist, eliminating etching defects, and realizing a high-density fine pattern.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(c)は、それぞれ本発明の一実施形
態に係る半導体装置の製造方法の要部であり、ウェハに
対する洗浄工程及びリソグラフィ工程の一部を示す断面
図である。
FIGS. 1A to 1C are cross-sectional views each showing a main part of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and showing a part of a cleaning step and a lithography step for a wafer.

【図2】図1のBPSG膜に対するSPM洗浄におい
て、硫酸比重の違いに影響するレジストに従ったウェッ
ト比を表す図である。
FIG. 2 is a diagram illustrating a wet ratio according to a resist which affects a difference in specific gravity of sulfuric acid in SPM cleaning of the BPSG film of FIG. 1;

【図3】図1におけるSPM洗浄液による処理バッチ数
に対する硫酸比重推移を示す特性図である。
FIG. 3 is a characteristic diagram showing a change in specific gravity of sulfuric acid with respect to the number of batches treated with the SPM cleaning solution in FIG. 1;

【図4】ウェハ上に設けられる配線のコンタクト部を形
成する従来技術を示す断面図である。
FIG. 4 is a cross-sectional view showing a conventional technique for forming a contact portion of a wiring provided on a wafer.

【符号の説明】[Explanation of symbols]

11,41…金属配線 12,42…BPSG膜 13,43…レジスト PTN…レジストパターン WF…Siウェハ 11, 41: metal wiring 12, 42: BPSG film 13, 43: resist PTN: resist pattern WF: Si wafer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウェハの上方に設けられた平坦化
層間絶縁膜を選択的にエッチングして下層の配線層との
コンタクト部を形成する方法であって、 前記平坦化層間絶縁膜上にレジストを塗布しレジストパ
ターンを形成する工程と、 前記レジストパターンに従って露出した前記平坦化層間
絶縁膜を部分的にウェットエッチングする等法性エッチ
ング工程と、 前記等法性エッチング工程後に前記レジストパターンに
従って前記平坦化層間絶縁膜を下層の配線層が露出する
までドライエッチングする異方性エッチング工程と、を
具備し、 前記平坦化層間絶縁膜上へのレジスト塗布前処理として
硫酸比重が1.60より大きく、1.75より小さい硫
酸−過酸化水素水混合液による洗浄を行うことを特徴と
する半導体装置の製造方法。
1. A method for selectively etching a planarized interlayer insulating film provided above a semiconductor wafer to form a contact portion with a lower wiring layer, wherein a resist is formed on the planarized interlayer insulating film. Applying a resist pattern to form a resist pattern; an isotropic etching step of partially wet-etching the planarized interlayer insulating film exposed according to the resist pattern; and the flattening according to the resist pattern after the isotropic etching step. Anisotropic etching step of dry-etching the patterned interlayer insulating film until a lower wiring layer is exposed, wherein the specific gravity of sulfuric acid is greater than 1.60 as a pre-treatment of resist application on the planarized interlayer insulating film; A method for manufacturing a semiconductor device, comprising performing cleaning with a mixed solution of sulfuric acid and hydrogen peroxide smaller than 1.75.
JP2000241359A 2000-08-09 2000-08-09 Method for manufacturing semiconductor device Withdrawn JP2002057213A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000241359A JP2002057213A (en) 2000-08-09 2000-08-09 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000241359A JP2002057213A (en) 2000-08-09 2000-08-09 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2002057213A true JP2002057213A (en) 2002-02-22

Family

ID=18732556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000241359A Withdrawn JP2002057213A (en) 2000-08-09 2000-08-09 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2002057213A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100895826B1 (en) * 2002-12-03 2009-05-06 주식회사 하이닉스반도체 Method for forming contact hole in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100895826B1 (en) * 2002-12-03 2009-05-06 주식회사 하이닉스반도체 Method for forming contact hole in semiconductor device

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