JP2002049354A - Self-luminescence device and electric appliance using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise the aperture ratio in a pixel than in the conventional practice in a self-luminescence device. SOLUTION: In this device, source signal lines connected to a source line driving circuit 102 and current supplying lines connected to a power source 106 are connected respectively to a changeover circuit 105. Moreover, the changeover circuit 105 and a pixel part 101 are connected by wirings. Furthermore, in these wirings, the same wiring can be used as a source signal line or a current supplying line by a changeover signal to be inputted to the changeover circuit 105. As a result, since the number of wirings in the pixel part can be reduced, the aperture ratio can be raised.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a self-luminous device. The present invention particularly relates to an active matrix type self-luminous device having a thin film transistor (TFT) formed on an insulator.

[0002]

2. Description of the Related Art In recent years, the technology for forming a TFT on a substrate has been greatly advanced, and its application to an active matrix display device (self-luminous device) has been promoted. In particular, a TFT using a polysilicon film has higher field-effect mobility (also referred to as mobility) than a TFT using a conventional amorphous silicon film, and thus can operate at high speed. Therefore, the control of the pixel, which has been conventionally performed by the drive circuit outside the substrate, can be performed by the drive circuit formed on the same substrate as the pixel.

[0003] Such an active matrix type self-luminous device can be manufactured by manufacturing various circuits and elements on the same substrate to reduce the manufacturing cost, downsize the electro-optical device, increase the yield, and reduce the throughput. Various advantages are obtained.

Further, an active matrix self-luminous device (EL) having an EL element as a self-luminous element
Display) research is active. The EL display is an organic EL display (OELD: Organic EL D)
isplay) or organic light emitting diode (O
LEDs are also called Organic Light Emitting Diodes.

[0005] The EL display is a self-luminous type. E
The L element has a structure in which an EL layer is sandwiched between a pair of electrodes (anode and cathode), and the EL layer usually has a laminated structure. A typical example is a laminated structure of “hole transport layer / light emitting layer / electron transport layer” proposed by Tang et al. Of Kodak Eastman Company. This structure has a very high luminous efficiency, and EL which is currently being researched and developed
Most displays adopt this structure.

In addition, a hole injection layer / hole transport layer / light-emitting layer / electron transport layer, or a hole injection layer / hole transport layer / light-emitting layer / electron transport layer / electron injection layer may be provided on the anode. A structure in which layers are sequentially stacked may be used. The light emitting layer may be doped with a fluorescent dye or the like.

In this specification, all layers provided between a cathode and an anode are collectively called an EL layer. Specifically, E
L (Electro Luminescence: a layer containing an organic EL material from which luminescence generated by applying an electric field) is obtained. The above-described hole injection layer, hole transport layer, light emitting layer, electron transport layer, electron injection All the layers and the like are included in the EL layer.

The luminescence obtained from the organic EL material includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state. . For the self-luminous device of the present invention, it is possible to use an EL element containing either organic EL material.

Then, a predetermined voltage is applied to the EL layer having the above-mentioned structure from a pair of electrodes, whereby recombination of carriers occurs in the light emitting layer to emit light. In this specification, a light emitting element formed by an anode, an EL layer, and a cathode is referred to as E.
It is called an L element.

In an EL display, a plurality of pixels are provided in a matrix, and each of the plurality of pixels has a thin film transistor (TFT) and an EL element. FIG.
The enlarged view of the pixel of the EL display is shown in FIG. Pixel 170
0 is a switching TFT 1701, a current control TF
T1702, EL element 1703, source signal line 170
4, a gate signal line 1705, a current supply line 1706, and a capacitor 1707.

A gate electrode of the switching TFT 1701 is connected to a gate signal line 1705. One of a source region and a drain region of the switching TFT 1701 is a source signal line, and the other is a current control TF.
It is connected to the gate electrode of T1702. The source region of the current controlling TFT 1702 is connected to the current supply line 1706,
The drain region is connected to the anode or the cathode of the EL element 1703.

The anode of the EL element 1703 is a current control TF.
When connected to the drain region of T1702, the anode of the EL element 1703 serves as a pixel electrode and the cathode serves as a counter electrode.
Conversely, the cathode of the EL element 1703 is
2 is connected to the drain region, the EL element 170
The anode 3 is a counter electrode and the cathode is a pixel electrode.

In this specification, the difference between the potential of the pixel electrode and the potential of the counter electrode is referred to as an EL drive voltage.
An L drive voltage is applied to the EL layer.

Note that the capacitor 1707 need not always be provided. When it is provided, as shown in FIG. 17, it is provided so as to be connected to the current control TFT 1702 and the current supply line 1706.

The potential (power supply potential) of the current supply line 1706 is kept constant. Further, the potential of the opposite electrode of the EL element 1703 is also kept constant. The potential of the counter electrode has a potential difference from the power supply potential to such an extent that the EL element emits light when the power supply potential is applied to the pixel electrode of the EL element.

The switching TFT 1701 is turned on by a selection signal input to the gate signal line 1705. Note that in this specification, turning on a TFT means that the drain current of the TFT is 0 or more.

When the switching TFT 1701 is turned on, a video signal input from the source signal line 1704 is input to the gate electrode of the current controlling TFT 1702 via the switching TFT 1701. Note that inputting a signal to the gate electrode of the current control TFT 1702 via the switching TFT 1701 means that a signal is input to the gate electrode of the current control TFT 1702 through the active layer of the switching TFT 1701.

The amount of current flowing through the channel forming region of the current controlling TFT 1702 is determined by a gate voltage Vg which is a potential difference between the gate electrode and the source region of the current controlling TFT 1702.
s. Therefore, the potential applied to the pixel electrode of the EL element 1703 is controlled by the current control TFT 1702.
Is determined by the height of the potential of the video signal input to the gate electrode of the video signal. The luminance of the EL element (the luminance of light emitted from the EL element) is controlled by the level of the potential applied to the pixel electrode. That is, the luminance of the EL element 1703 is controlled by the potential of the video signal input to the source signal line 1704, and gradation display is performed.

[0019]

In recent years, the pixel size has been miniaturized, and a higher definition image has been demanded. With the miniaturization of the pixel size, the formation area of the TFT and the wiring occupying one pixel is increased, and the pixel aperture ratio is reduced.

Therefore, in order to obtain a high aperture ratio of each pixel within a specified pixel size, it is essential to efficiently lay out circuit elements required for a pixel circuit configuration.

As described above, in order to realize an active matrix type self-luminous device having a pixel aperture ratio, an unprecedented new pixel configuration is required.

The present invention satisfies such a demand, and uses a pixel having a configuration in which the same wiring is used for the source signal line and the current supply line, and the pixel having a high aperture ratio is realized. It is an object to provide a light emitting device.

[0023]

According to the present invention, the source signal line and the current supply line connected to the pixel portion are shared by the same wiring to increase the aperture ratio in the pixel.

The source signal line connected to the source signal line drive circuit and the current supply line connected to the power supply are connected to the switching circuit, respectively. The switching circuit and the pixel portion are connected by wiring. The wiring becomes a source signal line or a current supply line according to a switching signal input to the switching circuit.

[0025]

FIG. 1 is a block diagram of a self-luminous device according to the present invention. Note that there is no particular limitation on the TFT used in the self-luminous device used in the present invention, and a TFT having a structure such as a planar type or an inverted staggered type may be used. further,
The driving circuit of the self-luminous device used in the present invention may be a combination of known circuits.

In the present invention, known elements can be used for the element structure and EL material of the EL element included in the self-luminous device. On the other hand, the configuration of the present invention can be used for a known liquid crystal device.

In the self-luminous device of FIG. 1, a pixel portion 101, a source signal line driving circuit 102 and a gate signal line driving circuit 103 arranged around the pixel portion are formed by TFTs formed on a substrate. Reference numeral 104 denotes a time-division grayscale data signal generation circuit (SPC; Serial-to-Parallel Conversio).
n Circuit).

The source signal line driving circuit 102 basically has a shift register 102a, a latch (A) 102b, and a latch (B) 102c. In addition, it has a buffer (not shown).

Although the self-luminous device of this embodiment has only one source signal line driving circuit, two source signal line driving circuits may be provided so as to sandwich the pixel portion from above and below.

In the present invention, the source signal line driving circuit 102 and the gate signal line driving circuit 103
01 may be provided on the substrate provided with the FPC or TAB provided on the IC chip.
May be connected to the pixel portion 101 via the.

In the source signal line driving circuit 102, a clock signal (CLK) and a start pulse (SP) are input to the shift register 102a. The shift register 102a sequentially generates a timing signal based on the clock signal (CLK) and the start pulse (SP), and sequentially supplies the timing signal to a subsequent circuit through a buffer or the like (not shown).

The timing signal from the shift register 102a is buffer-amplified by a buffer or the like. The wiring to which the timing signal is supplied has a large load capacitance (parasitic capacitance) because many circuits or elements are connected. This buffer is provided to prevent "dulling" of the rise or fall of the timing signal caused by the large load capacitance.

The timing signal buffer-amplified by the buffer is supplied to the latch (A) 102b. The latch (A) 102b outputs an n-bit digital data signal (n bi
t digital data signals). When the timing signal is input, the latch (A) 102b sequentially captures and holds the n-bit digital data signal supplied from the time-division grayscale data signal generation circuit 104.

When a digital data signal is taken into the latch (A) 102b, the digital data signal may be sequentially inputted to a plurality of stages of latches of the latch (A) 102b. However, the present invention is not limited to this configuration. The latches of a plurality of stages included in the latch (A) 102b may be divided into several groups, and a so-called divided drive in which digital data signals are input simultaneously in parallel for each group may be performed. The number of groups at this time is called a division number. For example, when the latch is divided into groups for every four stages, it is referred to as divided drive in four divisions.

The time until the writing of the digital data signal to the latches of all the stages in the latch (A) 102b is completed is called a line period. That is,
The time interval from the start of writing the digital data signal to the latch of the leftmost stage in the latch (A) 102b to the end of writing the digital data signal to the latch of the rightmost stage is a line. Period. Actually, the line period may include a period obtained by adding the horizontal retrace period to the line period.

When one line period ends, the latch (B)
A latch signal (LatchSignal) is supplied to 102c. At this moment, the digital data signal written and held in the latch (A) 102b is
c, and is written to and held by the latches of all the stages of the latch (B) 102c.

The digital data signal is latched (B) 102
The digital data signal supplied from the time-division grayscale data signal generation circuit 104 is sequentially written into the latch (A) 102b which has finished sending the data to the latch (A) 102b based on the timing signal from the shift register 102a.

During the second one line period, the digital data signal written and held in the latch (B) 102b is input to the source signal line. Note that, in the present invention, the source signal line is connected to the switching circuit 105.

The switching circuit 105 includes a power supply 10
The current supply line connected to 6 is also connected. A wiring that electrically connects the switching circuit 105 and the pixel electrode is switched to a source signal line or a current supply line by a switching signal input to the switching circuit 105.

Further, the switching signal is generated when the adjacent wiring
This is a signal that is alternately switched to be a source signal line and a current supply line. That is, neither of the adjacent wirings becomes a source signal line or a current supply line.

When the wiring connected to the switching TFT of the pixel is connected to the source signal line, the pixel having the switching TFT emits light by a digital data signal input from the source signal line driving circuit. Alternatively, no light is emitted. However, the pixel switching TFT
Is connected to the current supply line, the pixel having the switching TFT does not function.

On the other hand, when the wiring connected to the current control TFT of the pixel is connected to the current supply line, the pixel having the current control TFT receives the digital data input from the source signal line drive circuit. Light emission or non-light emission is indicated by a signal. However, when the wiring connected to the current control TFT of the pixel is connected to the source signal line, the pixel having the current control TFT does not function.

On the other hand, the gate signal line driving circuit 103 has a shift register and a buffer (neither is shown). In some cases, the gate signal line driving circuit 10
3 may have a level shifter in addition to the shift register and the buffer.

In the gate signal line driving circuit 103, a timing signal from a shift register (not shown) is supplied to a buffer (not shown) and supplied to a corresponding gate signal line (also referred to as a scanning line). For the gate signal line,
Since the gate electrodes of the pixel TFTs for one line are connected and all the pixel TFTs for one line must be turned on at the same time, a buffer capable of flowing a large current is used.

In the time-division grayscale data signal generating circuit 104, an analog or digital video signal (a signal containing image information) performs a digital data signal (Digital Data Signals) for performing a time-division grayscale.
And input to the latch (A) 102b. The time-division grayscale data signal generating circuit 104 is also a circuit that generates timing pulses and the like necessary for performing time-division grayscale display.

This time-division gradation data signal generating circuit 104
May be provided outside the self-luminous device of the present invention. In that case, the digital data signal formed there is input to the self-luminous device of the present invention. In this case, an electric appliance (self-luminous device) having the self-luminous device of the present invention as a display device includes the self-luminous device of the present invention and the time-division grayscale data signal generation circuit as separate components.

The time-division grayscale data signal generating circuit 10
4 may be mounted on the light emitting device of the present invention in the form of an IC chip or the like. In that case, a digital data signal formed by the IC chip is input to the self-luminous device of the present invention. In this case, an electric appliance having the self-luminous device of the present invention as a display device includes, as a component, the self-luminous device of the present invention mounted with an IC chip including a time-division grayscale data signal generation circuit.

Finally, the time division gray scale data signal generating circuit 104 is connected to the pixel portion 101 and the source signal line driving circuit 1.
02, T on the same substrate as the gate signal line driving circuit 103
It can be formed using FT. In this case, if a video signal containing image information is input to the self-luminous device, all can be processed on the substrate. In this case, the time division gray scale data signal generation circuit may be formed by a TFT using a polysilicon film as an active layer. In this case, in the electric appliance having the self-luminous device of the present invention as a display device, the time-division grayscale data signal generation circuit is built in the self-luminous device itself, so that the electric appliance can be downsized. is there.

The configuration of the source signal line driving circuit 102 described in this embodiment is an example of the embodiment and does not limit the configuration of the present invention.

Next, the structure of the pixel portion in the self-luminous device of the present invention will be described. Note that the pixel portion 10 shown in FIG.
1 is shown in FIG. 4 (A). FIG. 4A shows the source signal lines (S1 to Sx) or the current supply lines (V1 to Vx).
x) and the gate signal lines (G1 to Px)
Gy) is provided in the pixel portion 101.

Here, the source signal lines (S1 to Sx)
, Current supply lines (V1 to Vx), and gate signal lines (G1
To Gy) are the pixels 107.
In the pixel portion 101, a plurality of pixels 107 are arranged in a matrix.

A switching circuit 105 is provided outside the pixel unit 101 shown in FIG. Wirings (P1 to Px) connected to each pixel from the switching circuit 105 become source signal lines (S1 to Sx) or current supply lines (V1 to Vx).
Is determined by the switching signal (C) input to the switching circuit 105.

FIG. 4B shows an example of the wiring (Px-1) and Px in FIG.
5 shows a switching signal input to the switch 5 and a state in which the wiring (P1 to Px) is alternately switched between the source signal lines (S1 to Sx) and the current supply lines (V1 to Vx) every frame period by the switching signal. It is a thing. Further, in this specification, a pixel column having the wiring (Px-1) and the wiring Px is referred to as an (x-1) -th pixel column, and a wiring (Px-2)
The pixel column having the pixel line and the wiring (Px-1) is referred to as an (x-2) th pixel column.

However, what is shown here is an example of the switching signal in the first to third frame periods, and does not limit the present invention.

In this embodiment, the switching TF is used.
Either the drain region or the source region of T is electrically connected to the source signal line and the source region of the current controlling TFT of the adjacent pixel. Specifically, (x−
2) When one of the drain region and the source region of the switching TFT in the pixel in the column is electrically connected to the source signal line, the source of the switching TFT in the pixel in the (x-1) th column is One of the region and the drain region is electrically connected to the current supply line of the pixel in the (x−2) th column.

Next, FIG. 5 is an enlarged view of a region 108 including the pixel 107 and the switching circuit 105. In FIG.
Reference numeral 501 denotes a switching TFT. The gate electrode of the switching TFT 501 is connected to a gate signal line G (G1 to G1).
Gx). Switching TFT 501
One of the source region and the drain region has a source signal line S
(S1 to Sx) or the current supply line V (V1 to Vx)
The other is connected to the gate electrode of the current control TFT 502 and the capacitor 503 of each pixel. However, when the switching TFT 501 is connected to the current supply line by the switching circuit 105, this pixel does not function.

The capacitor 503 is a switching TFT.
When the TFT 501 is in a non-selection state (OFF state), it is provided to hold a gate voltage (a potential difference between a gate electrode and a source region) of the current control TFT 502. Although the configuration in which the capacitor 503 is provided is shown here, the present invention is not limited to this configuration, and a configuration in which the capacitor 503 is not provided may be employed.

One of a source region and a drain region of the current control TFT 502 has a current supply line V (V1 to V
x) or the source signal line S (S1 to Sx), and the other is connected to the EL element 504. Note that the current supply line V is connected to the capacitor 503.

However, when the current control TFT 502 is connected to the source signal line S (S1 to Sx) by the switching circuit 105, this pixel does not function.

The EL element 504 comprises an EL layer provided between the anode and the cathode. The anode is a current control TFT 50
2 is connected to the source region or the drain region, the anode serves as a pixel electrode, and the cathode serves as a counter electrode. Conversely, when the cathode is connected to the source region or the drain region of the current controlling TFT 502, the cathode serves as a pixel electrode and the anode serves as a counter electrode.

A counter potential is applied to a counter electrode of the EL element 504. The power supply potential is applied to the current supply line V. The power supply potential and the counter potential are provided to the self-luminous device of the present invention by a power supply provided by an external IC or the like.

As the switching TFT 501 and the current control TFT 502, either an n-channel TFT or a p-channel TFT can be used. Note that when the source region or the drain region of the current control TFT 502 is connected to the anode of the EL element 504, the current control TFT 502 is preferably a p-channel TFT. When the source region or the drain region of the current control TFT 502 is connected to the cathode of the EL element 504, the current control TFT 502 is an n-channel type TF.
Desirably T.

The switching TFT 501 and the current control TFT 502 may have a multi-gate structure such as a double gate structure or a triple gate structure instead of a single gate structure.

Next, a method for driving the self-luminous device of the present invention having the above-described configuration will be described with reference to FIG. FIG. 6 shows the display period of the pixels on the first line when the horizontal axis represents time (Time) and the vertical axis represents the position of the gate signal line (V-Scan).

Here, the source signal line S is connected to the source region of the switching TFT by the switching circuit 105.
(S1 to Sx) are connected, and a current supply line V (V1 to Vx) is connected to one of the current control TFTs.

First, the power supply potential of the current supply line becomes the same as the potential of the counter electrode of the EL element. And the gate signal line G1
, A gate signal is input from the gate signal line driving circuit. As a result, the switching TFTs 5 of all the pixels (pixels of the first line) connected to the gate signal line G1
01 is turned on.

At the same time, the first bit digital video signal is inputted from the source signal line driving circuit to the source signal lines (S1 to Sx) electrically connected to the source signal line driving circuit switched by the switching circuit 105. Is done. The digital video signal is a switching TFT 501.
Through the gate electrode of the current control TFT 502.

Next, at the same time when the input of the gate signal to G1 is completed, the gate signal is similarly input to the gate signal line G2. Then, the switching TFTs 501 of all the pixels connected to the gate signal line G2 are turned on, and the source signal line (S1) electrically connected to the source signal line driving circuit by the switching circuit to the pixel on the second line. ~
The digital video signal of the first bit from Sx) is input.

Then, all the gate signal lines (G1 to G1)
Gx) is input with a gate signal. The period from when all the gate signal lines (G1 to Gx) are selected and when the first bit digital video signal is input to the pixels on all the lines is the writing period Ta1.

When the writing period Ta1 ends, the display period Tr1 starts next. In the display period Tr1, the power supply potential of the current supply line becomes a potential having a potential difference with the counter electrode to such an extent that the EL element emits light when the power supply potential is applied to the pixel electrode of the EL element.

In this embodiment, when the digital video signal has information of “0”, the current control TFT 5
02 is off. Therefore, the EL element 504
No power supply potential is applied to the pixel electrodes. as a result,
The EL element 504 of the pixel to which the digital video signal having the information “0” is input does not emit light.

On the other hand, when the information has the information “1”, the current control TFT 502 is in the ON state. Therefore, a power supply potential is applied to the pixel electrode of the EL element 504. As a result, the EL element 504 of the pixel to which the digital video signal having the information “1” is input emits light.

As described above, in the display period Tr1, the EL element 504 emits light or emits no light, and all the pixels perform display. A period during which the pixel performs display is called a display period Tr. In particular, a display period started when the first bit digital video signal is input to the pixel is referred to as Tr1. FIG.
For simplicity, only the display period of the pixels on the first line will be described. The timing at which the display periods of all the lines are started is the same.

When the display period Tr1 ends, the writing period Ta
The power supply potential of the current supply line becomes equal to the potential of the counter electrode of the EL element. Then, as in the case of the writing period Ta1, all the gate signal lines are sequentially selected, and the second bit digital video signal is input to all the pixels. A period until the digital video signal of the second bit is completely input to the pixels of all lines is referred to as a writing period Ta2.

When the writing period Ta2 ends, the display period Tr
2, the power supply potential of the current supply line becomes a potential having a potential difference from the counter electrode to such an extent that the EL element emits light when the power supply potential is applied to the pixel electrode of the EL element. Then, all the pixels perform display.

The above operation is repeated until the n-th bit digital video signal is input to the pixel, and the writing period Ta and the display period Tr appear repeatedly. When all the display periods (Tr1 to Trn) end, one image can be displayed. In the driving method of the present invention, a period during which one image is displayed is referred to as one frame period (F).
When one frame period ends, the next frame period starts. Then, the writing period Ta1 appears again, and the above operation is repeated.

In the self-luminous device of the present invention, it is preferable to provide 120 or more frame periods per second.
The frequency is more preferably from 120 to 240 Hz. In other words, it is desirable that one frame period is 1/240 to 1/120 s. When the number of images displayed in one second is less than 120, flickering of the images may start to be noticeable.

In the present invention, the sum of the lengths of all the writing periods is shorter than one frame period, and the length ratio of the display periods is Tr1: Tr2: Tr3:...: Tr (n−
1): Trn = 2 ⁰ : 2 ¹ : 2 ² : ...: 2 ^(n-2) : 2 ^(n-1)
It is necessary that A desired gradation display out of 2 ⁿ gradations can be performed by the combination of the display periods.

By calculating the sum of the lengths of the display periods in which the EL elements emit light during one frame period, the displayed gray scale of the pixel in the frame period is determined. For example, assuming that when the pixel emits light in all display periods when n = 8, the luminance is 100%, and when the pixel emits light in Tr1 and Tr2, 1% luminance can be expressed.
When Tr5 and Tr8 are selected, 60% luminance can be expressed.

The display periods Tr1 to Trn may appear in any order. For example, during one frame period, the display periods can appear in the order of Tr1, Tr5, Tr2,... Next to Tr1.

Here, the height of the power supply potential of the current supply line is changed between the writing period and the display period, but the present invention is not limited to this. The power supply potential and the potential of the counter electrode may always have a potential difference such that the EL element emits light when the power supply potential is applied to the pixel electrode of the EL element. In that case, the EL element can emit light even in the writing period. Therefore, the gray scale displayed by the pixel in the frame period is determined by the total length of the writing period and the display period in which the EL element emits light in one frame period. In this case, the ratio of the sum of the lengths of the writing period and the display period corresponding to the digital video signal of each bit is (T
a1 + Tr1): (Ta2 + Tr2): (Ta3 + Tr)
3): ...: (Ta (n-1) + Tr (n-1)): (T
an + Trn) = 2 ⁰ : 2 ¹ : 2 ² : ...: 2 ^(n-2) : 2
It is necessary to be ^(n-1) .

The top structure of the pixel portion described in the embodiment mode of the present invention will be described with reference to FIG.

In FIG. 7, the wiring indicated by 701 is
This is a gate wiring for electrically connecting the gate electrode of the switching TFT 702. Switching TFT
A source region 702 a of the 702 is connected to a source line 703, and a drain region 702 b is a drain line 704
Connected to. Further, the drain wiring 704 is electrically connected to the gate electrode 705a of the current controlling TFT 705. The source region 70 of the current controlling TFT 705
5b is electrically connected to the current supply line 706, and the drain region 705c is electrically connected to the drain wiring 707.

At this time, a storage capacitor is formed in a region 708. The storage capacitor 708 is connected to the current supply line 7
06, an insulating film (not shown) in the same layer as the gate insulating film, and a gate electrode 705.
It is formed between the wiring forming a. Note that the semiconductor film 709 includes a switching TFT and a current control TFT.
In the present invention, the semiconductor film is formed separately from the semiconductor film formed when the semiconductor device is manufactured. That is, as shown in FIG. 7, the separation semiconductor film 709 includes the source region 702a and the drain region 702b of the switching TFT 702 and the source region 702b of the current control TFT 705.
The active layer 05b and the active layer for forming the drain region 705c are formed in isolation. Note that in a region denoted by reference numeral 708, the separation semiconductor film 709 overlaps with the gate electrode 705a with the gate insulating film interposed therebetween. At this time, 60% or more of the separation semiconductor film 709 overlaps with a wiring forming the gate electrode 705a. It has become. Further, 60% or more of the separation semiconductor film 709 overlaps the current supply line 706 with the first interlayer insulating film interposed therebetween. Further, the capacitance formed by the gate electrode 705a, the same layer (not shown) as the first interlayer insulating film, and the current supply line 706 can also be used as the storage capacitance.

In the present embodiment, the pixel structure shown in FIG. 7 does not limit the present invention in any way, but is only a preferable example. Switching TFT, Current control TF
The position where the T or the storage capacitor is formed may be appropriately designed by a practitioner.

[0086]

[Embodiment 1] Here, the configuration of a switching circuit used in the present invention will be described with reference to FIGS. In FIGS. 2 and 3, the reference numerals used in FIG.

In FIG. 2, the switching circuit 105 has two transmission gates distinguished by a transmission gate 1 (201) and a transmission gate 2 (202). The transmission gate 1 (201) is connected to the source signal line (S) 20
3 and the transmission gate 2 (2
02) is connected to the current supply line 204.

The switching signal line 205 is connected to the transmission gate 1 (201) and the transmission gate 2 (202). The switching signal from the switching signal generating circuit 206 and the switching signal are inverted by the inverter 207. The circuit is configured such that the inversion switching signal is input to the transmission gate 1 (201) and the transmission gate 2 (202), respectively.

The switching signal input from the switching signal generation circuit 206 has information of “0” or “1”, and one of the switching signals of “0” and “1” is Hi and one of the switching signals is “Hi”. Is a signal having a voltage of Lo.

In this embodiment, when the switching signal has information of "0", the transmission gate 1 (201) is turned on and the transmission gate 2 (202) as shown in FIG. Is turned off. Therefore, transmission gate 1 (201)
Is turned on, a signal from the source signal line driving circuit 102 is input to the transmission gate 1 (201), and the pixel portion 101 is transmitted from the transmission gate 1 (201) and the transmission gate 2 (202).
The source signal line driving circuit 10
2 is input. At this time, the wiring 208 serves as a source signal line.

At this time, when the wiring 208 serving as a source signal line is connected to the switching TFT 301a of the pixel 107a as shown in FIG. 3A, the pixel 107a using the wiring 208 as a source signal line E in
The L element 302a emits light or does not emit light according to a digital video signal input from the source signal line driver circuit 102.

As described above, the source signal line driving circuit 102
In the present specification, a pixel in which the EL element emits light or does not emit light in response to a digital video signal input from the device will be referred to as a selected (state) pixel.

However, when the wiring 208 serving as a source signal line is connected to the current controlling TFT 303b of the pixel 107b as shown in FIG.
No signal is input to 07b, and the pixel 107b is in a non-selected state.

Conversely, when the switching signal has information of "1", the transmission gate 1 (201) is turned off and the transmission gate 2 (202) is turned on as shown in FIG. State. Accordingly, the transmission gate 2 (202) is turned on, and a signal input from the power supply 106 through the current supply line 205 is transmitted.
From 2), a signal from the power supply 106 is input to the wiring 208 connected to the pixel portion 101. That is, the wiring 208 functions as a current supply line.

At this time, the wiring 2 serving as a current supply line
08 is connected to the current controlling TFT in the pixel 107c as shown in FIG.
EL element 30 in the pixel 107c with the current supply line
2c indicates light emission or non-light emission according to the digital video signal input from the source signal line driving circuit 102. That is, at this time, the pixel 107c is selected.

However, the wiring 2 serving as a current supply line
08 is connected to the switching TFT 301d of the pixel 107d as shown in FIG. 3B, no signal is input to the pixel 107d, that is, the pixel 107d
d is in a non-selected state.

When a certain pixel is selected, all the pixel columns connected to the same wiring in the vertical direction toward the page are selected. When a certain pixel is not selected, it means that all the pixel columns connected to the same wiring in the vertical direction toward the page are not selected.

It is preferable that the pixel column selected for each frame is switched so that the source signal lines and the current supply lines are electrically alternated.

Therefore, for example, the first, third, and fifth odd-numbered pixel columns are selected from the left in the first frame,
In the second frame, the even, second, fourth, and sixth pixel rows can be selected from the left.

[Embodiment 2] Next, a description will be given of the structure of a pixel portion and a method of driving the same when a self-luminous device having a structure of a pixel portion different from that described above is used in the present invention. Where n
A case in which 2 ⁿ gray scale display is performed by using a bit digital data signal will be described.

FIG. 8 shows an example of a block diagram of the self-luminous device of the present invention. The self-luminous device in FIG. 8 includes a pixel portion 801 using a TFT formed over a substrate, a source signal line driving circuit 802 arranged around the pixel portion, a writing gate signal line driving circuit (a first gate signal line driving circuit). Circuit) 80
3. An erase gate signal line drive circuit (second gate signal line drive circuit) 804 is provided. In this embodiment, the self-luminous device has one source signal line drive circuit, but in the present invention, there may be two source signal line drive circuits.

In the present invention, the source signal line driving circuit 802, the writing gate signal line driving circuit 803 or the erasing gate signal line driving circuit 804 includes the pixel portion 801.
May be provided on a substrate provided with, or may be provided on an IC chip and connected to the pixel portion 801 via FPC or TAB.

The source signal line driving circuit 802 basically has a shift register 802a, a latch (A) 802b, and a latch (B) 802c.

In the source signal line driver circuit 802, a clock signal (CLK) and a start pulse (SP) are input to the shift register 802a. The shift register 802a sequentially generates a timing signal based on the clock signal (CLK) and the start pulse (SP), and sequentially supplies the timing signal to a subsequent circuit through a buffer or the like (not shown).

The timing signal from shift register 802a is buffer-amplified by a buffer or the like. The wiring to which the timing signal is supplied has a large load capacitance (parasitic capacitance) because many circuits or elements are connected. This buffer is provided to prevent "dulling" of the rise or fall of the timing signal caused by the large load capacitance.

The timing signal buffer-amplified by the buffer is supplied to the latch (A) 802b. The latch (A) 802b outputs an n-bit digital data signal (n bi
t digital data signals). When the timing signal is input, the latch (A) 802b sequentially captures and holds the n-bit digital data signal supplied from the time-division grayscale data signal generation circuit 805.

When the digital data signal is taken into the latch (A) 802b, the digital data signal may be sequentially input to the latches of a plurality of stages included in the latch (A) 802b. However, the present invention is not limited to this configuration. The latches of a plurality of stages included in the latch (A) 802b may be divided into several groups, and a so-called division drive in which digital data signals are input simultaneously in parallel for each group may be performed. The number of groups at this time is called a division number. For example, when the latch is divided into groups for every four stages, it is referred to as divided drive in four divisions.

The time until the digital data signal is completely written into the latches of all the stages of the latch (A) 802b is called a line period. That is, a time interval from the time when the writing of the digital data signal to the latch of the leftmost stage in the latch (A) 802b starts to the time when the writing of the digital data signal to the latch of the rightmost stage ends. Is a line period.
Actually, the line period may include a period obtained by adding the horizontal retrace period to the line period.

When one line period ends, the latch (B)
A latch signal (LatchSignal) is supplied to 802c. At this moment, the digital data signal written and held in the latch (A) 802b is changed to the latch (B) 802b.
c, and is written to and held in the latches of all the stages of the latch (B) 802c.

The digital data signal is latched (B) 802
The digital data signal supplied from the time-division grayscale data signal generation circuit 805 is sequentially written again into the latch (A) 802b which has finished sending the data to c, based on the timing signal from the shift register 802a.

During this second one line period, the digital data signal written and held in the latch (B) 802b is input to the source signal line.

The source signal line is connected to the switching circuit 80.
6 are electrically connected. On the other hand, a current supply line (not shown) connected to the power supply 807 is also electrically connected to the switching circuit 806 in the same manner. The pixel signal of the pixel portion 801 is selected from the source signal line and the current supply line by a switching signal for controlling the switching circuit 806.
Pixel is electrically connected.

In FIG. 8, a pixel 808 of the pixel portion 801 is provided.
A region including the switching circuit 806 is indicated by a region 809.

On the other hand, the write gate signal side drive circuit 8
03 and the erasing gate signal line driving circuit 804 each have a shift register and a buffer (both not shown). In some cases, the write gate signal line drive circuit 803 and the erase gate signal line drive circuit 80
4 may have a level shifter in addition to the shift register and the buffer.

In the write gate signal line drive circuit 803 and the erase gate signal line drive circuit 804, a timing signal from a shift register (not shown) is supplied to a buffer (not shown), and the corresponding gate signal line ( Scan lines). The gate signal lines are connected to the gate electrodes of pixel TFTs for one line, and all pixel TFTs for one line must be turned on at the same time. Used.

In the time division gradation data signal generation circuit 805, a digital data signal (Digital Data Signals) for performing time division gradation of an analog or digital video signal (a signal containing image information) is provided.
And input to the latch (A) 802b. The time-division grayscale data signal generation circuit 805 is a circuit that generates a timing pulse and the like necessary for performing time-division grayscale display.

This time-division gradation data signal generation circuit 805
May be provided outside the self-luminous device of the present invention. In that case, the digital data signal formed there is input to the self-luminous device of the present invention. In this case, an electric appliance (self-luminous device) having the self-luminous device of the present invention as a display includes the self-luminous device of the present invention and the time-division grayscale data signal generation circuit as separate components.

The time-division gradation data signal generation circuit 80
5 may be mounted on the light emitting device of the present invention in the form of an IC chip or the like. In that case, a digital data signal formed by the IC chip is input to the self-luminous device of the present invention. In this case, an electric appliance having the self-luminous device of the present invention as a display includes the self-luminous device of the present invention mounted with an IC chip including a time-division gradation data signal generation circuit as a component.

Finally, the time division gray scale data signal generating circuit 805 is connected to the pixel portion 801 and the source signal line driving circuit 8.
02, the writing gate signal line driving circuit 803 and the erasing gate signal line driving circuit 804 can be formed over the same substrate using a TFT. In this case, if a video signal containing image information is input to the self-luminous device, all can be processed on the substrate. In this case, the time division gray scale data signal generation circuit may be formed by a TFT using a polysilicon film as an active layer. In this case, in the electric appliance having the self-luminous device of the present invention as a display, the time-division grayscale data signal generation circuit is built in the self-luminous device itself, so that the electric appliance can be downsized. .

FIG. 9 is an enlarged view of the pixel portion 801. The source signal lines (S1 to Sx) connected to the latch (B) 802c of the source signal line driving circuit 802, and the current supply lines (V1 to V1) connected to a power supply external to the light emitting device via the FPC.
Vx), a write gate signal line (first gate signal line) connected to the write gate signal line drive circuit 803
(Ga1-Gay), erase gate signal line drive circuit 80
The erase gate signal line (second gate signal line) (Ge1 to Gey) connected to the pixel unit 4 is provided in the pixel unit 801.

The wiring (P1 to Px) connecting the switching circuit 806 and the pixel is connected to the source signal lines (S1 to S1) by the switching circuit 806 provided outside the pixel portion 801.
x) or the current supply line (V1 to Vx).

A source signal line (S1 to Sx), a current supply line (V1 to Vx), and a write gate signal line (Ga1
To Gay) and the gate signal line for erasing (Ge1 to Gey)
Is a pixel 901. In the pixel portion 801, a plurality of pixels 901 are arranged in a matrix.

Region 80 including pixel 901 and switching circuit
9 is shown in FIG. In FIG. 10, 1001
Is a switching TFT. Switching TFT
The gate electrode 1001 is connected to the write gate signal line Ga.
(1007). Switching TFT
One of a source region and a drain region 1001 is connected to the source signal line S, and the other is connected to the gate electrode of the current control TFT 1002, the capacitor 1003 of each pixel, and the source or drain region of the erasing TFT 1004. . However, the switching TFT1
When 001 is connected to the current supply line by the switching circuit 806, this pixel does not function.

The capacitor 1003 is a switching TF
When T1001 is in a non-selection state (OFF state), it is provided to hold the gate voltage of the current control TFT 1002. In this embodiment, the configuration in which the capacitor 1003 is provided is shown, but the present invention is not limited to this configuration.
A configuration without the capacitor 1003 may be employed.

One of a source region and a drain region of the current control TFT 1002 is connected to the current supply line V, and the other is connected to the EL element 1005. The current supply line V is connected to the capacitor 1003. However, when the current control TFT 1002 is connected to the source signal line S (S1 to Sx) by the switching circuit 806, this pixel does not function.

The other of the source and drain regions of the erasing TFT 1004 that is not connected to the source or drain region of the switching TFT 1001 is connected to the current supply line V. And erasing TF
The gate electrode of T1003 is connected to the erase gate signal line Ge.
(1008).

The EL element 1005 includes an anode and a cathode, and an EL layer provided between the anode and the cathode. When the anode is connected to the source region or the drain region of the current controlling TFT 1002, the anode serves as a pixel electrode and the cathode serves as a counter electrode. Conversely, when the cathode is connected to the source region or the drain region of the current controlling TFT 1002, the cathode serves as a pixel electrode and the anode serves as a counter electrode.

An opposing potential is applied to the opposing electrode of the EL element 1005. The power supply potential is applied to the current supply line V. The potential difference between the opposite potential and the power supply potential is always kept at such a level that the EL element emits light when the power supply potential is applied to the pixel electrode. The power supply potential and the counter potential are provided to the self-luminous device of the present invention by a power supply provided by an external IC or the like. Note that a power supply that provides a counter potential is particularly referred to as a counter power supply 1006 in this specification.

In a typical light emitting device at present, a light emitting amount per pixel emitting area is 200 cd / m ² ,
A current per area of the pixel portion is required to be about several mA / cm ² . Therefore, particularly when the screen size becomes large, it becomes difficult to control the level of the potential given from the power supply provided in the IC with the switch. In the present invention,
The power supply potential and the counter potential are always kept constant, and it is not necessary to control the height of the potential given from the power supply provided in the IC with a switch, which is useful for realizing a panel with a larger screen size.

In the present invention, the height of the power supply potential is such that the current control TFT 1002 is turned off when the power supply potential is applied to the gate electrode of the current control TFT 1002. It is necessary.

As the switching TFT 1001, the current controlling TFT 1002, and the erasing TFT 1004, either an n-channel TFT or a p-channel TFT can be used. Also, the switching TFT 1001,
The current controlling TFT 1002 and the erasing TFT 1004 are:
Instead of a single gate structure, a multi-gate structure such as a double gate structure or a triple gate structure may be employed.

Next, a method of driving the self-luminous device using the present invention shown in FIGS. 8 to 10 will be described with reference to FIG.

First, the write gate signal line driving circuit 803 sends the write gate signal line Ga1 (100
7), the write gate signal line Ga1 (100) is generated by the write gate signal (first gate signal).
7) is selected. Then, the write gate signal line Ga
The switching TFTs 1001 of all the pixels (pixels on the first line) connected to 1 are turned on.

At the same time, the source signal line driving circuit 80
2 is input to the source signal lines S1 to Sx, the first bit digital video signal is
1 is input to the gate electrode of the current control TFT 1002. Note that in this specification, a digital video signal is supplied to a current control TFT through a switching TFT 1001.
It is assumed that the input to the gate electrode of the FT 1002 is a digital video signal input to the pixel.

The digital video signal is "0" or "1"
The digital video signals of “0” and “1” are signals having one Hi voltage and one Lo voltage.

In this embodiment, when the digital video signal has information of “0”, the current control TFT 10
02 is off. Therefore, no power supply potential is applied to the pixel electrode of the EL element 1005. As a result, the EL element 1005 included in the pixel to which the digital video signal having the information “0” is input does not emit light.

Conversely, when the digital video signal has information of “1”, the current control TFT 1002 is turned on. Thus, a power supply potential is applied to the pixel electrode of the EL element 1005. As a result, the EL element 1 included in the pixel to which the digital video signal having the information “1” is input is provided.
005 emits light.

In this embodiment, when the digital video signal has information of “0”, the current control TFT 10
02 is in an off state, and the current control TFT 1002 is in an on state when it has information of “1”, but the present invention is not limited to this configuration. If the digital video signal has information of “0”, the current control TFT 10
02 may be turned on and the current control TFT 1002 may be turned off if it has the information of “1”.

As described above, at the same time when the digital video signal is input to the pixels on the first line, the EL element 1005 emits light or does not emit light, and the pixels on the first line perform display. A period during which the pixel performs display is called a display period Tr. In particular, a display period started when the first bit digital video signal is input to the pixel is referred to as Tr1. The timing at which the display period of each line is started has a time difference.

Next, when the selection of the write gate signal line Ga1 is completed, the write gate signal line Ga2 is selected by the write gate signal. Then, the switching TFTs 1001 of all the pixels connected to the write gate signal line Ga2 are turned on, and the first bit digital video signals are input to the pixels of the second line from the source signal lines S1 to Sx. .

Then, in order, all the write gate signal lines Ga (Ga1 to Gay) are selected, and 1 is applied to all the pixels.
The digital video signal of the bit is input. The period until the digital video signal of the first bit is input to all the pixels is the writing period Ta1.

On the other hand, before the digital video signal of the first bit is input to all the pixels, in other words, before the writing period Ta1 ends, in parallel with the input of the digital video signal of the first bit to the pixels, Erasing gate signal line Ge1 (1008) from erasing gate signal line driving circuit 804
, The erase gate signal line Ge1 (1008) is selected by the erase gate signal (second gate signal) input to the gate. Then, the erase gate signal line Ge1 (100
All pixels connected to 8) (pixels on the first line)
Erasing TFT 1004 is turned on. The power supply potentials of the current supply lines V1 to Vx are changed to the erasing TFT 1004.
To the gate electrode of the current controlling TFT 1002 via

When the power supply potential is applied to the gate electrode of the current control TFT 1002, the potential of the gate electrode and the source region of the current control TFT 1002 become the same, and the gate voltage becomes 0V. Therefore, the current control TFT 1002 is turned off. That is, the write gate signal line Ga
The digital video signal held by the gate electrode of the current control TFT since 1 (1007) is selected by the write gate signal is erased by applying a power supply potential to the gate electrode of the current control TFT. . Therefore, the power supply potential is not supplied to the pixel electrode of the EL element 1005, and the EL elements 1005 included in the pixels in the first line are all in a non-light emitting state, and the pixels in the first line do not perform display.

A period during which the pixel does not perform display is defined as a non-display period T.
Called d. In the pixels of the first line, the display period Tr1 ends at the same time when the erasing gate signal line Ge1 (1008) is selected, and the non-display period Td1 starts. Similarly to the display period, the start timing of the non-display period of each line has a time difference.

Then, the erase gate signal line Ge1 (100
When the selection in 8) is completed, the erasing gate signal line Ge2 is selected, and the erasing TFTs 100 of all the pixels (pixels on the second line) connected to the erasing gate signal line Ge2.
4 is turned on. Then, the power supply potentials of the current supply lines V1 to Vx are supplied to the current control T
It is provided to the gate electrode of FT1002. When the power supply potential is applied to the gate electrode of the current control TFT 1002,
The current control TFT 1002 is turned off. Therefore, the power supply potential is not applied to the pixel electrode of the EL element 1005. As a result, all the EL elements of the pixels on the second line are in a non-light emitting state, and the pixels on the second line are in a non-display state in which no display is performed.

Then, the erase gate signal is sequentially input to all the erase gate signal lines. An erasing period Te1 is a period from when all the erasing gate signal lines Ge1 to Gey are selected and when the first bit digital video signal held by all the pixels is erased.

On the other hand, before the digital video signal of the first bit held by all the pixels is erased, in other words, before the end of the erasing period Te1, 1
In parallel with the erasure of the digital video signal of the bit, the write gate signal line G is again generated by the write gate signal.
a1 is selected. Then, in the pixels on the first line, 2
The digital video signal of the bit is input. As a result, the pixels on the first line perform display again, so that the non-display period Td1 ends and the display period Tr2 starts.

Similarly, all the write gate signal lines are sequentially selected, and the digital video signal of the second bit is input to all the pixels. A period until the input of the second bit digital video signal to all the pixels is called a writing period Ta2.

On the other hand, before the digital video signal of the second bit is input to all the pixels, in other words, before the end of the writing period Ta2, in parallel with the input of the digital video signal of the second bit to the pixels. Then, the erase gate signal line Ge2 is selected by the erase gate signal. Accordingly, the EL elements of the pixels on the first line are all in a non-light emitting state, and the pixels on the first line do not perform display.
Accordingly, the display period Tr2 ends in the pixels on the first line, and the non-display period Td2 is set.

Then, in order, all the erase gate signal lines G
e1 to Gey are selected and all pixels hold 2
The digital video signal of the bit is deleted. The period until the second bit digital video signal held by all the pixels is erased is the erase period Te2.

The above operation is repeatedly performed until the m-bit digital video signal is input to the pixel, and the display period Tr and the non-display period Td appear repeatedly. The display period Tr1 is a period from the start of the write period Ta1 to the start of the erase period Te1. The non-display period Td1 is a period from the start of the erase period Te1 to the start of the next appearing write period (in this case, the write period Ta2). Then, the display period Tr2,
Tr3,..., Tr (m-1) and non-display periods Td2, T
Also, d3,..., Td (m-1) are the write periods Ta1, Ta2, respectively, similarly to the display period Tr1 and the non-display period Td1.
.., Tam and the erasing periods Te1, Te2,.
The period is determined by Te (m-1).

For the sake of simplicity, FIG.
Although the case of n-2 is shown as an example, it goes without saying that the present invention is not limited to this. In the present invention, m is 1
To n can be arbitrarily selected.

When a digital video signal of the m [n-2 (hereinafter, parentheses indicate m = n-2)] bit is input to the pixels of the first line, the pixels of the first line are displayed. During the period Trm [n-2], display is performed. Until the next bit of digital video signal is input, m [n-
2] The digital video signal of the bit is held in the pixel.

Then, when the (m + 1) [n-1] th bit digital video signal is input to the pixels on the first line, the m [n-2] th bit digital video signal held in the pixels is received. Is rewritten to the (m + 1) [n-1] th bit digital video signal. Then, the pixels on the first line enter a display period Tr (m + 1) [n-1], and display is performed. The (m + 1) [n-1] th bit digital video signal is held in the pixel until the next bit digital video signal is input.

The above operation is repeated until the n-th bit digital video signal is input to the pixel. The display period Trm [n−2],.
am [n-2],..., Tan, from the start to the start of the next appearing write period.

When all the display periods Tr1 to Trn are completed, one image can be displayed. In the present invention, a period during which one image is displayed is called one frame period (F).

After the end of one frame period, the write gate signal line Ga1 is selected again by the write gate signal. Then, the digital video signal of the first bit is input to the pixel, and the pixel of the first line again becomes the display period Tr1. Then, the above operation is repeated again.

It is preferable that the self-luminous device provide 60 or more frame periods per second. When the number of images displayed in one second is less than 60, flickering of the images may start to be noticeable.

In the present invention, it is important that the sum of the lengths in all the writing periods is shorter than one frame period. In addition, the length of the display period is Tr1: Tr2: Tr
3 ::: Tr (n-1): Trn = 2 ⁰ : 2 ¹ : 2 ² :
…: 2 ⁽ⁿ⁻²⁾ : 2 ⁽ⁿ⁻¹⁾ . A desired gradation display out of 2 ⁿ gradations can be performed by the combination of the display periods.

By calculating the sum of the lengths of the display periods in which the EL elements emit light during one frame period, the displayed gradation of the pixel in the frame period is determined. For example, assuming that when the pixel emits light in all display periods when n = 8, the luminance is 100%, and when the pixel emits light in Tr1 and Tr2, 1% luminance can be expressed.
When Tr5 and Tr8 are selected, 60% luminance can be expressed.

It is important that the writing period Tam in which the m-bit digital video signal is written to the pixel is shorter than the length of the display period Trm. Therefore, the value of the bit number m is such that the writing period Tam is the display period T among 1 to n.
The value must be shorter than the length of rm.

The display periods Tr1 to Trn may appear in any order. For example, during one frame period, the display periods can appear in the order of Tr1, Tr5, Tr2,... Next to Tr1. However, the order in which the display periods Tr1 to Trn do not overlap each other is more preferable. Also, the erasing periods Te1 to Ten are
A non-overlapping order is more preferred.

[0163] According to the present invention the above structure, even if there is some variation in the I _{D S} -V _GS characteristic by TFT, suppress variations in the amount of current output when applied gate voltage equal to the current controlling TFT be able to. Therefore I
The variation of _DS -V _GS characteristic, the amount of light emitted from the EL element even if a signal is input with the same voltage it is possible to avoid a situation that greatly different in neighboring pixels.

In this embodiment, the first current control TFT and the second current control TFT are used as current control TFTs.
And are provided in parallel. Thus, the heat generated by the current flowing through the active layer of the current control TFT can be efficiently radiated, and deterioration of the current control TFT can be suppressed. Further, it is possible to suppress variations in drain current caused by variations in characteristics such as the threshold value and mobility of the current control TFT.

In this embodiment, a non-light emitting period in which no display is performed can be provided. In the case of the conventional analog drive, when an all white image is displayed on the self-light-emitting device, the EL
The device emits light, which causes deterioration of the EL layer earlier. In this embodiment, since a non-light emitting period can be provided, deterioration of the EL layer can be suppressed to some extent.

In this embodiment, the display period and the writing period partially overlap. In other words, the pixels can be displayed even in the writing period. Therefore, the ratio (duty ratio) of the total length of the display periods in one frame period is not determined only by the length of the writing period.

In this embodiment, a capacitor is provided to hold the voltage applied to the gate electrode of the current controlling TFT. However, the capacitor may be omitted. When the current controlling TFT has an LDD region provided so as to overlap the gate electrode via the gate insulating film, a parasitic capacitance generally called a gate capacitance is formed in the overlapping region. This gate capacitance may be positively used as a capacitor for holding a voltage applied to the gate electrode of the current control TFT.

Since the capacitance value of the gate capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

Next, FIG. 12 shows a top view of a pixel of the self-luminous device in this embodiment, and the description will be made with reference to FIG.
Note that FIG. 9, FIG. 10, and FIG. 12 use the same reference numerals and may be referred to each other.

In FIG. 12, a source signal line (S),
Current supply line (V) and write gate signal line (Ga)
And a region 901 having one erase gate signal line (Ge) and one erase gate signal line (Ge) are pixels. The pixel 901 includes a switching TFT 1001 and a current controlling TFT 1002
And an erasing TFT 1004.

The switching TFT 1001 has an active layer 1001a and a gate electrode 1001b which is a part of a write gate signal line (Ga). The current control TFT 1002 has an active layer 1002a and a gate electrode 1002b which is a part of the gate wiring 1201. The erasing TFT 1004 includes an active layer 1004a,
And a gate electrode 1004b which is a part of the write gate signal line (Ge).

Active layer 1 of switching TFT 1001
One of a source region and a drain region included in 001a is a source signal line, and the other is a connection wiring 1202.
Is connected to the gate wiring 1201 through the gate. 1
Reference numeral 202 denotes a source wiring or a drain wiring depending on the potential of a signal input to the source signal line (S).

The active layer 1004a of the erasing TFT 1004
Are connected to a source signal line and the other is connected to a gate wiring 1201 via a connection wiring 1203. Note that reference numeral 1202 denotes a source wiring or a drain wiring depending on the power supply potential of the current supply line (V).

Active layer 100 of current controlling TFT 1002
The source region and the drain region of 2a are connected to a current supply line (V) and a drain wiring 1204, respectively. The drain wiring 1204 is connected to the pixel electrode 1205.

The capacitance wiring 1206 is formed of a semiconductor film. The capacitor 1003 is formed between the capacitor wiring 1206 electrically connected to the current supply line (V), an insulating film (not shown) in the same layer as the gate insulating film, and the gate wiring 1201. Further, the capacitance formed by the gate wiring 1201, the same layer (not shown) as the first interlayer insulating film, and the current supply line (V) can also be used as a capacitor.

A bank having an opening 1207 is formed on the pixel electrode 1205 by etching the organic resin film. Although not shown, the pixel electrode 120
The EL layer and the counter electrode are sequentially stacked on the layer 5. Pixel electrode 1
205 and the EL layer are in contact with each other at the opening 1207 of the bank, and the EL layer emits light only in a portion sandwiched between the counter electrode and the pixel electrode.

Note that the top view of the pixel portion in the self-luminous device of the present invention is not limited to the configuration shown in FIG. This embodiment can be implemented in combination with the configuration of the first embodiment.

[Embodiment 3] Next, a case where the self-luminous device of the present invention is driven by an analog system will be described with reference to FIGS.
4 will be described.

FIG. 13A is a block diagram of a self-luminous device in this embodiment. Reference numeral 1301 denotes a source signal line driver circuit, 1302 denotes a gate signal line driver circuit, and 1303 denotes a pixel portion. In this embodiment, one source signal line driving circuit and one gate signal line driving circuit are provided, but the present invention is not limited to this configuration. Two source signal line driver circuits may be provided, or two gate signal line driver circuits may be provided.

The source signal line driving circuit 1301 has a shift register 1301a, a level shifter 1301b, and a sampling circuit 1301c. Note that the level shifter 1301b may be used as needed, and need not necessarily be used. In this embodiment, the level shifter 13
Although 01b is provided between the shift register 1301a and the sampling circuit 1301c, the present invention is not limited to this configuration. A configuration in which the level shifter 1301b is incorporated in the shift register 1301a may be employed.

Note that the source signal line 1304 electrically connected to the source signal line driving circuit 1301 and the power source 130
The current supply line electrically connected to the
03 is not connected to the switching circuit 130
8 is electrically connected to the pixel, the switching signal input to the switching circuit 1308 switches to a source signal line or a current supply line, and the pixel portion 13
03 is electrically connected.

That is, the switching circuit 1308 and the pixel unit 1
The wiring for connecting the switch 303 is also used as a source signal line or a current supply line in accordance with a switching signal input to the switching circuit 1308. However, in this embodiment, it is assumed that a source signal line or a current supply line on a pixel is not adjacent to each other.

Further, since one wiring is switched to a source signal line or a current supply line as described above,
When the wiring connected to the switching TFT becomes a current supply line, the pixel in that portion does not function. That is, since the source signal lines or the current supply lines are alternately switched without being adjacent to each other, the functional pixels are alternately switched for each vertical pixel column.

[0184] In the pixel portion 1303, of the source signal lines connected to the source signal line driver circuit 1301, the source signal line 1304 selected by the switching circuit 1308 is used.
(1304_1 to 1304_X), and the switching circuit 13
A current supply line (not shown) selected by 08 intersects with y gate signal lines 1306 (1306_1 to 1306_Y) connected to the gate signal line driver circuit 1302, respectively. The current supply line 1305 is connected to the power supply 130
7 is maintained at a constant potential (power supply potential).

The gate signal line driving circuit 1302 has a shift register and a buffer (both not shown). Further, a level shifter may be provided.

The clock signal (CL) which is a panel control signal
K), the start pulse signal (SP) is supplied to the shift register 1
301a. A sampling signal for sampling a video signal is output from the shift register 1301a. The output sampling signal is input to the level shifter 1301b, and is output with its potential amplitude increased.

The sampling signal output from level shifter 1301b is input to sampling circuit 1301c. At the same time, a video signal is input to the sampling circuit 1301c via the video signal line.

In the sampling circuit 1301c, the input video signal is sampled by the sampling signal and input to the source signal line 1304, respectively.

FIG. 13B shows a pixel structure of the pixel portion 1303 of the self-luminous device shown in FIG. Y gate signal lines 1306 (1306_1 to 1306_y) for inputting a selection signal from the gate signal line driver circuit 1302
Is connected to the gate electrode of the switching TFT 1309 of each pixel. One of the source region and the drain region of the switching TFT 1309 included in each pixel is composed of x source signal lines 1 to which a video signal is input.
304 (1304_1 to 1304_x), the other is connected to the gate electrode of the current control TFT 1310 of each pixel and the capacitor 1311 of each pixel.

The current control TFT 1310 of each pixel
The source region is connected to the current supply line 1305, and the drain region is connected to the anode or cathode of the EL element 1313.
The current supply line 1305 is connected to a capacitor 1311 included in each pixel. In this embodiment, the configuration having the capacitor 1311 is shown.
1 does not necessarily have to be provided.

The EL element 1313 has an anode, a cathode, and an EL layer provided between the anode and the cathode. When the anode of the EL element 1313 is connected to the drain region of the current controlling TFT 1310, the anode of the EL element 1313 is a pixel electrode and the cathode is a counter electrode. Conversely, the EL element 1313
Is connected to the drain region of the current controlling TFT 1310, the anode of the EL element 1313 is a counter electrode,
The cathode serves as a pixel electrode.

Further, the self-luminous device described with reference to FIG.
FIG. 14 shows a timing chart in the case of driving by the analog method. After one gate signal line is selected,
Then, the period until another gate signal line is selected is set to 1
This is called a line period (L). Note that in this specification, selection of a gate signal line means that a selection signal having a potential such that the switching TFT is turned on is input to the gate signal line.

The period from the display of one image to the display of the next image corresponds to one frame period (F). For example, in a self-luminous device having y gate signal lines, y line periods (L1 to L
y) is provided.

In the first line period (L1), the gate signal line 1306 is selected by the selection signal input from the gate signal line driving circuit 1302, and the gate signal line 1
All the switching TFTs 1 connected to 306
309 are all turned on. Then, the source signal line driver circuit 1301 supplies x source signal lines (1304_
1 to 1304 — x) are sequentially input with video signals. The video signal input to the source signal lines (1304_1 to 1304_x) is input to the gate electrode of the current control TFT 1310 via the switching TFT 1309.

The amount of current flowing through the channel forming region of the current control TFT 1310 is determined by the gate voltage V _gs, which is the potential difference between the gate electrode and the source region of the current control TFT 1310.
Is controlled by Therefore, the potential applied to the pixel electrode of the EL element 1313 is determined by the height of the potential of the video signal input to the gate electrode of the current control TFT 1310. Therefore, the EL element 1313 emits light under the control of the potential of the video signal.

By repeating the above operation, the source signal line 1
When the input of the video signal to the 304 (1304_1 to 1304_x) ends, the first line period (L1) ends. Note that the source signal line 1304 (1304_1 to 1304_1)
The period until the input of the video signal to 304_x) is completed and the horizontal retrace period may be combined into one line period. Then, the second line period (L2) is started, the gate signal line 1306_2 is selected by the selection signal, and the video signal is sequentially transmitted to the source signal lines 1304 (1304_1 to 1304_x) similarly to the first line period (L1). Is entered.

Then, all the gate signal lines (1306_1)
１1306 — y), all the line periods (L1 to Ly) end. All line periods (L1 to
When Ly) ends, one frame period ends. All the pixels display during one frame period, and one image is formed. Note that all the line periods (L1 to L
y) and the vertical flyback period may be combined into one frame period.

As described above, the light emission amount of the EL element is controlled by the potential of the video signal, and gradation display is performed by controlling the light emission amount.

The structure of this embodiment is similar to those of the first and second embodiments.
It is possible to implement in combination with the above configuration.

[Embodiment 4] In implementing the self-luminous device of the present invention, it is preferable to drive the current controlling TFT in a region having the following voltage-current characteristics.

First, in the case of driving by the digital method, the operating points of both the current controlling TFT and the EL element (points at which the voltage-current characteristics of both elements coincide) are present in the linear region. It is preferable to drive the current controlling TFT and the EL element in advance. As a result, the current control T
It is possible to perform gradation display in which luminance unevenness of the EL element due to a shift in FT characteristics is suppressed. In the case of analog driving, the current control TF is controlled so that the operating point exists in a saturation region where the current value can be controlled only by | V _GS |.
It is preferable to drive the T and EL elements.

[Embodiment 5] The self-luminous device is of a self-luminous type, so that it has better visibility in a bright place than a liquid crystal display and has a wide viewing angle. Therefore, it can be used for display portions of various electric appliances. For example, the present invention is applied to a display unit of a light-emitting device (an electro-optical device in which a self-light-emitting device is incorporated in a housing) having a diagonal size of 30 inches or more (typically 40 inches or more) in order to watch a TV broadcast on a large screen. It is good to use the self-light-emitting device.

The self-luminous device includes all information displays such as a display for a personal computer, a display for receiving a TV broadcast, and a display for displaying an advertisement. In addition, the self-luminous device of the present invention can be used as a display portion of various electric appliances.

[0204] Such electric appliances of the present invention include a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproducing device (car audio, audio component, etc.), a notebook personal computer, a game. Devices, personal digital assistants (mobile computers, mobile phones,
An image reproducing apparatus provided with a recording medium (specifically, a digital video disc (D
VD) and the like, which reproduces a recording medium and has a display capable of displaying the image. In particular, it is desirable to use a self-luminous device for a portable information terminal, which is often viewed from an oblique direction, because importance is attached to a wide viewing angle. Specific examples of these electric appliances are shown in FIGS.

FIG. 15A shows a self-luminous device,
001, a support base 2002, a display unit 2003, and the like. The self-luminous device of the present invention can be used for the display portion 2003. Since the self-luminous device is a self-luminous type, it does not require a backlight and can be a display portion thinner than a liquid crystal display.

FIG. 15B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The self-luminous device of the present invention can be used for the display portion 2102.

FIG. 15C shows a part (right side) of a head-mounted electro-optical device, and includes a main body 2201, a signal cable 2202, a head fixing band 2203, a screen section 2204, an optical system 2205, and a display section. 2206 and the like.
The self-luminous device of the present invention can be used for the display portion 2206.

FIG. 15D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
1, recording medium (DVD or the like) 2302, operation switch 23
03, a display unit (a) 2304, a display unit (b) 2305, and the like. The display unit (a) 2304 mainly displays image information, and the display unit (b) 2305 mainly displays character information.
(B) It can be used for 2304 and 2305. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 15E shows a goggle type display (head-mounted display).
1, a display unit 2402, and an arm unit 2403. The self light emitting device of the present invention can be used for the display portion 2402.

FIG. 15F shows a personal computer, which includes a main body 2501, a housing 2502, a display portion 2503,
A keyboard 2504 and the like are included. The self-luminous device of the present invention can be used for the display portion 2503.

If the emission luminance of the EL material becomes higher in the future, the light including the output image information can be enlarged and projected by a lens or the like and used for a front-type or rear-type projector.

[0212] Further, the above-mentioned electric appliances are available on the Internet or C
Information distributed through an electronic communication line such as an ATV (cable television) is frequently displayed, and in particular, opportunities to display moving image information are increasing. Since the response speed of the EL material is extremely high, the self-luminous device is preferable for displaying moving images.

In the self-luminous device, since the light emitting portion consumes power, it is desirable to display information so that the light emitting portion is reduced as much as possible. Therefore, portable information terminals,
In particular, when a self-light-emitting device is used for a display portion mainly including character information such as a mobile phone or a sound reproducing device, it is desirable to drive the non-light-emitting portion as a background so that character information is formed by a light-emitting portion.

FIG. 16A shows a mobile phone, which includes a main body 2601, an audio output unit 2602, and an audio input unit 260.
3, including a display unit 2604, operation switches 2605, and an antenna 2606. The self-luminous device of the present invention has a display portion 2604.
Can be used. Note that the display portion 2604 can display power of the mobile phone by displaying white characters on a black background. If the surroundings are dark, lowering the applied voltage and lowering the luminance are effective in reducing power consumption.

FIG. 16B shows an audio reproducing apparatus, specifically, a car audio system.
702, and operation switches 2703 and 2704. The self-luminous device of the present invention can be used for the display portion 2702. In this embodiment, the in-vehicle audio is shown, but the present invention may be applied to a portable or home-use audio reproducing apparatus. Note that the display portion 2702 can suppress power consumption by displaying white characters on a black background. This is particularly effective in a portable sound reproducing device.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electric appliances in various fields. In addition, the electric appliance of this embodiment may use a self-luminous device having any of the configurations shown in the first to fourth embodiments.

[0219]

According to the present invention, in the active matrix type self-luminous device, the source signal line of the pixel portion and the wiring of the current supply line can be shared. Thus, the aperture ratio of the pixel portion can be increased. Further, by using such a self-luminous device for the display portion, an electric appliance with high emission luminance can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a self-luminous device of the present invention.

FIG. 2 is a diagram showing a switching circuit of the self-luminous device of the present invention.

FIG. 3 is a diagram showing a switching circuit of the self-luminous device of the present invention.

FIG. 4 is a circuit diagram of a pixel portion of the self-luminous device of the present invention.

FIG. 5 is a circuit diagram of a pixel of the self-luminous device of the present invention.

FIG. 6 is a diagram showing a driving method of the self-luminous device of the present invention.

FIG. 7 is a top view of the self-luminous device of the present invention.

FIG. 8 is a diagram showing a circuit configuration of a self-luminous device of the present invention.

FIG. 9 is a circuit diagram of a pixel portion of the self-luminous device of the present invention.

FIG. 10 is a circuit diagram of a pixel of the self-luminous device of the present invention.

FIG. 11 is a diagram showing a method for driving a self-luminous device of the present invention.

FIG. 12 is a top view of the self-luminous device of the present invention.

FIG. 13 is a diagram showing a circuit configuration of a self-luminous device of the present invention.

FIG. 14 is a diagram illustrating a driving method of a self-luminous device of the present invention.

FIG. 15 shows an electric appliance using the self-luminous device of the present invention.

FIG. 16 shows an electric appliance using the self-luminous device of the present invention.

FIG. 17 is a circuit diagram of a pixel portion of a conventional self-luminous device.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 641 G09G 3/20 641E 680 680G

Claims (10)

[Claims] A plurality of pixels, a plurality of gate signal lines, a plurality of source signal lines, a plurality of current supply lines, and a plurality of TFTs.
Wherein the plurality of source signal lines and the current supply lines are electrically alternated alternately. 2. The self-luminous device according to claim 1, wherein the source signal line and the current supply line are electrically switched every frame period. 3. The self-luminous device according to claim 2, wherein said one frame period is 1/240 to 1/120 s. 4. The self-luminous device according to claim 1, wherein the plurality of source signal lines and the current supply line are electrically connected to a switching circuit. 5. The self-luminous device according to claim 4, wherein a source signal line or a current supply line is electrically connected to a switching TFT in a pixel portion by a switching signal for controlling the switching circuit. . 6. The self-luminous device according to claim 1, wherein a source signal line or a current supply line is electrically connected to a current control TFT in a pixel portion. 7. The self-luminous device according to claim 4, wherein said switching circuit has a transmission gate. 8. A self-luminous device having a plurality of pixels, a plurality of gate signal lines, a plurality of source signal lines, a plurality of switching TFTs and a plurality of current control TFTs, wherein a drain region of the switching TFT or A self-luminous device, wherein one of the source regions is electrically connected to a source signal line and a source region of a current controlling TFT of an adjacent pixel. 9. A self-luminous device having a plurality of pixels, a plurality of gate signal lines, a plurality of source signal lines, a plurality of current supply lines, a plurality of switching TFTs and a plurality of current control TFTs, When either the drain region or the source region of the switching TFT in the pixel in the (x-2) th column is electrically connected to the source signal line, the switching TFT in the pixel in the (x-1) th column is used. T
One of a source region and a drain region of the FT is electrically connected to a current supply line of a pixel in an (x−2) -th column. 10. An electric appliance using the self-luminous device according to any one of claims 1 to 9.