JP4421641B2 - Driving method of light emitting device - Google Patents

Description

The present invention relates to a driving method of a light-emitting device formed by forming an electroluminescence (EL) element and a thin film transistor (hereinafter referred to as TFT) on a substrate. Further, the present invention relates to an electronic device using the light emitting device for a display portion. Here, an EL element will be described as an example of a typical light-emitting element.

Note that in this specification, an EL element refers to both an element that uses light emission (fluorescence) from a singlet exciton and an element that uses light emission (phosphorescence) from a triplet exciton.

In recent years, development of a light-emitting device having an EL element as a light-emitting element has been activated. Unlike the liquid crystal display device, the light emitting device is a self-luminous type. An EL element has a structure in which an EL layer is sandwiched between a pair of electrodes (anode and cathode), and the EL layer usually has a laminated structure. A typical example is a “hole transport layer / light emitting layer / electron transport layer” stacked structure proposed by Tang et al. Of Kodak Eastman Company. This structure has very high luminous efficiency, and most EL display devices currently under research and development employ this structure.

In addition, a structure in which a hole injection layer / a hole transport layer / a light emitting layer / an electron transport layer are stacked in this order on the anode, or a hole injection layer / a hole transport layer / a light emitting layer / an electron transport layer / an electron injection. A structure in which layers are stacked may be employed. You may dope a fluorescent pigment | dye etc. with respect to a light emitting layer.

Here, all layers provided between the cathode and the anode are collectively referred to as an EL layer. Therefore, the above-described hole injection layer, hole transport layer, light emitting layer, electron transport layer, electron injection layer, etc.
All are included in the EL layer.

Then, a predetermined voltage is applied between the pair of electrodes (both electrodes) to the EL layer having the above structure,
Thereby, recombination of carriers occurs in the light emitting layer to emit light. At this time, EL
The light emission luminance of the element is proportional to the current flowing through the EL element.

In a light emitting device using an EL element, the luminance changes even when a constant current is passed due to deterioration of the element itself. When such deterioration occurs, when an EL element is used as a light emitting device, a display pattern is burned out or accurate gradation display cannot be performed.

In particular, a change in luminance due to deterioration of the EL element itself during initial lighting, which is called “initial deterioration”, is remarkable. Therefore, methods for applying a reverse bias to the EL element in order to suppress degradation of the EL element itself are disclosed in Japanese Patent Laid-Open Nos. 2001-109432 and 20.
This is proposed in Japanese Patent Application No. 01-222255. Here, a state in which a voltage is applied between the anode and the cathode so that a current flows through the EL element, that is, a state in which the anode potential is higher than the cathode potential is a forward bias, and conversely, the cathode potential is the anode potential. The higher state is the reverse bias. When a forward bias is applied, a current corresponding to the voltage flows through the EL element to emit light. When reverse bias is applied,
No current flows through the EL element and no light is emitted.

Further, a method for driving the EL element by periodically switching and applying a forward bias and a reverse bias is defined as AC driving.

There are two types of light-emitting devices: passive matrix type and active matrix type. The active matrix type is suitable for those that require high-speed operation because of the increase in the number of pixels and the display of moving images as resolution increases. ing.

As a driving method of the active matrix light emitting device, there is a digital time gray scale method which is not easily affected by variation in characteristics of the driving TFT.

Further, as disclosed in Japanese Patent Application Laid-Open No. 2001-343933, each pixel is erased in addition to the driving TFT / switching TFT by the digital time gray scale method.
By using FT, high-precision multi-gradation display can be realized. Hereinafter, in this specification, this driving method is referred to as SES (Simultaneous Erase Scan) driving.

As described above, when the degradation of the EL element itself occurs, even if the same current is supplied to each pixel, the luminance of each pixel varies depending on the degree of degradation, and the display pattern becomes tight. Accurate gradation display cannot be performed.

In particular, a change in luminance due to deterioration of the EL element itself during initial lighting, which is called “initial deterioration”, is remarkable. Therefore, a method of applying a reverse bias to the EL element has been proposed in order to suppress degradation of the EL element itself.

It is an object of the present invention to propose a specific pixel configuration and driving method in the case of adopting SES driving in an active matrix EL panel and applying a reverse bias in order to reduce deterioration of the EL element itself. And

The present invention is characterized in that a reverse bias is applied to the EL element without raising and lowering both the anode and the cathode. Specifically, when the reverse bias is applied by the conventional method, it is performed by changing the power supply potential, and accordingly, withstands the breakdown voltage of the TFTs constituting other parts, which tends to be a problem. In the present invention, a power supply line having a reverse bias potential is newly provided, and the reverse bias application timing is determined by turning on and off a dedicated TFT. further,
With the dedicated TFT, it is possible to determine the reverse bias application timing for each row.
Therefore, the reverse bias period can be synchronized with the erase period of each line,
A high duty ratio can be realized.

Furthermore, by making the reverse bias smaller than the forward bias, the effect of preventing deterioration by applying the reverse bias can be sufficiently obtained, and there is also a problem in the consumption current, the breakdown voltage of the TFT and the EL element, and the like. There can be no configuration.

  The configuration of the present invention will be described below.

The light emitting device of the present invention is
A panel provided with a pixel portion in which a plurality of pixels provided with light-emitting elements are arranged in a matrix, a source signal line driver circuit and a gate signal line driver circuit for driving the pixel portion,
First means for generating a timing signal and a video signal for driving the source signal line driving circuit and the gate signal line driving circuit;
A light emitting device having a second means for supplying a desired power source used in the panel,
Each of the plurality of pixels is
A third means for controlling the input of the video signal to the pixel;
According to the input video signal, determine whether the previous light emitting element emits light or not,
A fourth means for supplying a current by applying a forward bias between the first electrode and the second electrode of the light emitting element when the light emitting element emits light;
A fifth means for forcibly cutting off the current supplied to the light emitting element;
And a sixth means for applying a reverse bias between the first electrode and the second electrode of the light emitting element.

Here, the first means and the second means may be integrally formed with the panel. Further, the third to sixth means may be any means that uses a video signal as a control signal and can select the same or non-conduction.

The light emitting device of the present invention is
A light emitting device having a plurality of pixels provided with a light emitting element,
Each of the plurality of pixels is
A source signal line, first to third gate signal lines, first to third power supply lines,
Having first to fourth transistors and the light emitting element;
A gate electrode of the first transistor is electrically connected to the first gate signal line, a first electrode is electrically connected to the source signal line, and a second electrode is connected to the second gate signal line. Electrically connected to the first electrode of the transistor and the gate electrode of the third transistor;
A gate electrode of the second transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to the first power supply line;
The first electrode of the third transistor is electrically connected to the first power supply line, and the second electrode includes the first electrode of the light emitting element and the first electrode of the fourth transistor. Electrically connected to the electrode,
A gate electrode of the fourth transistor is electrically connected to the third gate signal line; a second electrode is electrically connected to the second power supply line;
The second electrode of the light emitting element is electrically connected to the third power supply line.

The light emitting device of the present invention is
A light emitting device having a plurality of pixels provided with a light emitting element,
Each of the plurality of pixels is
A source signal line, first and second gate signal lines, first to third power supply lines, first to fourth transistors, and the light emitting element;
A gate electrode of the first transistor is electrically connected to the first gate signal line, a first electrode is electrically connected to the source signal line, and a second electrode is connected to the second gate signal line. Electrically connected to the first electrode of the transistor and the gate electrode of the third transistor;
A gate electrode of the second transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to the first power supply line;
The first electrode of the third transistor is electrically connected to the first power supply line, and the second electrode includes the first electrode of the light emitting element and the first electrode of the fourth transistor. Electrically connected to the electrode,
A gate electrode of the fourth transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to the second power supply line;
The second electrode of the light emitting element is electrically connected to the third power supply line.

The light emitting device of the present invention is
A light emitting device having a plurality of pixels provided with a light emitting element,
Each of the plurality of pixels is
A source signal line, first to third gate signal lines, first to third power supply lines,
Having first to fourth transistors and the light emitting element;
A gate electrode of the first transistor is electrically connected to the first gate signal line, a first electrode is electrically connected to the source signal line, and a second electrode is connected to the second gate signal line. Electrically connected to the gate electrode of the transistor of
A first electrode of the second transistor is electrically connected to the first power supply line; a second electrode is electrically connected to a first electrode of the third transistor;
The gate electrode of the third transistor is electrically connected to the second gate signal line, and the second electrode includes the first electrode of the fourth transistor and the first electrode of the light emitting element. Electrically connected with
A gate electrode of the fourth transistor is electrically connected to the third gate signal line; a second electrode is electrically connected to the second power supply line;
The second electrode of the light emitting element is electrically connected to the third power supply line.

The light emitting device of the present invention is
A light emitting device having a plurality of pixels provided with a light emitting element,
Each of the plurality of pixels is
A source signal line, first and second gate signal lines, first to third power supply lines, first to fourth transistors, and the light emitting element;
A gate electrode of the first transistor is electrically connected to the first gate signal line, a first electrode is electrically connected to the source signal line, and a second electrode is connected to the second gate signal line. Electrically connected to the gate electrode of the transistor of
A first electrode of the second transistor is electrically connected to the first power supply line; a second electrode is electrically connected to a first electrode of the third transistor;
The gate electrode of the third transistor is electrically connected to the second gate signal line, and the second electrode includes the first electrode of the fourth transistor and the first electrode of the light emitting element. Electrically connected with
A gate electrode of the fourth transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to the second power supply line;
The second electrode of the light emitting element is electrically connected to the third power supply line.

The driving method of the light emitting device of the present invention is as follows:
A driving method of a light emitting device having a plurality of pixels provided with a light emitting element, and expressing gradation by controlling a difference in light emission time of the light emitting element,
One frame period has n (n is a natural number, 2 <n) subframe periods,
Each of the subframe periods is
An address (write) period during which video signals are written to pixels, and
Based on the video signal written to the pixel, the display is controlled by controlling light emission and non-light emission of the light emitting element, and has a sustain (light emission) period,
M selected from the n subframe periods (m is a natural number, 0 <m ≦ n−1)
Each subframe period of
After the end of the sustain (light emission) period, a reset signal is written to the pixel.
M reset periods whose periods do not overlap each other;
In the row in which the reset signal is written, the light emitting element is forced to be in a non-light emitting state, and there are m erasing periods that do not overlap each other,
Each of the k subframe periods (k is a natural number, 0 <k ≦ m) selected from the m subframe periods,
When the light emitting element emits light, a reverse bias voltage having an inverted polarity is applied to a forward bias voltage applied between the first electrode and the second electrode of the light emitting element, and the periods overlap each other. Not k reverse bias periods;
K reverse bias application periods in which the reverse bias voltage applied in the reverse bias period is continuously applied between the first electrode and the second electrode of the light emitting element;
The address (write) period, the sustain (light emission) period, the reset period, the erase period, the reverse bias period, and the reverse bias application period each have a period that partially overlaps each other,
In the specific subframe period, the reverse bias application period is provided during the erasing period.

In the driving method of the light emitting device of the present invention,
When the forward bias voltage is V ₁ and the reverse bias voltage is V ₂ ,
It is characterized by satisfying | V ₁ | ≧ | V ₂ |.

The light emitting device of the present invention makes it possible to apply a reverse bias to the EL element without changing the potential of both the pixel electrode and the counter electrode. Furthermore, unlike the conventional method of applying a reverse bias, the reverse bias is not applied to all the pixels in the plane at the same time by changing the potential of the power supply line, but in reverse direction for each row. Since a bias can be applied, a reverse bias period can be provided in synchronization with the erase period in SES driving. Therefore, a reverse bias period can be provided without newly providing a period and causing a decrease in the duty ratio, which contributes to a longer life of the EL element.

Furthermore, by making the reverse bias voltage smaller than the forward bias voltage,
Since it is not necessary to increase the power supply voltage of the gate signal line driving circuit, it is advantageous in terms of power consumption.

[Embodiment 1]
FIG. 1 shows an embodiment of a pixel configuration for performing AC driving in the present invention.

As shown in FIG. 1A, each pixel includes a source signal line (S) 101, a write gate signal line (SEL) 102, an erase gate signal line (RSE) 103, a reverse bias gate signal line ( RBS) 104, switching TFT 105 corresponding to the third means, erasing TFT 106 corresponding to the fifth means, and driving TFT 107 corresponding to the fourth means.
, A reverse bias TFT 108, an EL element 109, a current supply line (V _A ) 111, and a reverse bias power supply line (V _B ) 112 corresponding to a sixth means. One electrode (pixel electrode) of the EL element 109 is connected to either the source region or the drain region of the driving TFT 107, and the other electrode (counter electrode) is a counter power line.
(V _C ) 113.

In FIG. 1A, the potential attached to each signal line and power supply line indicates the power supply potential or the L level / H level potential of the signal. For example, in the case of the source signal line 101, it is 0V when the signal is at the L level and 7V when the signal is at the H level. The potential of the current supply line 111 is 6V, and the potential of the reverse bias power supply line 112 is -14V. Note that the potential given here is merely an example, and the circuit in FIG. 1A can operate without necessarily using this potential. What is necessary is just to determine suitably, considering the ON / OFF timing of the TFT of each part, the gate-source voltage, and the like.

Next, as an example, the switching TFT 105, the erasing TFT 106, and the reverse bias TFT 108 are all N-channel type, the driving TFT 107 is P-channel type, and the EL element 109 has an anode on the side connected to the current supply line 111,
The operation when the side connected to the counter power line 113 is a cathode will be described.

First, in the address (write) period, as shown in FIG. 1B, a pulse is input to the write gate signal line 102 and becomes H level (9 V), the switching TFT 105 is turned on, and the source signal line The video signal output to 101 is input to the gate electrode of the driving TFT 107. Here, since the driving TFT 107 is a P-channel type, it is turned off when the video signal is at the H level (7 V), and the L level (0 V).
Turns on when.

Subsequently, in the sustain (light emission) period, as shown in FIG.
When T107 is turned ON, the potential (6V) of the current supply line 111 is input to the pixel electrode, and the EL element 109 is detected by the potential difference with the potential (−10V) of the counter power supply line 113.
A forward bias is applied to the EL element 109 and a current flows through the EL element 109 to emit light. Further, when the driving TFT 107 is OFF, no current flows through the EL element 109 and no light is emitted.

Subsequently, in the reset period, as shown in FIG. 1D, a pulse is input to the erasing gate signal line 103 and becomes H level (9 V), and the erasing TFT 106 is turned on.
N. When the erasing TFT 106 is turned on, the potential (6 V) of the current supply line 111 is input to the gate electrode of the driving TFT 107, and therefore the driving TFT
The gate-source voltage of 107 becomes 0, and the driving TFT 107 is turned off.
Therefore, the EL element 109 does not emit light.

On the other hand, in the reverse bias period, as shown in FIG. 1E, a pulse is input to the reverse bias gate signal line 104 and becomes H level (−10 V), and the reverse bias TFT 108 is turned on. When the reverse bias TFT 108 is turned on, the potential (−14 V) of the reverse bias power supply line 112 is input to the pixel electrode. Here, since the potential (−14V) of the reverse bias power supply line 112 is set lower than the potential (−10V) of the counter power supply line 113, a reverse bias is applied to the EL element 109. While the H-level potential (−10 V) is input to the reverse bias gate signal line 104, the reverse bias is continuously applied to the EL element 109.

Further, even when the pulse input to the reverse bias gate signal line 104 is completed and the reverse bias TFT 108 is turned off, the EL element 109 itself, that is, the capacitance parasitic between the anode and the cathode of the EL element 109, or the pixel electrode The charge provided to the pixel electrode is held by a capacitor provided between the EL element 109 and a constant potential, and a reverse bias is continuously applied to the EL element 109.

According to the configuration shown in FIG. 1, since the erase gate signal line and the reverse bias gate signal line are provided separately, the reverse bias period can be set to an arbitrary length with respect to the erase period. I can do it. Further, by providing the reverse bias period and the erasing period of each line at the same timing, AC driving is possible without reducing the duty ratio.

[Embodiment 2]
FIG. 2 shows a pixel configuration for performing AC driving in the present invention, which is an embodiment different from the first embodiment.

As shown in FIG. 2A, each pixel includes a source signal line (S) 201, a write gate signal line (SEL) 202, an erase / reverse bias gate signal line (RSE) 203, a switching TFT 204, One electrode of the EL element 208 includes an erasing TFT 205, a driving TFT 206, a reverse bias TFT 207, an EL element 208, a current supply line (V _A ) 210, and a reverse bias power supply line (V _B ) 211. The (pixel electrode) is connected to either the source region or the drain region of the driving TFT 206, and the other electrode (counter electrode) is connected to the counter power line (V _C ) 212.

In FIG. 2A, the potential attached to each signal line and power supply line indicates the power supply potential or the L level / H level potential of the signal. For example, in the case of the source signal line 201, it is 0V when the signal is at the L level and 7V when the signal is at the H level. The potential of the current supply line 210 is 6V, and the potential of the reverse bias power supply line 211 is −14V. Note that the potential given here is merely an example, and the circuit in FIG. 2A can operate without necessarily using this potential. What is necessary is just to determine suitably, considering the ON / OFF timing of the TFT of each part, the gate-source voltage, and the like.

Here, as an example, the switching TFT 204, the erasing TFT 205, and the reverse bias TFT 207 are all N-channel type, the driving TFT 206 is P-channel type, and in the EL element 208, the side connected to the current supply line 210 is an anode, The operation when the side connected to the counter power line 212 is a cathode will be described.

First, in the address (write) period, as shown in FIG. 2B, a pulse is input to the write gate signal line 202 to become H level (9 V), and the switching TFT 204 is turned ON and output to 201. The displayed video signal is the driving TFT 206.
Are input to the gate electrode. Here, since the driving TFT 206 is a P-channel type, it is turned off when the video signal is at the H level (7 V), and turned on when the video signal is at the L level (0 V).

Subsequently, in the sustain (light emission) period, as shown in FIG.
When T206 is turned ON, the potential (6V) of the current supply line 210 is input to the pixel electrode, and the EL element 208 is caused by a potential difference with the potential (−10V) of the counter power supply line 212.
A forward bias is applied to the EL element 208, and a current flows through the EL element 208 to emit light. When the driving TFT 206 is OFF, no current flows through the EL element 208 and no light is emitted.

Subsequently, in the reset / reverse bias period, as shown in FIG.
A pulse is input to the gate signal line 203 for erasing / reverse bias, and an H level (9
V), and the erasing TFT 205 and the reverse bias TFT 207 are turned ON.
When the erasing TFT 205 is turned on, the potential (6V) of the current supply line 210 is input to the gate electrode of the driving TFT 206, the potential difference between the gate electrode and the source electrode of the driving TFT 206 becomes 0, and the driving TFT 206 is turned off. .

At the same time, when the reverse bias TFT 207 is turned on, the potential (−14 V) of the reverse bias power supply line 211 is input to the pixel electrode. Here, since the potential (−14V) of the reverse bias power supply line 211 is set lower than the potential (−10V) of the counter power supply line 212, a reverse bias is applied to the EL element 208.
While the H-level potential (−10 V) is input to the erase / reverse bias gate signal line 203, the reverse bias is continuously applied to the EL element 208.

Further, even when the pulse input to the erase / reverse bias gate signal line 203 is finished and the reverse bias TFT 207 is turned off, the EL element 208 itself is provided between the capacitor or the pixel electrode and a certain potential. The charged capacitance holds the charge of the pixel electrode, and a reverse bias is continuously applied to the EL element 208.

At this time, the erase period and the reverse bias period of each line are the same period, and the high du
A ty ratio can be realized. Further, the erase / reverse bias period may be extended and set to an arbitrary length.

[Embodiment 3]
FIG. 3 shows a pixel configuration for performing AC driving in the present invention, and shows an embodiment different from the first and second embodiments.

As shown in FIG. 3A, each pixel has a source signal line (S) 301, a write gate signal line (SEL) 302, an erase gate signal line (RSE) 303, a reverse bias gate signal line ( RBS) 304, switching TFT 305, driving TFT 306,
The EL element 30 includes an erasing TFT 307, a reverse bias TFT 308, an EL element 309, a current supply line (V _A ) 311, and a reverse bias power supply line (V _B ) 312.
One electrode (pixel electrode) 9 is connected to either the source region or the drain region of the driving TFT 306, and the other electrode (counter electrode) is the counter power supply line (V _C ).
313.

In FIG. 3A, the potential attached to each signal line and power supply line indicates the power supply potential or the L level / H level potential of the signal. For example, in the case of the source signal line 301, it is 0V when the signal is at the L level and 7V when the signal is at the H level. The potential of the current supply line 311 is 6V, and the potential of the reverse bias power supply line 312 is -14V. Note that the potential given here is merely an example, and the circuit in FIG. 3A can operate without necessarily using this potential. What is necessary is just to determine suitably, considering the ON / OFF timing of the TFT of each part, the gate-source voltage, and the like.

Here, as an example, switching TFT 305, reverse bias TFT 3
In the case where 08 is an N-channel type, driving TFT 306 and erasing TFT 307 are P-channel type, and EL element 309 has a side connected to current supply line 311 as an anode and a side connected to counter power line 313 as a cathode. The operation will be described.

First, in the address (write) period, as shown in FIG. 3B, a pulse is input to the write gate signal line 302 and becomes H level (9 V), the switching TFT 305 is turned on, and the source signal line The video signal output to 301 is input to the gate electrode of the driving TFT 306. Here, since the driving TFT 306 is a P-channel type, it is turned off when the video signal is at the H level (7 V), and the L level (0 V).
Turns on when.

Further, an L-level potential (−2 V) is input to the erasing gate signal line 303, and the erasing TFT 307 is turned on.

Subsequently, in the sustain (light emission) period, as shown in FIG. 3C, the L-level potential (−2 V) is always input to the erase gate signal line 303, and the erase TFT 30.
7 keeps on. Further, when the driving TFT 306 is turned on, the potential (6V) of the current supply line 311 is input to the pixel electrode, and the potential (−1 of the counter power supply line 313).
0V), a forward bias is applied to the EL element 309, and a current flows through the EL element 309 to emit light. When the driving TFT 306 is OFF, E
No current flows through the L element 309 and no light is emitted.

Subsequently, in the reset period, as shown in FIG. 3D, an H-level potential (9 V) is always input to the erasing gate signal line 303, and the erasing TFT 307 is turned off.
Keep doing. When the erasing TFT 307 is turned off, the current supply path from the current supply line 311 to the EL element 309 is blocked, and the EL element 309 does not emit light. Unlike the cases of Embodiments 1 and 2, here, the erasing TFT 307 continues to be turned on throughout the light emission period and kept off during the erasing period.

On the other hand, in the reverse bias period, as shown in FIG. 3E, a pulse is input to the reverse bias gate signal line 304 and becomes H level (−10 V), and the reverse bias TFT 308 is turned on. When the reverse bias TFT 308 is turned on, the potential (−14 V) of the reverse bias power supply line 312 is input to the pixel electrode. Here, since the potential (−14V) of the reverse bias power supply line 312 is set lower than the potential (−10V) of the counter power supply line 313, a reverse bias is applied to the EL element. The reverse bias gate signal line 304 has an H level potential.
While (−10 V) is input, the reverse bias is continuously applied to the EL element 309.

Further, even when the pulse input to the reverse bias gate signal line 304 is finished and the reverse bias TFT 308 is turned off, the capacitance of the EL element 309 itself,
Alternatively, the electric charge of the pixel electrode is held by a capacitor provided between the pixel electrode and a certain potential, and a reverse bias is continuously applied to the EL element 309.

During the erasing period, it is necessary to always turn off the erasing TFT 307, and the reverse bias period diagram and the erasing period of each line can be overlapped, so that a high duty ratio can be realized. Further, the reverse bias period can be set to an arbitrary length.

[Embodiment 4]
FIG. 4 shows a pixel configuration for performing AC driving in the present invention, which is an embodiment different from the first to third embodiments.

As shown in FIG. 4A, each pixel includes a source signal line (S) 401, a write gate signal line (SEL) 402, an erase / reverse bias gate signal line (RSE) 403, a switching TFT 404, A driving TFT 405, an erasing TFT 406, a reverse bias TFT 407, an EL element 408, a current supply line (V _A ) 410, a reverse bias power supply line (V _B ) 411, and one electrode of the EL element 408 The (pixel electrode) is connected to either the source region or the drain region of the driving TFT 405, and the other electrode (counter electrode) is connected to the counter power line (V _C ) 412.

In FIG. 4A, the potential attached to each signal line and power supply line indicates the power supply potential or the L level / H level potential of the signal. For example, in the case of the source signal line 401, it is 0V when the signal is at the L level and 7V when the signal is at the H level. The potential of the current supply line 410 is 6V, and the potential of the reverse bias power supply line 411 is -14V. Note that the potential given here is merely an example, and the circuit in FIG. 4A can operate without necessarily using this potential. What is necessary is just to determine suitably, considering the ON / OFF timing of the TFT of each part, the gate-source voltage, and the like.

Here, the switching TFT 404 and the reverse bias TFT 407 are N
A description will be given of driving when the channel type, driving TFT 405 and erasing TFT 406 are P-channel type, the current supply line 410 is an anode potential, and the counter power supply line 412 is a cathode potential. In the EL element 408, an operation when the side connected to the current supply line 410 is an anode and the side connected to the counter power supply line 412 is a cathode will be described.

First, in the address (write) period, as shown in FIG. 4B, a pulse is input to the write gate signal line 402 to become H level (9 V), the switching TFT 404 is turned ON, and output to 401. The displayed video signal is a driving TFT 405.
Are input to the gate electrode. Here, since the driving TFT 405 is a P-channel type, it is turned off when the video signal is at the H level (7 V) and turned on when the video signal is at the L level (0 V).

The erase / reverse bias gate signal line 403 has an L level potential (−16 V).
Is input, the erasing TFT 406 is turned on, and the reverse bias TFT 407 is turned on.
FF.

Subsequently, in the sustain (light emission) period, as shown in FIG. 4C, an L-level potential (−16 V) is always input to the erase / reverse bias gate signal line 403, and the erase TFT 406 is turned on. Then, the reverse bias TFT 407 is kept off.

Further, when the driving TFT 405 is turned on, the potential of the current supply line 410 is increased.
(6V) is input to the pixel electrode, a forward bias is applied to the EL element 408 due to the potential difference with the potential (−10V) of the counter power supply line 412, and a current flows through the EL element 408 to emit light. Further, when the driving TFT 405 is OFF, no current flows through the EL element 408 and no light is emitted.

Subsequently, in the reset / reverse bias period, as shown in FIG.
An H-level potential (9 V) is always input to the erase / reverse bias gate signal line 403, the erase TFT 406 is turned off, and the reverse bias TFT 407 is turned on. By this operation, the potential (−14 V) of the reverse bias power supply line is input to the pixel electrode. Here, since the potential (−14 V) of the reverse bias power supply line 411 is set lower than the potential (−10 V) of the counter power supply line 412, the reverse bias is applied to the EL element 408. While the H-level potential (9 V) is input to the erase / reverse bias gate signal line 403, the current supply path from the current supply line 410 to the EL element 408 is interrupted by the erase TFT 406 being kept off. Then, the EL element 408 does not emit light, and the reverse bias is continuously applied to the EL element 408 as the reverse bias TFT 407 is kept on.

At this time, the erase period and the reverse bias period of each line are the same period, and the high du
A ty ratio can be realized. In addition, the erase / reverse bias period can be extended and set to an arbitrary length.

As in Embodiments 1 to 4, by applying a reverse bias power supply line to each pixel, a reverse bias of an arbitrary value is applied to each of the R, G, and B EL elements in a color display light emitting device. I can do it.

Further, the potential of the reverse bias power line is made common to the potential when the highest reverse bias is applied among R, G, and B, and the reverse bias power line is shared by adjacent pixels. Also good. In this case, the number of wirings can be reduced and a high aperture ratio can be expected.

In the first to fourth embodiments, the case where the driving TFT is operated in the linear region, that is, the constant voltage driving method is described as an example. However, when the lifetime of the EL element is considered, the driving TFT is set in the saturation region. It is desirable to perform constant current driving that can supply a constant current to the EL element.

  Examples of the present invention will be described below.

As shown in FIG. 12, when a light emitting device is used as a display unit of an electronic device such as a mobile phone, the light emitting device 1201 is incorporated. Here, the light emitting device 1201
The term “panel” refers to a configuration in which a panel and a substrate on which a signal processing LSI, a memory, and the like for driving the panel are mounted are connected.

A block diagram of the light-emitting device 1201 is shown in FIG. The light emitting device 1201 includes a panel 650 and a drive circuit 660.

The drive circuit 660 includes a signal generation unit 611 and a power supply unit 612. The power supply unit 612 generates and supplies power with a plurality of desired voltage values to the source signal line drive circuit, the gate signal line drive circuit, the light emitting element, the signal generation unit 611, and the like from the power supplied from the external battery. To do. The signal generator 611 receives a power source, a video signal, and a synchronization signal, and converts various signals so that the light emitting device 650 can perform processing.
A clock signal and the like for driving the source signal line driver circuit and the gate signal line driver circuit are generated.

The panel 650 includes a pixel portion 601 and a source signal line driver circuit 602 over a substrate.
, A write gate signal line drive circuit 603, an erase gate signal line drive circuit 604, a reverse bias gate signal line drive circuit 605, an FPC 606, and the like are arranged.

A pixel portion 601 is disposed in the central portion of the substrate, and a source signal line driving circuit 602, a writing gate signal line driving circuit 603, an erasing gate signal line driving circuit 604, and a reverse bias gate are provided in the periphery thereof. A signal line driver circuit 605 and the like are arranged.
The counter electrode of the EL element is formed on the entire surface of the pixel portion 601, and a counter potential is applied through the FPC 606. Signals for driving the source signal line drive circuit 602, the write gate signal line drive circuit 603, the erase gate signal line drive circuit 604, the reverse bias gate signal line drive circuit 605, and the supply of power are supplied by the FPC 60.
6 from the drive circuit 660.

Further, as shown in FIG. 6B, when the erase period and the reverse bias period are provided at the same timing, the erase / reverse bias gate signal line drive circuit 607,
The same drive circuit can be used, and the frame can be narrowed.

A light emitting device 1201 shown in this embodiment includes a panel 650 and a signal generation unit 611.
In addition, the driving circuit 660 including the power supply unit 612 is formed independently, but these may be formed integrally on a substrate.

FIG. 7 shows a schematic diagram of a source signal line driver circuit and FIG. 8 shows a schematic diagram of a gate signal line driver circuit when displaying a video using a digital video signal.

The source signal line driver circuit includes a shift register 702 using a plurality of stages of D flip-flops 701, a first latch circuit 703a, a second latch circuit 703b,
A level shifter 704, a buffer 705, and the like are included. The signal input from the outside is
Clock signal (S-CK), inverted clock signal (S-CKb), start pulse (S
-SP), a digital video signal. In the case of the configuration as shown in FIG. 7, the digital video signal is, for example, “the first row of the most significant bit → the second row →... The last row, the first row of the second bit → the second row →. The last row,..., The first row of the least significant bit, the second row, and the last row are input in series.

First, sampling pulses are sequentially output from the shift register 702 in accordance with the timing of the clock signal, the clock inversion signal, and the start pulse.
Subsequently, the sampling pulse is input to the first latch circuit 703a, and the digital video signal for each bit is captured and held at the timing when the sampling pulse is input. This operation is performed in order from the first column.

When the holding of the digital video signal is completed in the first latch circuit 703a at the final stage, a latch pulse is input during the horizontal blanking period. At this timing, the digital video signal held in the first latch circuit 703a is , All at once are transferred to the second latch circuit 703b. Thereafter, the level shifter receives pulse amplitude conversion, and after the video signal waveform is shaped in the buffer, it is output to the respective source signal lines S1 to Sx.

On the other hand, the gate signal line driver circuit includes a shift register 802 using a plurality of stages of D-flip flops 801, a level shifter 803, a buffer 804, and the like.
Signals input from the outside are the clock signal (G-CK) and the inverted clock signal (G-
CKb) and a start pulse (G-SP).

First, pulses are sequentially output from the shift register 802 in accordance with the timing of the clock signal, the clock inversion signal, and the start pulse. Subsequently, the amplitude of the pulse is received by the level shifter 803. Subsequently, after the pulse waveform is shaped in the buffer, the pulse is output to each gate signal line as a pulse for sequentially selecting the gate signal lines G1 to Gy. When the selection on the last line Gy is finished,
After the vertical blanking period, a pulse is output again from the shift register 802, and the gate signal lines are selected in order.

Further, when the first and third embodiments are adopted and pulses having exactly the same timing are input to the erase gate signal line and the reverse bias gate signal line, the erase gate signal line is driven by the method shown in FIG. The circuit and the reverse bias gate signal line driving circuit can be made the same, and the frame can be narrowed.

9 includes a shift register 902 using a plurality of stages of D-flip flops 901, a level shifter 903, a buffer 904, a voltage conversion circuit 905, and the like. Signals input from the outside are a clock signal (G-CK), an inverted clock signal (G-CKb), and a start pulse (G-SP).

The operation is almost the same as that of the gate signal line driving circuit described above. Shift register 90
The pulses sequentially output from 2 are subjected to amplitude conversion by the level shifter 903, and after being subjected to pulse waveform shaping by the buffer 904, the pulses are output to the erasing gate signal lines G1 to Gy as they are, and to the voltage conversion circuit 905. It is divided into what is input. The latter is converted into a pulse having a desired amplitude (between V _{H and} V _L ) by the voltage conversion circuit 905 and output to the reverse bias gate signal lines Gb1 to Gby. The voltage conversion circuit 905 may be provided on the side of the erasing gate signal lines G1 to Gy.

The actual operation timing when the pixel configuration described in the embodiment is SES-driven and a reverse bias is applied will be described with reference to FIGS.

  First, normal SES driving will be described with reference to FIG.

One frame period is divided into a plurality of subframe periods. Here, as an example, it is divided into six subframe periods SF1 to SF6. Each subframe period includes an address (writing) period Ta and a sustain (light emission) period Ts.
The sustain (light emission) period of each subframe period is different in length, and the light emission time of each pixel per frame period is determined depending on which subframe the EL element emits light. Perform gradation display.

Here, as the number of subframe periods is increased, multi-grayscale display is possible, but in some subframe periods, the sustain (light emission) period is shorter than the address (write) period. appear. In this case, since the address (write) periods included in different subframe periods cannot be overlapped, a reset period Tr and an erase period Te are further provided.

The reset period Tr is a period during which a signal for forcibly turning off the EL element is input to the pixel, and the erase period Tr is based on the signal input during the reset period.
This is a period during which the non-light emitting state of the EL element continues.

As an operation, first, in the address (write) period Ta1 of SF1, pulses are input to the write gate signal line in order from the first row, and the digital video signal output to the source signal line is written. In the row where the digital video signal is written, the operation immediately proceeds to the sustain (light emission) period Ts1. When the writing operation is completed from the first line to the last line, the address (writing) period Ta1 ends. Next, from the first row where the sustain (light emission) period Ta1 ends, a pulse is input to the write gate signal line, and an address (write) period Ta2 of SF2 is started.

The above operation is repeated, SF2 and SF3 are finished, and an address (write) period Ta4 of SF4 is started. Here, since the address (write) period Ta4 is longer than the sustain (light emission) period Ts4, the next address (write) period Ta5 cannot be started immediately after the end of the sustain (light emission) period Ts4. Therefore, the reset period Tr4 is started from the first row where the sustain (light emission) period Ts4 ends. The length of the erase period Te4 at this time is usually the length from the end of the sustain (light emission) period of the first row to the end of the address (write) period of the last row as shown in FIG. It becomes.

Subsequently, the address (write) period Ta5 of SF5 is started. SF5, SF
When 6 is completed, one frame period ends and the next frame period is reached.

Next, the operation timing in the circuits shown in Embodiments 1 to 4 is shown in FIG.
This will be described using 0.

One frame period is divided into six subframe periods SF1 to SF6. Each sub-frame has an address (writing) period Ta and a sustain (light emission) period Ts. In addition, subframes (here, SF4, SF5, and SF6 correspond) in which the address (write) period Ta is longer than the sustain (light emission) period Ts are address (write).
In addition to the period Ta and the sustain (light emission) period Ts, the reset period Tr and the erase period Te
, A reverse bias period Tb and a reverse bias application period Ti.

The address (writing) period Ta is a period in which a digital video signal is written to the pixel, and the sustain (light emission) period Ts is an EL element that emits light based on the written digital video signal in the address (writing) period, or This is a period in which a non-light emitting state is taken. The light emission time of each pixel per frame period is determined depending on which subframe period the EL element emits light, and gradation display is performed based on this length.

The reset period Tr is a period during which a signal for forcibly turning off the EL element is input to the pixel, and the erase period Tr is based on the signal input during the reset period.
This is a period during which the non-light emitting state of EL continues. The reverse bias period Tb is a period during which a signal for applying a reverse bias to the EL element is input to the pixel, and the reverse bias application period Ti is a signal input during the reverse bias period Tb. Based on this, this is a period in which the reverse bias is applied to the EL element.

As an operation, first, in the address (write) period Ta1 of SF1, pulses are input to the write gate signal line in order from the first row, and the digital video signal output to the source signal line is written. In the row where the digital video signal is written, the operation immediately proceeds to the sustain (light emission) period Ts1. When the writing operation is completed from the first line to the last line, the address (writing) period Ta1 ends. Next, sustain (emission)
From the first row where the period Ta1 ends, a pulse is input to the write gate signal line, and S
The address (write) period Ta2 of F2 is started.

The above operation is repeated, SF2 and SF3 are completed, and the address of SF4 (writing)
Period Ta4 is started. Here, the address (write) period Ta4 is the sustain period.
Since it is longer than the (light emission) period Ts4, the next address (writing) period Ta5 cannot be started immediately after the end of the sustain (light emission) period Ts4. Therefore, the reset period Tr4 is started from the first row where the sustain (light emission) period Ts4 ends. The length of the erasing period Te4 at this time is usually the length from the end of the sustain (light emission) period of the first row until the end of the address (writing) period of the last row as shown in FIG. It becomes.

At this time, the reverse bias period Tb4 is started at the same time as the reset period Tr4, the erase period Te4 and the reverse bias application period are simultaneous, and the reverse bias is applied to each row. Subsequently, the address (write) period Ta5 of SF5
Is started. When SF5 and SF6 are finished, one frame period is finished and the next frame period is reached.

As shown in FIG. 10B, the erase / reverse bias application period Tei4, Tei5,
It is also possible to adjust the time during which the reverse bias is applied to the EL element by extending Tei6 to an arbitrary length.

Further, when the first and third embodiments are adopted, as shown in FIG. 10C, the reset period Tr4 and the reverse bias period Tb4 can be made independent, and the reverse bias application period Ti4 is the erase period Te4. And the reverse bias period Tb adjacent to each other can be arbitrarily set, and the time during which the reverse bias is applied to the EL element can be adjusted.

Further, here, the case where only the subframe in which the address (write) period Ta is longer than the sustain (light emission) period Ts has the reset period Tr, the erase period Te, the reverse bias period Tb, and the reverse bias application period Ti has been described. However, the address (write) period Ta is shorter than the sustain (light emission) period Ts, or each period is provided in a subframe period having the same length, and a reverse bias can be applied to the EL element.

In addition, when it is desired to increase the number of display gradations, the number of subframe periods may be increased, and the order of subframe periods does not necessarily have to be the order of upper bits → lower bits, and is random during one frame period. You may line up.

FIG. 5A shows an example of an element layout in the case where a pixel having the configuration of FIG. 1 shown in Embodiment Mode 1 is actually manufactured. FIG. 5B shows a cross-sectional view of a portion indicated by XX ′ in FIG.

In FIG. 5B, reference numeral 500 denotes a substrate having an insulating surface. On the substrate 500, a driving TFT 507 and the like are provided, and source / drain electrodes made of a wiring material are formed so as to be connected to an impurity region that forms a source / drain region of the driving TFT 507. The pixel electrode 509 is provided so as to be connected at an overlapping portion. An organic conductor film 522 is provided on the pixel electrode 509, and an organic thin film (light emitting layer) 523 is further provided. Organic thin film (light emitting layer) 52
3 is provided with a counter electrode 524. The counter electrode 524 is formed in a solid form so as to be commonly connected to all the pixels.

Among them, what is described as an EL element in the text corresponds to a stacked body of a pixel electrode 509, an organic conductor film 522, an organic thin film (light emitting layer) 523, and a counter electrode 524 in FIG. One of the pixel electrode 509 and the counter electrode 524 is an anode, and the other is a cathode.

Light emitted from the organic thin film (light emitting layer) 523 is emitted through either the pixel electrode 509 or the counter electrode 524. At this time, in FIG.
The case where light is emitted to the pixel electrode side, that is, the side where the TFT or the like is formed is called bottom emission, and the case where light is emitted to the counter electrode side is called top emission.

In the case of bottom emission, the pixel electrode 509 is formed of a transparent conductive film. Conversely, in the case of top emission, the counter electrode 524 is formed of a transparent conductive film.

Note that the structure shown in this embodiment is merely an example, and the pixel layout, the cross-sectional structure, the stacking order of the electrodes of the EL element, and the like are not limited thereto.

In a light emitting device for color display, EL elements having emission colors of R, G, and B may be separately applied, or a monochrome EL element may be applied in a solid form, and R, G, and B may be applied by a color filter. You may make it obtain light emission.

In this example, in a light emitting device in which a polymer compound is applied as a light emitting layer and a buffer layer made of a conductive polymer compound is provided between the anode and the light emitting layer,
The following describes the results of measurement of luminance degradation during direct current drive (always forward bias applied) and alternating current drive (forward bias and reverse bias applied alternately at fixed intervals).

14A and 14B show a forward bias: 3.7 V, a reverse bias: 1.7 V,
The result of the reliability test at the time of performing an alternating current drive in 50% duty and 60 Hz alternating frequency is shown. The initial luminance was about 400 cd / cm ² . For comparison, the results of a reliability test when DC driving (forward bias: 3.65 V) was performed are also shown. As a result, in the direct current drive, the luminance was reduced by half in about 400 hours, whereas in the alternating current drive, even after about 700 hours, the brightness was not reduced to half.

14C and 14D show the forward bias: 3.8V, the reverse bias: 1.7V,
The result of the reliability test at the time of performing an alternating current drive in 50% duty and 600 Hz alternating frequency is shown. The initial luminance was about 300 cd / cm ² . For comparison, the results of a reliability test when DC driving (forward bias: 3.65 V) was performed are also shown. As a result, in direct current drive, the brightness was halved in about 500 hours,
In AC driving, about 60% of the initial luminance was maintained after about 700 hours.

Since the light-emitting device using a light-emitting element is a self-luminous type, compared to a liquid crystal display,
Excellent visibility in bright places and wide viewing angle. Therefore, it can be used for display portions of various electronic devices.

As an electronic device using the light emitting device of the present invention, a video camera, a digital camera,
Goggle type display (head mounted display), navigation system, sound playback device (car audio, audio component, etc.), notebook type personal computer, game machine, portable information terminal (mobile computer, mobile phone,
A portable game machine or an electronic book), and an image playback device (specifically, a recording medium)
And a device equipped with a display capable of reproducing a recording medium such as a digital versatile disc (DVD) and displaying the image thereof. In particular, it is desirable to use a light-emitting device for a portable information terminal that often has an opportunity to see a screen from an oblique direction because the wide viewing angle is important. Specific examples of these electronic devices are shown in FIGS.

FIG. 13A illustrates an EL display, which includes a housing 3001, an audio output unit 3002,
A display portion 3003 and the like are included. The light emitting device of the present invention can be used for the display portion 3003. Since the light-emitting device is a self-luminous type, a backlight is not necessary, and a display portion thinner than a liquid crystal display can be obtained. The light emitting element display device includes all information display devices such as a personal computer, a TV broadcast receiver, and an advertisement display.

FIG. 13C illustrates a large EL display, which includes a housing 3021, an audio output portion 3022, and a display portion 3023 as in FIG. 13A. The light emitting device of the present invention can be used for the display portion 3023.

FIG. 13B illustrates a mobile computer, which includes a main body 3011 and a stylus 3012.
, A display unit 3013, operation buttons 3014, an external interface 3015, and the like. The light emitting device of the present invention can be used for the display portion 3013.

FIG. 13D illustrates a game machine, which includes a main body 3031, a display portion 3032, and operation buttons 3.
033 etc. are included. The light-emitting device of the present invention can be used for the display portion 3032.

FIG. 13E illustrates a mobile phone, which includes a main body 3041, an audio output portion 3042, an audio input portion 3043, a display portion 3044, operation switches 3045, an antenna 3046, and the like. The light emitting device of the present invention can be used for the display portion 3044. Display unit 3
No. 044 can suppress current consumption of the mobile phone by displaying white characters on a black background.

If the light emission luminance of the organic light emitting material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used for a front type or rear type projector.

In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the organic light emitting material has a very high response speed, the light emitting device is preferable for displaying moving images.

In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background. It is desirable to do.

As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic device of this embodiment may use the light emitting device having any structure shown in Embodiments 1 to 5.

The figure which shows one Embodiment of this invention. The figure which shows one Embodiment of this invention. The figure which shows one Embodiment of this invention. The figure which shows one Embodiment of this invention. 4A and 4B are a pixel portion layout example and a cross-sectional view of a light-emitting device manufactured by applying the present invention. FIG. 3 is a block diagram illustrating a structure of a light-emitting device. FIG. 6 is a diagram illustrating a configuration example of a source signal line driver circuit. FIG. 6 is a diagram illustrating a configuration example of a gate signal line driver circuit. The figure which shows the example of 1 structure of the gate signal line drive circuit shared by erase and reverse bias. The figure which shows the timing chart of SES drive which provided the reverse direction bias period. The figure which shows the timing chart of normal SES drive. FIG. 14 illustrates a light-emitting device incorporated in an electronic device. FIG. 11 illustrates an example of an electronic device to which the present invention is applicable. The figure which shows the result of the reliability test in direct current drive and alternating current drive.

Explanation of symbols

101 Source signal line 102 Write gate signal line 103 Erase gate signal line 104 Reverse bias gate signal line 105 Switching TFT
106 TFT for erasing
107 Driving TFT
108 Reverse bias TFT
109 EL element 110 Capacitance 111 Current supply line 112 Reverse bias power line 113 Opposite power line

Claims (6)

A driving method of a light emitting device having a pixel including a light emitting element,
One frame period has n (n is a natural number, 2 <n) subframe periods,
Each of the n subframe periods is
An address period for writing video signals to the pixels;
A sustain period during which the light emitting element emits light or does not emit light based on the video signal,
The m subframe periods (m is a natural number, 0 <m ≦ n−1) selected from the n subframe periods are respectively
Based on a reset signal written to the pixel, the light emitting element has an erasing period in which the pixel does not emit light,
Each of the k subframe periods (k is a natural number, 0 <k ≦ m) selected from the m subframe periods,
A reverse bias application period in which a reverse bias voltage is applied to the light emitting element based on a signal for applying a reverse bias voltage written to the pixel;
A driving method of a light emitting device, wherein the erasing period and the reverse bias application period overlap. Oite to claim 1,
Wherein a forward bias voltage V ₁ applied to the light emitting element when the light emitting element emits light, the reverse bias voltage V ₂ polarity inverted with respect to the forward bias voltage, _| V 1 | ≧ | A driving method of a light-emitting device characterized by satisfying V ₂ |. A driving method of a light emitting device having a pixel including first to fourth transistors and a light emitting element,
The gate electrode of the first transistor is electrically connected to a first gate signal line, the first electrode is electrically connected to a source signal line, and the second electrode is connected to the second transistor. Electrically connected to the first electrode and the gate electrode of the third transistor,
A gate electrode of the second transistor is electrically connected to a second gate signal line; a second electrode is electrically connected to the first power supply line;
The first electrode of the third transistor, said the first power supply line and electrically connected to the second electrode, the first of the first electrode 及 beauty said fourth transistor of said light emitting element Electrically connected to the electrode,
A gate electrode of the fourth transistor is electrically connected to a third gate signal line; a second electrode is electrically connected to a second power supply line;
A second electrode of the light emitting element is electrically connected to a third power supply line;
Within one frame period
A first period in which the first transistor is on, and the second and fourth transistors are off;
A second period in which the first, second, and fourth transistors are off;
A third period in which the second transistor is on, and the first, third, and fourth transistors are off;
A fourth period in which the first, second and third transistors are off and the fourth transistor is on;
In the third period, the light emitting element does not emit light,
A driving method of a light-emitting device, wherein a reverse bias voltage is applied to the light-emitting element in the fourth period. A driving method of a light emitting device having a pixel including first to fourth transistors and a light emitting element,
The gate electrode of the first transistor is electrically connected to a first gate signal line, the first electrode is electrically connected to a source signal line, and the second electrode is connected to the second transistor. Electrically connected to the first electrode and the gate electrode of the third transistor,
A gate electrode of the second transistor is electrically connected to a second gate signal line; a second electrode is electrically connected to the first power supply line;
The first electrode of the third transistor, said the first power supply line and electrically connected to the second electrode, the first of the first electrode 及 beauty said fourth transistor of said light emitting element Electrically connected to the electrode,
A gate electrode of the fourth transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to the second power supply line;
A second electrode of the light emitting element is electrically connected to a third power supply line;
Within one frame period
A first period in which the first transistor is on, and the second and fourth transistors are off;
A second period in which the first, second, and fourth transistors are off;
A third period in which the first and third transistors are off, and the second and fourth transistors are on,
A driving method of a light emitting device, wherein a reverse bias voltage is applied to the light emitting element in the third period. A driving method of a light emitting device having a pixel including first to fourth transistors and a light emitting element,
The gate electrode of the first transistor is electrically connected to a first gate signal line, the first electrode is electrically connected to a source signal line, and the second electrode is connected to the second transistor. Electrically connected to the gate electrode of
A first electrode of the second transistor is electrically connected to a first power supply line; a second electrode is electrically connected to a first electrode of the third transistor;
The gate electrode of the third transistor is connected to the second electrically gate signal line, a second electrode, a first electrode of the first electrode 及 beauty the light emitting element of the fourth transistor Electrically connected,
A gate electrode of the fourth transistor is electrically connected to a third gate signal line; a second electrode is electrically connected to a second power supply line;
A second electrode of the light emitting element is electrically connected to a third power supply line;
Within one frame period
A first period in which the first and third transistors are on and the fourth transistor is off;
A second period in which the third transistor is on, and the first and fourth transistors are off;
A third period in which the first, third, and fourth transistors are off;
A fourth period in which the first and third transistors are off and the fourth transistor is on,
In the third period, the light emitting element does not emit light,
A driving method of a light-emitting device, wherein a reverse bias voltage is applied to the light-emitting element in the fourth period. A driving method of a light emitting device having a pixel including first to fourth transistors and a light emitting element,
The gate electrode of the first transistor is electrically connected to a first gate signal line, the first electrode is electrically connected to a source signal line, and the second electrode is connected to the second transistor. Electrically connected to the gate electrode of
A first electrode of the second transistor is electrically connected to a first power supply line; a second electrode is electrically connected to a first electrode of the third transistor;
The gate electrode of the third transistor is connected to the second electrically gate signal line, a second electrode, a first electrode of the first electrode 及 beauty the light emitting element of the fourth transistor Electrically connected,
A gate electrode of the fourth transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to a second power supply line;
A second electrode of the light emitting element is electrically connected to a third power supply line;
Within one frame period
A first period in which the first and third transistors are on and the fourth transistor is off;
A second period in which the third transistor is on and the first and fourth transistors are off;
A third period in which the first and third transistors are off and the fourth transistor is on,
A driving method of a light-emitting device, wherein a reverse bias voltage is applied to the light-emitting element in the third period.

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