JP2002043913A - Buffer circuit and semiconductor power converting apparatus using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buffer circuit that instantaneously controls an output voltage to have a level of an input voltage and suppresses a generated loss even when a capacitive load is connected to an output of the buffer circuit. SOLUTION: A speed up transistor(TR) is connected in parallel with a resistor through which a base current is supplied to a base of a TR connected to an emitter follower. Since the base current can be supplied to the TR of the emitter follower via the speedup TR, even when a capacitive load is connected to an output of the buffer circuit, the output potential is instantaneously brought into an input potential through charging/discharging by a large current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an analog circuit using a transistor, and more particularly to a so-called buffer circuit having a function of transmitting an input potential to an output, and a semiconductor power conversion device using the same.

[0002]

2. Description of the Related Art As a circuit for transmitting the potential of an input point to an output point, there is known a buffer circuit using a transistor as introduced on pages 81 to 85 of "Design of Transistor Circuit (CQ Publishing)". I have. Only the main parts are extracted in FIGS. In any of the circuit systems, when the input potential becomes higher than the output potential, the transistor 1 is turned on to increase the output voltage. On the other hand, when the potential at the input point becomes lower than the potential at the output point, the transistor 2 is turned on and the transistor 1 is turned off. Thus, the output potential is controlled so as to decrease and follow the input potential.

However, in order for the transistor to turn on, the potential difference between the base potential and the emitter potential needs to exceed the built-in voltage between the base and the emitter. Therefore, in the buffer circuit of FIG. 2, in order for transistor 1 to be turned on, the input potential must be higher than the output potential by "the built-in voltage between the base and the emitter of transistor 1" and transistor 2 is turned on. Requires that the input voltage be lower than the output voltage by "the built-in voltage between the base and the emitter of the transistor 2".

Therefore, if the potential difference between the input and output of the buffer circuit is smaller than the built-in state of the transistor,
Since both the transistor 1 and the transistor 2 remain off, the buffer circuit cannot control the potential at the output point.
That is, the potential of the output point includes an error corresponding to the built-in voltage between the base and the emitter of the transistor with respect to the potential of the input point.

FIGS. 3 and 4 show a circuit system for reducing this error. This will be described with reference to FIG. Diode 3
And diode 4 are always on, and diode 3
, The base of transistor 1 is higher than the input point voltage by the built-in voltage of diode 3. Similarly, the cathode of the diode 4, that is, the transistor 2
Is lower than the voltage at the input point by the built-in voltage of the diode 4. By canceling the base-emitter potential of the transistor, the output voltage can be controlled to the input voltage with a very small error. In FIG. 4, the pn junction between the base and the emitter of the transistors 5 and 6 functions similarly to the diodes 3 and 4.

Although these buffer circuits are used for various purposes, they are often used for IGBT gate drivers of IGBT power converters. For example, IEEE, IA
S International Conference 1998 Conference Material "Series Connection of Hi
gh Voltage IGBT Modules ”as used in gate drivers with overvoltage protection. When an arm of the IGBT power converter is turned off, a surge voltage is applied to the arm by the energy stored in the wiring at the time of turning off. In the overvoltage protection technique disclosed in this document, the collector voltage is divided by a resistor or the like, and the gate driver is provided with an active gate control function of controlling the gate voltage at the voltage at the voltage dividing point, thereby suppressing the overvoltage. As shown in FIG. 6, when the voltage dividing point and the gate of the IGBT are connected via a buffer circuit, the gate voltage is controlled so as to be the voltage at the voltage dividing point, and the above-described active gate control can be easily realized.

Referring to FIG. 6, a gate driver and an IGB
The operation of T will be described. When the on / off pulse generator 37 outputs a negative potential while the IGBT 31 is in the on state, the charge stored in the gate of the IGBT 31 is extracted through the gate resistor 38, the gate voltage is reduced, and the IGBT 31 is turned off and the collector of the IGBT 31 is turned off. The voltage rises. IG
Even when a surge overvoltage is applied to the collector of the BT31, if this control method is used, the potential of the voltage dividing point follows the rise according to the collector voltage of the IGBT31, the gate voltage of the IGBT31 also increases, and the impedance of the IGBT31 increases. Since it decreases, the rise of the collector voltage of the IGBT 31 can be clamped to protect the element from overvoltage destruction.

[0008]

As described above, buffer circuits are used in various fields. However, a capacitive load such as an insulated gate (M) of an insulated gate semiconductor switching element such as an IGBT or MOSFET is used.
When the OS gate is connected, there arises a problem that the output voltage cannot instantaneously follow a change in the input voltage. FIG.
In this buffer, the base current of the transistor 1 or the transistor 2 is supplied via the resistor 7 or 8. In order to instantaneously control the output voltage to the input voltage, it is necessary to charge / discharge the capacitive load with a large current via the transistor 1 or the transistor 2.
Is limited by the resistor 7 or the resistor 8 and a sufficient current cannot be supplied. If the resistance values of the resistor 7 and the resistor 8 are reduced, the base current can be supplied abundantly.
-Since current constantly flows through the path of the resistor 8, there is a problem that power consumption (loss) of the buffer circuit increases.

[0009] The above-mentioned problem is described in the document "Series Connection of High Vol.
IGBT Modules ”, the active gate control method introduced in FIG. 3 and the main circuit power supply method via a voltage dividing resistor as introduced in“ The main circuit power supply method of the gate power supply for IGBT converter ”at the 1999 IEEJ National Convention. This makes it difficult to achieve a technology for self-supply of gate power that supplies energy for operating a gate driver from a circuit. Because, in active gate control, I
If the gate voltage of the GBT cannot instantaneously follow the voltage at the voltage dividing point, the clamping of the collector voltage will fail and the IGBT may fail due to overvoltage application, but since the gate of the IGBT is a capacitive load, In order to instantaneously control the voltage at the voltage point to the gate voltage, the resistance values of the resistors 7 and 8 must be reduced. However, if the resistors 7 and 8 are reduced, the loss of the buffer circuit increases,
It exceeds the energy supplied from the voltage dividing resistor, making it difficult to operate the gate driver.

The active control technology and the main circuit power supply technology of the gate power supply are very important technologies for a power converter in which IGBTs are connected in series. The former is used to adjust the voltage balance between series elements due to non-uniform element characteristics and to protect against overvoltage, and the latter is used to supply power to each gate driver.
There is an advantage that an insulating transformer having a high withstand voltage is not required.

[0011] The present invention has been made in view of the above,
Even with a buffer circuit connected to a capacitive load, a new buffer circuit that instantaneously controls the output voltage to the same voltage as the input voltage and suppresses the generation loss, and both the active control control technology and the main power supply technology for the gate power supply An object is to provide an IGBT power converter to which the technology is applied.

[0012]

In order to solve the above-mentioned problems, the collector and the emitter of a speed-up transistor are connected in parallel to the resistors 7 and 8 in FIGS. 3 and 4, respectively. What is necessary is just to connect the base of the transistor to the input of the buffer circuit.

It is assumed that the voltage at the input terminal changes abruptly, that is, the input and output of the buffer circuit are out of balance. Here, it is assumed that the input potential suddenly increases. Since the input potential becomes higher than the output potential, a base transistor can be supplied to the output transistor abundantly by turning on the speed-up transistor connected in parallel to the negative resistor. On the other hand, in the steady state, all of the speed-up transistors are turned off, so that the input and output voltages can be made substantially equal, as in the circuits of FIGS. Further, since the speed-up transistor is off, the steady-state loss is negligible.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings describing the embodiments, components having the same functions are denoted by the same reference numerals. (Embodiment 1) The circuit configuration of the first embodiment will be described with reference to FIG. Power supply lines 90 and 91 having different potentials
Between them, the NPN transistor 1 and the PNP transistor 2 are complementarily connected in the form of an emitter follower. The power supply line 90 has a higher potential than the power supply line 91. Base of transistor 1 and input 60 of buffer circuit
Are connected via the built-in compensation diode 3. Similarly, the base of the transistor 2 and the input 60 are connected via the built-in compensation diode 4. Further, the base of the transistor 1 is connected to the power supply line 90 via the resistor 7. An NPN-type speed-up transistor 9 is connected in parallel to the resistor 7, and the base of the transistor 9 is connected to the input 60. The base of transistor 2 is connected to power supply line 91 via resistor 8. A PNP-type speed-up transistor 10 is connected in parallel with the resistor 8, and the base of the transistor 10 is connected to the input. On the other hand, between each emitter of the transistor 1 and the transistor 2 is connected to the output, and the output is connected to the capacitive load 8.
1 is connected.

Next, the operation will be described.

First, assume that the potential of the input 60 has become higher than the potential of the output 61. Input 60 potential is output 6
When the potential becomes higher than 1, the transistor 1 and the speed-up transistor 9 are turned on, and the transistor 2 and the speed-up transistor 10 are turned off. Even if the resistance value of the resistor 7 is large, the abundant base current is supplied to the transistor 1 via the speed-up transistor 9, so that the capacitive load 81 can be rapidly charged by the large current via the transistor 1. , The potential of the output 61 can be instantaneously controlled to the potential of the input 60. Next, it is assumed that the potential of the input 60 is lower than the potential of the output 61. The transistor 2 and the speed-up transistor 10 are turned on because the base potential is lower than the emitter potential, and the transistor 1 and the speed-up transistor 9 are turned off. Even if the resistance value of the resistor 8 is large, abundant base current is supplied to the transistor 2 via the speed-up transistor 10.
The electric charge of the capacitive load 81 can be rapidly discharged by the large current via the transistor 2, and the potential of the output 61 can be instantaneously controlled to the potential of the input 60.

On the other hand, when the potential difference between the input 60 and the output 61 is small (when the potential difference between the input 60 and the output 61 is smaller than the built-in voltage between the base and the emitter of the transistor 9 or the transistor 10), the speed-up transistor 9 and the speed-up transistor 9 are increased. Since the transistor 10 is turned off, a current flowing from the power supply line 90 to the power supply line 90 via the diode 3 and the diode 4 is generated because it is a very small current passing through the resistor 7 and the resistor 8. There is little loss. Although a very small amount of current flows from the power supply line 91 to the power supply line 91 via the resistor 7, the diode 3, the diode 4, and the resistor 8, the impedance of the diode 3 or the diode 4 decreases. And the impedance between the base and the emitter of the transistor 10 is smaller than the impedance between the base and the emitter of the transistor 10, so that the built-in voltage of the diode 3 and the diode 4 compensates for the built-in voltage of the base-emitter voltage of the transistor 1 and the transistor 2, and the potential of the input 60 and the output 61 Can be adjusted within an extremely small error range. (Embodiment 2) A circuit configuration of a second embodiment will be described with reference to FIG. Power supply lines 90 and 91 having different potentials
In the meantime, the transistor 1 and the transistor are complementary connected in the form of an emitter follower. Power line 90
Has a higher potential than the power supply line 91. The base and input of the transistor 1 are connected via the emitter and base of the built-in compensation transistor 5. The collector of built-in compensation transistor 5 is connected to power supply line 91.
Similarly, the base and the input of the transistor 2 are connected via the emitter and the base of the built-in compensation transistor 6. The collector of built-in compensation transistor 6 is connected to power supply line 90. Further, the base of the transistor 1 is connected to the power supply line 90 via the resistor 7. A speed-up transistor 9 is connected to the resistor 7 in parallel, and the base of the transistor 9 is connected to the input. The base of transistor 2 is connected to power supply line 91 via resistor 8. A speed-up transistor 10 is connected to the resistor 8 in parallel, and the base of the transistor 10 is connected to the input.

On the other hand, between the emitters of the transistor 1 and the transistor 2 is connected to an output, and a capacitive load 8 is connected to the output.
1 is connected.

Next, the operation will be described.

If the input potential is within the range between the power supply line 90 and the power supply line 91, the built-in compensation transistor 5 and the built-in compensation transistor 6 are always on.
The built-in voltage between the base and the emitter of the transistor 1 and the transistor 2 is applied between the base and the emitter of the transistor 5 and between the cathode and the anode of the built-in compensation diode 4 of the first embodiment. It works to compensate.

First, assume a situation in which the potential of the input 60 has become higher than the potential of the output 61. The transistor 2 and the speed-up transistor 10 are turned off because the base potential is lower than the emitter potential, and the transistor 1 and the speed-up transistor 9 are turned on. Even if the resistance value of the resistor 7 is large, the abundant base current is supplied to the transistor 1 via the speed-up transistor 9, so that the capacitive load 81 can be rapidly charged by the large current via the transistor 1. , The potential of the output 61 can be instantaneously controlled to the potential of the input 60. next,
Assume that the potential of the input 60 is lower than the potential of the output 61. The transistor 2 and the speed-up transistor 10 are turned on because the base potential is lower than the emitter potential, and the transistor 1 and the speed-up transistor 9 are turned off. Even if the resistance value of the resistor 8 is large, abundant base current is supplied to the transistor 2 via the speed-up transistor 10, so that the capacitive load 8 is rapidly supplied by the large current via the transistor 2.
1 can be discharged, and the potential of the output 61 can be instantaneously controlled to the potential of the input 60.

On the other hand, when the potential difference between the input 60 and the output 61 is small (when the potential difference between the input 60 and the output 61 is smaller than the built-in voltage between the base and the emitter of the transistor 9 or the transistor 10), the speedup transistor 9 and the speedup transistor 9 are used. Since the transistor 10 is turned off, a current flowing from the power supply line 60 to the power supply line 90 via the transistor 5 and the transistor 6 is generated because the current is a very small current passing through the resistor 7 and the resistor 8. There is little loss. However, although very small, the power supply line 90 → the resistor 7 → the transistor 5 → the power supply line 91 or the power supply line 90 → the transistor 6 → the resistor 8 → the power supply line 9
1 because there is a current flowing through the
Since the impedance between the base and the emitter of the transistor 6 becomes smaller than the impedance between the base and the emitter of the transistor 9 and the transistor 10, the built-in voltage between the base and the emitter of the transistor 5 and the transistor 6 becomes lower than the base of the transistor 1 and the transistor 2. Compensate for the built-in voltage of the emitter-to-emitter voltage, and
The potential of 0 and the potential of the output 61 can be aligned within a very small error range. Embodiment 3 The third embodiment is characterized in that the buffer shown in FIG. 1 or FIG. 7 is applied to a part of a gate driver for driving an IGBT forming an arm of a power converter.

First, the configuration of the power converter will be described with reference to FIGS. FIG. 5 shows a main part of a power converter to which the present invention is applied, and FIG. 6 shows a configuration of a main part of the arm of FIG. The configuration of the arm 20 is as follows. IGBT31
Is connected to the freewheeling diode 32 in antiparallel. Also, IG
An on / off pulse generator 37 for generating an on / off signal for a switching command is connected to the gate of the BT 31 via a gate resistor 38. Power is supplied from a power supply 43 to the pulse generator 37. A high-voltage-side voltage dividing resistor 33 and a low-voltage-side voltage dividing resistor 34 are connected between the collector terminal and the emitter terminal of the IGBT 31. Further, the voltage dividing point 60 and the gate of the IGBT 31 are connected via a buffer circuit 36.
The circuit configuration shown in FIG.

As shown in FIG. 5, in the power converter, 2
Three arms 20 connected in series are connected in parallel, and each arm is connected to a DC voltage source 21. Each midpoint of the paired arms is connected to a load 22.

Next, the operation will be described. The power necessary for the operation of the pulse generator 37 is supplied from the power supply 43, and the PWM or P
The drive signal controlled by the AM control is output to the pulse generator 3
Generated from 7. The generated drive signal is input to the gate of the IGBT via the gate resistor 38 and the IGBT 31
Is turned on or off, the arm 20 is turned on and off, an AC voltage is generated, and the load 22 is applied. Do not turn on the paired arms at the same time (for example,
Arm 20 (P) and arm 20 (N)).

Here, the on / off control of the arm 20 (N) and the arm 20 (P) is alternately performed, and attention is paid to the case where the drive signal to the arm 20 (P) is on and the arm 20 (N) is off. . When the arm 20 (P) is on, the current is
It flows from a DC voltage source 21 through a path such as an arm 20 (P) and an inductance load 22. When the arm 20 (P) is turned off, the wiring inductance existing in the path of the main circuit (DC voltage source 21 → arm 20 (P) → arm 20 (N) → DC voltage source 21) is provided to the arm 20 (P). The voltage generated at 23 is superimposed on the voltage of the DC voltage source 21 and applied to the arm 20, so that the collector voltage of the IGBT 31 increases. As the collector voltage increases, the potential at the voltage dividing point 60 also increases. Since the voltage dividing point and the gate of the IGBT 31 are connected by the buffer having the circuit configuration shown in FIGS. 1 and 7, the gate potential instantaneously follows the potential of the voltage dividing point,
By lowering the impedance of the IGBT 31, the IGBT can be protected from application of an overvoltage between the collector and the emitter of the IGBT 31. In addition, the loss of the buffer can be reduced. (Embodiment 4) FIG. 8 shows a circuit system of a fourth embodiment. The third embodiment is characterized in that the IGBTs are connected in multiple series, while the arms are formed of one series of IGBTs. The buffer circuit 36 includes a circuit configuration having the configuration shown in FIGS. Power for the buffer circuit 36 and the pulse generator 37 was supplied from a power supply 50 via a transformer 49.

When elements having different element characteristics such as gate capacitance are connected in series, an element having a small gate capacitance and a fast turn-off timing turns off earlier than the other elements. As a result, the collector voltage rises sharply as compared with turn-off in one series. However, in the circuit system of the present embodiment, since the voltage dividing point 60 and the gate of the IGBT 31 are connected by the buffer 36 including the circuit configuration of the configuration shown in FIG. 1 and FIG. Can be instantaneously controlled to the potential of the voltage dividing point 60, and application of an overvoltage can be prevented. Also, the transistor 1 is provided in the buffer circuit.
And a device (diodes 3 and 4 or transistors 5 and 6) for compensating the built-in voltage of the transistor 2, so that the IGB
The gate potential of T31 can be accurately controlled. IGBT31
Can accurately control the gate voltage of
This means that the impedance of the GBT 31 can be accurately controlled. Therefore, even in the steady state, each IGB
The voltage of T can be equalized.

The buffer circuit 36 and the pulse generator 3
The same operation can be performed by supplying the power supply 7 from an independent voltage source 43 as shown in FIG. (Embodiment 5) FIG. 9 shows a circuit system of a fifth embodiment. The fourth embodiment is characterized in that the power for gate operation is supplied from a transformer, but is supplied from a main circuit via a voltage dividing resistor 44. The buffer circuit 36 includes a circuit configuration having the configuration shown in FIGS. The current is supplied from the voltage dividing resistor 44 to the Zener diode 45 and the capacitor 46, the voltage is smoothed, and supplied to the power supply line of the gate driver via the DC-DC converter 47. This method can eliminate the insulating transformer. Voltage dividing resistor 44
, The power supplied is small, but as described in the first and second embodiments, since the loss of the buffer circuit is small, sufficient power for gate driving the IGBT 31 can be obtained. (Embodiment 6) In Embodiments 3 to 5, the IGBT 1 is replaced by
The same effect can be obtained by replacing the device with a device that controls on / off by a voltage applied to a MOS gate such as a power MOSFET.

[0029]

Since the base current can be supplied to the emitter follower transistor via the speed-up transistor, even if a capacitive load is connected to the output, the output potential is instantaneously changed to the input potential by charging and discharging with a large current. It can be controlled and the loss is small. Thereby, IG
Since the gate voltage of the BT can be controlled in accordance with the collector voltage, overvoltage protection is facilitated and the power consumption is low.
T can be driven.

[Brief description of the drawings]

FIG. 1 shows a main part of a buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a main part of a buffer circuit according to the related art.

FIG. 3 shows a main part of a buffer circuit according to the related art.

FIG. 4 shows a main part of a buffer circuit according to the prior art.

FIG. 5 is a main part of a power converter to which the present invention is applied.

FIG. 6 shows a main part of one arm of the power converter.

FIG. 7 shows a main part of a buffer circuit according to a second embodiment of the present invention.

FIG. 8 shows a main part of one arm of the power converter.

FIG. 9 shows a main part of one arm of the power converter.

[Explanation of symbols]

1,2 ... transistor, 3,4 ... built-in voltage compensation diode, 5,6 ... built-in voltage compensation transistor, 7,8 ... resistor, 9,10 ... speed-up transistor, 11 ... current backflow prevention diode, 12 ... A point at which the voltage between the collector and the emitter is divided, 13... A power supply for an on / off pulse generator, 15... An inductance, 20... An arm, 20 (P).
BT, 32: reflux diode, 33: high-voltage side voltage dividing resistor,
34: low voltage side voltage dividing resistor, 35: high voltage side voltage dividing resistor parallel capacitor, 36: buffer circuit, 37: on / off pulse generator, 38: gate resistor, 44: voltage dividing resistor, 45: Zener diode, 46: smoothing Capacitors, 47 ... D
C-DC converter, 60 input (voltage division point), 61 output, 81 capacitive load, 90, 91 power line, 612
Output current limiting resistor.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 17/60 H03K 17/60 A (72) Inventor Shigeta Ueda 7-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Hitachi Research Laboratories (72) Inventor Hiromitsu Sakai 1-1-1, Kokubuncho, Hitachi City, Ibaraki Prefecture F-term in the Electric Systems Division, Hitachi, Ltd. F-term (reference) 5H007 AA03 BB06 CA01 CB05 CC07 DB03 FA01 FA13 5H740 AA05 BA11 BB05 BB07 BB08 BB10 HH03 KK01 MM01 5J055 AX02 AX12 AX32 AX64 BX16 CX07 CX12 DX04 DX05 DX09 DX43 DX56 DX84 EX04 EY01 EY03 EY10 EY12 EY13 EY17 EZ61 EZ63 GX01

Claims (5)

[Claims] A pnp is provided between two pairs of power supply lines having different potentials.
A transistor and an npn transistor are complementary connected to each other as an emitter follower, and a device for built-in voltage compensation is provided between a base and an input of each transistor to compensate for a built-in voltage between a base and an emitter of each transistor. A buffer circuit, wherein a resistor is connected between a base of each transistor and a power supply line, and another transistor is connected in parallel with the resistor. 2. The buffer circuit according to claim 1, wherein said built-in voltage compensation device is a built-in voltage compensation diode. 3. The buffer circuit according to claim 1, wherein said built-in voltage compensation device is a built-in voltage compensation transistor. 4. A circuit configuration in which a voltage between an arbitrary potential in the collector of the IGBT and an arbitrary potential in the gate driver is divided by two resistors or a plurality of electric components including the two resistors.
By controlling the potential of the gate of the IGBT to the potential of the voltage dividing point, the overvoltage is prevented from being applied to the collector to prevent the IGBT from
A semiconductor power conversion device having a function of protecting a power supply, wherein a voltage dividing point and a gate driver are connected via the buffer circuit according to any one of claims 1 to 3. 5. A circuit configuration in which a voltage between an arbitrary potential in a collector of a MOS control device and an arbitrary potential in a gate driver is divided by two resistors or a plurality of electric components including two resistors. In a power converter having a function of protecting a MOS control device from application of an overvoltage to a collector by controlling a potential of a gate of the MOS control device to a potential of a point, between a voltage dividing point and a gate driver. 3. A semiconductor power conversion device, wherein the semiconductor power conversion device is connected via any one of the buffer circuits of 3.