JP2002042491A - Semiconductor test apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor test apparatus in which generation of a vector pattern for VPG from an ALPG side can be controlled in real time and the generation of a pattern can be controlled with a synchronous relation, in a semiconductor test device provided with ALPG and VPG. SOLUTION: In an address signal generation in which the control signal of the prescribed number of bits which is generated on the basis of sequence control of ALPG is supplied to VPG, an address pointer provided in the VPG is generated and supplied to a vector memory storing a test vector provided to the VPG, the AP is provided additionally with an ADDRESS jump means which can generate an address signal which can jump to the prescribed jump address according to a control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor test apparatus for generating a test pattern for a device test. In particular, when a semiconductor test apparatus dedicated to a memory device includes an algorithmic pattern generator ALPG and a vector pattern generator VPG, the VPG
The present invention relates to a semiconductor test apparatus capable of real-time controlling the generation of a vector pattern, which is a test pattern for a random logic test, generated from an ALPG.

[0002]

2. Description of the Related Art FIG. 1 is a conceptual configuration diagram of a semiconductor test apparatus. The main components are a timing generator TG, a pattern generator PG, a programmable data selector PDS, a waveform shaper FC, a driver DR, a comparator CP, a logical comparator DC, an address fail And a memory AFM. In this drawing, other signals and components are ordinary components included in the semiconductor test apparatus, except for the main part according to the present application, and need not be described because they are known.

The pattern generator PG according to the present application mainly includes a test pattern (test vector) for testing a memory circuit section.
And a vector pattern generator VPG that is mainly responsible for generating test vectors for testing the logic circuit unit.

[0004] On the other hand, the ALPG is for generating a dedicated test pattern for testing the memory section of the DUT. The ALPG is provided with an internal calculation function to generate a complicated address pattern and generate a data pattern for writing or the like. This is the form that occurs. Therefore, a relatively small capacity of several KW is sufficient for the address space of the sequence control memory. Because of this small capacity, the capacity is insufficient for generating a random test pattern, which is not suitable. To cope with this, a VPG is provided. In the ALPG shown in FIG. 1, a 1-bit control signal CS11 that can be generated as desired based on sequence control is provided.
Is supplied to the VPG. The ALPG is controlled by a tester bus TB based on a tester bus control instruction based on sequence control.
The internal setting conditions of an arbitrary device can be asynchronously changed and controlled via the US. The tester bus TBUS operates with a dedicated clock, and the execution time takes 1 to 2 μs.

As shown in FIG. 2, a main part of the other VPG stores a desired test pattern in a vector memory VM, accesses the vector memory VM while sequentially counting addresses by +1, and continuously accesses the vector memory VM. This is a mode in which test patterns are sequentially generated. For this reason, the address space to be stored has a large memory capacity of several hundred KW or more. This VP
The main components of G are an address pointer (AP) 110
And a vector memory (VM) 120.

The AP 110 has a load input terminal ld and an increment enable input terminal inc.
It generates an output address pointer 110a which is a 0-bit address counter and a 20-bit address signal to be supplied to the VM. The initial value of the address is ALPG
A 20-bit initial value is supplied to the data input terminal D by a tester bus control instruction generated via the tester bus TBUS.
i, and is preset by the load control to the load input terminal ld. Since the preset is asynchronous with the generation of the test pattern, the preset is executed in a paused state after the generation of a group of continuous vector patterns PAT4 is completed. AP when pattern occurs
Is operated by receiving a 1-bit control signal CS11 generated from the ALPG as an increment enable signal INC8. That is, when the increment enable signal INC8 is asserted, the test cycle clock (rate clock) RCLK1 unit
The output address pointer 110a is incremented by one. Then, this output is supplied to the VM.

The VM 120 is a pattern memory having a capacity of, for example, 1 MW × N bits, and stores desired random test pattern contents in advance.
A bit-length output address pointer 110a is received at an address input terminal Ai, and the corresponding address content is read out and generated and output as a vector pattern PAT4.

According to this, in order to generate a group of continuous vector patterns PAT4 from the VPG, it is necessary to temporarily stop immediately before generation and preset an address initial value corresponding to the AP 110 via the tester bus. . Therefore, when the VPG occurs, the execution procedure is to temporarily stop and preset the address initial value. As a result, there is a drawback that the generation of vector patterns for a plurality of groups can be continuously generated without being temporarily stopped, with the conventional VPG.

On the other hand, among memory device types, there is a memory device incorporating a complicated logic circuit. In such a memory device, it is necessary to frequently preset an address initial value and perform a test. In addition, it is desired that the address initial value can be preset in real time instead of the pause. Further, there is a case where the same address initial value is frequently preset and the same vector pattern group is to be repeatedly and continuously generated. For this reason, in the conventional semiconductor test apparatus, it is necessary to create a continuous and large pattern and individually prepare it on the memory for a memory device incorporating a complicated logic circuit as described above. However, there is a case where a limitation on pattern storage occurs due to a finite memory capacity. As a result, there is a problem that it is difficult to conduct a practical test. On the other hand, the control signal CS of the ALPG
There is also a method in which a preset pattern having a length of 20 bits to be supplied to the address pointer 110 is directly supplied to generate a pattern synchronized in real time by applying the extension 11 to the address pointer 110. In this case, for the control of the ALPG, The number of applicable bits is finite. Further, expanding the bit width of the control memory is not preferable because the memory capacity and the circuit scale are increased, and the cost of the device is increased.

[0010]

As described above, the prior art has a drawback that it cannot be practically applied to a test mode in which it is required that the AP 110 can preset an address initial value in real time.
Further, since the preset address initial value has an asynchronous relationship with the generation of the test pattern, there is a drawback that the initial address value cannot be preset in a synchronous relationship with the generation of the test pattern. Accordingly, an object of the present invention is to provide a semiconductor test apparatus including an ALPG and a VPG, in which the generation of a vector pattern from the ALPG to the VPG can be controlled in real time and in a synchronized relationship in a semiconductor test apparatus. It is to provide a test device.

[0011]

First, in order to solve the above-mentioned problems, it is necessary to generate a test pattern on a device under test having a memory circuit unit. Algorithmic pattern generator AL responsible for generating patterns (test vectors)
In a semiconductor test apparatus including both a PG and a vector pattern generator VPG which is mainly responsible for generating a test vector for testing a logic circuit portion of the DUT, a predetermined bit generated based on the ALPG sequence control. Number of control signals CS11 to the VPG, and an address pointer (AP) provided in the VPG.
The test 110 to be provided in the VPG
In generating an address signal to be supplied to a vector memory (VM) 120 for storing a vector, the control signal CS11
And an address jump means for generating an address signal capable of jumping to a predetermined jump address based on the AP. According to the present invention, in a semiconductor test apparatus including an ALPG and a VPG, a semiconductor test apparatus capable of controlling the generation of a vector pattern from the ALPG to the VPG in real time and in a synchronized relationship can be realized.

Second, in order to solve the above-mentioned problem, a test pattern is generated on a device under test provided with a memory circuit, and the test pattern (test vector) is mainly generated on the memory circuit of the DUT. And a vector pattern generator VPG mainly responsible for generating a test vector for testing the logic circuit section of the DUT. A control signal CS11 of a predetermined number of bits generated based on the sequence control is supplied to the VPG, a vector memory (VM) 120 which is a memory for storing the test vector, and an address to the VM. An address pointer (AP) 110 for generating and supplying a signal. When an address signal (output address pointer 110a) generated by sequentially incrementing the clock RCLK1 by a predetermined amount is supplied to the address input terminal of the VM, the address signal generated by the AP is determined based on the control signal CS11. An address jump means capable of generating an address signal capable of jumping to a jump address is additionally provided to the AP.

FIGS. 3 and 4 show the solution according to the present invention. Further, one mode of the above-mentioned address jump means includes a plurality of predetermined registers R1 to Rn (where n is an integer value of 2 or more) for storing an initial address value for jumping to a predetermined address, and a corresponding multiplexer ( MUX) 150 and a preset data generating unit 2
60 and M added as the control signal CS11.
The MUX 150 receives a plurality of address initial values output from the predetermined plurality of registers R1 to Rn based on a control bit for UX selection, and sets a predetermined selected address initial value 150s for presetting of the AP. And based on the preset load signal LD7 added as the control signal CS11, when the load signal LD7 is asserted, the selected address initial value 150s is loaded into the AP, There is the semiconductor test apparatus described above, wherein jumping to a predetermined address is possible.

Further, one mode of the address jump means stores an initial value of an address for jumping to a predetermined address when one jump address is sufficient.
Preset data generation unit 26 including the three registers R1
0, and when the load signal LD7 is asserted based on the preset load signal LD7 added as the control signal CS11, the one register R1
The above-mentioned semiconductor test apparatus is characterized in that an initial address value R1s output from the memory is loaded into the AP so that a jump to a predetermined address is enabled.

FIG. 5 shows a solution according to the present invention. Further, one mode of the jump means to the above address is as follows.
A preset data generation unit 260 including a table memory 160 having a predetermined capacity for storing an initial address value for jumping to a predetermined address, and supplying a predetermined plurality of control bits added as the control signal CS11 as an address to the table memory 160. Based on this, the selected address initial value 150s read from the table memory 160 is supplied to the preset data input terminal Di of the AP, and based on the preset load signal LD7 added as the control signal CS11. When the load signal LD7 is asserted, the selected address initial value 150s is loaded into the AP to enable jumping to a predetermined address.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Further, the scope of the claims is not limited by the following description of the embodiments, and the elements and connection relationships described in the embodiments are not necessarily essential to the solving means.
Further, the description of the elements and connection relations described in the embodiments is an example, and is not limited to the description.

The present invention will be described below with reference to FIGS. Elements corresponding to those of the conventional configuration are denoted by the same reference numerals, and description of overlapping parts is omitted.

As shown in FIG. 3, the main components of the VPG of the present application include an address generating means 200 and a VM 120. The internal components of the address generator 200 include a preset data generator 260 and an AP 110. Also, the control signal CS11 generated from the ALPG
Is a 4-bit selection signal SL9 and a load signal LD.
7 is additionally provided. FIG. 3 illustrates a specific example including 16 registers as the plurality of registers R1 to R16. In addition, AP110 and VM1
Since 20 is the same element as the conventional one, no explanation is required.

The internal components of the preset data generator 260 include a plurality of registers R1 to R16 and a multiplexer (MUX) 150. The 16 registers R1 to R16 are 20-bit registers holding initial addresses of 16 preset addresses. The contents of each register are set in advance via a tester bus. The 20-bit address initial values R1s to R16s output from the registers R1 to R16 are supplied to the MUX 150.

The MUX 150 is a 16-input 1-output 20
A bit width multiplexer that receives the address initial values R1s to R16s and receives an additional 4-bit selection signal SL which is a control signal CS11 generated from the ALPG.
In response to this, based on this, the 20-bit selected address initial value 150 s selected from any of them is supplied to the data input terminal Di of the AP 110.

The AP 110 receives an additional 1-bit load signal LD which is a control signal CS11 generated from the ALPG.
7, when this is asserted, the selected address initial value 150s is preset at a timing synchronized with the rate clock RCLK1. In the same manner as in the prior art, the output address pointer 110 which has +1 counted as desired based on the increment enable signal INC8 is provided.
a is supplied to the VM 120.

Next, the operation of the configuration of FIG. 3 will be further described with reference to the timing chart of FIG. This figure shows a specific example in which the register R1 is applied to repeatedly execute a loop in real time. It is also assumed that the initial address value R1s of the register R1 is "m", and a loop is performed every four cycles. Note that the cycles C1 to C
Reference numeral 12 denotes each cycle number of the rate clock RCLK1 unit.

The 4-bit selection signal SL9 is used to select at least the cycle C in order to select the address initial value R1s.
3. AL so that register R1 is selected by C7 and C11
Generated from PG and supplied. The load signal LD7 is set to ALP so as to be asserted in cycles C3, C7 and C11.
Generated from G and supplied. The increment enable signal INC8 is set to A so that it is asserted in every cycle.
Generated and supplied from LPG.

As a result, in the cycles C1 to C3, the address of the output address pointer 110a based on the previous preset is generated (see FIG. A). In cycle C4, the address initial value R1s "m" is preset based on the load signal LD7 in cycle 3 (see FIG. 4C) (see FIG. D). In cycles C5 to C7, the address of the output address pointer 110a in which the preset value of "m" is sequentially counted by +1 is generated (see FIG. F).

In cycle C8, based on the load signal LD7 in cycle 7 (see FIG. 4G), the address initial value R1
s "m" is preset again (see FIG. H). In cycles C9 to C11, the output address pointer 110 in which the preset value of “m” is sequentially incremented by +1.
The address a is generated in the same manner as in the cycles C5 to C7 (see FIG. J).

As a result, the cycles C4 to C7 (see FIG. 4K) and the cycles C8 to C11 (see FIG. 4L) form the same repetitive loop, and there is no cycle for the temporary stop period, so It can be seen that a continuous repetition loop is executed by jumping to a predetermined address position. As a result, the conventional vector pattern PAT associated with the preset address initial value is used.
4 has a great advantage that the problem that the suspension period of the occurrence of 4 occurs is eliminated. As a result, a plurality of groups of vector patterns can be continuously generated even for a memory device incorporating a complicated logic circuit, and there is an advantage that it is not necessary to provide a long pattern. As a result, there is obtained a great advantage that a semiconductor test apparatus capable of performing a practical test can be realized even with the capacity of the existing vector memory VM. Note that, in the configuration of FIG. 3, the desired initial point can be selected from 16 points, and the preset address initial value is continuously generated by jumping to a different arbitrary address position in real time. Let me
It is easily applicable from the above description.

Note that the technical concept of the present invention is not limited to the specific configuration examples and connection examples of the above-described embodiment. Furthermore, based on the technical idea of the present invention, the above-described embodiment may be appropriately modified and widely applied. For example, in the preset data generation unit 260 of the above-described embodiment, a specific example including the plurality of registers R1 to R16 and the MUX 150 has been described. However, as another configuration example, as illustrated in FIG.
A 256-word small-capacity memory and a corresponding 8-bit selection signal SL9 may be applied. In this case, there is an advantage that 256 more address initial values can be applied.

Further, as another example of the configuration of the preset data generating section 260 of the above-described embodiment, as shown in FIG. 6, there is an example of a configuration having a medium memory table memory 160 of, for example, 64K words and a second address pointer 170. is there. The table memory 160 receives the address signal of 16-bit length, reads the corresponding address content, and supplies it to the AP 110 as the selected address initial value 150s. The contents stored in the table memory 160 include a selected address initial value 150 used in order based on the device test.
s are sequentially stored in the memory. The second address pointer 170 sets a desired initial value in advance via the tester bus. During subsequent tests, ALP
Each time it receives the added 1-bit increment enable signal INC9, which is a control signal CS11 generated from G, it generates a + 1-counted order address signal 170a. Note that the increment enable signal INC9
Is preferably generated from the ALPG so that it is asserted one cycle before the load signal LD7 supplied from the ALPG to the AP 110 side. However, if the selected address initial value 150s may be the same as in a repetitive loop, the same order address signal 170a may be used, and the increment enable signal INC9 is used.
Can be left negated, needless to say. In this case, there is an advantage that a larger number of address initial values can be applied when the number of control signals CS11 is as small as three.

[0029]

According to the present invention, the following effects can be obtained from the above description. As described above, according to the present invention, when the vector pattern PAT4 is generated,
Based on the control signal from the ALPG side, the vector pattern PAT4 can be generated by jumping to a predetermined address position in real time, and can be generated at a timing synchronized with the ALPG side. As a result, a plurality of groups of vector patterns can be continuously generated without temporarily stopping the generation of the vector patterns, and a great advantage that the necessity of providing a long pattern is eliminated is obtained. Therefore, among the types of memory devices, it becomes possible to generate a vector pattern corresponding to a memory device having a built-in complicated logic circuit. As a result, it is possible to practically apply the test of these device tests. A notable advantage is obtained in that the coverage is extended. Therefore, the technical effect of the present invention is great, and the industrial economic effect is also great.

[Brief description of the drawings]

FIG. 1 is a conceptual configuration diagram of a semiconductor test apparatus.

FIG. 2 is a configuration diagram of a main part of a conventional VPG.

FIG. 3 is a configuration diagram of a main part of a VPG according to the present invention.

FIG. 4 is a timing chart for explaining the operation of FIG. 3;

FIG. 5 is a configuration diagram of another main part of the address generating means of the present invention.

FIG. 6 is a configuration diagram of another main part of the address generating means of the present invention.

[Explanation of symbols]

 R1 to R16 Register 110 Address pointer (AP) 120 Vector memory (VM) 150 Multiplexer (MUX) 160 Table memory 170 Second address pointer 200 Address generation means 260 Preset data generation unit DC logical comparator FC waveform shaper PDS programmable data・ Selector PG pattern generator TG timing generator VPG vector pattern generator ALPG algorithmic pattern generator TBUS tester bus

Claims (5)

[Claims] 1. A method for generating a test pattern on a device under test (DUT) having a memory circuit unit, the method comprising:
An algorithmic pattern generator ALPG that is in charge of generating a test pattern (test vector) in the memory circuit portion of the UT, and a vector pattern and an image signal that is mainly in charge of generating a test vector that tests the logic circuit portion of the DUT. In the semiconductor test apparatus including both the generator VPG, a control signal of a predetermined number of bits generated based on the sequence control of the ALPG is supplied to the VPG, and an address pointer (AP) provided in the VPG is generated. Address jump means for generating an address signal capable of jumping to a predetermined jump address based on the control signal in generating an address signal to be supplied to a vector memory (VM) for storing the test vector provided in the VPG Semiconductor test equipment, which is additionally provided to the AP. . 2. A method for generating a test pattern on a device under test (DUT) including a memory circuit unit, the method comprising:
An algorithmic pattern generator ALPG that is in charge of generating a test pattern (test vector) in the memory circuit portion of the UT, and a vector pattern and an image signal that is mainly in charge of generating a test vector that tests the logic circuit portion of the DUT. In a semiconductor test apparatus including both a generator VPG, a control signal of a predetermined number of bits generated based on the sequence control of the ALPG is supplied to the VPG, and a memory for storing the test vector is provided in the VPG. A vector memory (VM); and an address pointer (AP) for generating and supplying an address signal to the VM. An address signal generated by the AP sequentially incrementing at a predetermined rate by a rate clock is input to the address input of the VM. When supplying to the end, the control signal is Zui by an address jump means capable of generating a jump can address signal to a predetermined jump address by adding to the AP, the semiconductor testing apparatus, characterized in that. 3. An address jump means comprising: a plurality of registers for storing an address initial value for jumping to a predetermined address; and a multiplexer (MUX) corresponding to the plurality of registers.
A preset data generating section comprising: a plurality of address initial values output from a plurality of predetermined registers based on a control bit for selecting a MUX added as the control signal; Is supplied to the preset data input terminal of the AP, and based on the preset load signal added as the control signal, when the load signal is asserted, the selected address initial value 3 is loaded into the AP so that jumping to a predetermined address is possible.
The semiconductor test apparatus according to claim 1. 4. A preset data generating section comprising one register for storing an initial address value for jumping to a predetermined address, the address jump means comprising: 3. The method according to claim 1, wherein when the load signal is asserted, an initial address value output from the one register is loaded into the AP to enable jumping to a predetermined address. Semiconductor test equipment. 5. A preset data generating unit comprising a table memory having a predetermined capacity for storing an initial value of an address for jumping to a predetermined address, wherein said control signal includes a predetermined plurality of control bits added as said control signal. The AP is supplied as an address to the table memory, and based on this, the selected address initial value read from the table memory is supplied to the preset data input terminal of the AP, and is added to the preset load signal added as the control signal. 3. The method according to claim 1, wherein when the load signal is asserted, the initial value of the selected address is loaded into the AP to enable jumping to a predetermined address.
The semiconductor test apparatus according to claim 1.