JP2002041494A - Single-chip microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a single-chip microcomputer which can start different programs according to the operation mode and in which a user can use a program in a program area for the manufacturer. SOLUTION: This microcomputer has at least two or more operation modes; arranges, in an internal ROM, a plurality of different vector address areas that make the number of the operation modes maximum as a plurality of banks at the same address of the same ROM address space; respectively arranges a plurality of programs used in the respective operation modes at the shared program area of the ROM address space; and also arranges programs that are common to different operation modes among a plurality of programs used in the respective operation modes at the same address of the shared program area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-chip microcomputer, and more particularly, to a vector address of a single-chip microcomputer for reading a starting address of a program for starting processing upon reset or acceptance of an interrupt from a specific vector address area. In the control method.

[0002]

2. Description of the Related Art Read-only memory (hereinafter abbreviated as ROM)
A single-chip microcomputer having a built-in memory usually has a mode in which instructions are fetched from outside the chip in order to test the chip. This mode may be provided as a processor mode, which is one of the modes used by the user, and may be provided as a test mode used by the manufacturer. In any case, since it is necessary to input and output an address and an instruction code from a specific terminal, a state different from the single-chip mode operating using the built-in ROM must be performed for the specific terminal. No. That is, in the above-described mode, the function of the terminal in the single-chip mode cannot be tested.

However, in order to guarantee the function of the chip, the manufacturer needs to test whether the chip operates correctly in all the operation states. Therefore, in order to test pin functions that cannot be tested in the mode in which instructions are fetched from the outside of the chip, a maker program area is built in, and in the same state as in the single-chip mode, the maker program area is used instead of the user program area. There are provided a means for fetching an instruction and performing a test, a means for writing a program in a built-in RAM and fetching an instruction from the built-in RAM and performing a test.

Next, a conventional general single-chip microcomputer will be described with reference to FIGS. 14 and 15. FIG. FIG. 14 is a block diagram showing a configuration of a conventional single-chip microcomputer. Figure 1
In 4, 1 is a CPU, 2 is a ROM, 3 is a RAM, 4
Is an I / O, DB is a data bus, and AB is an address bus.

[0005] The single-chip microcomputer having the above-described configuration transfers data stored in the ROM address designated by the CPU 1 via the address bus AB to the R.
The instruction is executed while being read from the OM 2 via the data bus DB as needed. Also, data is written to and read from the RAM 3 as necessary, and command processing is performed. In some cases, it is also possible to execute an instruction arranged on the RAM 3.

FIG. 15A is a diagram showing a storage state of ROM data of a conventional single-chip microcomputer. FIG. 15B is a diagram showing the storage state of ROM data in the user operation mode. FIG. 15C is a diagram showing the storage state of ROM data in the manufacturer operation mode.

In FIG. 15, an area A (x'0000)
0 'to x'0FFFF') are a RAM area and an area B (x'1
0000 'to x'1FFFF') are a maker vector address area and a maker program area, and an area C (x'1
0000 ′ to x′1FFFF ′) are a user vector address area and a user program area, and an area D (x′2
0000 'to x'3FFFF') are shared program areas. The maker vector address area and the user vector address area are arranged in different banks (area B and area C) of the same address in the same logical address space. Also,
The maker program is in the maker program area (area B
In). The single chip microcomputer uses the vector address area (x '
The execution of the program is started from the reset vector address stored in (10000 ′ to x′10100).

Note that the logical address space is x'0000
It is 256 Kbytes from 0 'to x'3FFFF'.
The RAM capacity is 64 Kbytes, and the vector address area is 256 bytes.

The operation of the conventional single-chip microcomputer will be described below. In a conventional reset start or an interrupt acceptance, a start address at which processing is started is set to a specific vector address area (in this embodiment, x'100
In a single-chip microcomputer reading from 00 ′ to x′10100 ′), when a user program or a maker program is used, the head address of the process is read from the same vector address area. However, it is generally very difficult for the user program and the maker program to set the above-mentioned processing start address to the same value. Therefore, in order to set the start address to a different value, as shown in an area B and an area C in FIG. 15A, a maker program and a user program are arranged in different bank spaces having the same address. Note that the bank space area B and the area C include a unique program and a unique vector address area, respectively. When the user program is used, FIG.
As shown in the figure, the bank is placed on the user program side (area C).
Switch to. In the case of performing a test, FIG.
The bank is switched to the maker program area (area B) as shown in FIG. Such switching is performed by changing the state of a specific terminal (I /
The operation mode is determined by the operation mode control signal S100.

When the built-in RAM is used, a test program is written in the built-in RAM in a special operation mode, and the test for fetching an instruction is switched from the ROM to the RAM to perform the test. Of course, in this case,
The vector address area is allocated on the RAM side.

In recent years, the number of single-chip microcomputers having a built-in flash EEPROM capable of electrically erasing and writing data has been increasing. In such a single-chip microcomputer, as a method of erasing and writing to a built-in flash EEPROM, the terminals of the single-chip microcomputer are made to be in the same state as a single flash EEPROM, and address, data and control signals are externally supplied to individual terminals. And a serial mode in which a single-chip microcomputer is operated, write data is transmitted and received by serial communication, and writing is performed by executing instructions of the single-chip microcomputer.

In the serial mode, the built-in flash EE
When rewriting the PROM, it is necessary to cause a single-chip microcomputer to execute a special program. In a single-chip microcomputer that reads a start address from which a process is started from a specific vector address area at the time of a reset start or acceptance of an interrupt, a program that changes the vector address area according to an operation mode and switches a program to be executed, or in a user program, It is necessary to switch the program to be executed by judging the state of the terminal.

[0013]

As described above, the RO built in a conventional single-chip microcomputer is described.
The capacity of M is limited, and it is desired to effectively use the capacity of a test program. For example, it is conceivable to call a subroutine program in the manufacturer program area (area B) or a program routine such as the BIOS from the user program side.
However, in the above-described bank arrangement means, when a user uses a program in the maker program area (area B), a complicated procedure of switching banks must be taken. User program area (area C)
And the maker program area (area B) each include a unique vector address area. In order for the user to use the program in the maker program area (area B), the maker program area (area B) side Interrupts cannot be accepted while the bank is being switched. This is because if an interrupt is received while the bank is being switched to the maker program area (area B), the maker interrupt processing program is started.

In general, the capacity of a RAM built into a single-chip microcomputer is smaller than that of a ROM, so that a sufficient program cannot be stored, and it is difficult to perform various kinds of complicated tests at one time. Therefore, it is necessary to rewrite the program for each test item. In addition, an operation of writing a test program into the built-in RAM is also required, which causes a problem that the test becomes complicated.

On the other hand, in rewriting a flash EEPROM in a serial mode, it is generally prohibited to erase a rewriting program (hereinafter referred to as a loader program). This is because if an error occurs in the single-chip microcomputer during rewriting, the loader program is destroyed, and the rewriting cannot be performed again in the serial mode. Therefore, when the loader program is arranged in the user program, the vector address area is shared with the user program, and the problem that the vector address area cannot be rewritten for the above reason occurs.

Also, the addresses to be stored in the vector address area always change depending on the user program, and if the vector address cannot be rewritten, it will be a major obstacle in creating the user program.

Further, in recent years, there has been a movement to register design resources as IP (Intellectual Property) and promote utilization thereof in order to increase design efficiency. IP-based CPU
Is used, there is no problem in the case where the function of switching the area of the vector address is provided. Also, regarding a memory such as a flash EEPROM, when it is converted to an IP, a capacity of a power of 2 (for example, 64 Kbytes, 12
8 Kbytes, 256 Kbytes, etc.) in many cases. For example, if a CPU having a space of 256 Kbytes as a logical address is to have 16 Kbytes of RAM and the remainder to be a flash EEPROM, a 256 Kbyte I
A P core will be used. In this case, 16 Kbytes of the total capacity of the flash EEPROM cannot be assigned a logical address and cannot be used, resulting in waste.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a different program can be started according to an operation mode, and a program in a manufacturer program area can be used by a user. It is an object of the present invention to provide a chip microcomputer and to make the most of hardware to be mounted.

[0019]

According to a first aspect of the present invention, there is provided a single-chip microcomputer comprising: a ROM storing various programs; a RAM storing data;
CPU for executing a program stored in the ROM
And a single-chip microcomputer incorporating an input / output device for outputting various control signals, the ROM having at least two or more operation modes,
A plurality of different vector address areas that maximize the number of the operation modes are arranged as a plurality of banks at the same address in the same ROM address space, and each of the plurality of programs used in each of the operation modes is the ROM address. A program that is arranged in a shared program area of a space and that is common to different operation modes among the plurality of programs used in each of the operation modes is arranged at the same address of the shared program area, and the single-chip microcomputer Sets one of the plurality of operation modes based on an operation mode control signal output from the input / output device, and switches the bank to use a different vector address area to set the operation mode. It is possible to change the program to be executed according to In consisting operation mode, characterized in that it is a possible execution of the program stored in the same address of the shared program area.

Thus, different programs can be started according to the operation mode. In different operation modes, programs stored at the same address in the shared program area can be used. Further, the capacity of the ROM can be saved by effectively utilizing the program capacity.

According to a second aspect of the present invention, there is provided a single-chip microcomputer which stores various programs.
At least two or more operation modes in a single-chip microcomputer including an OM, a RAM storing data, a CPU executing a program stored in the ROM, and an input / output device for inputting / outputting various control signals. And a vector address conversion means for converting a vector address output as a logical address from the CPU according to a vector address output signal output from the CPU and an operation mode control signal output from the input / output device, In the ROM, a plurality of different vector address areas for maximizing the number of the operation modes are the same R address.
Each of the plurality of programs used at each address in the OM address space and used in each of the operation modes is arranged in the shared program area of the ROM address space, and each of the plurality of programs used at each of the operation modes is used. Programs common to different operation modes among the programs are arranged at the same address of the shared program area,
The single-chip microcomputer sets one of the plurality of operation modes based on an operation mode control signal output from the input / output device, and stores the one in the vector address area determined by the vector address conversion means. And executing the programs stored at the same address in the shared program area in the different operation modes.

Thus, a different program can be started by determining the vector address to be used by the vector address conversion means. In different operation modes, programs stored at the same address in the shared program area can be used. Further, the capacity of the ROM can be saved by effectively utilizing the program capacity.

A single chip microcomputer according to a third aspect of the present invention is the single chip microcomputer according to the first or second aspect, wherein the operation modes include a user operation mode used by one or more users. And a maker operation mode used by one or more manufacturers. The ROM has two different vector address areas used in the user operation mode and a vector address area used in the maker operation mode. The vector address area is arranged in the same ROM address space, and each of the plurality of user programs and manufacturer programs used in one of the user operation mode and the maker operation mode is provided in the ROM address space. It is located in a shared program area and has the user operation mode. And a common program among the plurality of programs used in any of the operation modes for the manufacturer and the manufacturer is arranged at the same address in the shared program area, and the single-chip microcomputer operates in each of the operation modes. The user program and the manufacturer program can be selected by using different vector address areas in accordance with each other, and in any one of the user operation mode and the manufacturer operation mode, The program stored in the same address of the shared program area can be executed.

Thus, the user program and the maker program can be started in accordance with the operation mode, and the user can use the program in the maker program area. Furthermore, by effectively utilizing the program capacity, R
OM capacity can be saved.

According to a fourth aspect of the present invention, there is provided a single-chip microcomputer which stores various programs.
At least two or more operation modes in a single-chip microcomputer including an OM, a RAM storing data, a CPU executing a program stored in the ROM, and an input / output device for inputting / outputting various control signals. ROM address conversion means for converting a logical address output from a CPU into a physical address, and a signal processing circuit for performing required processing on all bits of an address signal to the ROM according to each operation mode Wherein the single-chip microcomputer comprises:
One of the plurality of operation modes is set based on an operation mode control signal output from the input / output device, and the ROM address converted by the ROM address conversion means is set according to the set operation mode. The required processing is performed on all the bits of to determine the ROM address,
The program stored in the ROM address determined according to the operation mode can be executed.

Thus, different programs can be started by performing required processing on all bits of the address input to the ROM according to the operation mode. Further, the maker can use the maker program without using the user program area. Furthermore, the unusable area of the built-in ROM can be effectively used, and the ROM capacity can be saved.

According to a fifth aspect of the present invention, there is provided a single-chip microcomputer which stores various programs.
At least two or more operation modes in a single-chip microcomputer including an OM, a RAM storing data, a CPU executing a program stored in the ROM, and an input / output device for inputting / outputting various control signals. ROM address conversion means for converting the logical address output from the CPU into a physical address, and the upper m bits (m is an arbitrary integer) of the address signal to the ROM according to each operation mode A signal processing circuit for performing required processing, the single-chip microcomputer sets one of the plurality of operation modes based on an operation mode control signal output from the input / output device, The RO converted by the ROM address conversion means according to the set operation mode.
It is characterized in that a ROM address for performing required processing on an arbitrary upper bit of the M addresses is determined, and a program stored in the ROM address determined according to the operation mode can be executed.

Thus, a different program can be started by performing required processing only on an arbitrary number of high-order bits of an address input to the ROM according to an operation mode, and exclusive logic can be performed. The number of sums can be reduced. Furthermore, the unusable area of the built-in ROM can be effectively used, and the ROM capacity can be saved.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. The embodiment described here is merely an example, and the present invention is not necessarily limited to this embodiment.

(Embodiment 1) Hereinafter, a single-chip microcomputer according to Embodiment 1 of the present invention will be described with reference to FIGS. 1, 2 and 3. FIG. FIG.
FIG. 2 is a block diagram illustrating a configuration of a single-chip microcomputer according to the first embodiment. In FIG. 1, reference numeral 1 denotes a CPU (Central Processing Unit), which executes a program stored in a ROM 2. 2 is ROM (read only memory)
And stores various programs. 3 is RAM
(Random access memory), which mainly stores data. Reference numeral 4 denotes an I / O (input / output device);
It outputs various control signals to the inside and outside of the device. 5 is I
/ O terminal. DB is a data bus for transmitting and receiving information. AB is an address bus for transmitting address information. S100 is an operation mode control signal, which is a signal for instructing switching between the user operation mode and the manufacturer operation mode.

The single-chip microcomputer having such a configuration has at least two or more operation modes. In the ROM, a plurality of different vector address areas for maximizing the number of the operation modes are provided in the same ROM address space. It is arranged as multiple banks at the same address,
Each of the plurality of programs used in each of the operation modes is arranged in a shared program area of the ROM address space, and is common to a different operation mode among the plurality of programs used in each of the operation modes. The program is located at the same address in the shared program area.

The first embodiment or the second embodiment
In the single-chip microcomputer according to
The operation modes include a user operation mode used by one or more users and a manufacturer operation mode used by one or more manufacturers. In the ROM, a vector address area used in the user operation mode is set. And the vector address area used in the manufacturer operation mode.
Two different vector address areas are arranged in the same ROM address space, and each of the plurality of user programs and the manufacturer program used in one of the user operation mode and the manufacturer operation mode is stored in the ROM address space. A program that is arranged in the shared program area and is shared between a plurality of programs used in one of the user operation mode and the manufacturer operation mode is assigned to the same address of the shared program area. Are located.

FIG. 2A is a diagram showing a storage state of ROM data of the single-chip microcomputer according to the first embodiment. FIG. 2B shows the RO in the user mode.
FIG. 4 is a diagram illustrating a storage state of M address data. FIG. 2 (c)
FIG. 4 is a diagram showing a storage state of ROM address data in a maker mode. In FIG. 2, a region A (x'000
00 'to x'0FFFF') are a RAM area and an area B '
(x'10000 'to x'100FF') is a maker vector address area, area C '(x'10000' to x'1)
00FF ') is a user vector address area, area D
(x'10100 'to x'3FFFF') are shared program areas.

A single-chip microcomputer is:
When the reset is released, the vector address area (x'1000
The execution of the program is started from the reset vector address stored at 0 'to x'100FF').

Note that the vector address area is x'0000
0 'to x'100FF', but it goes without saying that the same applies to other addresses. For simplicity, the logical address space is defined as x'00000 'to x'3F
256K bytes up to FFF ', RAM capacity 64
It is assumed that K bytes and the vector address area are 256 bytes.
Of course, these capacities can be set arbitrarily.

The operation of the single-chip microcomputer according to the first embodiment will be described below. First, the CPU 1 outputs a ROM address to the ROM 2 via the address bus AB. The I / O 4 outputs an operation mode control signal S 1 based on a signal input from the I / O terminal 5.
00 is generated and output to the ROM 2. ROM2 has I / O
One of a plurality of operation modes is set based on the operation mode control signal S100 output from O4, and the bank is switched to use a different vector address area, thereby executing according to the set operation mode. Can change the program. Further, it is possible to execute a program stored in the shared program area in different operation modes.

When the operation mode control signal S100 is at an L level, the user vector address area C 'is selected as shown in FIG. 2B, and when the operation mode control signal S100 is at an H level, as shown in FIG. As shown in c), the maker vector address area B 'is selected. Thus, the user program and the maker program can be changed according to each operation mode.

The program is executed while the data stored at the ROM address specified by the CPU 1 via the address bus AB is read from the ROM 2 via the data bus DB as needed. Also, if necessary, RA
Data is written to and read from M3, and instruction processing is performed. In some cases, it is also possible to execute an instruction arranged on the RAM 3.

Next, the comparison between the ROM data storage states of the conventional single-chip microcomputer and the single-chip microcomputer according to the first embodiment of the present invention will be described with reference to FIG. FIG. 3 shows a conventional single-chip microcomputer and the RO of the single-chip microcomputer according to the first embodiment of the present invention.
FIG. 6 is a diagram showing an M data storage state.

In a conventional single-chip microcomputer, as shown in FIG. 3A, a maker program area B and a user program area C are arranged in banks and used exclusively. For example, three user programs (U
1, U2, U3) and three manufacturer programs (M1, M
2, M3), they are arranged in the areas C and B, respectively. If the maker program M3 and the user program U1 have the same address, they must be individually arranged in the conventional single-chip microcomputer. . However, in the single-chip microcomputer according to the first embodiment of the present invention, each program (U1, U2, U3,
M1, M2, and M3), and when the user program U1 and the maker program M3 have the same address, only one of them is required, and either the user operation mode or the maker operation mode is required. In the operation mode, a program stored at the same address in the shared program area can be executed. As described above, the ROM capacity can be saved by the program size of the user program (U1) or the maker program (M3), and the user can use the maker program having the same address as the user program. Can be.

As described above, according to the single-chip microcomputer according to the first embodiment, the ROM storing various programs, the RAM storing data,
CPU for executing a program stored in the ROM
And a single-chip microcomputer incorporating an input / output device for outputting various control signals, the ROM having at least two or more operation modes,
A plurality of different vector address areas for maximizing the number of the operation modes are arranged as a plurality of banks at the same address in the same ROM address space, and each of the plurality of programs used in each of the operation modes is ROM
Located in the shared program area of the address space, and
Among the plurality of programs used in each of the operation modes, programs common to different operation modes are arranged at the same address in the shared program area, and the single-chip microcomputer is output from the input / output device. By setting one of the plurality of operation modes based on the operation mode control signal, and switching between banks to use different vector address areas,
The program to be executed can be changed according to the set operation mode, and in the different operation mode, the program stored at the same address in the shared program area can be executed. By switching banks according to different vector addresses, different programs can be started, and programs stored at the same address in the shared program area can be executed in different operation modes, thereby effectively utilizing the program capacity. A single-chip microcomputer with a reduced ROM capacity can be provided.

In the single-chip microcomputer according to the first or second embodiment, the operation modes include a user operation mode used by one or more users and a user operation mode used by one or more manufacturers. In the ROM, two different vector address areas, a vector address area used in the user operation mode and a vector address area used in the manufacturer operation mode, are arranged in the same ROM address space. A plurality of user programs and a plurality of manufacturer programs used in one of the user operation mode and the manufacturer operation mode are arranged in the shared program area of the ROM address space; Used in one of the operation mode and the operation mode for the manufacturer Programs common to a plurality of programs are arranged at the same address of the shared program area, and the single-chip microcomputer uses different vector address areas according to the respective operation modes, thereby enabling the user A program stored in the same address of the shared program area in one of the operation mode for the user and the operation mode for the manufacturer. Therefore, the user can use a maker's program at the same address as the user's program, and can provide a single-chip microcomputer that can effectively use the program capacity and save the ROM capacity.

(Embodiment 2) A single-chip microcomputer according to Embodiment 2 of the present invention will be described below with reference to FIGS. FIG.
FIG. 6 is a block diagram showing a configuration of a single-chip microcomputer according to a second embodiment. In FIG. 4, reference numeral 6 denotes a vector address conversion means, which is provided in accordance with a vector address output signal S101 and an operation mode control signal S100.
The vector address output from the CPU 1 as a logical address is converted. S101 is a vector address output signal, which is a signal that becomes active while the CPU 1 is outputting a vector address.

The single-chip microcomputer having such a configuration has at least two or more operation modes, and a vector address output signal output from the CPU;
Vector address conversion means for converting a vector address output as a logical address from the CPU according to an operation mode control signal output from the input / output device;
In the ROM, a plurality of different vector address areas for maximizing the number of the operation modes are arranged at different addresses in the same ROM address space, and each of the plurality of programs used in each of the operation modes stores the ROM address. Programs that are arranged in the shared program area of the space and are common to different operation modes among the plurality of programs used in each of the operation modes are arranged at the same address of the shared program area. The same or corresponding components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

FIG. 5 shows a storage state of ROM data of the single-chip microcomputer according to the second embodiment. In FIG. 5, the area A (x'00000 'to x'0F)
FFF ') is a RAM area, an area B'(x'10000'to
x'100FF ') is a vector address area for the user, area C'(x'3FF00'tox'3FFFF') is a vector address area for the maker, and area D (x'10100 ')
x'3FEFF ') is a shared program area.

The single-chip microcomputer is:
Area B '(x'10000' to x'1) when reset is released
The program execution is started from the reset vector address stored in the area C ′ (00 ′ ′) or the reset vector address stored in the area C ′ (x′3FF00 ′ to x′3FFFF ′).

In the second embodiment, two different vector address areas, a vector address area used in the user operation mode and a vector address area used in the maker operation mode, have different addresses in the same ROM address space. Are located in Further, the vector address areas are defined as x'00000 'to x'100FF' and x'3F
Although F00 'to x'3FFFF' are used, it goes without saying that the same applies to other addresses. For simplicity, the logical address space is defined as x'00000 'to x'.
The size is 256 Kbytes up to 3FFFF ', the RAM capacity is 64 Kbytes, and the vector address area is 256 bytes. Of course, these capacities can be set arbitrarily.

The operation of the single-chip microcomputer according to the second embodiment will be described below. First, the CPU 1 sets x'10000 'as a logical address.
.. X'100FF 'are output to the vector address conversion means 6. Also, I / O4 is I / O4
Mode control signal S based on the signal input from / O5
100 is generated and output to the vector address conversion means 6. Then, one of a plurality of operation modes is set based on the operation mode control signal S100, and x'10000 'to x'1 output as logical addresses from the CPU 1 are set.
00FF 'is converted to x' by the vector address conversion means 6.
10000 'to x'100FF' or x'3FF00 '
~ X'3FFFF 'to determine the address of the vector address area to be used. Then, the program stored in the determined vector address area can be executed. Further, programs stored at the same address in the shared program area can be executed in different operation modes.

When the operation mode control signal S100 is at the H level and the vector address output signal S101 output from the CPU 1 is active, the vector address conversion means 6 applies x'3F to the logical address output from the CPU 1.
F00 'is added to convert to the address of area C'. In other cases, the logical address output from the CPU 1 is passed as it is.

The program is executed while the data stored at the ROM address determined via the address bus AB is read from the ROM 2 via the data bus DB as needed. In addition, data is written to and read from the RAM 3 as needed, and command processing is performed. In some cases, it is also possible to execute an instruction arranged on the RAM 3.

Next, a comparison of the ROM data storage state between the conventional single-chip microcomputer and the single-chip microcomputer according to the second embodiment of the present invention will be described with reference to FIG. FIG. 6 shows a conventional single-chip microcomputer and a second embodiment of the present invention.
1 shows a ROM data storage state of the single-chip microcomputer according to the first embodiment.

In a conventional single-chip microcomputer, a program area B for a maker and a program area C for a user are arranged in banks and used exclusively. For example, if there are three user programs (U1, U2, U3) and three maker programs (M1, M2, M3), these are arranged in the area C and the area B, respectively, and the maker program M3 and the user If the programs U1 are the same, they must be individually arranged in a conventional single-chip microcomputer. However, in the single-chip microcomputer of the present invention, each program (U1, U2, U2) is stored in the shared program area.
3, M1, M2, M3) are arranged. If the addresses of the user program U1 and the maker program M3 are the same, only one of them needs to be arranged, and either the user operation mode or the maker operation mode is required. In such an operation mode, a program stored at the same address in the shared program area can be executed. That is, it is possible to save the ROM capacity by the program size of the user program (U1) or the maker program (M3). Further, the user can use a maker program having the same address as the user program.

As described above, according to the single-chip microcomputer according to the second embodiment, the ROM storing various programs, the RAM storing data,
CPU for executing a program stored in the ROM
And a single-chip microcomputer having an input / output device for inputting / outputting various control signals, having at least two or more operation modes, a vector address output signal output from the CPU, and a vector output signal output from the input / output device. Vector address conversion means for converting a vector address output as a logical address from the CPU in accordance with the operation mode control signal, and a plurality of different vector address areas for maximizing the number of operation modes are provided in the ROM. Each of the plurality of programs arranged at different addresses in the same ROM address space and used in each of the operation modes is arranged in a shared program area of the ROM address space and used in each of the operation modes. A program common to different operation modes among multiple programs RAM is disposed at the same address of the shared program area, the single-chip microcomputer sets one of the plurality of operation modes based on an operation mode control signal output from the input / output device, Since the program stored in the vector address area determined by the vector address conversion means can be executed, and the program stored at the same address in the shared program area can be executed in the different operation modes, There is no need to switch banks as in the first embodiment, and different programs can be started by changing the address of the vector address area according to the operation mode. Further, in different operation modes, it is possible to execute programs stored at the same address in the shared program area. Further, the capacity of the ROM can be saved by effectively utilizing the program capacity.

(Embodiment 3) Hereinafter, a single-chip microcomputer according to Embodiment 3 of the present invention will be described with reference to FIGS. The single-chip microcomputer according to the third embodiment has at least two or more operation modes, a ROM address conversion means for converting a logical address output from a CPU into a physical address, and a ROM address conversion means according to each of the operation modes. RO
And a signal processing circuit for performing required processing on all bits of the address signal to M.

The third embodiment or the fourth embodiment
A ROM address conversion means for converting an address, and a signal processing circuit (in the present embodiment, an exclusive OR) with the CPU and the R
It can be realized only by inserting between OM.

FIG. 7 is a block diagram showing a configuration of a single-chip microcomputer according to the third embodiment. In FIG. 7, reference numeral 7 denotes ROM address conversion means for converting a logical address output from the CPU 1 into a physical address. An exclusive OR 8 inverts or inverts all address signals to the ROM according to each operation mode. The same or corresponding components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

FIG. 8 is a diagram showing the relationship between physical addresses and logical addresses. In FIG. 8, the area is divided into four areas from area 2 to area 5 for convenience. Each area is 64K bytes. The physical address of each area is x'00000 'to x'0FFFF' for area 2 and x'1 for area 3
0000 'to x'1FFFF', area 4 is x'2000
0'-x'2FFFF ', area 5 is x'30000'-
x'3FFFF '. Since the physical address is a value obtained by subtracting x'10000 'from the logical address, when the operation mode control signal S100 is at the L level, the area 2 has x'10000' to x'1FFF.
F ', region 3 is x'20000' to x'2FFFF ',
The area 4 becomes x'30000 'to x'3FFFF'.
The area 5 is outside the logical address, cannot be accessed from the CPU 1, and becomes an unusable area. On the other hand, when the operation mode control signal S100 is at the H level,
Are x'1FFFF 'to x'10000', area 4 is x '
2FFFF 'to x'20000', area 3 is x'3FF
FF 'to x'30000'. The area 2 is outside the logical address and cannot be accessed from the CPU 1 and becomes an unusable area.

FIG. 9 is a diagram showing a storage state of ROM data of the single-chip microcomputer according to the third embodiment of the present invention, wherein ROM 2 and RAM 3 are arranged on the same logical address. 9 (a) and 9 (b) show the storage state of the CPU 1 on the logical address.
FIGS. 9C and 9D are diagrams showing the storage state on the physical address of the ROM. FIGS. 9A and 9C show the operation mode for the user (the operation mode control signal S100 is at the L level).
9 (b) and 9 (d) are views showing the storage state in the maker operation mode (operation mode control signal S100 is at H level).

In the third embodiment, the logical address space is defined as x'00000 'to x'3FFFF' for simplicity.
Up to 256 Kbytes. Also, if the RAM capacity is 64
It is assumed that K bytes and the vector address area are 256 bytes.
ROM2 has a capacity of 256 Kbytes, and x'00
It is assumed that physical addresses from 000 'to x'3FFFF' are provided. It goes without saying that these capacities can be set arbitrarily.

The operation of the single-chip microcomputer according to the third embodiment will be described below. First, the CPU 1 outputs a ROM address to the ROM address conversion means 7 via the address bus AB. And
The ROM address conversion means 7 converts the input ROM address and outputs it to the exclusive OR 8. Also, I / O
4 generates an operation mode control signal S100 based on the signal input from the I / O terminal 5, and outputs the operation mode control signal S100 to the exclusive OR 8. The exclusive OR 8 sets one of a plurality of operation modes based on the operation mode control signal S100 input from the I / O 4, and converts the converted ROM according to the set operation mode. All the addresses are rotated forward or inverted to determine the ROM address.

In the operation mode for the user, FIG.
The user vector address area is arranged in area 2 as shown in FIG.
The execution of the program is started from the reset vector address stored in (x'10000 'to x'100FF'). In this case, the logical address is not assigned to the area 5 and the area 5 becomes an unusable area, and the maker program stored in the area 5 cannot be executed in the user mode. On the other hand, in the maker operation mode, since the address signal is inverted by the exclusive OR 7, the physical address is inverted from that in the user operation mode.
As shown in the figure, the logical address x'10000 '
x'100FF 'is allocated. In the area 5, a maker vector address area and a maker program area are arranged.
The execution of the program is started from the reset vector address stored in (x'10000 'to x'100FF'). In this case, the logical address is not assigned to the area 2 and the area 2 becomes an unusable area.

That is, the ROM address conversion means 7
By subtracting x'10000 'from the logical address from PU1, for example, the logical address x'10000' of CPU1 is changed to the physical address x'000 of ROM2.
To 00 '. The exclusive OR 8 is stored in the ROM 2
Has a role of inverting the arrangement of the physical addresses of the operation modes.
Is at the L level, the ROM address converted by the ROM address conversion means 7 is supplied to the ROM 2 without inversion. On the other hand, in the case of the maker operation mode, the operation mode control signal S100 becomes H level, and the ROM address converted by the ROM address
Feed to 2. As described above, the usable area differs between the user operation mode (the operation mode control signal S100 is at the L level) and the manufacturer operation mode (the operation mode control signal S100 is at the H level). By arranging the maker vector address area and the maker program area in the area 5, the maker can arrange and execute the maker program without using the user program area.

The program is executed while reading the data stored at the determined ROM address from the ROM 2 via the data bus DB as needed. In addition, data is written to and read from the RAM 3 as needed, and command processing is performed. In some cases, it is also possible to execute an instruction arranged on the RAM 3.

Hereinafter, the third embodiment or the fourth embodiment will be described.
Rewriting in the serial mode of such a single-chip microcomputer with a built-in flash EEPROM will be described with reference to FIG. FIG. 13 is a flowchart showing a procedure for rewriting the built-in flash EEPROM in the serial mode.

First, the single-chip microcomputer is set to the maker operation mode, and the reset is released.
At this time, the maker program is started using the maker vector address (S201). The manufacturer program is
As described in the third or fourth embodiment, the data is stored in the area 5 that cannot be used in the user operation mode. The manufacturer program includes a loader program, and transfers the loader program to the RAM 3 (area 1) (S202). When the loader program is transferred to the RAM 3, the execution of the program branches to the loader program on the RAM 3 (S203). By executing the loader program, the flash EEPROM is set in a rewritable state, and the user vector address area and the user program area are erased and written.
(S204). Flash EEP by the above sequence
Although the ROM is rewritten, the area to be rewritten is all the areas that can be used by the user including the vector address area, so that it is possible to eliminate a trouble that occurs in creating a program.

As described above, it is possible to provide a single-chip microcomputer with a built-in flash EEPROM capable of rewriting all user program areas and vector address areas.

As described above, according to the single-chip microcomputer according to the third embodiment, a ROM storing various programs, a RAM storing data,
A CPU for executing a program stored in the ROM;
A single-chip microcomputer having an input / output device for inputting / outputting various control signals, a ROM address conversion unit having at least two or more operation modes, and converting a logical address output from the CPU into a physical address; A signal processing circuit for performing required processing on all bits of the address signal to the ROM in accordance with each of the operation modes, wherein the single-chip microcomputer operates in an operation mode output from the input / output device. One of the plurality of operation modes is set based on a control signal, and a required process is performed on all bits of the ROM address converted by the ROM address conversion means according to the set operation mode. To determine the ROM address, and determine the R address determined according to the operation mode.
Since the program stored in the OM address can be executed, the ROM address can be rotated or inverted, and a different program can be started according to each operation mode. Also, since the usable areas of the user operation mode and the maker operation mode are different, the maker can use the maker program without using the user program area. Further, the capacity of the ROM can be saved by effectively utilizing the program capacity.

Further, according to the single-chip microcomputer according to the third or fourth embodiment, the ROM address conversion means for converting the address and the signal processing circuit (in this embodiment, exclusive OR) The CPU
It can be realized simply by inserting it between the CPU and the ROM. Therefore, even if it is difficult to design individual products such as an IP-based CPU core or a memory core, the operation mode for the user and the manufacturer A flash EEPROM capable of switching operation modes and rewriting all user program areas and vector address areas.
A single-chip microcomputer incorporating M can be provided.

(Embodiment 4) A single-chip microcomputer according to Embodiment 4 will be described below with reference to FIGS. 10, 11, and 12. FIG. The single-chip microcomputer according to the fourth embodiment has at least two or more operation modes, ROM address conversion means for converting a logical address output from a CPU into a physical address, and ROM
And a signal processing circuit for performing a required process on the upper m bits (m is an arbitrary integer) of the address signal to the memory.

FIG. 10 is a block diagram showing a configuration of a single-chip microcomputer according to the fourth embodiment. Reference numeral 7 denotes ROM address conversion means for converting a logical address into a physical address. An exclusive OR 8 inverts or inverts the upper m bits (m is an arbitrary integer) of the address signal to the ROM according to each operation mode.

FIG. 11 is a diagram showing the relationship between physical addresses and logical addresses. In FIG. 11, the area is divided into four areas from area 2 to area 5 for convenience. Each area is 64K
Bytes. The physical address of each area is area 2
Are x'00000 'to x'0FFFF', and region 3 is x '
10000 'to x'1FFFF', area 4 is x'200
00 'to x'2FFFF', area 5 is x'30000 '
~ X'3FFFF '. When the operation mode control signal S100 is at the L level, each logical address is stored in the area 2
Are x'10000 'to x'1FFFF', and region 3 is x '
20000 'to x'2FFFF', area 4 is x'300
00 'to x'3FFFF'. The area 5 is outside the logical address, cannot be accessed from the CPU 1, and becomes an unusable area. On the other hand, the operation mode control signal S
When 100 is at the H level, area 5 is x'10000 '
~ X'1FFFF ', area 4 is x'20000' ~
x'2FFFF ', area 3 is x'30000'-x'
3FFFF '. The area 2 is outside the logical address and cannot be accessed from the CPU 1 and becomes an unusable area.

FIG. 12 is a diagram showing a storage state of the ROM data. The ROM and the RAM are arranged on the same logical address. 12A and 12B show the storage state on the logical address of the CPU 1, and FIGS. 12C and 12D show the storage state on the physical address of the ROM. 12 (a) and 12 (c) show the stored state in the user operation mode (operation mode control signal S100 is at L level), and FIGS. 12 (b) and 12 (d) show the manufacturer operation mode. Time
(Operation mode control signal S100 is at H level). Since the fourth embodiment is almost the same as the third embodiment, description of common parts will be omitted.

The operation of the single-chip microcomputer according to the fourth embodiment will be described below. First, the CPU 1 outputs a ROM address to the ROM address conversion means 7 via the address bus AB. And
The ROM address conversion means 7 converts the input ROM address and outputs it to the exclusive OR 8. Also, I / O
4 generates an operation mode control signal S100 based on the signal input from the I / O terminal 5, and outputs the operation mode control signal S100 to the exclusive OR 8. The exclusive OR 8 sets one of a plurality of operation modes based on the operation mode control signal S100 input from the I / O 4, and converts the converted ROM according to the set operation mode. An address is determined by inverting or inverting any upper bit of the address.

The program is executed while the data stored at the determined ROM address is read from the ROM 2 via the data bus DB as needed. In addition, data is written to and read from the RAM 3 as needed, and command processing is performed. In some cases, it is also possible to execute an instruction arranged on the RAM 3.

The difference from the third embodiment is that the exclusive OR 8
The number of bits for inverting the output of the ROM address conversion means 7 is all bits in the third embodiment, but is an arbitrary number of upper bits in the fourth embodiment.
This number of bits is determined by how many areas the ROM 2 is divided into. In the fourth embodiment, since the region is divided into four regions from region 2 to region 5, the number of bits that need to be inverted is the upper two bits. As described above, since the inversion operation of the ROM address is performed only on the upper bits, the required number of exclusive ORs 8 can be reduced.

The arrangement of the physical addresses in the ROM 2 in the user operation mode is the same as that of the third embodiment. However, the arrangement of the physical addresses in the ROM 2 in the manufacturer operation mode is shown in FIG. 11 and FIG. As shown, this is different from the third embodiment. However, the areas that cannot be used because logical addresses are not assigned are the same.

As described above, according to the single-chip microcomputer according to the fourth embodiment, the single-chip microcomputer according to the fifth aspect of the present invention includes:
In a single-chip microcomputer including a ROM storing various programs, a RAM storing data, a CPU executing the programs stored in the ROM, and an input / output device for inputting / outputting various control signals, at least 2 R that has one or more operation modes and converts a logical address output from the CPU into a physical address
OM address conversion means, and a signal processing circuit for performing required processing on upper m bits (m is an arbitrary integer) of address signals to the ROM in accordance with each of the operation modes; The chip microcomputer sets one of the plurality of operation modes based on an operation mode control signal output from the input / output device, and, in accordance with the set operation mode, the ROM address conversion means Among the converted ROM addresses, a ROM address for performing a required process on an upper arbitrary bit is determined, and an R address determined according to the operation mode is determined.
Since the program stored in the OM address can be executed, the number of necessary exclusive OR can be reduced, and the unusable area of the built-in ROM can be effectively used.
Saves space. In addition, CPU core converted to IP,
Even when design processing is difficult when designing individual products like a memory core, it is possible to switch between the user operation mode and the manufacturer operation mode.

[0078]

According to the single-chip microcomputer of the first aspect of the present invention, a plurality of different vectors having at least two or more operation modes and having the maximum number of the operation modes in the built-in ROM are provided. The address area is arranged as a plurality of banks at the same address in the same ROM address space, each of the plurality of programs used in each of the operation modes is arranged in a shared program area of the ROM address space, and Since a program common to different operation modes is arranged at the same address of the shared program among a plurality of programs used in each operation mode, different programs can be started according to the operation mode. In different operation modes, programs stored at the same address in the shared program area can be used. Further, the capacity of the ROM can be saved by effectively utilizing the program capacity.

According to the single-chip microcomputer of the second aspect of the present invention, the microcomputer has at least two or more operation modes, and further has a vector address output signal output from the CPU and a vector address output signal output from the input / output device. And a vector address conversion means for converting a vector address output as a logical address from the CPU in accordance with the operation mode control signal. A plurality of different vector address areas for maximizing the number of the operation modes are stored in the internal ROM. Each of the plurality of programs used in each of the operation modes is arranged in a shared program area of the ROM address space, and each of the plurality of programs used in each of the operation modes is arranged at a different address in the ROM address space. A program common to different operation modes among a plurality of programs, Having located at the same address in use program area, to determine the vector address to be used by the vector address conversion means can perform different program. In different operation modes, programs stored at the same address in the shared program area can be used. In addition, make effective use of program capacity,
ROM capacity can be saved.

According to the single-chip microcomputer of the third aspect of the present invention, there is provided a user operation mode used by one or more users and a manufacturer operation mode used by one or more manufacturers. In the internal ROM, two different vector address areas, a vector address area used in the user operation mode and a vector address area used in the maker operation mode, are arranged in the same ROM address space. A plurality of user programs and a plurality of manufacturer programs used in one of the operation mode and the manufacturer operation mode are arranged in the shared program area of the ROM address space, and the user operation mode and the Common to multiple programs used in any of the manufacturer's operating modes Are allocated at the same address in the shared program area, the user program and the maker-program use separate vector address areas, and both can use the same program area. It is possible to provide a single-chip microcomputer in which a program and a program for a maker can be selected, a program capacity can be effectively used, and a ROM capacity can be saved.

According to the single-chip microcomputer of the fourth aspect of the present invention, there is provided a ROM address conversion means having at least two or more operation modes and converting a logical address output from the CPU into a physical address,
A signal processing circuit for performing required processing on all bits of the address signal to the ROM according to each of the operation modes, so that the maker can use the maker program without using the user program area. can do. In addition, the unusable area of the built-in ROM can be effectively used, and the ROM capacity can be saved. In addition, since it can be realized only by inserting a control means (ROM address conversion means, exclusive OR) for converting an address between the CPU and the ROM, it can be realized individually as in a CPU core converted into an IP or a memory core. It is possible to switch between the operation mode for the user and the operation mode for the manufacturer even when the design processing is difficult when designing the product. Further, it is possible to provide a single-chip microcomputer with a built-in flash EEPROM capable of rewriting all user program areas and vector address areas.

According to the single-chip microcomputer of the fifth aspect of the present invention, there is provided ROM address conversion means having at least two or more operation modes, and converting a logical address output from the CPU into a physical address,
A signal processing circuit for performing a required process on the upper m bits (m is an arbitrary integer) of the address signal to the ROM according to each of the operation modes. Since only the upper-order arbitrary number of bits of the address to be inverted is inverted or inverted, it is possible to start a different program according to the operation mode and to reduce the number of exclusive ORs. In addition, built-in RO
The unusable area of M can be effectively used, and the ROM capacity can be saved. Furthermore, even when an optimum memory capacity cannot be selected as in the case of a memory core converted into an IP, and there is an area that cannot be used as it is, the memory can be effectively used. It is possible to provide a single-chip microcomputer with a built-in flash EEPROM that can utilize the unusable ROM area and can rewrite all user program areas and vector address areas.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a single-chip microcomputer according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing a storage state of ROM data of the single-chip microcomputer according to the first embodiment of the present invention.

FIG. 3 is a comparison diagram of a ROM data storage state between a conventional single-chip microcomputer and the single-chip microcomputer according to the first embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a single-chip microcomputer according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a storage state of ROM data of a single-chip microcomputer according to a second embodiment of the present invention.

FIG. 6 is a comparison diagram of a ROM data storage state between a conventional single-chip microcomputer and the single-chip microcomputer according to the second embodiment of the present invention.

FIG. 7 is a block diagram of a single-chip microcomputer according to Embodiment 3 of the present invention.

FIG. 8 is a diagram showing a relationship between a physical address and a logical address of the single-chip microcomputer according to the third embodiment of the present invention.

FIG. 9 is a diagram showing a storage state of ROM data of a single-chip microcomputer according to Embodiment 3 of the present invention.

FIG. 10 is a block diagram showing a configuration of a single-chip microcomputer according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a relationship between physical addresses and logical addresses of a single-chip microcomputer according to a fourth embodiment of the present invention.

FIG. 12 is a diagram showing a storage state of ROM data of a single-chip microcomputer according to a fourth embodiment of the present invention.

FIG. 13: Flash EEPROM in serial mode
9 is a flowchart showing a procedure for rewriting the data.

FIG. 14 is a block diagram showing a configuration of a conventional single-chip microcomputer.

FIG. 15 is a diagram showing a storage state of ROM data of a conventional single-chip microcomputer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 ROM 3 RAM 4 I / O 5 I / O terminal 6 Vector address conversion means 7 ROM address conversion means 8 Exclusive OR DB Data bus AB Address bus S100 Operation mode control signal S101 Vector address output signal

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[Procedure amendment]

[Submission date] November 8, 2001 (2001.11.
8)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0061

[Correction method] Change

[Correction contents]

In the operation mode for the user, FIG.
The user vector address area is arranged in the area 2 as shown in FIG.
The execution of the program is started from the reset vector address stored in (x'10000 'to x'100FF'). In this case, the logical address is not assigned to the area 5 and the area 5 becomes an unusable area, and the maker program stored in the area 5 cannot be executed in the user mode. On the other hand, in the maker operation mode, since the address signal is inverted by the exclusive OR 8 , the physical address is inverted from that in the user operation mode.
As shown in the figure, the logical address x'10000 '
x'100FF 'is allocated. In the area 5, a maker vector address area and a maker program area are arranged.
The execution of the program is started from the reset vector address stored in (x'10000 'to x'100FF'). In this case, a logical address is not assigned to the area 2 and the area 2 becomes an unusable area.

Claims (5)

[Claims] A single-chip microcomputer including a ROM storing various programs, a RAM storing data, a CPU for executing the programs stored in the ROM, and an input / output device for outputting various control signals. In the ROM, a plurality of different vector address areas that maximize the number of the operation modes are arranged as a plurality of banks at the same address in the same ROM address space, Each of the plurality of programs used in each of the operation modes is arranged in a shared program area of the ROM address space, and is shared by different operation modes among the plurality of programs used in each of the operation modes. Are located at the same address in the shared program area, The single-chip microcomputer sets one of the plurality of operation modes based on an operation mode control signal output from the input / output device, switches banks, and uses different vector address areas. The program to be executed can be changed according to the set operation mode, and the program stored at the same address in the shared program area can be executed in the different operation mode. Single-chip microcomputer. 2. A single chip micro-computer having a ROM storing various programs, a RAM storing data, a CPU for executing the programs stored in the ROM, and an input / output device for inputting / outputting various control signals. The computer has at least two or more operation modes, and according to a vector address output signal output from the CPU and an operation mode control signal output from the input / output device,
Vector address conversion means for converting a vector address output as a logical address from the CPU, wherein in the ROM, a plurality of different vector address areas for maximizing the number of operation modes are different addresses in the same ROM address space. Each of the plurality of programs used in each of the operation modes is arranged in a shared program area of the ROM address space, and differs among the plurality of programs used in each of the operation modes. A program common to the operation modes is arranged at the same address in the shared program area, and the single-chip microcomputer is configured to output one of the plurality of operation modes based on an operation mode control signal output from the input / output device. And the vector address conversion means Can execute the program stored in the determined vector address area,
And a single-chip microcomputer capable of executing programs stored at the same address in the shared program area in the different operation modes. 3. The single-chip microcomputer according to claim 1, wherein the operation modes include: a user operation mode used by one or more users;
The ROM includes two different vector addresses: a vector address area used in the user operation mode, and a vector address area used in the manufacturer operation mode. Areas are arranged in the same ROM address space, and each of the plurality of user programs and manufacturer programs used in one of the user operation mode and the manufacturer operation mode is the shared program in the ROM address space. A program common to a plurality of programs used in one of the user operation mode and the maker operation mode, which is arranged in an area, and is arranged at the same address of the shared program area; Single-chip microcomputer, each of the above operation modes The user program and the manufacturer program can be selected by using different vector address areas in accordance with each other, and in any one of the user operation mode and the manufacturer operation mode, A single-chip microcomputer capable of executing programs stored at the same address in a shared program area. 4. A single chip micro-computer having a ROM storing various programs, a RAM storing data, a CPU for executing the programs stored in the ROM, and an input / output device for inputting / outputting various control signals. A computer having at least two or more operation modes, a ROM address conversion means for converting a logical address output from a CPU into a physical address, and all bits of an address signal to the ROM according to each operation mode And a signal processing circuit for performing required processing on the single-chip microcomputer, wherein the single-chip microcomputer sets one of the plurality of operation modes based on an operation mode control signal output from the input / output device. R converted by the ROM address conversion means in accordance with the set operation mode. A single chip that is capable of performing a required process on all bits of the OM address to determine a ROM address, and executing a program stored in the ROM address determined according to the operation mode. Microcomputer. 5. A single-chip micro-computer having a ROM storing various programs, a RAM storing data, a CPU for executing the programs stored in the ROM, and an input / output device for inputting / outputting various control signals. A computer having at least two or more operation modes, a ROM address conversion means for converting a logical address output from a CPU into a physical address, and a higher-order address signal to the ROM in accordance with each operation mode a signal processing circuit for performing a required process on m bits (m is an arbitrary integer), wherein the single-chip microcomputer performs the plurality of operations based on an operation mode control signal output from the input / output device. Setting one of the modes, and converting the ROM address according to the set operation mode. It is possible to determine a ROM address for performing a required process on upper arbitrary bits from among the ROM addresses converted by the stage, and to execute a program stored in the ROM address determined according to the operation mode. A single-chip microcomputer, characterized in that: