JP2002033433A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2002033433A JP2002033433A JP2000217240A JP2000217240A JP2002033433A JP 2002033433 A JP2002033433 A JP 2002033433A JP 2000217240 A JP2000217240 A JP 2000217240A JP 2000217240 A JP2000217240 A JP 2000217240A JP 2002033433 A JP2002033433 A JP 2002033433A
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- terminal electrode
- lead frame
- semiconductor device
- main circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、導体パターンの上
にスイッチング用半導体素子が固着され、これが絶縁材
料によって電気的に絶縁された半導体装置に係り、特
に、熱抵抗を容易に低減し、かつ、高耐電圧構造の半導
体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a switching semiconductor element is fixed on a conductor pattern and is electrically insulated by an insulating material. And a semiconductor device having a high withstand voltage structure.
【0002】[0002]
【従来の技術】従来、パワー半導体装置としては特公平
3−63822号および特公平6−80748号公報に
示される構成のものがある。即ち、導体パターンを構成
するリードフレーム上に半導体素子を載置して主回路部
を形成し、第1の樹脂モールドを形成する。次いで、ベ
ース板上に所定間隔の隙間を設けて前記主回路部を配置
して第2の樹脂モールドを行い、リードフレームの一部
を側面に導出して端子電極と成して一体の半導体装置と
するものである。この構造によれば次のような問題があ
る。2. Description of the Related Art Conventionally, as a power semiconductor device, there is a power semiconductor device having a configuration disclosed in Japanese Patent Publication No. 3-63822 and Japanese Patent Publication No. 6-80748. That is, a semiconductor element is mounted on a lead frame constituting a conductor pattern to form a main circuit portion, and a first resin mold is formed. Next, the main circuit portion is disposed on the base plate with a predetermined gap therebetween, and the second resin molding is performed. A part of the lead frame is led out to the side surface to form a terminal electrode, thereby forming an integrated semiconductor device. It is assumed that. This structure has the following problems.
【0003】通常、この種の半導体装置は、外部への熱
放散のために放熱フィンが下面に固着,形成される。こ
の放熱フィンは、端子電極と電気的に絶縁する必要があ
る。しかし、上記の従来構造では端子電極が側面から導
出されているため、3次元的に放熱フィンからの電気的
な絶縁空間距離を十分に確保しにくいと云う問題があ
る。Usually, in this type of semiconductor device, a heat radiation fin is fixedly formed on a lower surface for heat dissipation to the outside. The radiation fins need to be electrically insulated from the terminal electrodes. However, in the above-described conventional structure, since the terminal electrode is led out from the side surface, there is a problem that it is difficult to sufficiently secure an electrical insulation space distance from the radiation fins three-dimensionally.
【0004】また、この他のこうしたパワー半導体装置
としては、特開平7−22576号公報がある。本構造
の半導体装置の導体パターンは、エッチングによって形
成される。そのため導体パターンの層厚は、実用面から
最大でも0.3mm程度である。従って、大電流を流す
ためには基板(ベース板)の面方向に、幅広の導体パタ
ーンを形成する必要がある。その結果、導体パターンを
配置する基板面積が増大し、ひいては半導体装置そのも
のが大型化すると云う問題がある。Another such power semiconductor device is disclosed in JP-A-7-22576. The conductor pattern of the semiconductor device having this structure is formed by etching. Therefore, the layer thickness of the conductor pattern is at most about 0.3 mm from a practical point of view. Therefore, in order to flow a large current, it is necessary to form a wide conductor pattern in the plane direction of the substrate (base plate). As a result, there is a problem that the area of the substrate on which the conductor pattern is arranged increases, and the semiconductor device itself becomes larger.
【0005】[0005]
【発明が解決しようとする課題】本発明の目的は、前記
の従来技術の問題である端子電極−放熱フィン間の絶縁
空間距離を十分確保すると共に、導体パターンの線幅、
即ち、実装面積を広くすることなしに許容電流を増すこ
とができ、低熱抵抗性、高絶縁耐圧で高信頼性パワー半
導体装置を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to secure a sufficient insulating space distance between a terminal electrode and a radiating fin, which is a problem of the prior art, and to reduce the line width of a conductor pattern.
That is, an object of the present invention is to provide a power semiconductor device which can increase the allowable current without increasing the mounting area, and has a low thermal resistance, a high dielectric strength and a high reliability.
【0006】[0006]
【課題を解決するための手段】上記目的を達成する本発
明の要旨次のとおりである。The gist of the present invention to achieve the above object is as follows.
【0007】上下に相対する主面1と主面2を有し、か
つ、導体パターンを有する主回路部と、端子電極および
ベース板を有する半導体装置において、前記主回路部
は、主面1側に配置された前記ベース板上に、フィラー
を含む樹脂材料で構成された絶縁層を介して導体パター
ンが形成され、前記導体パターンは少なくとも1つの立
ち上げ部を有し、該立ち上げ部の延長部分に前記端子電
極が形成され、該端子電極は主面2から外部に導出され
ており、前記導体パターン上に少なくとも1つのスイッ
チング用半導体素子が固着されており、前記導体パター
ンおよび前記端子電極とが同一材料で一体に形成された
リードフレームであって、前記主回路部が樹脂モールド
されており、前記導体パターンの層厚が少なくとも0.
5mmである半導体装置にある。In a semiconductor device having a main circuit portion having upper and lower opposing main surfaces 1 and 2 and having a conductor pattern, and a terminal electrode and a base plate, the main circuit portion is located on the main surface 1 side. A conductive pattern is formed on the base plate disposed on the base plate via an insulating layer made of a resin material containing a filler, and the conductive pattern has at least one rising portion, and is an extension of the rising portion. The terminal electrode is formed in a portion, the terminal electrode is led out from the main surface 2, at least one switching semiconductor element is fixed on the conductor pattern, and the terminal electrode Is a lead frame integrally formed of the same material, wherein the main circuit portion is resin-molded, and a layer thickness of the conductor pattern is at least 0.3.
The semiconductor device is 5 mm.
【0008】上記の構成とすることにより、主面2に固
着された放熱フィンを端子電極の対面に配置できるの
で、絶縁空間距離を容易に確保することができる。With the above configuration, the radiation fins fixed to the main surface 2 can be arranged on the opposite surface of the terminal electrode, so that the insulation space distance can be easily secured.
【0009】また、前記導体パターンの層厚を少なくと
も0.5mmとしたことで、熱抵抗が低減でき、単位面
積の電流容量が格段に増すことができ、該半導体装置の
小形化を容易に図ることができる。Further, by setting the layer thickness of the conductor pattern to at least 0.5 mm, the thermal resistance can be reduced, the current capacity per unit area can be significantly increased, and the size of the semiconductor device can be easily reduced. be able to.
【0010】なお、上記半導体装置において、前記端子
電極の立ち上げ部にくびれ部を設け、該くびれ部の断面
積が、該くびれ部の直近の断面積を1としたとき、0.
7以下に設定した。本構成とすることで前記リードフレ
ームの垂直立上げのための折り曲げ加工が極めて容易と
なる。In the above-mentioned semiconductor device, a constricted portion is provided at a rising portion of the terminal electrode, and a cross-sectional area of the constricted portion is 0.1 when a cross-sectional area immediately adjacent to the constricted portion is 1.
7 or less. With this configuration, the bending process for vertically raising the lead frame becomes extremely easy.
【0011】[0011]
【発明の実施の形態】以下、本発明を実施例に基づき詳
細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.
【0012】〔実施例 1〕図1は本実施例による半導
体装置の模式断面図であり、図2はその平面模式図であ
る。図1では、上側が本半導体装置の主面2、下側が主
面1を示す。例えば、IGBT(Insulated Gate Bi
polar Transistor)などのスイッチング用半導体素子
11が、はんだ接着層12を介してリードフレーム13
の上面に固着され、これら一連の主回路構成部品が樹脂
モールド30によって被覆され、主面2側に端子電極1
7が導出される。Embodiment 1 FIG. 1 is a schematic sectional view of a semiconductor device according to the present embodiment, and FIG. 2 is a schematic plan view thereof. In FIG. 1, the upper side shows the main surface 2 of the present semiconductor device, and the lower side shows the main surface 1. For example, IGBT (Insulated Gate Bi
A switching semiconductor element 11 such as a polar transistor is connected to a lead frame 13 via a solder bonding layer 12.
, And a series of main circuit components are covered with a resin mold 30, and the terminal electrode 1
7 is derived.
【0013】リードフレーム13の下面は、フィラーと
してのアルミナを70重量%含む樹脂絶縁層18を介し
てベース板15に接着される。The lower surface of the lead frame 13 is bonded to the base plate 15 via a resin insulating layer 18 containing 70% by weight of alumina as a filler.
【0014】前記半導体素子11は、アルミニウムのワ
イヤボンデイング部16によりリードフレーム13と電
気的に接続される。該リードフレーム13の一部が端子
電極17と成り、樹脂モールド30の主面2の表面にほ
ぼ垂直に導出され、主回路を構成する。なお、本構成で
は、リードフレーム13の材料として、Niメッキされ
た厚さ0.4mmの無酸素銅を用い、フィラーを含む樹
脂絶縁層に接着する構造としたので、高い熱伝導性と電
気伝導性を確保することができる。The semiconductor element 11 is electrically connected to the lead frame 13 by an aluminum wire bonding portion 16. A part of the lead frame 13 becomes a terminal electrode 17 and is led out almost perpendicularly to the surface of the main surface 2 of the resin mold 30 to form a main circuit. In this configuration, Ni-plated 0.4 mm thick oxygen-free copper is used as the material of the lead frame 13, and the lead frame 13 is bonded to the resin insulating layer containing the filler. Nature can be secured.
【0015】本構造のパワー半導体装置は、次の工程に
よって作製される。The power semiconductor device having this structure is manufactured by the following steps.
【0016】プレス加工により所定パターン形状で、厚
さ0.4mmの銅製リードフレーム13を形成する。こ
の工程で導体パターンおよび端子電極を構成する両部分
とで図3に示す段差33が付与される。なお、本工程に
おけるリードフレームの全体構造を図3に、また、図3
のA部の詳細図を図4にそれぞれ示す。A copper lead frame 13 having a predetermined pattern and a thickness of 0.4 mm is formed by pressing. In this step, a step 33 shown in FIG. 3 is given to both portions constituting the conductor pattern and the terminal electrode. FIG. 3 shows the overall structure of the lead frame in this step.
4 is shown in detail in FIG.
【0017】図1に示すように、前記リードフレーム1
3の導体パターン部とベース板15との間に、厚さ0.
16mmの未硬化性樹脂シートを挿入し、加熱圧着によ
り一体化して、樹脂絶縁層18を形成する。次いで、段
差部33を上方に折り曲げて端子電極部17を垂直に立
ち上げる。リードフレーム13の導体パターン上に半導
体素子11としてIGBTチップを搭載し、はんだ接合
する。次いで、直径0.3mmφのAlワイヤによっ
て、素子11およびリードフレーム13を電気的に接続
して主回路を構成する。As shown in FIG.
3 between the conductive pattern portion 3 and the base plate 15.
A resin insulating layer 18 is formed by inserting a 16 mm uncured resin sheet and integrating it by heating and pressing. Next, the step portion 33 is bent upward to vertically raise the terminal electrode portion 17. An IGBT chip is mounted as a semiconductor element 11 on the conductor pattern of the lead frame 13 and soldered. Next, the element 11 and the lead frame 13 are electrically connected by an Al wire having a diameter of 0.3 mmφ to form a main circuit.
【0018】上記工程で形成された主回路部にPPS
(Poly Phenylene Sulfide)製ケース32をシリコ
ーン樹脂によって接着,固定し、所定条件でフィラーを
含むエポキシ系樹脂(液状の樹脂)を前記ケース32内
に注入,充填し、加熱硬化することにより樹脂モールド
30を成形して、パワー半導体装置を得る。In the main circuit portion formed in the above process, PPS is used.
(Poly Phenylene Sulfide) case 32 is adhered and fixed with a silicone resin, and an epoxy resin (liquid resin) containing a filler is injected and filled into the case 32 under predetermined conditions, and is cured by heating. To obtain a power semiconductor device.
【0019】本実施例では、樹脂モールド30の材料と
して表1に示すものを用いた。なお、表1において、配
合比は重量部を示す。In this embodiment, the materials shown in Table 1 were used as the material of the resin mold 30. In Table 1, the compounding ratio indicates parts by weight.
【0020】[0020]
【表1】 [Table 1]
【0021】本材料は、フィラーとして酸化けい素(平
均粒径10〜200μm)を多量に含むので線膨張係数
が18ppm/℃と低く、成形,硬化後のベース板15
の反りを抑制できる。This material has a low linear expansion coefficient of 18 ppm / ° C. because it contains a large amount of silicon oxide (average particle size of 10 to 200 μm) as a filler.
Warpage can be suppressed.
【0022】モールド成形後、アフターキュアを施しモ
ールド樹脂の硬化を促進する。次いで、樹脂モールド3
0の外部に導出されたリードフレーム13の端子電極相
当部を切断および/または成形して、所定形状の端子電
極17を形成した半導体装置を得る。After the molding, after-curing is performed to accelerate the curing of the molding resin. Next, the resin mold 3
The semiconductor device in which the terminal electrode 17 having a predetermined shape is formed by cutting and / or shaping a portion corresponding to the terminal electrode of the lead frame 13 led out of the lead frame 13.
【0023】図5に、放熱フィン21を装着した本発明
による半導体装置の模式断面図を示す。該半導体装置
は、そのグランド電位を有するフィン21と、端子電極
17とが上下の主面にそれぞれ配置され、両者の間隔は
凡そ10mm以上となるので、絶縁空間距離を十分に確
保することができる。FIG. 5 is a schematic cross-sectional view of a semiconductor device according to the present invention having the radiation fins 21 mounted thereon. In the semiconductor device, the fin 21 having the ground potential and the terminal electrode 17 are arranged on the upper and lower main surfaces, respectively, and the interval between them is about 10 mm or more, so that a sufficient insulation space distance can be secured. .
【0024】本実施例では半導体素子11として、単数
のIGBT素子を用いた例について示したが、例えば、
MOS系トランジスタ,ダイオードなど他の種類の半導
体素子であってよい。さらにまた、これら複数素子の組
み合わせによる特定の回路、例えば、インバータ用パワ
ーモジュール等であってよい。In this embodiment, an example in which a single IGBT element is used as the semiconductor element 11 has been described.
Other types of semiconductor elements such as MOS transistors and diodes may be used. Furthermore, a specific circuit formed by a combination of these plural elements, for example, an inverter power module or the like may be used.
【0025】また、本実施例では樹脂モールド30に含
まれるフィラーとして、表1に示す酸化けい素を示した
が、他の材料、例えば、アルミナ,ベリリヤ,ジルコニ
ヤ,窒化けい素,窒化アルミニウム,炭化けい素等であ
ってよい。In this embodiment, the silicon oxide shown in Table 1 is shown as a filler contained in the resin mold 30, but other materials such as alumina, beryllia, zirconia, silicon nitride, aluminum nitride, and carbonized It may be silicon or the like.
【0026】本実施例によれば、リードフレーム13に
段差部33が形成されるので、導体パターンの接着工程
においても端子電極部17は接着されず、自由な状態で
あるため、立ち上げ工程が容易となる効果がある。According to the present embodiment, since the step portion 33 is formed on the lead frame 13, the terminal electrode portion 17 is not bonded even in the bonding step of the conductor pattern and is in a free state. This has the effect of being easier.
【0027】〔実施例 2〕図1に示す実施例1とほぼ
同様の構造の他の実施例として、リードフレーム13の
層厚を、例えば、0.6mm,1.0mm,1.4mmと
増し、その他は実施例1と同様の構造とした。[Embodiment 2] As another embodiment having a structure substantially similar to that of Embodiment 1 shown in FIG. 1, the layer thickness of the lead frame 13 is increased to, for example, 0.6 mm, 1.0 mm, and 1.4 mm. The other structure was the same as that of the first embodiment.
【0028】本構造によれば、半導体素子11で発生す
る熱が水平方向に容易に拡散でき、実施例1の構成に比
較して熱抵抗を凡そ10〜20%低減できる。According to this structure, the heat generated in the semiconductor element 11 can be easily diffused in the horizontal direction, and the thermal resistance can be reduced by about 10 to 20% as compared with the structure of the first embodiment.
【0029】リードフレーム13の層厚を変えて、半導
体素子11とベース板15との間の熱抵抗の測定結果の
グラフを図6に示す。リードフレーム13の厚さが0.
5mm以下の領域では熱抵抗の急峻な上昇がある。この
ため、リードフレーム13の厚さを0.5mm以上と厚
く設定することにより、特に熱抵抗の低減に有効であ
る。FIG. 6 is a graph showing the measurement results of the thermal resistance between the semiconductor element 11 and the base plate 15 by changing the layer thickness of the lead frame 13. When the thickness of the lead frame 13 is
In the region of 5 mm or less, there is a sharp rise in thermal resistance. Therefore, setting the thickness of the lead frame 13 to be as thick as 0.5 mm or more is particularly effective for reducing the thermal resistance.
【0030】〔実施例 3〕実施例1とほぼ同様の構造
の他の実施例を図7,図8に示す。実施例1と異なる点
はこれら図7,8に示すように、導体パターン部と端子
電極部との境界にくびれ部19を形成したことにある。
なお、本実施例ではその端子電極部の幅1.5mm、く
びれ部の幅1mmとした。[Embodiment 3] Another embodiment having substantially the same structure as that of Embodiment 1 is shown in FIGS. The difference from the first embodiment is that, as shown in FIGS. 7 and 8, a constricted portion 19 is formed at the boundary between the conductor pattern portion and the terminal electrode portion.
In this example, the width of the terminal electrode portion was 1.5 mm, and the width of the constricted portion was 1 mm.
【0031】また、くびれ部19のパターン幅を1.5
mmから0.3mmまで段階的に変え、リードフレーム
13を接着した後、垂直に折り曲げる実験をした。端子
電極17の幅は1.5mmとし、リードフレーム厚さは
前記くびれ部19も含め0.8mm一定とした。The pattern width of the constricted portion 19 is set to 1.5.
An experiment was conducted in which the lead frame 13 was adhered to the lead frame 13 and then vertically bent after changing the thickness stepwise from 0.3 mm to 0.3 mm. The width of the terminal electrode 17 was 1.5 mm, and the thickness of the lead frame including the constricted portion 19 was 0.8 mm.
【0032】折り曲げ加工後のサンプルを絶縁浴(3M
製:フロリナート)中にセットして絶縁層18の破壊電
圧を測定した。図9に示すように、くびれ部/端子電極
部の断面積比が0.7を超えると破壊電圧値が低下し
た。これはくびれが小さいと折り曲げ時の機械的抵抗力
が大きく、絶縁層18に損傷を与えてしまうためであ
る。The sample after bending is placed in an insulating bath (3M
(Fluorinert). The breakdown voltage of the insulating layer 18 was measured. As shown in FIG. 9, when the sectional area ratio of the constricted portion / terminal electrode portion exceeded 0.7, the breakdown voltage decreased. This is because if the constriction is small, the mechanical resistance at the time of bending is large, and the insulating layer 18 is damaged.
【0033】一方、断面積比0.2未満では、折り曲げ
加工は容易になる反面、折り曲げ後の形状が不安定で、
その電気抵抗の上昇も大きくなるので好ましくない。On the other hand, when the cross-sectional area ratio is less than 0.2, the bending process is facilitated, but the shape after the bending is unstable.
This is not preferable because the increase in the electric resistance also increases.
【0034】本実施例では図7に示すようにリードフレ
ーム13の厚さが一定で平面図上にくびれ部を設けた例
について示したが、この折り曲げ部に厚さ方向のくびれ
部を設けても同様に折り曲げ加工が容易にできる。この
場合にもくびれ部19の断面積比は0.3〜0.7の範囲
が好ましい。In this embodiment, as shown in FIG. 7, an example is shown in which the thickness of the lead frame 13 is constant and a constricted portion is provided on a plan view. However, a constricted portion in the thickness direction is provided in the bent portion. Similarly, bending can be easily performed. Also in this case, the sectional area ratio of the constricted portion 19 is preferably in the range of 0.3 to 0.7.
【0035】また、図7に示すようにリードフレーム1
3は、段差部33を有しているので、導体パターン部を
樹脂絶縁層18に接着後、端子電極部17を容易に垂直
方向に折り曲げることができ、十分な絶縁距離を確保す
ることができる。Also, as shown in FIG.
3 has the step portion 33, so that after bonding the conductor pattern portion to the resin insulating layer 18, the terminal electrode portion 17 can be easily bent in the vertical direction, and a sufficient insulation distance can be secured. .
【0036】〔実施例 4〕実施例1とほぼ同様の構造
の他の実施例を図10〜図12に示す。実施例1と異な
る点は図11に示すように、リードフレーム13の非接
着部分の層厚、即ち肉の厚さを予め薄くしておくことに
よって前記段差33を形成したものである。Embodiment 4 FIGS. 10 to 12 show another embodiment having a structure substantially similar to that of the first embodiment. The difference from the first embodiment is that, as shown in FIG. 11, the step 33 is formed by previously reducing the layer thickness of the non-adhesive portion of the lead frame 13, that is, the thickness of the wall.
【0037】次いで、図12に示すように絶縁層18へ
の接着工程の後、図に示すように端子電極部17を垂直
方向に折り曲げる。これ以外の工程については実施例1
と同様に行い、本発明の半導体装置を作製した。Next, after the step of bonding to the insulating layer 18 as shown in FIG. 12, the terminal electrode portion 17 is bent vertically as shown in the figure. For other steps, see Example 1.
The semiconductor device of the present invention was manufactured in the same manner as described above.
【0038】リードフレーム13の厚さを局所的に薄く
する手段としては、例えば、エッチング、もしくは機械
的手段によるプレス加工、切削加工などがある。Means for locally reducing the thickness of the lead frame 13 include, for example, etching, mechanical pressing, and cutting.
【0039】本実施例による段差部33を設けることに
よって、実施例3と同様に導体パターン部を樹脂絶縁層
18に接着後、端子電極部17を容易に垂直に折り曲げ
ることができ、十分な絶縁距離を確保することができ
る。By providing the step portion 33 according to the present embodiment, the terminal electrode portion 17 can be easily bent vertically after the conductor pattern portion is bonded to the resin insulating layer 18 in the same manner as in the third embodiment. The distance can be secured.
【0040】〔実施例 5〕実施例1とほぼ同様の構造
の他の実施例を図13〜図15に示す。実施例1と異な
る点は図13に示すように、リードフレーム13には段
差が形成されておらず平坦なことである。Embodiment 5 FIGS. 13 to 15 show another embodiment having a structure substantially similar to that of the first embodiment. The difference from the first embodiment is that, as shown in FIG. 13, the lead frame 13 is flat with no steps formed.
【0041】次いで、図14に示すように絶縁層18へ
の接着工程において、リードフレーム13の端子電極部
17に離形材31を挿入または当接する。該離形材31
としては厚さ0.05mmのポリイミドシートを用い
た。導体パターン部接着後、図15に示すように端子電
極部17を垂直に折り曲げて、ポリイミドシートを除去
した。その他の工程は実施例1と同様に行い本発明の半
導体装置を作製した。Next, as shown in FIG. 14, in the step of bonding to the insulating layer 18, the release material 31 is inserted or brought into contact with the terminal electrode portion 17 of the lead frame 13. Release material 31
A polyimide sheet having a thickness of 0.05 mm was used. After bonding the conductor pattern portion, the terminal electrode portion 17 was vertically bent as shown in FIG. 15 to remove the polyimide sheet. Other steps were performed in the same manner as in Example 1 to manufacture a semiconductor device of the present invention.
【0042】本実施例では離形材31としてポリイミド
シートを用いたが、他の材料による離形材であってよ
い。さらにリードフレーム13の所定部分に塗布型の離
形材を塗布してもよい。Although a polyimide sheet is used as the release material 31 in this embodiment, a release material made of another material may be used. Further, a coating type release material may be applied to a predetermined portion of the lead frame 13.
【0043】上記離形材31を配置することによって、
導体パターン部を樹脂絶縁層18に接着後、端子電極部
17を容易に垂直に折り曲げることができ、十分な絶縁
距離を確保することができる。By disposing the release material 31,
After bonding the conductor pattern portion to the resin insulation layer 18, the terminal electrode portion 17 can be easily bent vertically, and a sufficient insulation distance can be secured.
【0044】〔実施例 6〕実施例1とほぼ同様の構造
の他の実施例を図16に示す。実施例1と異なる点は図
16に示すように、端子電極部を予め垂直に折り曲げた
形状のリードフレーム13を準備し、導体パターン部を
樹脂絶縁層18に直接接着するものである。[Embodiment 6] FIG. 16 shows another embodiment having a structure substantially similar to that of the first embodiment. The difference from the first embodiment is that, as shown in FIG. 16, a lead frame 13 having a terminal electrode portion bent vertically in advance is prepared, and the conductor pattern portion is directly bonded to the resin insulating layer 18.
【0045】本実施例によれば、実施例1,2で示した
くびれ部19は特に必要とせず、前記実施例3に示す導
体パターン部接着後の端子電極部17の折り曲げ工程を
省くことができ、組立工程を簡略化できる。According to this embodiment, the constricted portion 19 shown in the first and second embodiments is not particularly required, and the step of bending the terminal electrode portion 17 after the bonding of the conductor pattern portion shown in the third embodiment can be omitted. And the assembly process can be simplified.
【0046】〔実施例 7〕図17は、リードフレーム
の厚さ0.8mm、端子電極17およびくびれ部19の
パターン幅をそれぞれ1.5mm、1mmに設定して、
実施例1により作製した半導体装置を適用した家庭用空
調機の回路構成図である。Embodiment 7 FIG. 17 shows that the thickness of the lead frame is set to 0.8 mm, and the pattern widths of the terminal electrode 17 and the constricted portion 19 are set to 1.5 mm and 1 mm, respectively.
1 is a circuit configuration diagram of a home air conditioner to which a semiconductor device manufactured according to a first embodiment is applied.
【0047】本図のうち、圧縮機駆動用のモータ3を制
御するスイッチング回路に、本発明による半導体装置を
適用したものである。In the figure, a semiconductor device according to the present invention is applied to a switching circuit for controlling a motor 3 for driving a compressor.
【0048】図18に、上記のスイッチング回路部の詳
細を示す。図中、PおよびNの端子が電源回路に接続さ
れる。本構成の空調機とすることにより、低熱抵抗で、
かつ、高信頼性のスイッチング回路部が得られ、省エネ
ルギー型の空調機を提供することができる。FIG. 18 shows the details of the switching circuit section. In the figure, terminals P and N are connected to a power supply circuit. With the air conditioner of this configuration, low heat resistance,
In addition, a highly reliable switching circuit can be obtained, and an energy-saving air conditioner can be provided.
【0049】図19は、本スイッチング回路部の半導体
装置の模式断面図である。スイッチング素子11として
の6個のIGBTを配置し、リードフレーム13上に主
回路を形成し、樹脂基板14上にドライバIC19を含
む制御回路部を形成したものである。FIG. 19 is a schematic sectional view of a semiconductor device of the present switching circuit section. A main circuit is formed on a lead frame 13, and a control circuit section including a driver IC 19 is formed on a resin substrate 14.
【0050】本実施例の構成を、家庭用もしくは産業用
などのモータを具備する電気機器、例えば、冷蔵庫,冷
凍庫,ポンプ,搬送機などに適用することにより、前記
のように端子電極17の絶縁空間距離を十分確保でき、
かつ、厚さが厚いリードフレーム17の作用により低熱
抵抗化が可能となり、省エネルギー型の高信頼性電気機
器を提供することができる。By applying the structure of this embodiment to electric equipment having a motor for home use or industrial use, for example, a refrigerator, a freezer, a pump, a transporter, etc., the insulation of the terminal electrode 17 as described above is achieved. You can secure enough space distance,
In addition, the thermal resistance can be reduced by the action of the lead frame 17 having a large thickness, and an energy-saving high-reliability electrical device can be provided.
【0051】[0051]
【発明の効果】本発明によれば、放熱フィンと端子電極
との絶縁空間距離を十分確保でき、信頼性の高い半導体
装置を提供することができる。According to the present invention, it is possible to secure a sufficient insulating space distance between the radiation fin and the terminal electrode, and to provide a highly reliable semiconductor device.
【0052】導体パターンの層厚を0.5mm以上と厚
く設定することで、熱抵抗を低減すると共に導体パター
ンの配線幅を小さくでき、該半導体装置を小形化でき
る。By setting the layer thickness of the conductor pattern to be as thick as 0.5 mm or more, the thermal resistance can be reduced and the wiring width of the conductor pattern can be reduced, so that the semiconductor device can be downsized.
【0053】また、導体パターンの接着工程において、
端子電極部17と樹脂絶縁層18とが接着しない手段を
講じたことで、端子電極部17の折り曲げ加工が容易と
なり、高信頼性の半導体装置を容易に実現できる。In the bonding step of the conductor pattern,
By taking measures to prevent the terminal electrode portion 17 from adhering to the resin insulating layer 18, the bending process of the terminal electrode portion 17 becomes easy, and a highly reliable semiconductor device can be easily realized.
【図1】実施例1のパワー半導体装置の模式断面図であ
る。FIG. 1 is a schematic sectional view of a power semiconductor device according to a first embodiment.
【図2】図1のパワー半導体装置の模式平面図である。FIG. 2 is a schematic plan view of the power semiconductor device of FIG.
【図3】実施例1のリードフレームの構造図である。FIG. 3 is a structural diagram of a lead frame according to the first embodiment.
【図4】図3のリードフレームのA部詳細図である。FIG. 4 is a detailed view of a portion A of the lead frame of FIG. 3;
【図5】実施例1の放熱フィンを装着したパワー半導体
装置の模式断面図である。FIG. 5 is a schematic cross-sectional view of the power semiconductor device to which the heat radiation fin of Example 1 is attached.
【図6】実施例2のパワー半導体装置の熱抵抗の測定結
果を示すグラフである。FIG. 6 is a graph showing the measurement results of the thermal resistance of the power semiconductor device of Example 2.
【図7】実施例3のリードフレーム構造図である。FIG. 7 is a structural view of a lead frame according to a third embodiment.
【図8】図7のリードフレームのA部詳細図である。FIG. 8 is a detailed view of a portion A of the lead frame of FIG. 7;
【図9】実施例3のパワー半導体装置の絶縁破壊電圧の
測定結果を示すグラフである。FIG. 9 is a graph showing a measurement result of a dielectric breakdown voltage of the power semiconductor device of Example 3.
【図10】実施例4のリードフレーム構造図である。FIG. 10 is a structural view of a lead frame according to a fourth embodiment.
【図11】実施例4のリードフレームの側面構造図であ
る。FIG. 11 is a side view of a lead frame according to a fourth embodiment.
【図12】実施例4のリードフレームの側面構造図であ
る。FIG. 12 is a side view of a lead frame according to a fourth embodiment.
【図13】実施例5のリードフレームの構造図である。FIG. 13 is a structural diagram of a lead frame according to a fifth embodiment.
【図14】実施例5のリードフレームの側面構造図であ
る。FIG. 14 is a side view of a lead frame according to a fifth embodiment.
【図15】実施例5のリードフレームの側面構造図であ
る。FIG. 15 is a side view of a lead frame according to a fifth embodiment.
【図16】実施例6のリードフレームの側面構造図であ
る。FIG. 16 is a side view of a lead frame according to a sixth embodiment.
【図17】実施例7の家庭用空調機の回路構成図であ
る。FIG. 17 is a circuit configuration diagram of a home air conditioner according to a seventh embodiment.
【図18】図17のスイッチング回路部の構成図であ
る。18 is a configuration diagram of the switching circuit unit of FIG.
【図19】実施例7のスイッチング回路部の半導体装置
の模式断面図である。FIG. 19 is a schematic sectional view of a semiconductor device of a switching circuit unit according to a seventh embodiment.
11…スイッチング用半導体素子、12…はんだ接着
層、13…リードフレーム、14…プリント基板、15
…ベース板、16…ワイヤボンデイング部、17…端子
電極、18…樹脂絶縁層、19…くびれ部、20…ドラ
イバIC、21…放熱フィン、30…樹脂モールド、3
1…離形材、32…樹脂ケース、33…段差部。DESCRIPTION OF SYMBOLS 11 ... Switching semiconductor element, 12 ... Solder adhesive layer, 13 ... Lead frame, 14 ... Printed circuit board, 15
... Base plate, 16 ... Wire bonding part, 17 ... Terminal electrode, 18 ... Resin insulation layer, 19 ... Constriction part, 20 ... Driver IC, 21 ... Heat radiation fin, 30 ... Resin mold, 3
1 ... release material, 32 ... resin case, 33 ... stepped part.
フロントページの続き (72)発明者 小林 稔幸 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 神村 典孝 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 山田 一二 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 谷 昌吾 千葉県習志野市東習志野七丁目1番1号 株式会社日立製作所産業機器グループ内 (72)発明者 佐々木 康 千葉県習志野市東習志野七丁目1番1号 株式会社日立製作所産業機器グループ内 (72)発明者 中津 欣也 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 上野 巧 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 Fターム(参考) 5F067 AB10 BA04 BA08 BB08 BD01 CC07 CC09 Continued on the front page (72) Inventor Toshiyuki Kobayashi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Noritaka Kamimura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd.Hitachi Laboratory (72) Inventor Ichiji Yamada 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Laboratory (72) Inventor Shogo Tani 7-chome, Higashi Narashino, Narashino City, Chiba Prefecture No. 1-1 In the Hitachi, Ltd. Industrial Equipment Group (72) Inventor Yasushi Sasaki 7-1-1 Higashi Narashino, Narashino-shi, Chiba In-house Hitachi, Ltd. Industrial Equipment Group (72) Inventor Kinya Nakatsu Omika, Hitachi City, Ibaraki Prefecture 7-1-1, Machi-cho, Hitachi, Ltd. Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Takumi Ueno 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term, Hitachi Research Laboratory, Hitachi Ltd. F-term (reference) 5F067 AB10 BA04 BA08 BB08 BD01 CC07 CC09 </ S> </ s> </ s>
Claims (6)
かつ、導体パターンを有する主回路部と、端子電極およ
びベース板を有する半導体装置において、前記主回路部
は、主面1側に配置された前記ベース板上に、フィラー
を含む樹脂材料で構成された絶縁層を介して導体パター
ンが形成され、前記導体パターンは少なくとも1つの立
ち上げ部を有し、該立ち上げ部の延長部分に前記端子電
極が形成され、該端子電極は主面2から外部に導出さ
れ、前記導体パターン上に少なくとも1つのスイッチン
グ用半導体素子が固着されており、前記導体パターンお
よび前記端子電極とが同一材料で一体に形成されたリー
ドフレームからなり、前記主回路部が樹脂モールドされ
ており、前記導体パターンの層厚が少なくとも0.5m
mであることを特徴とする半導体装置。A main surface and a main surface facing each other vertically;
In a semiconductor device having a main circuit portion having a conductor pattern, a terminal electrode and a base plate, the main circuit portion is formed of a resin material containing a filler on the base plate disposed on the main surface 1 side. A conductor pattern is formed via the insulating layer, the conductor pattern has at least one rising portion, and the terminal electrode is formed on an extension of the rising portion. At least one switching semiconductor element is fixed on the conductor pattern, the conductor pattern and the terminal electrode are formed of a lead frame integrally formed of the same material, and the main circuit portion is formed of a resin. Molded, and the layer thickness of the conductor pattern is at least 0.5 m
m.
が形成されており、該くびれ部の断面積がくびれ部直近
の断面積を1としたとき、0.7以下である請求項1に
記載の半導体装置。2. A constricted portion is formed in a rising portion of the terminal electrode, and a cross-sectional area of the constricted portion is 0.7 or less when a cross-sectional area immediately near the constricted portion is set to 1. 3. The semiconductor device according to claim 1.
かつ、導体パターンを有する主回路部と、端子電極およ
びベース板を有する半導体装置において、前記主回路部
は、主面1側に配置された前記ベース板上に、フィラー
を含む樹脂材料で構成された絶縁層を介して導体パター
ンが形成され、前記導体パターンは少なくとも1つの立
ち上げ部を有し、該立ち上げ部の延長部分に前記端子電
極が形成され、該端子電極は主面2から外部に導出され
ており、前記導体パターン上に少なくとも1つのスイッ
チング用半導体素子が固着されており、前記導体パター
ンおよび前記端子電極とが実質的に一体に形成されたリ
ードフレームであって、前記主回路部が樹脂モールドに
より一体的に被覆された構造の半導体装置の製法におい
て、 前記リードフレームの一部に予め段差を設け前記端子電
極部および前記導体パターン部を形成する工程、前記導
体パターン部を前記絶縁層に接着する工程、前記端子電
極を垂直に立ち上げる工程、および、液状樹脂を用いて
モールドする工程を含むことを特徴とする半導体装置の
製法。3. It has a main surface 1 and a main surface 2 which are vertically opposed,
In a semiconductor device having a main circuit portion having a conductor pattern, a terminal electrode and a base plate, the main circuit portion is formed of a resin material containing a filler on the base plate disposed on the main surface 1 side. A conductor pattern is formed via the insulating layer, the conductor pattern has at least one rising portion, and the terminal electrode is formed on an extension of the rising portion. A lead frame in which at least one switching semiconductor element is fixed on the conductor pattern, and wherein the conductor pattern and the terminal electrodes are substantially integrally formed, wherein the main circuit In a method of manufacturing a semiconductor device having a structure in which a portion is integrally covered with a resin mold, a step is provided in advance on a part of the lead frame, and the terminal electrode portion and the front portion are provided. Forming a conductive pattern portion, bonding the conductive pattern portion to the insulating layer, vertically raising the terminal electrode, and molding using a liquid resin. Equipment manufacturing method.
予め局所的に薄く形成することによって前記段差部を形
成する請求項3に記載の半導体装置の製法。4. The method of manufacturing a semiconductor device according to claim 3, wherein the step portion is formed by locally reducing the thickness of a predetermined portion of the lead frame in advance.
かつ、導体パターンを有する主回路部と端子電極および
ベース板とを有する半導体装置において、前記主回路部
は、主面1側に配置された前記ベース板上に、フィラー
を含む樹脂材料で構成される絶縁層を介して導体パター
ンが形成され、前記導体パターンは少なくとも1つの立
ち上げ部を有し、該立ち上げ部の延長部分に前記端子電
極が形成され、該端子電極は主面2から外部に導出され
ており、前記導体パターン上に少なくとも1つのスイッ
チング用半導体素子が固着されており、前記導体パター
ンおよび前記端子電極とが実質的に一体に形成されたリ
ードフレームであって、前記主回路部が樹脂モールドに
より一体的に被覆された構造の半導体装置の製法におい
て、 前記リードフレームの一部に予め離形材を配置する工
程、または、前記絶縁層の特定表面部に離形材を配置す
る工程、前記絶縁層に前記リードフレームを接着する工
程、前記離形材を配置した部分を垂直に立ち上げ前記端
子電極を形成する工程、および、液状樹脂を用いてモー
ルドする工程を含むことを特徴とする半導体装置の製
法。5. It has a main surface 1 and a main surface 2 which are vertically opposed,
In a semiconductor device having a main circuit portion having a conductor pattern, a terminal electrode, and a base plate, the main circuit portion is formed of a resin material containing a filler on the base plate disposed on the main surface 1 side. A conductor pattern is formed with an insulating layer interposed therebetween, the conductor pattern has at least one rising portion, and the terminal electrode is formed on an extension of the rising portion. A lead frame in which at least one switching semiconductor element is fixed on the conductor pattern, and wherein the conductor pattern and the terminal electrode are substantially integrally formed, wherein the main circuit In a method of manufacturing a semiconductor device having a structure in which a part is integrally covered with a resin mold, a step of previously disposing a release material on a part of the lead frame; A step of disposing a release material on a specific surface portion of the insulating layer, a step of bonding the lead frame to the insulating layer, a step of vertically raising the portion where the release material is disposed, and forming the terminal electrode, and And a step of molding using a liquid resin.
かつ、導体パターンを有する主回路部と端子電極および
ベース板とを有する半導体装置において、前記主回路部
は、主面1側に配置された前記ベース板上に、フィラー
を含む樹脂材料で構成される絶縁層を介して導体パター
ンが形成され、前記導体パターンは少なくとも1つの立
ち上げ部を有し、該立ち上げ部の延長部分に前記端子電
極が形成され、該端子電極は主面2から外部に導出され
ており、前記導体パターン上に少なくとも1つのスイッ
チング用半導体素子が固着されており、前記導体パター
ンおよび前記端子電極とが実質的に一体に形成されたリ
ードフレームであって、前記主回路部が樹脂モールドに
より一体的に被覆された構造の半導体装置の製法におい
て、 前記リードフレームの一部を予め垂直に折り曲げて、前
記端子電極を形成する工程、次いで前記導体パターン部
を前記絶縁層に接着する工程、および、液状樹脂を用い
てモールドする工程を含むことを特徴とする半導体装置
の製法。6. It has a main surface 1 and a main surface 2 which are vertically opposed to each other,
In a semiconductor device having a main circuit portion having a conductor pattern, a terminal electrode, and a base plate, the main circuit portion is formed of a resin material containing a filler on the base plate disposed on the main surface 1 side. A conductor pattern is formed with an insulating layer interposed therebetween, the conductor pattern has at least one rising portion, and the terminal electrode is formed on an extension of the rising portion. A lead frame in which at least one switching semiconductor element is fixed on the conductor pattern, and wherein the conductor pattern and the terminal electrodes are substantially integrally formed, wherein the main circuit In a method of manufacturing a semiconductor device having a structure in which a part is integrally covered with a resin mold, a part of the lead frame is bent vertically in advance to form the terminal electrode. A method of manufacturing a semiconductor device, comprising: a forming step, a step of bonding the conductive pattern portion to the insulating layer, and a step of molding using a liquid resin.
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Cited By (5)
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WO2005098943A1 (en) * | 2004-04-06 | 2005-10-20 | Honda Giken Kogyo Kabushiki Kaisha | Semiconductor element mounting substrate, semiconductor module, and electric vehicle |
JP2009532912A (en) * | 2006-04-06 | 2009-09-10 | フリースケール セミコンダクター インコーポレイテッド | Molded semiconductor package with integral through-hole heat dissipation pins |
JP2010541190A (en) * | 2007-06-07 | 2010-12-24 | コミサリア ア レネルジ アトミク | Method for manufacturing vias in a reconfigurable substrate |
JP2014179603A (en) * | 2013-03-12 | 2014-09-25 | Internatl Rectifier Corp | Power quad flat no-lead (pqfn) package having control and driver circuit |
DE102017205116A1 (en) | 2016-05-26 | 2017-11-30 | Mitsubishi Electric Corporation | Semiconductor device and manufacturing method thereof |
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JP2000183281A (en) * | 1998-12-18 | 2000-06-30 | Hitachi Ltd | Semiconductor device and its manufacture |
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JPS60137048A (en) * | 1983-12-26 | 1985-07-20 | Matsushita Electronics Corp | Lead frame for semiconductor device |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005098943A1 (en) * | 2004-04-06 | 2005-10-20 | Honda Giken Kogyo Kabushiki Kaisha | Semiconductor element mounting substrate, semiconductor module, and electric vehicle |
JP2009532912A (en) * | 2006-04-06 | 2009-09-10 | フリースケール セミコンダクター インコーポレイテッド | Molded semiconductor package with integral through-hole heat dissipation pins |
US8659146B2 (en) | 2006-04-06 | 2014-02-25 | Freescale Semiconductor, Inc. | Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing |
JP2010541190A (en) * | 2007-06-07 | 2010-12-24 | コミサリア ア レネルジ アトミク | Method for manufacturing vias in a reconfigurable substrate |
JP2014179603A (en) * | 2013-03-12 | 2014-09-25 | Internatl Rectifier Corp | Power quad flat no-lead (pqfn) package having control and driver circuit |
DE102017205116A1 (en) | 2016-05-26 | 2017-11-30 | Mitsubishi Electric Corporation | Semiconductor device and manufacturing method thereof |
US10074598B2 (en) | 2016-05-26 | 2018-09-11 | Mitsubishi Electric Corporation | Semiconductor device and manufacturing method thereof |
CN112382576A (en) * | 2016-05-26 | 2021-02-19 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
DE102017205116B4 (en) | 2016-05-26 | 2022-08-18 | Mitsubishi Electric Corporation | Semiconductor device and manufacturing method thereof |
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