JP2002033433A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having high reliability and low thermal resistance. SOLUTION: A part of a lead frame is bent vertically and led outside to constitute a terminal electrode. A main circuit is bonded to a base plate through a resin layer, and the terminal electrode of the lead frame is raised after element formation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a switching semiconductor element is fixed on a conductor pattern and is electrically insulated by an insulating material. And a semiconductor device having a high withstand voltage structure.

[0002]

2. Description of the Related Art Conventionally, as a power semiconductor device, there is a power semiconductor device having a configuration disclosed in Japanese Patent Publication No. 3-63822 and Japanese Patent Publication No. 6-80748. That is, a semiconductor element is mounted on a lead frame constituting a conductor pattern to form a main circuit portion, and a first resin mold is formed. Next, the main circuit portion is disposed on the base plate with a predetermined gap therebetween, and the second resin molding is performed. A part of the lead frame is led out to the side surface to form a terminal electrode, thereby forming an integrated semiconductor device. It is assumed that. This structure has the following problems.

Usually, in this type of semiconductor device, a heat radiation fin is fixedly formed on a lower surface for heat dissipation to the outside. The radiation fins need to be electrically insulated from the terminal electrodes. However, in the above-described conventional structure, since the terminal electrode is led out from the side surface, there is a problem that it is difficult to sufficiently secure an electrical insulation space distance from the radiation fins three-dimensionally.

Another such power semiconductor device is disclosed in JP-A-7-22576. The conductor pattern of the semiconductor device having this structure is formed by etching. Therefore, the layer thickness of the conductor pattern is at most about 0.3 mm from a practical point of view. Therefore, in order to flow a large current, it is necessary to form a wide conductor pattern in the plane direction of the substrate (base plate). As a result, there is a problem that the area of the substrate on which the conductor pattern is arranged increases, and the semiconductor device itself becomes larger.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to secure a sufficient insulating space distance between a terminal electrode and a radiating fin, which is a problem of the prior art, and to reduce the line width of a conductor pattern.
That is, an object of the present invention is to provide a power semiconductor device which can increase the allowable current without increasing the mounting area, and has a low thermal resistance, a high dielectric strength and a high reliability.

[0006]

The gist of the present invention to achieve the above object is as follows.

In a semiconductor device having a main circuit portion having upper and lower opposing main surfaces 1 and 2 and having a conductor pattern, and a terminal electrode and a base plate, the main circuit portion is located on the main surface 1 side. A conductive pattern is formed on the base plate disposed on the base plate via an insulating layer made of a resin material containing a filler, and the conductive pattern has at least one rising portion, and is an extension of the rising portion. The terminal electrode is formed in a portion, the terminal electrode is led out from the main surface 2, at least one switching semiconductor element is fixed on the conductor pattern, and the terminal electrode Is a lead frame integrally formed of the same material, wherein the main circuit portion is resin-molded, and a layer thickness of the conductor pattern is at least 0.3.
The semiconductor device is 5 mm.

With the above configuration, the radiation fins fixed to the main surface 2 can be arranged on the opposite surface of the terminal electrode, so that the insulation space distance can be easily secured.

Further, by setting the layer thickness of the conductor pattern to at least 0.5 mm, the thermal resistance can be reduced, the current capacity per unit area can be significantly increased, and the size of the semiconductor device can be easily reduced. be able to.

In the above-mentioned semiconductor device, a constricted portion is provided at a rising portion of the terminal electrode, and a cross-sectional area of the constricted portion is 0.1 when a cross-sectional area immediately adjacent to the constricted portion is 1.
7 or less. With this configuration, the bending process for vertically raising the lead frame becomes extremely easy.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

Embodiment 1 FIG. 1 is a schematic sectional view of a semiconductor device according to the present embodiment, and FIG. 2 is a schematic plan view thereof. In FIG. 1, the upper side shows the main surface 2 of the present semiconductor device, and the lower side shows the main surface 1. For example, IGBT (Insulated Gate Bi
A switching semiconductor element 11 such as a polar transistor is connected to a lead frame 13 via a solder bonding layer 12.
, And a series of main circuit components are covered with a resin mold 30, and the terminal electrode 1
7 is derived.

The lower surface of the lead frame 13 is bonded to the base plate 15 via a resin insulating layer 18 containing 70% by weight of alumina as a filler.

The semiconductor element 11 is electrically connected to the lead frame 13 by an aluminum wire bonding portion 16. A part of the lead frame 13 becomes a terminal electrode 17 and is led out almost perpendicularly to the surface of the main surface 2 of the resin mold 30 to form a main circuit. In this configuration, Ni-plated 0.4 mm thick oxygen-free copper is used as the material of the lead frame 13, and the lead frame 13 is bonded to the resin insulating layer containing the filler. Nature can be secured.

The power semiconductor device having this structure is manufactured by the following steps.

A copper lead frame 13 having a predetermined pattern and a thickness of 0.4 mm is formed by pressing. In this step, a step 33 shown in FIG. 3 is given to both portions constituting the conductor pattern and the terminal electrode. FIG. 3 shows the overall structure of the lead frame in this step.
4 is shown in detail in FIG.

As shown in FIG.
3 between the conductive pattern portion 3 and the base plate 15.
A resin insulating layer 18 is formed by inserting a 16 mm uncured resin sheet and integrating it by heating and pressing. Next, the step portion 33 is bent upward to vertically raise the terminal electrode portion 17. An IGBT chip is mounted as a semiconductor element 11 on the conductor pattern of the lead frame 13 and soldered. Next, the element 11 and the lead frame 13 are electrically connected by an Al wire having a diameter of 0.3 mmφ to form a main circuit.

In the main circuit portion formed in the above process, PPS is used.
(Poly Phenylene Sulfide) case 32 is adhered and fixed with a silicone resin, and an epoxy resin (liquid resin) containing a filler is injected and filled into the case 32 under predetermined conditions, and is cured by heating. To obtain a power semiconductor device.

In this embodiment, the materials shown in Table 1 were used as the material of the resin mold 30. In Table 1, the compounding ratio indicates parts by weight.

[0020]

[Table 1]

This material has a low linear expansion coefficient of 18 ppm / ° C. because it contains a large amount of silicon oxide (average particle size of 10 to 200 μm) as a filler.
Warpage can be suppressed.

After the molding, after-curing is performed to accelerate the curing of the molding resin. Next, the resin mold 3
The semiconductor device in which the terminal electrode 17 having a predetermined shape is formed by cutting and / or shaping a portion corresponding to the terminal electrode of the lead frame 13 led out of the lead frame 13.

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to the present invention having the radiation fins 21 mounted thereon. In the semiconductor device, the fin 21 having the ground potential and the terminal electrode 17 are arranged on the upper and lower main surfaces, respectively, and the interval between them is about 10 mm or more, so that a sufficient insulation space distance can be secured. .

In this embodiment, an example in which a single IGBT element is used as the semiconductor element 11 has been described.
Other types of semiconductor elements such as MOS transistors and diodes may be used. Furthermore, a specific circuit formed by a combination of these plural elements, for example, an inverter power module or the like may be used.

In this embodiment, the silicon oxide shown in Table 1 is shown as a filler contained in the resin mold 30, but other materials such as alumina, beryllia, zirconia, silicon nitride, aluminum nitride, and carbonized It may be silicon or the like.

According to the present embodiment, since the step portion 33 is formed on the lead frame 13, the terminal electrode portion 17 is not bonded even in the bonding step of the conductor pattern and is in a free state. This has the effect of being easier.

[Embodiment 2] As another embodiment having a structure substantially similar to that of Embodiment 1 shown in FIG. 1, the layer thickness of the lead frame 13 is increased to, for example, 0.6 mm, 1.0 mm, and 1.4 mm. The other structure was the same as that of the first embodiment.

According to this structure, the heat generated in the semiconductor element 11 can be easily diffused in the horizontal direction, and the thermal resistance can be reduced by about 10 to 20% as compared with the structure of the first embodiment.

FIG. 6 is a graph showing the measurement results of the thermal resistance between the semiconductor element 11 and the base plate 15 by changing the layer thickness of the lead frame 13. When the thickness of the lead frame 13 is
In the region of 5 mm or less, there is a sharp rise in thermal resistance. Therefore, setting the thickness of the lead frame 13 to be as thick as 0.5 mm or more is particularly effective for reducing the thermal resistance.

[Embodiment 3] Another embodiment having substantially the same structure as that of Embodiment 1 is shown in FIGS. The difference from the first embodiment is that, as shown in FIGS. 7 and 8, a constricted portion 19 is formed at the boundary between the conductor pattern portion and the terminal electrode portion.
In this example, the width of the terminal electrode portion was 1.5 mm, and the width of the constricted portion was 1 mm.

The pattern width of the constricted portion 19 is set to 1.5.
An experiment was conducted in which the lead frame 13 was adhered to the lead frame 13 and then vertically bent after changing the thickness stepwise from 0.3 mm to 0.3 mm. The width of the terminal electrode 17 was 1.5 mm, and the thickness of the lead frame including the constricted portion 19 was 0.8 mm.

The sample after bending is placed in an insulating bath (3M
(Fluorinert). The breakdown voltage of the insulating layer 18 was measured. As shown in FIG. 9, when the sectional area ratio of the constricted portion / terminal electrode portion exceeded 0.7, the breakdown voltage decreased. This is because if the constriction is small, the mechanical resistance at the time of bending is large, and the insulating layer 18 is damaged.

On the other hand, when the cross-sectional area ratio is less than 0.2, the bending process is facilitated, but the shape after the bending is unstable.
This is not preferable because the increase in the electric resistance also increases.

In this embodiment, as shown in FIG. 7, an example is shown in which the thickness of the lead frame 13 is constant and a constricted portion is provided on a plan view. However, a constricted portion in the thickness direction is provided in the bent portion. Similarly, bending can be easily performed. Also in this case, the sectional area ratio of the constricted portion 19 is preferably in the range of 0.3 to 0.7.

Also, as shown in FIG.
3 has the step portion 33, so that after bonding the conductor pattern portion to the resin insulating layer 18, the terminal electrode portion 17 can be easily bent in the vertical direction, and a sufficient insulation distance can be secured. .

Embodiment 4 FIGS. 10 to 12 show another embodiment having a structure substantially similar to that of the first embodiment. The difference from the first embodiment is that, as shown in FIG. 11, the step 33 is formed by previously reducing the layer thickness of the non-adhesive portion of the lead frame 13, that is, the thickness of the wall.

Next, after the step of bonding to the insulating layer 18 as shown in FIG. 12, the terminal electrode portion 17 is bent vertically as shown in the figure. For other steps, see Example 1.
The semiconductor device of the present invention was manufactured in the same manner as described above.

Means for locally reducing the thickness of the lead frame 13 include, for example, etching, mechanical pressing, and cutting.

By providing the step portion 33 according to the present embodiment, the terminal electrode portion 17 can be easily bent vertically after the conductor pattern portion is bonded to the resin insulating layer 18 in the same manner as in the third embodiment. The distance can be secured.

Embodiment 5 FIGS. 13 to 15 show another embodiment having a structure substantially similar to that of the first embodiment. The difference from the first embodiment is that, as shown in FIG. 13, the lead frame 13 is flat with no steps formed.

Next, as shown in FIG. 14, in the step of bonding to the insulating layer 18, the release material 31 is inserted or brought into contact with the terminal electrode portion 17 of the lead frame 13. Release material 31
A polyimide sheet having a thickness of 0.05 mm was used. After bonding the conductor pattern portion, the terminal electrode portion 17 was vertically bent as shown in FIG. 15 to remove the polyimide sheet. Other steps were performed in the same manner as in Example 1 to manufacture a semiconductor device of the present invention.

Although a polyimide sheet is used as the release material 31 in this embodiment, a release material made of another material may be used. Further, a coating type release material may be applied to a predetermined portion of the lead frame 13.

By disposing the release material 31,
After bonding the conductor pattern portion to the resin insulation layer 18, the terminal electrode portion 17 can be easily bent vertically, and a sufficient insulation distance can be secured.

[Embodiment 6] FIG. 16 shows another embodiment having a structure substantially similar to that of the first embodiment. The difference from the first embodiment is that, as shown in FIG. 16, a lead frame 13 having a terminal electrode portion bent vertically in advance is prepared, and the conductor pattern portion is directly bonded to the resin insulating layer 18.

According to this embodiment, the constricted portion 19 shown in the first and second embodiments is not particularly required, and the step of bending the terminal electrode portion 17 after the bonding of the conductor pattern portion shown in the third embodiment can be omitted. And the assembly process can be simplified.

Embodiment 7 FIG. 17 shows that the thickness of the lead frame is set to 0.8 mm, and the pattern widths of the terminal electrode 17 and the constricted portion 19 are set to 1.5 mm and 1 mm, respectively.
1 is a circuit configuration diagram of a home air conditioner to which a semiconductor device manufactured according to a first embodiment is applied.

In the figure, a semiconductor device according to the present invention is applied to a switching circuit for controlling a motor 3 for driving a compressor.

FIG. 18 shows the details of the switching circuit section. In the figure, terminals P and N are connected to a power supply circuit. With the air conditioner of this configuration, low heat resistance,
In addition, a highly reliable switching circuit can be obtained, and an energy-saving air conditioner can be provided.

FIG. 19 is a schematic sectional view of a semiconductor device of the present switching circuit section. A main circuit is formed on a lead frame 13, and a control circuit section including a driver IC 19 is formed on a resin substrate 14.

By applying the structure of this embodiment to electric equipment having a motor for home use or industrial use, for example, a refrigerator, a freezer, a pump, a transporter, etc., the insulation of the terminal electrode 17 as described above is achieved. You can secure enough space distance,
In addition, the thermal resistance can be reduced by the action of the lead frame 17 having a large thickness, and an energy-saving high-reliability electrical device can be provided.

[0051]

According to the present invention, it is possible to secure a sufficient insulating space distance between the radiation fin and the terminal electrode, and to provide a highly reliable semiconductor device.

By setting the layer thickness of the conductor pattern to be as thick as 0.5 mm or more, the thermal resistance can be reduced and the wiring width of the conductor pattern can be reduced, so that the semiconductor device can be downsized.

In the bonding step of the conductor pattern,
By taking measures to prevent the terminal electrode portion 17 from adhering to the resin insulating layer 18, the bending process of the terminal electrode portion 17 becomes easy, and a highly reliable semiconductor device can be easily realized.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a power semiconductor device according to a first embodiment.

FIG. 2 is a schematic plan view of the power semiconductor device of FIG.

FIG. 3 is a structural diagram of a lead frame according to the first embodiment.

FIG. 4 is a detailed view of a portion A of the lead frame of FIG. 3;

FIG. 5 is a schematic cross-sectional view of the power semiconductor device to which the heat radiation fin of Example 1 is attached.

FIG. 6 is a graph showing the measurement results of the thermal resistance of the power semiconductor device of Example 2.

FIG. 7 is a structural view of a lead frame according to a third embodiment.

FIG. 8 is a detailed view of a portion A of the lead frame of FIG. 7;

FIG. 9 is a graph showing a measurement result of a dielectric breakdown voltage of the power semiconductor device of Example 3.

FIG. 10 is a structural view of a lead frame according to a fourth embodiment.

FIG. 11 is a side view of a lead frame according to a fourth embodiment.

FIG. 12 is a side view of a lead frame according to a fourth embodiment.

FIG. 13 is a structural diagram of a lead frame according to a fifth embodiment.

FIG. 14 is a side view of a lead frame according to a fifth embodiment.

FIG. 15 is a side view of a lead frame according to a fifth embodiment.

FIG. 16 is a side view of a lead frame according to a sixth embodiment.

FIG. 17 is a circuit configuration diagram of a home air conditioner according to a seventh embodiment.

18 is a configuration diagram of the switching circuit unit of FIG.

FIG. 19 is a schematic sectional view of a semiconductor device of a switching circuit unit according to a seventh embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Switching semiconductor element, 12 ... Solder adhesive layer, 13 ... Lead frame, 14 ... Printed circuit board, 15
... Base plate, 16 ... Wire bonding part, 17 ... Terminal electrode, 18 ... Resin insulation layer, 19 ... Constriction part, 20 ... Driver IC, 21 ... Heat radiation fin, 30 ... Resin mold, 3
1 ... release material, 32 ... resin case, 33 ... stepped part.

Continued on the front page (72) Inventor Toshiyuki Kobayashi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Noritaka Kamimura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd.Hitachi Laboratory (72) Inventor Ichiji Yamada 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Laboratory (72) Inventor Shogo Tani 7-chome, Higashi Narashino, Narashino City, Chiba Prefecture No. 1-1 In the Hitachi, Ltd. Industrial Equipment Group (72) Inventor Yasushi Sasaki 7-1-1 Higashi Narashino, Narashino-shi, Chiba In-house Hitachi, Ltd. Industrial Equipment Group (72) Inventor Kinya Nakatsu Omika, Hitachi City, Ibaraki Prefecture 7-1-1, Machi-cho, Hitachi, Ltd. Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Takumi Ueno 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term, Hitachi Research Laboratory, Hitachi Ltd. F-term (reference) 5F067 AB10 BA04 BA08 BB08 BD01 CC07 CC09 </ S> </ s> </ s>

Claims (6)

[Claims] A main surface and a main surface facing each other vertically;
In a semiconductor device having a main circuit portion having a conductor pattern, a terminal electrode and a base plate, the main circuit portion is formed of a resin material containing a filler on the base plate disposed on the main surface 1 side. A conductor pattern is formed via the insulating layer, the conductor pattern has at least one rising portion, and the terminal electrode is formed on an extension of the rising portion. At least one switching semiconductor element is fixed on the conductor pattern, the conductor pattern and the terminal electrode are formed of a lead frame integrally formed of the same material, and the main circuit portion is formed of a resin. Molded, and the layer thickness of the conductor pattern is at least 0.5 m
m. 2. A constricted portion is formed in a rising portion of the terminal electrode, and a cross-sectional area of the constricted portion is 0.7 or less when a cross-sectional area immediately near the constricted portion is set to 1. 3. The semiconductor device according to claim 1. 3. It has a main surface 1 and a main surface 2 which are vertically opposed,
In a semiconductor device having a main circuit portion having a conductor pattern, a terminal electrode and a base plate, the main circuit portion is formed of a resin material containing a filler on the base plate disposed on the main surface 1 side. A conductor pattern is formed via the insulating layer, the conductor pattern has at least one rising portion, and the terminal electrode is formed on an extension of the rising portion. A lead frame in which at least one switching semiconductor element is fixed on the conductor pattern, and wherein the conductor pattern and the terminal electrodes are substantially integrally formed, wherein the main circuit In a method of manufacturing a semiconductor device having a structure in which a portion is integrally covered with a resin mold, a step is provided in advance on a part of the lead frame, and the terminal electrode portion and the front portion are provided. Forming a conductive pattern portion, bonding the conductive pattern portion to the insulating layer, vertically raising the terminal electrode, and molding using a liquid resin. Equipment manufacturing method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step portion is formed by locally reducing the thickness of a predetermined portion of the lead frame in advance. 5. It has a main surface 1 and a main surface 2 which are vertically opposed,
In a semiconductor device having a main circuit portion having a conductor pattern, a terminal electrode, and a base plate, the main circuit portion is formed of a resin material containing a filler on the base plate disposed on the main surface 1 side. A conductor pattern is formed with an insulating layer interposed therebetween, the conductor pattern has at least one rising portion, and the terminal electrode is formed on an extension of the rising portion. A lead frame in which at least one switching semiconductor element is fixed on the conductor pattern, and wherein the conductor pattern and the terminal electrode are substantially integrally formed, wherein the main circuit In a method of manufacturing a semiconductor device having a structure in which a part is integrally covered with a resin mold, a step of previously disposing a release material on a part of the lead frame; A step of disposing a release material on a specific surface portion of the insulating layer, a step of bonding the lead frame to the insulating layer, a step of vertically raising the portion where the release material is disposed, and forming the terminal electrode, and And a step of molding using a liquid resin. 6. It has a main surface 1 and a main surface 2 which are vertically opposed to each other,
In a semiconductor device having a main circuit portion having a conductor pattern, a terminal electrode, and a base plate, the main circuit portion is formed of a resin material containing a filler on the base plate disposed on the main surface 1 side. A conductor pattern is formed with an insulating layer interposed therebetween, the conductor pattern has at least one rising portion, and the terminal electrode is formed on an extension of the rising portion. A lead frame in which at least one switching semiconductor element is fixed on the conductor pattern, and wherein the conductor pattern and the terminal electrodes are substantially integrally formed, wherein the main circuit In a method of manufacturing a semiconductor device having a structure in which a part is integrally covered with a resin mold, a part of the lead frame is bent vertically in advance to form the terminal electrode. A method of manufacturing a semiconductor device, comprising: a forming step, a step of bonding the conductive pattern portion to the insulating layer, and a step of molding using a liquid resin.