JP2000183281A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JP2000183281A
JP2000183281A JP36027898A JP36027898A JP2000183281A JP 2000183281 A JP2000183281 A JP 2000183281A JP 36027898 A JP36027898 A JP 36027898A JP 36027898 A JP36027898 A JP 36027898A JP 2000183281 A JP2000183281 A JP 2000183281A
Authority
JP
Japan
Prior art keywords
resin layer
semiconductor element
lead
semiconductor device
electrode plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP36027898A
Other languages
Japanese (ja)
Inventor
Toshio Ogawa
敏夫 小川
Masaaki Takahashi
正昭 高橋
Masahiro Aida
正広 合田
Noritaka Kamimura
典孝 神村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP36027898A priority Critical patent/JP2000183281A/en
Publication of JP2000183281A publication Critical patent/JP2000183281A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device that is sealed with resin. SOLUTION: A semiconductor device is provided with a structure body, that has a semiconductor element 11, a first resin layer 1 for covering an electrode plate 13 where a semiconductor element is mounted and lead electrodes 4 and 5, and a second resin layer 2 adhering to the electrode plate, the lead electrodes, and a base substrate 6 among the electrode plate, the lead electrodes, and the base substrate 6, and a third resin layer 3 for covering the structure body, so that one portion of the lead electrode and the surface of the base substrate are exposed. Protection by the first resin layer 1 prevents failures from occurring, when cutting a lead to evaluate electrical characteristics in a manufacturing process.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子が樹脂
によって封止された半導体装置に関する。
The present invention relates to a semiconductor device in which a semiconductor element is sealed with a resin.

【0002】[0002]

【従来の技術】従来のこの種パワー半導体装置として特
開平9−102580 号公報に開示される構成がある。すなわ
ち、リードフレーム上に半導体素子を載置して主回路部
を形成する。次いで、第1の樹脂によってリードフレー
ムを固定し、第2の樹脂によって一体封止して半導体装
置を構成するものである。この構造によれば次の問題点
がある。
2. Description of the Related Art As a conventional power semiconductor device of this type, there is a structure disclosed in Japanese Patent Application Laid-Open No. 9-102580. That is, a semiconductor element is mounted on a lead frame to form a main circuit portion. Next, the lead frame is fixed with the first resin and integrally sealed with the second resin to form a semiconductor device. This structure has the following problems.

【0003】製造工程中に電気的特性を評価する為に
は、リードフレームの一部を切断分離する必要がある。
しかしながら、本構造の半導体装置では、パワー半導体
素子を搭載したままの状態でリードフレームを切断する
ことになり、切断時に発生する機械的な応力、熱もしく
は塵埃などによって、半導体素子の故障を発生しやす
い、もしくはリードフレームと第1の樹脂との接着部の
剥離を発生しやすという問題点がある。
In order to evaluate the electrical characteristics during the manufacturing process, it is necessary to cut and separate a part of the lead frame.
However, in the semiconductor device having this structure, the lead frame is cut while the power semiconductor element is mounted, and a failure of the semiconductor element occurs due to mechanical stress, heat or dust generated at the time of cutting. However, there is a problem in that the adhesion portion between the lead frame and the first resin is easily separated.

【0004】[0004]

【発明が解決しようとする課題】本発明は、上記従来法
の問題点を考慮してなされ、製造工程中におけるリード
フレームの一部切断もしくは成形加工及び特性評価を容
易にし信頼性を高めるとともに、熱抵抗の低いパワー半
導体装置を提供するものである。
SUMMARY OF THE INVENTION The present invention has been made in consideration of the problems of the above-mentioned conventional method, and facilitates partial cutting or molding of a lead frame during a manufacturing process and evaluation of characteristics to improve reliability. A power semiconductor device having a low thermal resistance is provided.

【0005】[0005]

【課題を解決するための手段】本発明による半導体装置
は、半導体素子と、半導体素子が搭載される電極板と、
半導体素子と電気的に接合されるリード電極と、半導体
素子,電極板及びリード電極が搭載される基板と、を備
える。半導体素子,電極板及びリード電極は第1の樹脂
層で被覆されるとともに、電極板及びリード電極と基板
との間において、電極板,リード電極と基板とが第2の
樹脂層によって接着される。以上のような構造体が、リ
ード電極の一部と基板の表面が露出するように、第3の
樹脂層によって被覆される。
A semiconductor device according to the present invention comprises: a semiconductor element; an electrode plate on which the semiconductor element is mounted;
The semiconductor device includes a lead electrode electrically connected to the semiconductor element, and a substrate on which the semiconductor element, the electrode plate, and the lead electrode are mounted. The semiconductor element, the electrode plate and the lead electrode are covered with a first resin layer, and the electrode plate, the lead electrode and the substrate are bonded to each other between the electrode plate and the lead electrode by the second resin layer. . The above-described structure is covered with the third resin layer so that a part of the lead electrode and the surface of the substrate are exposed.

【0006】上記の半導体装置は、半導体素子,電極板
及びリード電極が第1の樹脂層で保護された状態で、リ
ードを切断することや電気的特性を評価することができ
る。従って、リード切断時や電気的特性評価時に発生し
得る故障を防止することができる。
In the above-described semiconductor device, it is possible to cut the lead and evaluate the electrical characteristics while the semiconductor element, the electrode plate and the lead electrode are protected by the first resin layer. Therefore, it is possible to prevent a failure that may occur at the time of cutting the lead or evaluating the electrical characteristics.

【0007】上記構成の半導体装置においては、さらに
樹脂層内に位置するスペーサ手段を備えることが好まし
い。スペーサ手段により、第2の樹脂層が均一に所望の
厚さに設定できるので、絶縁性が確保でき、また熱伝導
性を向上し熱抵抗を低減することができる。なお、スペ
ーサ手段としては、第1の樹脂層の突起部や、絶縁性材
料であるアルミナ,マグネシア,シリカ,ベリリア,ジ
ルコニヤ,窒化けい素,窒化アルミニウム,炭化けい素
の内のいずれかを材料とする部材が有る。また、スぺー
サ手段の形状としては球状が好ましく、さらにその球状
の直径が第2の樹脂層の厚さと略等しいことが好まし
い。なお、熱抵抗を下げるためには、第2の樹脂層中
に、50体積%以上95体積%以下の無機材料系フィラ
ーが含まれることも有効である。
[0007] The semiconductor device having the above structure preferably further includes a spacer means located in the resin layer. Since the second resin layer can be uniformly set to a desired thickness by the spacer means, insulation can be ensured, and thermal conductivity can be improved and thermal resistance can be reduced. As the spacer means, the protrusion of the first resin layer or any one of the insulating materials of alumina, magnesia, silica, beryllia, zirconia, silicon nitride, aluminum nitride, and silicon carbide is used. There is a member to do. The spacer means is preferably spherical in shape, and the diameter of the spherical shape is preferably substantially equal to the thickness of the second resin layer. In order to reduce the thermal resistance, it is also effective that the second resin layer contains 50% by volume or more and 95% by volume or less of an inorganic material-based filler.

【0008】上記本発明による半導体装置は、次の本発
明による半導体装置の製造方法により製作することがで
きる。すなわち、本発明による製造方法は、電極板部と
リード電極部とを有するリードフレームの電極板部に半
導体素子を搭載する第1の工程と、半導体素子及びリー
ドフレームを第1の樹脂層で被覆する第2の工程と、リ
ードフレームを切断する第3の工程と、基板とリードフ
レームとを第2の樹脂層を介して圧着する第4の工程
と、リードフレーム,半導体素子,第1及び第2の樹脂
層及び基板を含む構造体を第3の樹脂層で被覆する第5
の工程と、を含んでいる。
The semiconductor device according to the present invention can be manufactured by the following method for manufacturing a semiconductor device according to the present invention. That is, the manufacturing method according to the present invention includes a first step of mounting a semiconductor element on an electrode plate of a lead frame having an electrode plate and a lead electrode, and covering the semiconductor element and the lead frame with a first resin layer. A second step of cutting the lead frame, a fourth step of crimping the substrate and the lead frame via the second resin layer, a step of cutting the lead frame, the semiconductor element, the first and the second steps. A fifth resin layer covering the structure including the second resin layer and the substrate with the third resin layer;
And a step of

【0009】上記の製造方法によれば、半導体素子及び
リードフレームが第1の樹脂層で保護された状態で、リ
ードを切断する。従って、リード切断時に発生し得る故
障を防止することができる。
According to the above manufacturing method, the lead is cut while the semiconductor element and the lead frame are protected by the first resin layer. Therefore, it is possible to prevent a failure that may occur when the lead is cut.

【0010】上記の製造方法においては、第3の工程と
第4の工程との間に、半導体素子を含む回路の電気的特
性を評価する工程を含むことが好ましい。これにより、
電気的特性評価時に発生する故障を防止することができ
る。
In the above-described manufacturing method, it is preferable that a step of evaluating an electric characteristic of a circuit including a semiconductor element is included between the third step and the fourth step. This allows
It is possible to prevent a failure that occurs at the time of evaluating the electrical characteristics.

【0011】また、上記製造方法においては、第2の工
程において、第1の樹脂層に突起を形成し、この突起
が、第4の工程において、基板に圧着されることが好ま
しい。この突起は、上述したスペーサ手段となる。ま
た、第4の工程において、第2の樹脂層内にスペーサが
含まれていてもよい。このスペーサは、上述したような
絶縁材料の部材であることや形状であることが好まし
い。
In the above-mentioned manufacturing method, it is preferable that a projection is formed on the first resin layer in the second step, and that the projection is pressure-bonded to the substrate in the fourth step. This projection serves as the spacer means described above. Further, in the fourth step, a spacer may be included in the second resin layer. It is preferable that the spacer is a member or a shape of the insulating material as described above.

【0012】なお、半導体素子としてはバイポーラトラ
ンジスタ,MOSFETなどの各種のスイッチング素子
やダイオード等が適用できる。また、半導体素子を含む
回路に、さらに抵抗,コンデンサ,インダクタ等の受動
素子が含まれていてもよい。これら、電気素子または電
子素子はプリント基板のような回路基板上に搭載されて
いてもよい。さらに、本発明による半導体装置は、熱抵
抗を低減できることから、特にパワートランジスタ,パ
ワーMOSFET,絶縁ゲートバイポーラトランジスタ
(以下IGBTと記す)などのパワー半導体素子が樹脂
封止される半導体装置に好適である。
As the semiconductor element, various switching elements such as bipolar transistors and MOSFETs, diodes and the like can be applied. Further, the circuit including the semiconductor element may further include a passive element such as a resistor, a capacitor, and an inductor. These electric or electronic elements may be mounted on a circuit board such as a printed board. Further, the semiconductor device according to the present invention is suitable for a semiconductor device in which a power semiconductor element such as a power transistor, a power MOSFET, and an insulated gate bipolar transistor (hereinafter, referred to as IGBT) is resin-sealed, because the thermal resistance can be reduced. .

【0013】[0013]

【発明の実施の形態】以下、本発明を実施例によってさ
らに詳細に説明するが、本発明はこれらに限定されな
い。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited thereto.

【0014】(実施例1)図1に本発明の実施例1によ
る半導体装置の断面構成図を示す。例えば、IGBT(Insu
lated Gate Bipolar Transisitor)などのパワー半導体
素子11,12がはんだ接着層14を介してリードフレ
ームの電極板部13の主面上に固着され搭載される。電
極板部13の他方の主面すなわち上記部品搭載された主
面の裏面は、樹脂層2を介して金属ベース基板6に接着
される。パワー半導体素子11,12は、アルミニウム
のワイヤボンディング部15によりリード電極部4,5
と電気的に接合され、リード電極部4,5の一部が端子
として外部に導出され、主回路を構成する。さらに主回
路部は樹脂層1によって被覆され構造体をなし、リード
電極部4,5の端子部、並びに金属ベース基板6の裏面
を露出する形で構造体全体が樹脂層3により一体モール
ド封止される。樹脂層1は、電極板部13またはリード
電極部4,5と金属ベース基板6との間において、突起
部8を有する。突起部8は、樹脂2をその厚み方向にほ
ぼ貫通している。このため突起部8は、スペーサとなっ
ており、樹脂2の厚みを確保している。
(Embodiment 1) FIG. 1 is a sectional view of a semiconductor device according to Embodiment 1 of the present invention. For example, IGBT (Insu
Power semiconductor elements 11 and 12 such as a related gate bipolar transistor are fixed and mounted on the main surface of the electrode plate portion 13 of the lead frame via the solder adhesive layer 14. The other main surface of the electrode plate portion 13, that is, the back surface of the main surface on which the above components are mounted, is bonded to the metal base substrate 6 via the resin layer 2. Power semiconductor elements 11 and 12 are connected to lead electrode sections 4 and 5 by aluminum wire bonding section 15.
Are electrically connected to each other, and a part of the lead electrode portions 4 and 5 is led out as terminals to form a main circuit. Further, the main circuit portion is covered with the resin layer 1 to form a structure, and the entire structure is integrally molded with the resin layer 3 so that the terminal portions of the lead electrode portions 4 and 5 and the back surface of the metal base substrate 6 are exposed. Is done. The resin layer 1 has a projection 8 between the electrode plate 13 or the lead electrodes 4 and 5 and the metal base substrate 6. The protrusion 8 substantially penetrates the resin 2 in its thickness direction. For this reason, the projection 8 serves as a spacer, and secures the thickness of the resin 2.

【0015】本実施例のパワー半導体装置は次の製造方
法によって作製される。図2に一連の工程を一括して示
す。例えば、プレス加工により所定パターン形状で、厚
さ0.7mm のCu製リードフレームを形成する(工程
1)。リードフレームの電極板部の一方の主面にパワー
半導体素子としてのIGBTチップを搭載し、はんだ接
合する(工程2)。次いで、直径0.3mm のAlワイヤ
によってパワー半導体素子とリードフレームのリード電
極部とを電気的に接続(工程3)して主回路を構成す
る。この主回路部を保護するように、エポキシ系樹脂に
より一次モールド成形して樹脂層1を形成する(工程
4)。この時、他方の主面側に突出する突起部8を樹脂
層1により同時に成形する。その状態で、特性測定が可
能となるようにリードフレームの一部を切断し(工程
5)、電気的特性評価をする(工程6)。さらに、未硬化
性のエポキシ系樹脂生シートを貼着したベース基板上
に、上記特性確認された一次モールドされた回路部の他
方の主面側を加熱圧着により一体化し、樹脂シートによ
って樹脂層2を構成する(工程7)。この工程におい
て、突起部8により、均一な安定した層厚を有し、熱伝
導特性及び絶縁特性が良好な樹脂層2が得られる。
The power semiconductor device of this embodiment is manufactured by the following manufacturing method. FIG. 2 shows a series of steps collectively. For example, a Cu lead frame having a predetermined pattern shape and a thickness of 0.7 mm is formed by press working (step 1). An IGBT chip as a power semiconductor element is mounted on one main surface of the electrode plate portion of the lead frame and soldered (step 2). Next, a main circuit is formed by electrically connecting the power semiconductor element and the lead electrode portion of the lead frame with an Al wire having a diameter of 0.3 mm (step 3). The resin layer 1 is formed by primary molding with an epoxy resin so as to protect the main circuit portion (step 4). At this time, the protrusion 8 protruding toward the other main surface side is formed simultaneously with the resin layer 1. In this state, a part of the lead frame is cut so that characteristics can be measured (Step 5), and electrical characteristics are evaluated (Step 6). Further, the other main surface side of the primary molded circuit portion whose characteristics have been confirmed is integrated by heating and pressing on a base substrate to which an uncured epoxy resin green sheet is adhered. (Step 7). In this step, the resin layer 2 having a uniform and stable layer thickness and excellent heat conduction properties and insulation properties is obtained by the projections 8.

【0016】上記工程で準備された構造体を金型中にセ
ットし、所定条件で型内にエポキシ系樹脂を充填するこ
とによって樹脂層3を成形し、一体樹脂封止する(工程
8)。成形後、十分な硬化処理を施し(工程9)、最終
的に、リードフレームの不要部を切断,リード成形し所
定形状の半導体装置を得る(工程10)。上述した工程
7は、工程8の中で、金型中に接着すべき両者を別々に
位置合わせしてセットし、モールド成形と接着とを同時
に行うことも可能である。図3に工程7及び工程8を1
つの工程にした例を示す。図には樹脂層1の上面にも突
起部9を形成している。この突起部9の配置により、接
着工程(工程7)における加圧部を選択的に設定するこ
とができる。これにより均一な加圧が可能になる。
The structure prepared in the above steps is set in a mold, and the mold is filled with an epoxy resin under predetermined conditions to form a resin layer 3 and integrally resin-sealed (step 8). After the molding, a sufficient curing treatment is performed (Step 9), and finally, unnecessary portions of the lead frame are cut and lead-molded to obtain a semiconductor device having a predetermined shape (Step 10). In the above-mentioned step 7, in step 8, the two pieces to be bonded in the mold can be separately positioned and set, and the molding and the bonding can be performed simultaneously. FIG. 3 shows steps 7 and 8 as 1
An example in which one process is performed is shown. In the figure, a protrusion 9 is also formed on the upper surface of the resin layer 1. By the arrangement of the protrusions 9, the pressurizing portion in the bonding step (step 7) can be selectively set. This enables uniform pressurization.

【0017】本実施例では、樹脂層3用の材料としてエ
ポキシ系樹脂材料を用いたが、例えばポリフェニレン系
樹脂など熱可塑性樹脂であってもよい。また、樹脂層2
には良好な熱伝導特性を得るために、含有量が50体積
%以上の無機材料フィラー(例えばアルミナ,マグネシ
ア,シリカ,ベリリヤ,ジルコニヤ,窒化けい素,窒化
アルミニウム,炭化けい素など)を含む構造が望まし
い。一方、過度に多量にフィラーを含むと、樹脂層2に
微小なボイドが発生しやすくなるので、フィラーの含有
量は95体積%以下が好ましい。
In this embodiment, an epoxy resin material is used as a material for the resin layer 3, but a thermoplastic resin such as a polyphenylene resin may be used. Also, the resin layer 2
In order to obtain good thermal conductivity, a structure containing an inorganic material filler (for example, alumina, magnesia, silica, beryllia, zirconia, silicon nitride, aluminum nitride, silicon carbide, etc.) having a content of 50% by volume or more is required. Is desirable. On the other hand, if the filler is contained in an excessively large amount, minute voids are likely to be generated in the resin layer 2. Therefore, the content of the filler is preferably 95% by volume or less.

【0018】本実施例ではパワー半導体素子11とし
て、IGBT素子を用いた半導体装置の例について示し
たが、例えばMOS系トランジスタ,ダイオードなど他
の種類の半導体素子であってもよい。さらに、これら複
数素子の組み合わせによる特定の回路、例えばインバー
タ用パワーモジュールなどであってもよい。また回路中
に抵抗やコンデンサなどの受動素子が含まれていてもよ
い。
In this embodiment, an example of a semiconductor device using an IGBT element as the power semiconductor element 11 has been described. However, another type of semiconductor element such as a MOS transistor or a diode may be used. Furthermore, a specific circuit formed by a combination of these plural elements, for example, an inverter power module may be used. Further, a passive element such as a resistor or a capacitor may be included in the circuit.

【0019】(実施例2)実施例1とほぼ同様の構造を
有する本発明の他の実施例を図4に示す。実施例1との
相違は次のとおりである。すなわち、実施例1の樹脂層
1によって形成した突起部8に替えて、アルミナボール
のスペーサ7を配置した構造である。
(Embodiment 2) FIG. 4 shows another embodiment of the present invention having a structure substantially similar to that of Embodiment 1. The difference from the first embodiment is as follows. That is, the structure is such that the spacers 7 of alumina balls are arranged in place of the protrusions 8 formed by the resin layer 1 of the first embodiment.

【0020】図2に示す一連の製造工程中の工程7にお
いて、前記樹脂生シート表面に直径0.15mm のアルミ
ナボールを複数配置して、一次モールドされたリードフ
レームの主面2側を熱圧着して両者を接着することによ
り本実施例の構造を実現できる。本実施例ではスペーサ
7の材料としてアルミナボールの例について示したが、
他の絶縁性材料例えばマグネシア,シリカ,ベリリヤ,
ジルコニヤ,窒化けい素,窒化アルミニウム,炭化けい
素などの無機材料で有って良く、形状も球には限定され
ない。なお、球の直径は、必要とする樹脂層2の厚みと
略同じ大きさとする。
In step 7 of a series of manufacturing steps shown in FIG. 2, a plurality of alumina balls having a diameter of 0.15 mm are arranged on the surface of the green resin sheet, and the main surface 2 of the primary molded lead frame is thermocompression-bonded. Then, the structure of this embodiment can be realized by bonding the two. In the present embodiment, the example of the alumina ball is shown as the material of the spacer 7.
Other insulating materials such as magnesia, silica, beryllia,
It may be an inorganic material such as zirconia, silicon nitride, aluminum nitride, or silicon carbide, and the shape is not limited to a sphere. The diameter of the sphere is substantially the same as the required thickness of the resin layer 2.

【0021】(実施例3)実施例2とほぼ同様の構造を
有する本発明の他の実施例を図5に示す。実施例2との
相違を次のとおりである。すなわち、実施例2のスペー
サ7を予め樹脂層2の内部に複数配置した構造である。
(Embodiment 3) Another embodiment of the present invention having substantially the same structure as that of the embodiment 2 is shown in FIG. The difference from the second embodiment is as follows. That is, it has a structure in which a plurality of the spacers 7 of the second embodiment are arranged in advance inside the resin layer 2.

【0022】図2に示す一連の製造工程中の工程7にお
いて、前記樹脂生シートを作製する過程で予め該シート
内に直径0.15mm のアルミナボールを複数配置された
状態で準備し、前記一次モールドされたリードフレーム
の他方の主面側を熱圧着して両者を接着することにより
本実施例の構造を実現できる。本実施例ではスペーサ7
の材料としてアルミナボールの例について示したが、例
えばマグネシア,シリカ,ベリリヤ,ジルコニヤ,窒化
けい素,窒化アルミニウム,炭化けい素などの無機材料
で有っても良く、形状も球には限定されない。
In step 7 in the series of manufacturing steps shown in FIG. 2, in the process of producing the green resin sheet, a plurality of alumina balls having a diameter of 0.15 mm are prepared in advance in the sheet and the primary sheet is prepared. The structure of the present embodiment can be realized by thermocompression bonding the other main surface side of the molded lead frame and bonding them together. In this embodiment, the spacer 7
Although an example of an alumina ball has been shown as a material for the above, an inorganic material such as magnesia, silica, beryllia, zirconia, silicon nitride, aluminum nitride, and silicon carbide may be used, and the shape is not limited to a sphere.

【0023】(実施例4)本発明のいずれかの実施例に
よる半導体装置を適用した家庭用空調機の回路ブロック
図を図6に示す。本図のうち、圧縮機駆動用のモータ3
を制御するスイッチング回路に、本発明による半導体装
置を適用したものである。図7に、そのスッチング回路
部の詳細を示す。図中、P及びNの端子が電源回路に接
続される。本構成の空調機とすることにより、低熱抵抗
でかつ高信頼性のスイッチング回路部が得られ、省エネ
ルギー型の空調機を提供できる。
(Embodiment 4) FIG. 6 is a circuit block diagram of a home air conditioner to which a semiconductor device according to any of the embodiments of the present invention is applied. In the drawing, a motor 3 for driving the compressor is shown.
The semiconductor device according to the present invention is applied to a switching circuit for controlling the power supply. FIG. 7 shows details of the switching circuit section. In the figure, terminals P and N are connected to a power supply circuit. With the air conditioner having this configuration, a switching circuit portion having low heat resistance and high reliability can be obtained, and an energy-saving air conditioner can be provided.

【0024】図8に本スイッチング回路部の断面構成図
を示す。パワー半導体素子11としての6個のIGBT
を配置してリードフレームの電極板部13上に主回路を
形成し、樹脂基板21上にドライバIC19を含む制御
回路部を形成したものである。樹脂基板21も、IGB
T部とは別の電極板部13上に搭載され、樹脂層1によ
って被覆される。本半導体装置は、ヒートシンク20に
取り付けられて使用される。金属基板6の樹脂で被覆さ
れない外部露出面がヒートシンク表面と接触し、接触面
を介してIGBTで発生した熱が放熱される。
FIG. 8 shows a cross-sectional configuration diagram of the present switching circuit section. Six IGBTs as power semiconductor elements 11
And a main circuit is formed on the electrode plate 13 of the lead frame, and a control circuit including the driver IC 19 is formed on the resin substrate 21. Resin substrate 21 is also IGB
It is mounted on an electrode plate portion 13 different from the T portion, and is covered with the resin layer 1. The present semiconductor device is used by being attached to a heat sink 20. The externally exposed surface of the metal substrate 6 that is not covered with the resin contacts the heat sink surface, and the heat generated by the IGBT is radiated through the contact surface.

【0025】本実施例の構成を、家庭用もしくは産業用
などモータを具備する他の電気機器、例えば冷蔵庫,冷
凍庫,ポンプ,搬送機などに適用することにより、同様
に省エネルギー型の電気機器を実現できる。
By applying the configuration of this embodiment to other electric equipment having a motor, such as a household or industrial use, such as a refrigerator, a freezer, a pump, and a transporter, it is possible to realize an energy-saving electric equipment. it can.

【0026】[0026]

【発明の効果】本発明によれば、信頼性が高く、熱抵抗
が小さな樹脂封止型の半導体装置が得られる。
According to the present invention, a resin-encapsulated semiconductor device having high reliability and low thermal resistance can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例であるパワー半導体装置の断面
構成図。
FIG. 1 is a sectional configuration view of a power semiconductor device according to an embodiment of the present invention.

【図2】図1の実施例の製造工程図。FIG. 2 is a manufacturing process diagram of the embodiment of FIG. 1;

【図3】本発明の他の実施例であるパワー半導体装置の
断面構成図。
FIG. 3 is a sectional configuration diagram of a power semiconductor device according to another embodiment of the present invention.

【図4】本発明の他の実施例であるパワー半導体装置の
断面構成図。
FIG. 4 is a sectional configuration diagram of a power semiconductor device according to another embodiment of the present invention.

【図5】本発明の他の実施例であるパワー半導体装置の
断面構成図。
FIG. 5 is a sectional configuration diagram of a power semiconductor device according to another embodiment of the present invention.

【図6】本発明の実施例である空調機の回路ブロック
図。
FIG. 6 is a circuit block diagram of an air conditioner according to an embodiment of the present invention.

【図7】本発明の実施例による空調機スイッチング部の
回路ブロック図。
FIG. 7 is a circuit block diagram of an air conditioner switching unit according to an embodiment of the present invention.

【図8】本発明の実施例による空調機スイッチング部の
断面構成図。
FIG. 8 is a cross-sectional configuration diagram of an air conditioner switching unit according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1,2,3…樹脂層、4,5…リードフレームのリード
電極部、6…ベース基板、7…スペーサ、8…突起部
a、9…突起部b、11…パワー半導体素子a、12…
パワー半導体素子b、13…リードフレームの電極板
部、14…はんだ層、15…ワイヤボンディング部、1
6…樹脂挿入口、17…上金型、18…下金型、19…
ドライバIC、20…ヒートシンク、21…樹脂基板。
1, 2, 3 ... resin layer, 4, 5 ... lead electrode part of lead frame, 6 ... base substrate, 7 ... spacer, 8 ... protrusion a, 9 ... protrusion b, 11 ... power semiconductor elements a, 12 ...
Power semiconductor elements b, 13: Lead frame electrode plate part, 14: Solder layer, 15: Wire bonding part, 1
6 ... resin insertion opening, 17 ... upper mold, 18 ... lower mold, 19 ...
Driver IC, 20 heat sink, 21 resin board.

フロントページの続き (72)発明者 合田 正広 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 神村 典孝 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 Fターム(参考) 4M109 AA02 BA02 CA21 DB02 DB15 EB11 5F067 AA03 AA19 CA01 DE04 Continued on the front page (72) Inventor Masahiro Goda 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Noritaka Kamimura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term in Hitachi Research Laboratory, Hitachi, Ltd. (Reference) 4M109 AA02 BA02 CA21 DB02 DB15 EB11 5F067 AA03 AA19 CA01 DE04

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】半導体素子と、 前記半導体素子が搭載される電極板と、 前記半導体素子と電気的に接合されるリード電極と、 前記半導体素子、前記電極板及び前記リード電極が搭載
される基板と、 前記半導体素子、前記電極板及び前記リード電極を被覆
する第1の樹脂層と、 前記電極板及びリード電極と前記基板との間において、
前記電極板、前記リード電極及び基板と接着する第2の
樹脂層と、を有する構造体と、 前記リード電極の一部と前記基板の表面が露出するよう
に、前記構造体を被覆する第3の樹脂層と、を備えるこ
とを特徴とする半導体装置。
A semiconductor element; an electrode plate on which the semiconductor element is mounted; a lead electrode electrically connected to the semiconductor element; and a substrate on which the semiconductor element, the electrode plate, and the lead electrode are mounted. And a first resin layer covering the semiconductor element, the electrode plate and the lead electrode, and between the electrode plate and the lead electrode and the substrate,
A structure having a second resin layer adhered to the electrode plate, the lead electrode and the substrate; and a third covering the structure so that a part of the lead electrode and a surface of the substrate are exposed. And a resin layer.
【請求項2】請求項1において、前記第2の樹脂層内に
位置する、スペーサ手段を備えることを特徴とする半導
体装置。
2. The semiconductor device according to claim 1, further comprising spacer means located in said second resin layer.
【請求項3】請求項1において、前記第2の樹脂層中
に、50体積%以上95体積%以下の無機材料系フィラ
ーが含まれることを特徴とする半導体装置。
3. The semiconductor device according to claim 1, wherein the second resin layer contains 50% by volume to 95% by volume of an inorganic material-based filler.
【請求項4】電極板部とリード電極部とを有するリード
フレームの前記電極板部に半導体素子を搭載する第1の
工程と、 前記半導体素子,前記電極板部及び前記リード電極部を
第1の樹脂層で被覆する第2の工程と、 前記リードフレームを切断する第3の工程と、 基板と前記リードフレームとを、第2の樹脂層を介して
圧着する第4の工程と、 リードフレーム,半導体素子,第1及び第2の樹脂層、
及び基板を含む構造体を第3の樹脂層で被覆する第5の
工程と、を含むことを特徴とする半導体装置の製造方
法。
4. A first step of mounting a semiconductor element on the electrode plate portion of a lead frame having an electrode plate portion and a lead electrode portion, wherein the semiconductor element, the electrode plate portion, and the lead electrode portion are firstly mounted. A second step of coating the lead frame with a resin layer, a third step of cutting the lead frame, a fourth step of pressing a substrate and the lead frame through a second resin layer, and a lead frame. , Semiconductor element, first and second resin layers,
And a fifth step of covering a structure including the substrate with a third resin layer.
【請求項5】請求項4において、前記第3の工程と前記
第4の工程との間に、前記半導体素子を含む前記回路の
電気的特性を評価する工程を含むことを特徴とする半導
体装置の製造方法。
5. The semiconductor device according to claim 4, further comprising a step of evaluating an electrical characteristic of the circuit including the semiconductor element between the third step and the fourth step. Manufacturing method.
【請求項6】請求項4において、前記第2の工程におい
て、前記第1の樹脂層に突起を形成し、前記第4の工程
において、前記突起が前記基板に圧着されることを特徴
とする半導体装置の製造方法。
6. The method according to claim 4, wherein in the second step, a projection is formed on the first resin layer, and in the fourth step, the projection is pressure-bonded to the substrate. A method for manufacturing a semiconductor device.
【請求項7】請求項4において、前記第4の工程におい
て、前記第2の樹脂層内にスペーサが含まれていること
を特徴とする半導体装置の製造方法。
7. The method according to claim 4, wherein in the fourth step, a spacer is included in the second resin layer.
JP36027898A 1998-12-18 1998-12-18 Semiconductor device and its manufacture Pending JP2000183281A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP36027898A JP2000183281A (en) 1998-12-18 1998-12-18 Semiconductor device and its manufacture

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Application Number Priority Date Filing Date Title
JP36027898A JP2000183281A (en) 1998-12-18 1998-12-18 Semiconductor device and its manufacture

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Publication Number Publication Date
JP2000183281A true JP2000183281A (en) 2000-06-30

Family

ID=18468707

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2000183281A (en)

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Publication number Priority date Publication date Assignee Title
JP2002033433A (en) * 2000-07-13 2002-01-31 Hitachi Ltd Semiconductor device and manufacturing method thereof
JP2002203940A (en) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp Semiconductor power module
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